Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3044

1

T1

3

T3

27

T5

1

auto[1]

232

1

T79

4

T102

6

T113

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T3	1		T11	1		T12	1
auto[134217728:268435455]	98	1			T3	1		T40	1		T99	1
auto[268435456:402653183]	93	1			T3	1		T71	2		T36	1
auto[402653184:536870911]	109	1			T3	1		T12	1		T38	1
auto[536870912:671088639]	101	1			T13	1		T193	1		T6	1
auto[671088640:805306367]	99	1			T3	1		T12	1		T16	1
auto[805306368:939524095]	106	1			T3	1		T11	1		T99	1
auto[939524096:1073741823]	108	1			T3	1		T193	1		T42	1
auto[1073741824:1207959551]	112	1			T3	1		T52	2		T101	2
auto[1207959552:1342177279]	104	1			T36	1		T16	1		T6	1
auto[1342177280:1476395007]	104	1			T3	1		T38	1		T79	1
auto[1476395008:1610612735]	104	1			T3	2		T12	1		T40	1
auto[1610612736:1744830463]	113	1			T3	2		T101	1		T6	1
auto[1744830464:1879048191]	106	1			T12	1		T36	1		T42	1
auto[1879048192:2013265919]	106	1			T3	1		T5	1		T36	1
auto[2013265920:2147483647]	95	1			T71	1		T40	1		T41	1
auto[2147483648:2281701375]	105	1			T1	1		T3	1		T101	1
auto[2281701376:2415919103]	97	1			T3	3		T14	2		T36	1
auto[2415919104:2550136831]	102	1			T3	1		T58	1		T79	1
auto[2550136832:2684354559]	93	1			T3	1		T38	1		T126	1
auto[2684354560:2818572287]	87	1			T3	1		T193	1		T6	3
auto[2818572288:2952790015]	101	1			T3	1		T11	1		T12	1
auto[2952790016:3087007743]	107	1			T40	1		T20	1		T79	2
auto[3087007744:3221225471]	100	1			T45	1		T79	1		T102	1
auto[3221225472:3355443199]	103	1			T3	2		T38	1		T36	3
auto[3355443200:3489660927]	98	1			T3	1		T58	1		T97	1
auto[3489660928:3623878655]	103	1			T38	1		T36	1		T58	1
auto[3623878656:3758096383]	99	1			T1	1		T45	1		T16	1
auto[3758096384:3892314111]	114	1			T71	1		T97	1		T6	2
auto[3892314112:4026531839]	97	1			T3	1		T14	1		T36	1
auto[4026531840:4160749567]	104	1			T131	1		T79	2		T42	1
auto[4160749568:4294967295]	106	1			T1	1		T3	1		T44	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	90	1			T3	1		T11	1		T12	1
auto[0:134217727]	auto[1]	12	1			T103	1		T280	1		T247	1
auto[134217728:268435455]	auto[0]	92	1			T3	1		T40	1		T99	1
auto[134217728:268435455]	auto[1]	6	1			T113	1		T247	1		T250	1
auto[268435456:402653183]	auto[0]	87	1			T3	1		T71	2		T36	1
auto[268435456:402653183]	auto[1]	6	1			T389	1		T395	1		T344	1
auto[402653184:536870911]	auto[0]	102	1			T3	1		T12	1		T38	1
auto[402653184:536870911]	auto[1]	7	1			T103	2		T280	1		T234	1
auto[536870912:671088639]	auto[0]	91	1			T13	1		T193	1		T6	1
auto[536870912:671088639]	auto[1]	10	1			T247	1		T250	1		T233	1
auto[671088640:805306367]	auto[0]	96	1			T3	1		T12	1		T16	1
auto[671088640:805306367]	auto[1]	3	1			T113	1		T250	1		T357	1
auto[805306368:939524095]	auto[0]	99	1			T3	1		T11	1		T99	1
auto[805306368:939524095]	auto[1]	7	1			T247	1		T302	1		T322	2
auto[939524096:1073741823]	auto[0]	102	1			T3	1		T193	1		T42	1
auto[939524096:1073741823]	auto[1]	6	1			T302	1		T389	2		T409	1
auto[1073741824:1207959551]	auto[0]	102	1			T3	1		T52	2		T101	2
auto[1073741824:1207959551]	auto[1]	10	1			T102	1		T113	1		T250	1
auto[1207959552:1342177279]	auto[0]	99	1			T36	1		T16	1		T6	1
auto[1207959552:1342177279]	auto[1]	5	1			T102	1		T113	1		T389	1
auto[1342177280:1476395007]	auto[0]	97	1			T3	1		T38	1		T196	1
auto[1342177280:1476395007]	auto[1]	7	1			T79	1		T273	1		T302	1
auto[1476395008:1610612735]	auto[0]	97	1			T3	2		T12	1		T40	1
auto[1476395008:1610612735]	auto[1]	7	1			T113	1		T280	2		T388	2
auto[1610612736:1744830463]	auto[0]	105	1			T3	2		T101	1		T6	1
auto[1610612736:1744830463]	auto[1]	8	1			T250	1		T252	1		T302	1
auto[1744830464:1879048191]	auto[0]	101	1			T12	1		T36	1		T42	1
auto[1744830464:1879048191]	auto[1]	5	1			T302	1		T403	1		T392	1
auto[1879048192:2013265919]	auto[0]	98	1			T3	1		T5	1		T36	1
auto[1879048192:2013265919]	auto[1]	8	1			T250	1		T273	1		T234	1
auto[2013265920:2147483647]	auto[0]	84	1			T71	1		T40	1		T41	1
auto[2013265920:2147483647]	auto[1]	11	1			T113	1		T103	1		T234	1
auto[2147483648:2281701375]	auto[0]	98	1			T1	1		T3	1		T101	1
auto[2147483648:2281701375]	auto[1]	7	1			T280	2		T302	1		T392	1
auto[2281701376:2415919103]	auto[0]	92	1			T3	3		T14	2		T36	1
auto[2281701376:2415919103]	auto[1]	5	1			T79	1		T273	1		T403	1
auto[2415919104:2550136831]	auto[0]	98	1			T3	1		T58	1		T79	1
auto[2415919104:2550136831]	auto[1]	4	1			T103	1		T344	1		T410	1
auto[2550136832:2684354559]	auto[0]	85	1			T3	1		T38	1		T126	1
auto[2550136832:2684354559]	auto[1]	8	1			T302	1		T389	1		T322	1
auto[2684354560:2818572287]	auto[0]	79	1			T3	1		T193	1		T6	3
auto[2684354560:2818572287]	auto[1]	8	1			T113	1		T234	1		T360	1
auto[2818572288:2952790015]	auto[0]	92	1			T3	1		T11	1		T12	1
auto[2818572288:2952790015]	auto[1]	9	1			T79	1		T233	1		T389	1
auto[2952790016:3087007743]	auto[0]	99	1			T40	1		T20	1		T79	2
auto[2952790016:3087007743]	auto[1]	8	1			T102	1		T247	1		T302	1
auto[3087007744:3221225471]	auto[0]	91	1			T45	1		T79	1		T102	1
auto[3087007744:3221225471]	auto[1]	9	1			T113	1		T103	1		T280	1
auto[3221225472:3355443199]	auto[0]	99	1			T3	2		T38	1		T36	3
auto[3221225472:3355443199]	auto[1]	4	1			T394	1		T307	1		T411	1
auto[3355443200:3489660927]	auto[0]	89	1			T3	1		T58	1		T97	1
auto[3355443200:3489660927]	auto[1]	9	1			T247	1		T233	1		T273	1
auto[3489660928:3623878655]	auto[0]	96	1			T38	1		T36	1		T58	1
auto[3489660928:3623878655]	auto[1]	7	1			T102	1		T302	3		T389	1
auto[3623878656:3758096383]	auto[0]	90	1			T1	1		T45	1		T16	1
auto[3623878656:3758096383]	auto[1]	9	1			T102	1		T280	1		T247	1
auto[3758096384:3892314111]	auto[0]	110	1			T71	1		T97	1		T6	2
auto[3758096384:3892314111]	auto[1]	4	1			T406	1		T328	1		T344	1
auto[3892314112:4026531839]	auto[0]	89	1			T3	1		T14	1		T36	1
auto[3892314112:4026531839]	auto[1]	8	1			T102	1		T247	1		T234	1
auto[4026531840:4160749567]	auto[0]	101	1			T131	1		T79	1		T42	1
auto[4026531840:4160749567]	auto[1]	3	1			T79	1		T410	1		T412	1
auto[4160749568:4294967295]	auto[0]	94	1			T1	1		T3	1		T44	1
auto[4160749568:4294967295]	auto[1]	12	1			T280	2		T250	1		T273	1