dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3042 1 T1 3 T3 27 T5 1
auto[1] 213 1 T102 3 T113 3 T103 7


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 102 1 T44 1 T20 2 T52 1
auto[134217728:268435455] 112 1 T12 1 T38 1 T44 1
auto[268435456:402653183] 88 1 T23 1 T6 1 T128 1
auto[402653184:536870911] 111 1 T16 1 T42 1 T102 1
auto[536870912:671088639] 91 1 T14 1 T6 1 T59 1
auto[671088640:805306367] 107 1 T38 1 T101 1 T6 2
auto[805306368:939524095] 105 1 T3 2 T58 1 T45 1
auto[939524096:1073741823] 93 1 T3 1 T36 1 T40 1
auto[1073741824:1207959551] 93 1 T3 2 T5 1 T36 2
auto[1207959552:1342177279] 97 1 T3 2 T99 1 T79 1
auto[1342177280:1476395007] 106 1 T3 2 T36 2 T40 2
auto[1476395008:1610612735] 101 1 T52 1 T79 1 T6 1
auto[1610612736:1744830463] 99 1 T11 1 T71 1 T44 1
auto[1744830464:1879048191] 89 1 T3 1 T40 1 T193 1
auto[1879048192:2013265919] 105 1 T3 2 T36 1 T32 1
auto[2013265920:2147483647] 99 1 T71 1 T102 1 T60 1
auto[2147483648:2281701375] 101 1 T38 1 T58 1 T16 1
auto[2281701376:2415919103] 91 1 T127 1 T42 2 T6 1
auto[2415919104:2550136831] 81 1 T36 1 T6 1 T60 1
auto[2550136832:2684354559] 93 1 T12 2 T16 1 T99 1
auto[2684354560:2818572287] 102 1 T38 1 T36 1 T97 1
auto[2818572288:2952790015] 108 1 T3 2 T71 1 T38 1
auto[2952790016:3087007743] 110 1 T1 1 T71 1 T44 1
auto[3087007744:3221225471] 116 1 T3 2 T44 1 T58 1
auto[3221225472:3355443199] 107 1 T3 1 T11 1 T45 1
auto[3355443200:3489660927] 113 1 T3 3 T16 1 T6 1
auto[3489660928:3623878655] 98 1 T1 1 T3 1 T12 1
auto[3623878656:3758096383] 117 1 T3 2 T11 1 T14 1
auto[3758096384:3892314111] 102 1 T3 1 T6 2 T102 1
auto[3892314112:4026531839] 118 1 T3 3 T12 2 T13 1
auto[4026531840:4160749567] 102 1 T14 1 T36 1 T58 1
auto[4160749568:4294967295] 98 1 T1 1 T36 1 T79 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 91 1 T44 1 T20 2 T52 1
auto[0:134217727] auto[1] 11 1 T280 1 T389 1 T322 1
auto[134217728:268435455] auto[0] 107 1 T12 1 T38 1 T44 1
auto[134217728:268435455] auto[1] 5 1 T250 1 T360 1 T235 1
auto[268435456:402653183] auto[0] 84 1 T23 1 T6 1 T128 1
auto[268435456:402653183] auto[1] 4 1 T404 1 T402 1 T378 1
auto[402653184:536870911] auto[0] 105 1 T16 1 T42 1 T60 1
auto[402653184:536870911] auto[1] 6 1 T102 1 T103 1 T377 1
auto[536870912:671088639] auto[0] 84 1 T14 1 T6 1 T59 1
auto[536870912:671088639] auto[1] 7 1 T247 1 T273 1 T392 1
auto[671088640:805306367] auto[0] 101 1 T38 1 T101 1 T6 2
auto[671088640:805306367] auto[1] 6 1 T113 1 T342 1 T402 1
auto[805306368:939524095] auto[0] 96 1 T3 2 T58 1 T45 1
auto[805306368:939524095] auto[1] 9 1 T247 1 T273 1 T389 2
auto[939524096:1073741823] auto[0] 83 1 T3 1 T36 1 T40 1
auto[939524096:1073741823] auto[1] 10 1 T392 1 T389 4 T322 1
auto[1073741824:1207959551] auto[0] 85 1 T3 2 T5 1 T36 2
auto[1073741824:1207959551] auto[1] 8 1 T280 1 T250 1 T392 1
auto[1207959552:1342177279] auto[0] 94 1 T3 2 T99 1 T79 1
auto[1207959552:1342177279] auto[1] 3 1 T395 1 T388 1 T410 1
auto[1342177280:1476395007] auto[0] 98 1 T3 2 T36 2 T40 2
auto[1342177280:1476395007] auto[1] 8 1 T252 1 T234 1 T342 1
auto[1476395008:1610612735] auto[0] 97 1 T52 1 T79 1 T6 1
auto[1476395008:1610612735] auto[1] 4 1 T234 1 T377 1 T402 1
auto[1610612736:1744830463] auto[0] 93 1 T11 1 T71 1 T44 1
auto[1610612736:1744830463] auto[1] 6 1 T302 1 T389 1 T402 1
auto[1744830464:1879048191] auto[0] 82 1 T3 1 T40 1 T193 1
auto[1744830464:1879048191] auto[1] 7 1 T280 1 T273 1 T302 1
auto[1879048192:2013265919] auto[0] 96 1 T3 2 T36 1 T32 1
auto[1879048192:2013265919] auto[1] 9 1 T103 1 T247 1 T250 1
auto[2013265920:2147483647] auto[0] 94 1 T71 1 T102 1 T60 1
auto[2013265920:2147483647] auto[1] 5 1 T396 1 T389 2 T395 1
auto[2147483648:2281701375] auto[0] 94 1 T38 1 T58 1 T16 1
auto[2147483648:2281701375] auto[1] 7 1 T103 1 T252 1 T234 1
auto[2281701376:2415919103] auto[0] 86 1 T127 1 T42 2 T6 1
auto[2281701376:2415919103] auto[1] 5 1 T236 1 T302 1 T389 1
auto[2415919104:2550136831] auto[0] 77 1 T36 1 T6 1 T60 1
auto[2415919104:2550136831] auto[1] 4 1 T389 1 T395 1 T235 1
auto[2550136832:2684354559] auto[0] 85 1 T12 2 T16 1 T99 1
auto[2550136832:2684354559] auto[1] 8 1 T103 1 T250 1 T389 2
auto[2684354560:2818572287] auto[0] 92 1 T38 1 T36 1 T97 1
auto[2684354560:2818572287] auto[1] 10 1 T113 1 T280 2 T250 1
auto[2818572288:2952790015] auto[0] 104 1 T3 2 T71 1 T38 1
auto[2818572288:2952790015] auto[1] 4 1 T103 1 T235 1 T413 1
auto[2952790016:3087007743] auto[0] 104 1 T1 1 T71 1 T44 1
auto[2952790016:3087007743] auto[1] 6 1 T233 1 T357 1 T322 1
auto[3087007744:3221225471] auto[0] 109 1 T3 2 T44 1 T58 1
auto[3087007744:3221225471] auto[1] 7 1 T302 1 T389 1 T357 1
auto[3221225472:3355443199] auto[0] 99 1 T3 1 T11 1 T45 1
auto[3221225472:3355443199] auto[1] 8 1 T103 1 T247 1 T389 1
auto[3355443200:3489660927] auto[0] 108 1 T3 3 T16 1 T6 1
auto[3355443200:3489660927] auto[1] 5 1 T102 1 T113 1 T236 1
auto[3489660928:3623878655] auto[0] 93 1 T1 1 T3 1 T12 1
auto[3489660928:3623878655] auto[1] 5 1 T395 1 T235 1 T328 1
auto[3623878656:3758096383] auto[0] 107 1 T3 2 T11 1 T14 1
auto[3623878656:3758096383] auto[1] 10 1 T280 1 T302 1 T234 1
auto[3758096384:3892314111] auto[0] 94 1 T3 1 T6 2 T59 1
auto[3758096384:3892314111] auto[1] 8 1 T102 1 T103 1 T233 1
auto[3892314112:4026531839] auto[0] 112 1 T3 3 T12 2 T13 1
auto[3892314112:4026531839] auto[1] 6 1 T389 1 T322 1 T278 2
auto[4026531840:4160749567] auto[0] 94 1 T14 1 T36 1 T58 1
auto[4026531840:4160749567] auto[1] 8 1 T250 2 T389 1 T405 1
auto[4160749568:4294967295] auto[0] 94 1 T1 1 T36 1 T79 1
auto[4160749568:4294967295] auto[1] 4 1 T280 3 T278 1 - -

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%