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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3045 1 T1 3 T3 27 T5 1
auto[1] 212 1 T79 3 T102 5 T113 4


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 114 1 T38 1 T6 5 T113 1
auto[134217728:268435455] 113 1 T40 1 T42 1 T59 1
auto[268435456:402653183] 100 1 T126 1 T20 1 T79 1
auto[402653184:536870911] 93 1 T3 2 T5 1 T36 1
auto[536870912:671088639] 112 1 T3 1 T36 1 T44 1
auto[671088640:805306367] 106 1 T3 1 T36 1 T32 1
auto[805306368:939524095] 108 1 T1 1 T3 1 T23 1
auto[939524096:1073741823] 95 1 T3 2 T14 1 T36 1
auto[1073741824:1207959551] 104 1 T3 1 T58 1 T99 1
auto[1207959552:1342177279] 99 1 T11 1 T20 1 T97 1
auto[1342177280:1476395007] 114 1 T12 1 T14 1 T44 1
auto[1476395008:1610612735] 105 1 T11 1 T12 1 T40 2
auto[1610612736:1744830463] 82 1 T1 1 T3 1 T13 1
auto[1744830464:1879048191] 97 1 T3 1 T44 1 T127 1
auto[1879048192:2013265919] 91 1 T12 1 T193 1 T41 1
auto[2013265920:2147483647] 107 1 T3 1 T14 1 T6 2
auto[2147483648:2281701375] 98 1 T3 2 T12 1 T45 1
auto[2281701376:2415919103] 79 1 T3 1 T16 1 T183 1
auto[2415919104:2550136831] 107 1 T3 1 T102 1 T59 2
auto[2550136832:2684354559] 109 1 T3 1 T71 1 T38 1
auto[2684354560:2818572287] 87 1 T3 1 T11 1 T12 1
auto[2818572288:2952790015] 104 1 T1 1 T3 3 T36 1
auto[2952790016:3087007743] 111 1 T3 1 T71 1 T38 1
auto[3087007744:3221225471] 98 1 T3 1 T71 2 T36 1
auto[3221225472:3355443199] 95 1 T38 1 T58 1 T40 1
auto[3355443200:3489660927] 97 1 T3 1 T36 1 T40 1
auto[3489660928:3623878655] 85 1 T12 1 T58 1 T42 1
auto[3623878656:3758096383] 103 1 T3 1 T36 2 T16 1
auto[3758096384:3892314111] 104 1 T3 1 T79 1 T60 1
auto[3892314112:4026531839] 115 1 T38 1 T44 1 T97 1
auto[4026531840:4160749567] 105 1 T3 2 T36 1 T44 1
auto[4160749568:4294967295] 120 1 T52 2 T193 1 T6 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 112 1 T38 1 T6 5 T60 2
auto[0:134217727] auto[1] 2 1 T113 1 T413 1 - -
auto[134217728:268435455] auto[0] 105 1 T40 1 T42 1 T59 1
auto[134217728:268435455] auto[1] 8 1 T252 1 T391 1 T377 1
auto[268435456:402653183] auto[0] 95 1 T126 1 T20 1 T79 1
auto[268435456:402653183] auto[1] 5 1 T113 1 T396 1 T389 1
auto[402653184:536870911] auto[0] 89 1 T3 2 T5 1 T36 1
auto[402653184:536870911] auto[1] 4 1 T113 1 T389 1 T278 1
auto[536870912:671088639] auto[0] 108 1 T3 1 T36 1 T44 1
auto[536870912:671088639] auto[1] 4 1 T79 1 T398 1 T388 1
auto[671088640:805306367] auto[0] 97 1 T3 1 T36 1 T32 1
auto[671088640:805306367] auto[1] 9 1 T247 2 T250 1 T356 1
auto[805306368:939524095] auto[0] 103 1 T1 1 T3 1 T23 1
auto[805306368:939524095] auto[1] 5 1 T103 1 T247 1 T389 1
auto[939524096:1073741823] auto[0] 91 1 T3 2 T14 1 T36 1
auto[939524096:1073741823] auto[1] 4 1 T398 1 T411 1 T414 1
auto[1073741824:1207959551] auto[0] 99 1 T3 1 T58 1 T99 1
auto[1073741824:1207959551] auto[1] 5 1 T247 1 T234 1 T389 2
auto[1207959552:1342177279] auto[0] 95 1 T11 1 T20 1 T97 1
auto[1207959552:1342177279] auto[1] 4 1 T103 1 T250 1 T322 1
auto[1342177280:1476395007] auto[0] 107 1 T12 1 T14 1 T44 1
auto[1342177280:1476395007] auto[1] 7 1 T280 1 T247 1 T302 1
auto[1476395008:1610612735] auto[0] 103 1 T11 1 T12 1 T40 2
auto[1476395008:1610612735] auto[1] 2 1 T302 1 T415 1 - -
auto[1610612736:1744830463] auto[0] 81 1 T1 1 T3 1 T13 1
auto[1610612736:1744830463] auto[1] 1 1 T410 1 - - - -
auto[1744830464:1879048191] auto[0] 91 1 T3 1 T44 1 T127 1
auto[1744830464:1879048191] auto[1] 6 1 T360 1 T402 1 T394 1
auto[1879048192:2013265919] auto[0] 81 1 T12 1 T193 1 T41 1
auto[1879048192:2013265919] auto[1] 10 1 T113 1 T250 1 T273 2
auto[2013265920:2147483647] auto[0] 100 1 T3 1 T14 1 T6 2
auto[2013265920:2147483647] auto[1] 7 1 T233 1 T234 1 T392 1
auto[2147483648:2281701375] auto[0] 93 1 T3 2 T12 1 T45 1
auto[2147483648:2281701375] auto[1] 5 1 T79 1 T103 1 T392 1
auto[2281701376:2415919103] auto[0] 70 1 T3 1 T16 1 T183 1
auto[2281701376:2415919103] auto[1] 9 1 T302 1 T234 1 T392 1
auto[2415919104:2550136831] auto[0] 98 1 T3 1 T59 2 T128 1
auto[2415919104:2550136831] auto[1] 9 1 T102 1 T252 1 T396 1
auto[2550136832:2684354559] auto[0] 96 1 T3 1 T71 1 T38 1
auto[2550136832:2684354559] auto[1] 13 1 T102 1 T280 2 T250 1
auto[2684354560:2818572287] auto[0] 78 1 T3 1 T11 1 T12 1
auto[2684354560:2818572287] auto[1] 9 1 T102 1 T247 1 T252 1
auto[2818572288:2952790015] auto[0] 98 1 T1 1 T3 3 T36 1
auto[2818572288:2952790015] auto[1] 6 1 T403 2 T322 1 T404 1
auto[2952790016:3087007743] auto[0] 104 1 T3 1 T71 1 T38 1
auto[2952790016:3087007743] auto[1] 7 1 T280 1 T322 3 T388 1
auto[3087007744:3221225471] auto[0] 87 1 T3 1 T71 2 T36 1
auto[3087007744:3221225471] auto[1] 11 1 T234 1 T389 2 T357 1
auto[3221225472:3355443199] auto[0] 88 1 T38 1 T58 1 T40 1
auto[3221225472:3355443199] auto[1] 7 1 T280 1 T395 1 T390 1
auto[3355443200:3489660927] auto[0] 90 1 T3 1 T36 1 T40 1
auto[3355443200:3489660927] auto[1] 7 1 T247 1 T273 1 T392 1
auto[3489660928:3623878655] auto[0] 78 1 T12 1 T58 1 T42 1
auto[3489660928:3623878655] auto[1] 7 1 T252 1 T403 1 T360 1
auto[3623878656:3758096383] auto[0] 94 1 T3 1 T36 2 T16 1
auto[3623878656:3758096383] auto[1] 9 1 T102 1 T103 1 T247 1
auto[3758096384:3892314111] auto[0] 98 1 T3 1 T60 1 T169 1
auto[3758096384:3892314111] auto[1] 6 1 T79 1 T103 1 T389 1
auto[3892314112:4026531839] auto[0] 110 1 T38 1 T44 1 T97 1
auto[3892314112:4026531839] auto[1] 5 1 T247 1 T389 1 T402 1
auto[4026531840:4160749567] auto[0] 97 1 T3 2 T36 1 T44 1
auto[4026531840:4160749567] auto[1] 8 1 T103 1 T247 1 T389 2
auto[4160749568:4294967295] auto[0] 109 1 T52 2 T193 1 T6 2
auto[4160749568:4294967295] auto[1] 11 1 T102 1 T234 1 T391 2

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