Unified Coverage Report :: Group Instance : sealing_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1615

1

T3

14

T12

3

T14

1

auto[1]

1856

1

T1

3

T3

18

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T3	1		T5	1		T14	1
auto[134217728:268435455]	110	1			T3	2		T11	1		T44	1
auto[268435456:402653183]	100	1			T3	1		T101	1		T42	1
auto[402653184:536870911]	100	1			T3	1		T11	1		T97	1
auto[536870912:671088639]	116	1			T3	3		T127	1		T6	1
auto[671088640:805306367]	108	1			T1	1		T3	2		T13	1
auto[805306368:939524095]	119	1			T3	1		T71	1		T16	1
auto[939524096:1073741823]	98	1			T36	1		T23	1		T131	1
auto[1073741824:1207959551]	93	1			T196	1		T117	1		T59	1
auto[1207959552:1342177279]	105	1			T3	1		T38	1		T99	1
auto[1342177280:1476395007]	93	1			T127	1		T197	1		T60	1
auto[1476395008:1610612735]	98	1			T1	1		T58	1		T40	1
auto[1610612736:1744830463]	111	1			T12	1		T58	1		T40	1
auto[1744830464:1879048191]	124	1			T3	1		T36	1		T40	1
auto[1879048192:2013265919]	114	1			T3	2		T12	1		T14	1
auto[2013265920:2147483647]	126	1			T14	1		T44	1		T16	1
auto[2147483648:2281701375]	116	1			T20	2		T196	1		T6	2
auto[2281701376:2415919103]	111	1			T1	1		T3	2		T71	1
auto[2415919104:2550136831]	96	1			T40	1		T99	1		T101	1
auto[2550136832:2684354559]	103	1			T71	1		T16	1		T127	1
auto[2684354560:2818572287]	112	1			T3	1		T12	1		T36	1
auto[2818572288:2952790015]	116	1			T38	1		T36	1		T44	1
auto[2952790016:3087007743]	121	1			T3	2		T12	1		T38	1
auto[3087007744:3221225471]	114	1			T3	3		T20	1		T97	2
auto[3221225472:3355443199]	104	1			T3	1		T97	1		T196	1
auto[3355443200:3489660927]	103	1			T12	1		T71	1		T38	1
auto[3489660928:3623878655]	104	1			T3	3		T20	1		T6	2
auto[3623878656:3758096383]	112	1			T11	1		T58	1		T45	1
auto[3758096384:3892314111]	105	1			T3	1		T12	1		T58	1
auto[3892314112:4026531839]	113	1			T3	1		T127	1		T193	1
auto[4026531840:4160749567]	109	1			T126	1		T127	1		T6	3
auto[4160749568:4294967295]	112	1			T3	3		T38	1		T58	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	43	1			T3	1		T14	1		T16	1
auto[0:134217727]	auto[1]	62	1			T5	1		T36	2		T131	1
auto[134217728:268435455]	auto[0]	43	1			T44	1		T45	1		T41	1
auto[134217728:268435455]	auto[1]	67	1			T3	2		T11	1		T79	2
auto[268435456:402653183]	auto[0]	45	1			T101	1		T41	1		T60	1
auto[268435456:402653183]	auto[1]	55	1			T3	1		T42	1		T41	1
auto[402653184:536870911]	auto[0]	45	1			T3	1		T97	1		T101	1
auto[402653184:536870911]	auto[1]	55	1			T11	1		T59	1		T130	1
auto[536870912:671088639]	auto[0]	49	1			T3	1		T127	1		T103	1
auto[536870912:671088639]	auto[1]	67	1			T3	2		T6	1		T59	1
auto[671088640:805306367]	auto[0]	50	1			T36	1		T44	1		T42	1
auto[671088640:805306367]	auto[1]	58	1			T1	1		T3	2		T13	1
auto[805306368:939524095]	auto[0]	60	1			T71	1		T16	1		T97	1
auto[805306368:939524095]	auto[1]	59	1			T3	1		T52	1		T101	1
auto[939524096:1073741823]	auto[0]	42	1			T190	1		T313	1		T130	2
auto[939524096:1073741823]	auto[1]	56	1			T36	1		T23	1		T131	1
auto[1073741824:1207959551]	auto[0]	45	1			T130	2		T250	1		T277	1
auto[1073741824:1207959551]	auto[1]	48	1			T196	1		T117	1		T59	1
auto[1207959552:1342177279]	auto[0]	53	1			T38	1		T6	1		T41	1
auto[1207959552:1342177279]	auto[1]	52	1			T3	1		T99	1		T52	1
auto[1342177280:1476395007]	auto[0]	45	1			T127	1		T323	1		T245	1
auto[1342177280:1476395007]	auto[1]	48	1			T197	1		T60	1		T236	1
auto[1476395008:1610612735]	auto[0]	47	1			T58	1		T40	1		T59	1
auto[1476395008:1610612735]	auto[1]	51	1			T1	1		T32	1		T194	1
auto[1610612736:1744830463]	auto[0]	56	1			T40	1		T6	1		T103	1
auto[1610612736:1744830463]	auto[1]	55	1			T12	1		T58	1		T52	1
auto[1744830464:1879048191]	auto[0]	61	1			T36	1		T40	1		T45	2
auto[1744830464:1879048191]	auto[1]	63	1			T3	1		T193	1		T6	1
auto[1879048192:2013265919]	auto[0]	49	1			T3	2		T12	1		T131	1
auto[1879048192:2013265919]	auto[1]	65	1			T14	1		T99	1		T52	1
auto[2013265920:2147483647]	auto[0]	61	1			T44	1		T42	1		T60	1
auto[2013265920:2147483647]	auto[1]	65	1			T14	1		T16	1		T102	1
auto[2147483648:2281701375]	auto[0]	47	1			T20	1		T6	1		T60	1
auto[2147483648:2281701375]	auto[1]	69	1			T20	1		T196	1		T6	1
auto[2281701376:2415919103]	auto[0]	62	1			T3	1		T71	1		T36	1
auto[2281701376:2415919103]	auto[1]	49	1			T1	1		T3	1		T6	2
auto[2415919104:2550136831]	auto[0]	44	1			T40	1		T101	1		T128	1
auto[2415919104:2550136831]	auto[1]	52	1			T99	1		T60	1		T166	1
auto[2550136832:2684354559]	auto[0]	46	1			T6	1		T283	1		T130	1
auto[2550136832:2684354559]	auto[1]	57	1			T71	1		T16	1		T127	1
auto[2684354560:2818572287]	auto[0]	54	1			T12	1		T36	1		T6	1
auto[2684354560:2818572287]	auto[1]	58	1			T3	1		T59	2		T60	1
auto[2818572288:2952790015]	auto[0]	61	1			T36	1		T45	1		T101	1
auto[2818572288:2952790015]	auto[1]	55	1			T38	1		T44	1		T182	1
auto[2952790016:3087007743]	auto[0]	54	1			T38	1		T36	2		T45	1
auto[2952790016:3087007743]	auto[1]	67	1			T3	2		T12	1		T79	2
auto[3087007744:3221225471]	auto[0]	53	1			T3	2		T20	1		T97	2
auto[3087007744:3221225471]	auto[1]	61	1			T3	1		T102	1		T261	1
auto[3221225472:3355443199]	auto[0]	46	1			T3	1		T97	1		T193	1
auto[3221225472:3355443199]	auto[1]	58	1			T196	1		T183	2		T60	1
auto[3355443200:3489660927]	auto[0]	46	1			T12	1		T71	1		T38	1
auto[3355443200:3489660927]	auto[1]	57	1			T16	1		T193	1		T101	1
auto[3489660928:3623878655]	auto[0]	50	1			T3	1		T20	1		T6	2
auto[3489660928:3623878655]	auto[1]	54	1			T3	2		T59	1		T60	1
auto[3623878656:3758096383]	auto[0]	58	1			T58	1		T45	1		T6	1
auto[3623878656:3758096383]	auto[1]	54	1			T11	1		T59	2		T60	1
auto[3758096384:3892314111]	auto[0]	48	1			T3	1		T101	1		T134	2
auto[3758096384:3892314111]	auto[1]	57	1			T12	1		T58	1		T6	2
auto[3892314112:4026531839]	auto[0]	49	1			T3	1		T127	1		T193	1
auto[3892314112:4026531839]	auto[1]	64	1			T6	1		T60	1		T167	1
auto[4026531840:4160749567]	auto[0]	56	1			T126	1		T127	1		T6	1
auto[4026531840:4160749567]	auto[1]	53	1			T6	2		T60	2		T190	1
auto[4160749568:4294967295]	auto[0]	47	1			T3	2		T193	1		T6	1
auto[4160749568:4294967295]	auto[1]	65	1			T3	1		T38	1		T58	1