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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 7083 1 T1 4 T3 60 T5 2
auto[1] 232 1 T79 1 T102 3 T113 4



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 2960 1 T1 1 T3 26 T5 1
auto[134217728:268435455] 185 1 T11 1 T12 1 T40 1
auto[268435456:402653183] 156 1 T1 1 T3 1 T36 1
auto[402653184:536870911] 156 1 T12 2 T36 1 T40 1
auto[536870912:671088639] 146 1 T3 1 T5 1 T14 1
auto[671088640:805306367] 146 1 T3 3 T13 1 T52 1
auto[805306368:939524095] 148 1 T3 1 T44 1 T20 1
auto[939524096:1073741823] 133 1 T1 1 T38 1 T16 1
auto[1073741824:1207959551] 171 1 T3 4 T71 1 T44 1
auto[1207959552:1342177279] 160 1 T3 3 T40 1 T99 2
auto[1342177280:1476395007] 134 1 T3 2 T11 1 T71 1
auto[1476395008:1610612735] 133 1 T3 1 T36 1 T58 1
auto[1610612736:1744830463] 136 1 T3 1 T44 1 T6 1
auto[1744830464:1879048191] 141 1 T3 2 T14 1 T71 1
auto[1879048192:2013265919] 128 1 T3 1 T23 1 T40 1
auto[2013265920:2147483647] 133 1 T3 2 T44 1 T20 1
auto[2147483648:2281701375] 128 1 T3 2 T12 1 T38 1
auto[2281701376:2415919103] 144 1 T3 3 T36 1 T45 1
auto[2415919104:2550136831] 127 1 T44 1 T20 1 T6 1
auto[2550136832:2684354559] 154 1 T1 1 T36 1 T131 3
auto[2684354560:2818572287] 125 1 T11 1 T38 1 T40 1
auto[2818572288:2952790015] 123 1 T3 1 T38 1 T44 1
auto[2952790016:3087007743] 121 1 T3 1 T12 1 T79 1
auto[3087007744:3221225471] 132 1 T14 1 T23 1 T196 1
auto[3221225472:3355443199] 128 1 T71 1 T44 1 T20 1
auto[3355443200:3489660927] 129 1 T42 1 T6 2 T41 1
auto[3489660928:3623878655] 136 1 T3 2 T12 1 T45 1
auto[3623878656:3758096383] 127 1 T3 1 T38 1 T36 1
auto[3758096384:3892314111] 136 1 T52 1 T193 1 T101 1
auto[3892314112:4026531839] 146 1 T3 1 T36 2 T44 1
auto[4026531840:4160749567] 145 1 T3 1 T12 2 T36 2
auto[4160749568:4294967295] 148 1 T20 1 T127 1 T6 1



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 2956 1 T1 1 T3 26 T5 1
auto[0:134217727] auto[1] 4 1 T250 1 T273 1 T302 1
auto[134217728:268435455] auto[0] 175 1 T11 1 T12 1 T40 1
auto[134217728:268435455] auto[1] 10 1 T79 1 T280 2 T389 1
auto[268435456:402653183] auto[0] 149 1 T1 1 T3 1 T36 1
auto[268435456:402653183] auto[1] 7 1 T113 1 T247 1 T233 1
auto[402653184:536870911] auto[0] 148 1 T12 2 T36 1 T40 1
auto[402653184:536870911] auto[1] 8 1 T103 1 T250 2 T392 1
auto[536870912:671088639] auto[0] 135 1 T3 1 T5 1 T14 1
auto[536870912:671088639] auto[1] 11 1 T113 1 T247 1 T250 2
auto[671088640:805306367] auto[0] 138 1 T3 3 T13 1 T52 1
auto[671088640:805306367] auto[1] 8 1 T273 1 T252 1 T392 1
auto[805306368:939524095] auto[0] 141 1 T3 1 T44 1 T20 1
auto[805306368:939524095] auto[1] 7 1 T113 1 T247 1 T322 1
auto[939524096:1073741823] auto[0] 125 1 T1 1 T38 1 T16 1
auto[939524096:1073741823] auto[1] 8 1 T234 1 T389 1 T322 1
auto[1073741824:1207959551] auto[0] 164 1 T3 4 T71 1 T44 1
auto[1073741824:1207959551] auto[1] 7 1 T250 1 T402 1 T395 1
auto[1207959552:1342177279] auto[0] 155 1 T3 3 T40 1 T99 2
auto[1207959552:1342177279] auto[1] 5 1 T392 1 T389 1 T344 1
auto[1342177280:1476395007] auto[0] 131 1 T3 2 T11 1 T71 1
auto[1342177280:1476395007] auto[1] 3 1 T234 1 T395 1 T388 1
auto[1476395008:1610612735] auto[0] 128 1 T3 1 T36 1 T58 1
auto[1476395008:1610612735] auto[1] 5 1 T247 1 T392 1 T389 1
auto[1610612736:1744830463] auto[0] 128 1 T3 1 T44 1 T6 1
auto[1610612736:1744830463] auto[1] 8 1 T103 1 T391 1 T392 1
auto[1744830464:1879048191] auto[0] 127 1 T3 2 T14 1 T71 1
auto[1744830464:1879048191] auto[1] 14 1 T280 1 T247 2 T250 1
auto[1879048192:2013265919] auto[0] 121 1 T3 1 T23 1 T40 1
auto[1879048192:2013265919] auto[1] 7 1 T103 1 T280 1 T342 1
auto[2013265920:2147483647] auto[0] 128 1 T3 2 T44 1 T20 1
auto[2013265920:2147483647] auto[1] 5 1 T389 1 T322 1 T394 1
auto[2147483648:2281701375] auto[0] 122 1 T3 2 T12 1 T38 1
auto[2147483648:2281701375] auto[1] 6 1 T388 2 T307 1 T344 1
auto[2281701376:2415919103] auto[0] 136 1 T3 3 T36 1 T45 1
auto[2281701376:2415919103] auto[1] 8 1 T403 1 T389 1 T404 1
auto[2415919104:2550136831] auto[0] 124 1 T44 1 T20 1 T6 1
auto[2415919104:2550136831] auto[1] 3 1 T250 1 T389 1 T311 1
auto[2550136832:2684354559] auto[0] 149 1 T1 1 T36 1 T131 3
auto[2550136832:2684354559] auto[1] 5 1 T103 1 T398 1 T307 1
auto[2684354560:2818572287] auto[0] 117 1 T11 1 T38 1 T40 1
auto[2684354560:2818572287] auto[1] 8 1 T247 1 T403 1 T388 2
auto[2818572288:2952790015] auto[0] 111 1 T3 1 T38 1 T44 1
auto[2818572288:2952790015] auto[1] 12 1 T302 1 T392 2 T394 1
auto[2952790016:3087007743] auto[0] 116 1 T3 1 T12 1 T79 1
auto[2952790016:3087007743] auto[1] 5 1 T103 1 T389 1 T405 1
auto[3087007744:3221225471] auto[0] 125 1 T14 1 T23 1 T196 1
auto[3087007744:3221225471] auto[1] 7 1 T273 1 T234 1 T388 1
auto[3221225472:3355443199] auto[0] 118 1 T71 1 T44 1 T20 1
auto[3221225472:3355443199] auto[1] 10 1 T102 1 T273 1 T252 1
auto[3355443200:3489660927] auto[0] 119 1 T42 1 T6 2 T41 1
auto[3355443200:3489660927] auto[1] 10 1 T113 1 T280 1 T250 1
auto[3489660928:3623878655] auto[0] 130 1 T3 2 T12 1 T45 1
auto[3489660928:3623878655] auto[1] 6 1 T102 1 T250 1 T360 1
auto[3623878656:3758096383] auto[0] 119 1 T3 1 T38 1 T36 1
auto[3623878656:3758096383] auto[1] 8 1 T102 1 T391 1 T389 1
auto[3758096384:3892314111] auto[0] 130 1 T52 1 T193 1 T101 1
auto[3758096384:3892314111] auto[1] 6 1 T280 1 T389 1 T388 2
auto[3892314112:4026531839] auto[0] 138 1 T3 1 T36 2 T44 1
auto[3892314112:4026531839] auto[1] 8 1 T396 1 T322 1 T406 1
auto[4026531840:4160749567] auto[0] 139 1 T3 1 T12 2 T36 2
auto[4026531840:4160749567] auto[1] 6 1 T388 1 T278 2 T344 1
auto[4160749568:4294967295] auto[0] 141 1 T20 1 T127 1 T6 1
auto[4160749568:4294967295] auto[1] 7 1 T103 1 T273 1 T356 1

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