Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4608

1

T1

4

T3

42

T11

6

auto[1]

2334

1

T1

2

T3

22

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	226	1			T1	2		T11	2		T12	2
auto[134217728:268435455]	224	1			T3	2		T71	2		T36	2
auto[268435456:402653183]	198	1			T3	6		T16	2		T127	2
auto[402653184:536870911]	232	1			T3	2		T14	2		T38	2
auto[536870912:671088639]	224	1			T12	2		T16	2		T52	2
auto[671088640:805306367]	216	1			T3	4		T127	2		T42	2
auto[805306368:939524095]	182	1			T3	2		T131	2		T193	2
auto[939524096:1073741823]	216	1			T3	6		T16	2		T97	2
auto[1073741824:1207959551]	216	1			T3	2		T36	2		T32	2
auto[1207959552:1342177279]	254	1			T1	2		T3	4		T6	2
auto[1342177280:1476395007]	188	1			T3	2		T36	4		T44	2
auto[1476395008:1610612735]	228	1			T12	2		T79	2		T6	2
auto[1610612736:1744830463]	186	1			T36	2		T79	2		T6	2
auto[1744830464:1879048191]	210	1			T14	2		T58	2		T97	2
auto[1879048192:2013265919]	222	1			T3	4		T5	2		T58	2
auto[2013265920:2147483647]	256	1			T38	2		T23	2		T20	2
auto[2147483648:2281701375]	198	1			T3	2		T36	2		T16	2
auto[2281701376:2415919103]	246	1			T3	6		T71	2		T44	2
auto[2415919104:2550136831]	192	1			T44	2		T40	4		T59	4
auto[2550136832:2684354559]	196	1			T1	2		T3	2		T99	2
auto[2684354560:2818572287]	208	1			T14	2		T126	2		T131	2
auto[2818572288:2952790015]	214	1			T3	4		T12	2		T45	2
auto[2952790016:3087007743]	220	1			T71	2		T38	2		T6	2
auto[3087007744:3221225471]	256	1			T44	2		T40	2		T20	2
auto[3221225472:3355443199]	180	1			T3	2		T12	2		T38	2
auto[3355443200:3489660927]	200	1			T3	2		T44	2		T45	2
auto[3489660928:3623878655]	250	1			T3	6		T71	2		T36	2
auto[3623878656:3758096383]	176	1			T38	2		T45	2		T99	2
auto[3758096384:3892314111]	220	1			T3	2		T11	2		T12	2
auto[3892314112:4026531839]	228	1			T3	2		T52	2		T196	4
auto[4026531840:4160749567]	226	1			T3	2		T40	2		T16	2
auto[4160749568:4294967295]	254	1			T11	2		T36	2		T45	4

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	152	1			T1	2		T11	2		T12	2
auto[0:134217727]	auto[1]	74	1			T36	2		T20	2		T42	2
auto[134217728:268435455]	auto[0]	156	1			T71	2		T101	2		T130	2
auto[134217728:268435455]	auto[1]	68	1			T3	2		T36	2		T59	4
auto[268435456:402653183]	auto[0]	128	1			T3	4		T16	2		T60	2
auto[268435456:402653183]	auto[1]	70	1			T3	2		T127	2		T6	2
auto[402653184:536870911]	auto[0]	164	1			T3	2		T14	2		T38	2
auto[402653184:536870911]	auto[1]	68	1			T36	2		T6	2		T60	2
auto[536870912:671088639]	auto[0]	148	1			T16	2		T52	2		T6	4
auto[536870912:671088639]	auto[1]	76	1			T12	2		T42	2		T6	2
auto[671088640:805306367]	auto[0]	140	1			T3	2		T127	2		T59	2
auto[671088640:805306367]	auto[1]	76	1			T3	2		T42	2		T6	2
auto[805306368:939524095]	auto[0]	118	1			T3	2		T193	2		T101	4
auto[805306368:939524095]	auto[1]	64	1			T131	2		T77	2		T401	2
auto[939524096:1073741823]	auto[0]	140	1			T3	4		T16	2		T6	2
auto[939524096:1073741823]	auto[1]	76	1			T3	2		T97	2		T42	2
auto[1073741824:1207959551]	auto[0]	156	1			T3	2		T36	2		T399	2
auto[1073741824:1207959551]	auto[1]	60	1			T32	2		T6	6		T59	2
auto[1207959552:1342177279]	auto[0]	182	1			T1	2		T6	2		T60	6
auto[1207959552:1342177279]	auto[1]	72	1			T3	4		T59	2		T105	2
auto[1342177280:1476395007]	auto[0]	124	1			T36	2		T44	2		T40	2
auto[1342177280:1476395007]	auto[1]	64	1			T3	2		T36	2		T58	2
auto[1476395008:1610612735]	auto[0]	172	1			T12	2		T6	2		T60	2
auto[1476395008:1610612735]	auto[1]	56	1			T79	2		T128	2		T400	2
auto[1610612736:1744830463]	auto[0]	112	1			T79	2		T130	2		T355	2
auto[1610612736:1744830463]	auto[1]	74	1			T36	2		T6	2		T60	2
auto[1744830464:1879048191]	auto[0]	130	1			T14	2		T103	2		T169	2
auto[1744830464:1879048191]	auto[1]	80	1			T58	2		T97	2		T102	2
auto[1879048192:2013265919]	auto[0]	146	1			T3	4		T58	2		T131	2
auto[1879048192:2013265919]	auto[1]	76	1			T5	2		T40	2		T60	2
auto[2013265920:2147483647]	auto[0]	158	1			T38	2		T20	2		T6	2
auto[2013265920:2147483647]	auto[1]	98	1			T23	2		T102	2		T182	2
auto[2147483648:2281701375]	auto[0]	126	1			T36	2		T99	2		T79	2
auto[2147483648:2281701375]	auto[1]	72	1			T3	2		T16	2		T52	2
auto[2281701376:2415919103]	auto[0]	172	1			T3	6		T71	2		T44	2
auto[2281701376:2415919103]	auto[1]	74	1			T97	4		T6	6		T182	4
auto[2415919104:2550136831]	auto[0]	122	1			T40	2		T59	4		T183	2
auto[2415919104:2550136831]	auto[1]	70	1			T44	2		T40	2		T130	4
auto[2550136832:2684354559]	auto[0]	140	1			T3	2		T99	2		T6	4
auto[2550136832:2684354559]	auto[1]	56	1			T1	2		T194	2		T60	2
auto[2684354560:2818572287]	auto[0]	148	1			T14	2		T131	2		T193	2
auto[2684354560:2818572287]	auto[1]	60	1			T126	2		T97	2		T105	2
auto[2818572288:2952790015]	auto[0]	144	1			T3	2		T12	2		T45	2
auto[2818572288:2952790015]	auto[1]	70	1			T3	2		T169	2		T33	2
auto[2952790016:3087007743]	auto[0]	150	1			T71	2		T38	2		T59	4
auto[2952790016:3087007743]	auto[1]	70	1			T6	2		T167	2		T236	2
auto[3087007744:3221225471]	auto[0]	148	1			T40	2		T20	2		T52	2
auto[3087007744:3221225471]	auto[1]	108	1			T44	2		T59	2		T113	2
auto[3221225472:3355443199]	auto[0]	110	1			T12	2		T38	2		T59	6
auto[3221225472:3355443199]	auto[1]	70	1			T3	2		T58	2		T196	2
auto[3355443200:3489660927]	auto[0]	130	1			T3	2		T45	2		T59	2
auto[3355443200:3489660927]	auto[1]	70	1			T44	2		T201	2		T236	2
auto[3489660928:3623878655]	auto[0]	162	1			T3	4		T71	2		T36	2
auto[3489660928:3623878655]	auto[1]	88	1			T3	2		T79	2		T193	2
auto[3623878656:3758096383]	auto[0]	112	1			T99	2		T127	2		T101	2
auto[3623878656:3758096383]	auto[1]	64	1			T38	2		T45	2		T193	2
auto[3758096384:3892314111]	auto[0]	142	1			T3	2		T11	2		T97	2
auto[3758096384:3892314111]	auto[1]	78	1			T12	2		T13	2		T58	2
auto[3892314112:4026531839]	auto[0]	152	1			T3	2		T196	4		T6	4
auto[3892314112:4026531839]	auto[1]	76	1			T52	2		T59	2		T399	2
auto[4026531840:4160749567]	auto[0]	150	1			T3	2		T40	2		T16	2
auto[4026531840:4160749567]	auto[1]	76	1			T193	2		T6	2		T128	2
auto[4160749568:4294967295]	auto[0]	174	1			T11	2		T36	2		T45	4
auto[4160749568:4294967295]	auto[1]	80	1			T32	2		T408	2		T174	2