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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.43 99.00 98.03 98.47 97.67 98.93 98.63 91.24


Total test records in report: 1075
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T1010 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1980566505 Aug 17 04:41:22 PM PDT 24 Aug 17 04:41:23 PM PDT 24 19339462 ps
T1011 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.4271454598 Aug 17 04:41:08 PM PDT 24 Aug 17 04:41:11 PM PDT 24 229153527 ps
T1012 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3241222210 Aug 17 04:41:17 PM PDT 24 Aug 17 04:41:19 PM PDT 24 60616195 ps
T1013 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.527783509 Aug 17 04:41:25 PM PDT 24 Aug 17 04:41:26 PM PDT 24 49607969 ps
T152 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1228113744 Aug 17 04:41:15 PM PDT 24 Aug 17 04:41:22 PM PDT 24 317705352 ps
T1014 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1558076999 Aug 17 04:41:18 PM PDT 24 Aug 17 04:41:19 PM PDT 24 43084782 ps
T1015 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3091630516 Aug 17 04:41:30 PM PDT 24 Aug 17 04:41:32 PM PDT 24 861915292 ps
T1016 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1267304024 Aug 17 04:41:30 PM PDT 24 Aug 17 04:41:32 PM PDT 24 70316613 ps
T1017 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.505644729 Aug 17 04:41:32 PM PDT 24 Aug 17 04:41:34 PM PDT 24 216442740 ps
T1018 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3948242346 Aug 17 04:41:15 PM PDT 24 Aug 17 04:41:17 PM PDT 24 627213593 ps
T1019 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3253710794 Aug 17 04:41:14 PM PDT 24 Aug 17 04:41:18 PM PDT 24 466122374 ps
T147 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2945353784 Aug 17 04:41:04 PM PDT 24 Aug 17 04:41:09 PM PDT 24 115236243 ps
T1020 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.315185801 Aug 17 04:41:16 PM PDT 24 Aug 17 04:41:21 PM PDT 24 349423525 ps
T1021 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.908524134 Aug 17 04:41:03 PM PDT 24 Aug 17 04:41:12 PM PDT 24 137341694 ps
T1022 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.226244411 Aug 17 04:41:02 PM PDT 24 Aug 17 04:41:04 PM PDT 24 55411955 ps
T1023 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3345466001 Aug 17 04:41:30 PM PDT 24 Aug 17 04:41:35 PM PDT 24 187248786 ps
T1024 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.616740943 Aug 17 04:41:13 PM PDT 24 Aug 17 04:41:15 PM PDT 24 79489251 ps
T1025 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2566866420 Aug 17 04:41:32 PM PDT 24 Aug 17 04:41:35 PM PDT 24 31873006 ps
T1026 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.514107867 Aug 17 04:41:17 PM PDT 24 Aug 17 04:41:18 PM PDT 24 87797482 ps
T1027 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1763055829 Aug 17 04:41:17 PM PDT 24 Aug 17 04:41:20 PM PDT 24 202607804 ps
T1028 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.252129995 Aug 17 04:41:17 PM PDT 24 Aug 17 04:41:18 PM PDT 24 77231538 ps
T1029 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2547002101 Aug 17 04:41:09 PM PDT 24 Aug 17 04:41:10 PM PDT 24 22930630 ps
T1030 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1939378879 Aug 17 04:41:19 PM PDT 24 Aug 17 04:41:23 PM PDT 24 145333412 ps
T1031 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3742060155 Aug 17 04:40:58 PM PDT 24 Aug 17 04:41:00 PM PDT 24 293013052 ps
T1032 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1323569715 Aug 17 04:41:03 PM PDT 24 Aug 17 04:41:04 PM PDT 24 26431598 ps
T1033 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1314275262 Aug 17 04:40:59 PM PDT 24 Aug 17 04:41:13 PM PDT 24 499396114 ps
T149 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1200885570 Aug 17 04:41:14 PM PDT 24 Aug 17 04:41:19 PM PDT 24 131600809 ps
T1034 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1537017750 Aug 17 04:41:04 PM PDT 24 Aug 17 04:41:13 PM PDT 24 227910016 ps
T1035 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3454439341 Aug 17 04:41:15 PM PDT 24 Aug 17 04:41:16 PM PDT 24 176987617 ps
T1036 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.151874964 Aug 17 04:41:01 PM PDT 24 Aug 17 04:41:02 PM PDT 24 182345847 ps
T1037 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3746650560 Aug 17 04:41:17 PM PDT 24 Aug 17 04:41:19 PM PDT 24 1131978702 ps
T1038 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.4081807908 Aug 17 04:41:29 PM PDT 24 Aug 17 04:41:31 PM PDT 24 43108704 ps
T158 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1341375288 Aug 17 04:41:08 PM PDT 24 Aug 17 04:41:15 PM PDT 24 251069026 ps
T150 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1042061622 Aug 17 04:41:16 PM PDT 24 Aug 17 04:41:27 PM PDT 24 1046721840 ps
T1039 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1159275707 Aug 17 04:40:59 PM PDT 24 Aug 17 04:41:15 PM PDT 24 2312941542 ps
T1040 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2365756376 Aug 17 04:41:01 PM PDT 24 Aug 17 04:41:01 PM PDT 24 15377042 ps
T1041 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.149720599 Aug 17 04:41:02 PM PDT 24 Aug 17 04:41:14 PM PDT 24 3960837958 ps
T1042 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1822485542 Aug 17 04:41:20 PM PDT 24 Aug 17 04:41:21 PM PDT 24 27201856 ps
T151 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1129868312 Aug 17 04:41:14 PM PDT 24 Aug 17 04:41:21 PM PDT 24 172958119 ps
T1043 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2078552425 Aug 17 04:41:29 PM PDT 24 Aug 17 04:41:32 PM PDT 24 124736903 ps
T1044 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2111753938 Aug 17 04:41:16 PM PDT 24 Aug 17 04:41:17 PM PDT 24 10554475 ps
T157 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1097117916 Aug 17 04:41:01 PM PDT 24 Aug 17 04:41:05 PM PDT 24 233452254 ps
T1045 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1593571865 Aug 17 04:41:16 PM PDT 24 Aug 17 04:41:17 PM PDT 24 18552758 ps
T1046 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4254822439 Aug 17 04:41:02 PM PDT 24 Aug 17 04:41:11 PM PDT 24 1327529254 ps
T1047 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.286488518 Aug 17 04:41:29 PM PDT 24 Aug 17 04:41:30 PM PDT 24 19257280 ps
T1048 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3438725112 Aug 17 04:41:11 PM PDT 24 Aug 17 04:41:12 PM PDT 24 41112634 ps
T144 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2448046049 Aug 17 04:41:03 PM PDT 24 Aug 17 04:41:13 PM PDT 24 529426205 ps
T1049 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3442646355 Aug 17 04:41:26 PM PDT 24 Aug 17 04:41:27 PM PDT 24 29461473 ps
T1050 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2265954710 Aug 17 04:40:59 PM PDT 24 Aug 17 04:41:00 PM PDT 24 67344032 ps
T1051 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2640732168 Aug 17 04:41:18 PM PDT 24 Aug 17 04:41:22 PM PDT 24 151073319 ps
T1052 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.796189650 Aug 17 04:41:10 PM PDT 24 Aug 17 04:41:12 PM PDT 24 213142738 ps
T1053 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1431400071 Aug 17 04:41:11 PM PDT 24 Aug 17 04:41:12 PM PDT 24 25780462 ps
T1054 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4028833450 Aug 17 04:41:26 PM PDT 24 Aug 17 04:41:27 PM PDT 24 23915720 ps
T1055 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3887128807 Aug 17 04:41:29 PM PDT 24 Aug 17 04:41:30 PM PDT 24 9801040 ps
T1056 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3113804866 Aug 17 04:41:16 PM PDT 24 Aug 17 04:41:26 PM PDT 24 452560897 ps
T1057 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.4036655093 Aug 17 04:41:05 PM PDT 24 Aug 17 04:41:06 PM PDT 24 13381547 ps
T1058 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2936561165 Aug 17 04:41:27 PM PDT 24 Aug 17 04:41:28 PM PDT 24 15541299 ps
T1059 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3815713797 Aug 17 04:41:24 PM PDT 24 Aug 17 04:41:25 PM PDT 24 10548922 ps
T1060 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2525825339 Aug 17 04:40:59 PM PDT 24 Aug 17 04:41:00 PM PDT 24 16404388 ps
T1061 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1656865281 Aug 17 04:41:27 PM PDT 24 Aug 17 04:41:28 PM PDT 24 10531684 ps
T1062 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1914814426 Aug 17 04:41:18 PM PDT 24 Aug 17 04:41:20 PM PDT 24 393566911 ps
T1063 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3440169415 Aug 17 04:41:32 PM PDT 24 Aug 17 04:41:32 PM PDT 24 48509575 ps
T1064 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3729431473 Aug 17 04:41:02 PM PDT 24 Aug 17 04:41:12 PM PDT 24 1789055315 ps
T154 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3267909341 Aug 17 04:41:03 PM PDT 24 Aug 17 04:41:09 PM PDT 24 165481941 ps
T1065 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2163017175 Aug 17 04:41:06 PM PDT 24 Aug 17 04:41:08 PM PDT 24 120496658 ps
T1066 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1748157388 Aug 17 04:41:00 PM PDT 24 Aug 17 04:41:01 PM PDT 24 49803221 ps
T1067 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1431287147 Aug 17 04:41:27 PM PDT 24 Aug 17 04:41:28 PM PDT 24 28007752 ps
T1068 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2864013350 Aug 17 04:40:59 PM PDT 24 Aug 17 04:41:01 PM PDT 24 105672563 ps
T1069 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.205366906 Aug 17 04:41:10 PM PDT 24 Aug 17 04:41:12 PM PDT 24 82031331 ps
T1070 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2997964636 Aug 17 04:41:18 PM PDT 24 Aug 17 04:41:19 PM PDT 24 22703958 ps
T1071 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3703815285 Aug 17 04:41:06 PM PDT 24 Aug 17 04:41:10 PM PDT 24 115703152 ps
T1072 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1131653787 Aug 17 04:41:25 PM PDT 24 Aug 17 04:41:26 PM PDT 24 13158671 ps
T1073 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2431718286 Aug 17 04:41:24 PM PDT 24 Aug 17 04:41:24 PM PDT 24 39136449 ps
T1074 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2097295933 Aug 17 04:41:26 PM PDT 24 Aug 17 04:41:27 PM PDT 24 15114761 ps
T1075 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1856716180 Aug 17 04:40:58 PM PDT 24 Aug 17 04:41:00 PM PDT 24 57944952 ps

Test location /workspace/coverage/default/20.keymgr_stress_all.917755709
Short name T3
Test name
Test status
Simulation time 10694163313 ps
CPU time 169.74 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:53:52 PM PDT 24
Peak memory 223060 kb
Host smart-199a2e4a-a681-4694-9482-865dd25ca865
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917755709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.917755709
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2731555011
Short name T60
Test name
Test status
Simulation time 4040988818 ps
CPU time 40.35 seconds
Started Aug 17 04:51:31 PM PDT 24
Finished Aug 17 04:52:12 PM PDT 24
Peak memory 223200 kb
Host smart-6ff7e556-a8a8-4fb0-a9ec-13ef115f6663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731555011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2731555011
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3330421375
Short name T77
Test name
Test status
Simulation time 426214019 ps
CPU time 11.67 seconds
Started Aug 17 04:51:07 PM PDT 24
Finished Aug 17 04:51:19 PM PDT 24
Peak memory 223016 kb
Host smart-7630c775-fa46-42fd-b2dc-980fd355dd6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330421375 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3330421375
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.3262160347
Short name T8
Test name
Test status
Simulation time 583187243 ps
CPU time 6.68 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:16 PM PDT 24
Peak memory 231932 kb
Host smart-c9fe7b26-fa32-4645-9d9c-2cd7617bef11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262160347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.3262160347
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.439465608
Short name T59
Test name
Test status
Simulation time 1502615818 ps
CPU time 31.69 seconds
Started Aug 17 04:51:01 PM PDT 24
Finished Aug 17 04:51:33 PM PDT 24
Peak memory 215948 kb
Host smart-dd5913bf-26f1-49eb-9a31-8f9153b3fd7b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439465608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.439465608
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3646156316
Short name T36
Test name
Test status
Simulation time 208302526 ps
CPU time 13.13 seconds
Started Aug 17 04:51:43 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 220872 kb
Host smart-e7fdac49-9d25-4017-bc31-2cf9a246ea90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646156316 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3646156316
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1653277920
Short name T130
Test name
Test status
Simulation time 19373546252 ps
CPU time 109.23 seconds
Started Aug 17 04:50:45 PM PDT 24
Finished Aug 17 04:52:34 PM PDT 24
Peak memory 215064 kb
Host smart-d43e4ec2-1deb-4fd9-b37d-269bdbea9576
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653277920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1653277920
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2863329701
Short name T41
Test name
Test status
Simulation time 235790174 ps
CPU time 3.55 seconds
Started Aug 17 04:51:34 PM PDT 24
Finished Aug 17 04:51:38 PM PDT 24
Peak memory 214848 kb
Host smart-1b876fe7-d2c5-4545-a562-ed0ef1f04c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863329701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2863329701
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.783140719
Short name T389
Test name
Test status
Simulation time 1539476938 ps
CPU time 21.69 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:24 PM PDT 24
Peak memory 216032 kb
Host smart-a8156228-3294-4670-979a-3476bb2e78f1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=783140719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.783140719
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3733918937
Short name T83
Test name
Test status
Simulation time 363156381 ps
CPU time 13.89 seconds
Started Aug 17 04:41:02 PM PDT 24
Finished Aug 17 04:41:16 PM PDT 24
Peak memory 220920 kb
Host smart-dcf2a0db-75b9-45dc-978d-04da6ab3c541
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733918937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3733918937
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3064637192
Short name T247
Test name
Test status
Simulation time 253909178 ps
CPU time 12.97 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:52:07 PM PDT 24
Peak memory 215488 kb
Host smart-b99537da-7a2d-4bf7-991e-f88c1ffeba33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3064637192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3064637192
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1235918832
Short name T16
Test name
Test status
Simulation time 1060807908 ps
CPU time 5.28 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 214996 kb
Host smart-b4e4820e-bda6-4dac-a66d-2285a53eaf36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235918832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1235918832
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3146861420
Short name T344
Test name
Test status
Simulation time 250840124 ps
CPU time 13.64 seconds
Started Aug 17 04:51:56 PM PDT 24
Finished Aug 17 04:52:10 PM PDT 24
Peak memory 214900 kb
Host smart-4f995606-a271-4234-ba5f-ec889d8f9994
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3146861420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3146861420
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3074802164
Short name T6
Test name
Test status
Simulation time 2116078075 ps
CPU time 28.44 seconds
Started Aug 17 04:51:57 PM PDT 24
Finished Aug 17 04:52:25 PM PDT 24
Peak memory 217148 kb
Host smart-c8122084-6ccd-4865-baab-9882954c5521
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074802164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3074802164
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3193163213
Short name T22
Test name
Test status
Simulation time 175083035 ps
CPU time 3.89 seconds
Started Aug 17 04:51:24 PM PDT 24
Finished Aug 17 04:51:28 PM PDT 24
Peak memory 214724 kb
Host smart-06535f7f-535a-42ba-ac21-0abb7f0ba719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193163213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3193163213
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2190223069
Short name T15
Test name
Test status
Simulation time 100657048 ps
CPU time 2.21 seconds
Started Aug 17 04:51:32 PM PDT 24
Finished Aug 17 04:51:34 PM PDT 24
Peak memory 210600 kb
Host smart-ed54086a-de5e-4137-a786-b9cd2eb61dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190223069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2190223069
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.813357186
Short name T143
Test name
Test status
Simulation time 426771704 ps
CPU time 6.26 seconds
Started Aug 17 04:41:08 PM PDT 24
Finished Aug 17 04:41:15 PM PDT 24
Peak memory 214352 kb
Host smart-9201b1b8-db01-4e37-b20b-666762b06896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813357186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.813357186
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.890107863
Short name T322
Test name
Test status
Simulation time 192139075 ps
CPU time 9.53 seconds
Started Aug 17 04:50:54 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 214764 kb
Host smart-fd93356f-b9a7-4961-9c93-2b5734dfec48
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=890107863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.890107863
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3661242152
Short name T134
Test name
Test status
Simulation time 5385567330 ps
CPU time 95.12 seconds
Started Aug 17 04:50:55 PM PDT 24
Finished Aug 17 04:52:30 PM PDT 24
Peak memory 216960 kb
Host smart-d5b30a4a-164c-41dc-b3e5-5f1e833ee42a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661242152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3661242152
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2935696297
Short name T410
Test name
Test status
Simulation time 898534876 ps
CPU time 12.63 seconds
Started Aug 17 04:50:20 PM PDT 24
Finished Aug 17 04:50:33 PM PDT 24
Peak memory 214764 kb
Host smart-c2873e67-03ce-47e6-ae43-64c5ac2959bb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2935696297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2935696297
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.877902913
Short name T33
Test name
Test status
Simulation time 73778100 ps
CPU time 3.87 seconds
Started Aug 17 04:52:20 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 218736 kb
Host smart-4f7fa608-e777-46d1-98f7-65f58a2df81f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877902913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.877902913
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4034076520
Short name T17
Test name
Test status
Simulation time 246572120 ps
CPU time 2.25 seconds
Started Aug 17 04:51:42 PM PDT 24
Finished Aug 17 04:51:44 PM PDT 24
Peak memory 216716 kb
Host smart-4aa7a64a-163f-46af-a45d-a40e6e70d442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034076520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4034076520
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1406481555
Short name T85
Test name
Test status
Simulation time 351820355 ps
CPU time 12.05 seconds
Started Aug 17 04:41:00 PM PDT 24
Finished Aug 17 04:41:12 PM PDT 24
Peak memory 214816 kb
Host smart-8f713679-f79e-4416-9d6d-cb4e6ddf5f08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406481555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1406481555
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1661786966
Short name T28
Test name
Test status
Simulation time 176829316 ps
CPU time 5.81 seconds
Started Aug 17 04:50:25 PM PDT 24
Finished Aug 17 04:50:31 PM PDT 24
Peak memory 220560 kb
Host smart-a17aa598-5d7b-48f7-801b-740d31002770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661786966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1661786966
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1091442003
Short name T116
Test name
Test status
Simulation time 35013609 ps
CPU time 2.4 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 218052 kb
Host smart-e7298f09-9ecd-4cbe-a432-f5329ef1eaaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091442003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1091442003
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3979014289
Short name T50
Test name
Test status
Simulation time 207003214 ps
CPU time 4.82 seconds
Started Aug 17 04:51:38 PM PDT 24
Finished Aug 17 04:51:43 PM PDT 24
Peak memory 209192 kb
Host smart-406ca03a-288b-4f13-a24c-928b9fd11afe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979014289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3979014289
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3626695566
Short name T137
Test name
Test status
Simulation time 5796772788 ps
CPU time 56.35 seconds
Started Aug 17 04:50:51 PM PDT 24
Finished Aug 17 04:51:48 PM PDT 24
Peak memory 216524 kb
Host smart-66cf4f91-0256-4824-800e-0df15bbec7da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626695566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3626695566
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1348178236
Short name T280
Test name
Test status
Simulation time 2319352981 ps
CPU time 9.23 seconds
Started Aug 17 04:51:59 PM PDT 24
Finished Aug 17 04:52:08 PM PDT 24
Peak memory 216244 kb
Host smart-5a9cf210-cf7c-453a-bb9f-6aa30217f32d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1348178236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1348178236
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.4218093348
Short name T205
Test name
Test status
Simulation time 3721147320 ps
CPU time 41.7 seconds
Started Aug 17 04:51:01 PM PDT 24
Finished Aug 17 04:51:43 PM PDT 24
Peak memory 216224 kb
Host smart-4dd8aa0b-8d2c-4a6a-b3d7-35fc20a5a6f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218093348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4218093348
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2902540684
Short name T413
Test name
Test status
Simulation time 680376580 ps
CPU time 10.2 seconds
Started Aug 17 04:50:55 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 214708 kb
Host smart-336f6769-78ee-4191-b173-9332a21bee7a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2902540684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2902540684
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2568633386
Short name T90
Test name
Test status
Simulation time 1044422090 ps
CPU time 17.18 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:52:08 PM PDT 24
Peak memory 223056 kb
Host smart-b5f85246-bd45-4b28-8d30-4e051fd91481
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568633386 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2568633386
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3885327913
Short name T388
Test name
Test status
Simulation time 2293217079 ps
CPU time 31 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:34 PM PDT 24
Peak memory 215876 kb
Host smart-0aeca73f-0975-4be4-9ba9-993e79a3716d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3885327913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3885327913
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2005152802
Short name T416
Test name
Test status
Simulation time 14006539 ps
CPU time 0.91 seconds
Started Aug 17 04:50:45 PM PDT 24
Finished Aug 17 04:50:46 PM PDT 24
Peak memory 206468 kb
Host smart-c3a8ba1c-f0b3-4218-9843-304899fd2296
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005152802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2005152802
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.4263995516
Short name T207
Test name
Test status
Simulation time 822257614 ps
CPU time 38.24 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:49 PM PDT 24
Peak memory 216992 kb
Host smart-c18559e6-32d3-4e41-b5e4-d91a1e1d2b15
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263995516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.4263995516
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2280858317
Short name T125
Test name
Test status
Simulation time 8670254612 ps
CPU time 106.84 seconds
Started Aug 17 04:52:37 PM PDT 24
Finished Aug 17 04:54:24 PM PDT 24
Peak memory 217668 kb
Host smart-f8e525c1-fd5e-499a-bf68-63a01af0b4a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2280858317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2280858317
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.427544258
Short name T113
Test name
Test status
Simulation time 271496386 ps
CPU time 4.52 seconds
Started Aug 17 04:51:43 PM PDT 24
Finished Aug 17 04:51:48 PM PDT 24
Peak memory 215964 kb
Host smart-23cd1985-d2ce-4d01-be7d-1865e00fe004
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=427544258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.427544258
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2979432394
Short name T318
Test name
Test status
Simulation time 734438949 ps
CPU time 4.28 seconds
Started Aug 17 04:51:48 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 222856 kb
Host smart-552d5e1a-c8b2-4446-9207-9aaa408c6b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979432394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2979432394
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1316687529
Short name T610
Test name
Test status
Simulation time 255551578 ps
CPU time 3.13 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 210244 kb
Host smart-1acb4d86-e607-4d40-b9c5-e243faf4d8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316687529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1316687529
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.4227218600
Short name T214
Test name
Test status
Simulation time 3246148811 ps
CPU time 52.57 seconds
Started Aug 17 04:50:56 PM PDT 24
Finished Aug 17 04:51:48 PM PDT 24
Peak memory 222936 kb
Host smart-26a7f47a-6723-4ef1-8249-6f1b7c651963
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227218600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.4227218600
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3106711731
Short name T102
Test name
Test status
Simulation time 372870593 ps
CPU time 4.82 seconds
Started Aug 17 04:52:17 PM PDT 24
Finished Aug 17 04:52:22 PM PDT 24
Peak memory 214676 kb
Host smart-a5acdb1c-95a1-42f5-b41b-a7d6a5e4eec6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3106711731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3106711731
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.275108148
Short name T114
Test name
Test status
Simulation time 174139581 ps
CPU time 2.66 seconds
Started Aug 17 04:51:05 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 223124 kb
Host smart-f9098156-1f79-4636-9cff-17d828e84b74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275108148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.275108148
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1490078605
Short name T395
Test name
Test status
Simulation time 863441534 ps
CPU time 8.49 seconds
Started Aug 17 04:50:55 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 214728 kb
Host smart-48fcf25b-e082-43a9-bf2a-d52e3b2a2f91
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1490078605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1490078605
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.143942943
Short name T42
Test name
Test status
Simulation time 193489906 ps
CPU time 3.41 seconds
Started Aug 17 04:51:49 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 222848 kb
Host smart-1539e45f-d851-46e0-b35d-a7642113216c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143942943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.143942943
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1582107077
Short name T235
Test name
Test status
Simulation time 573779889 ps
CPU time 4.34 seconds
Started Aug 17 04:52:14 PM PDT 24
Finished Aug 17 04:52:18 PM PDT 24
Peak memory 214640 kb
Host smart-615ab5bd-a845-45ec-801a-b5390c6ec861
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1582107077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1582107077
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.412955892
Short name T306
Test name
Test status
Simulation time 6292175474 ps
CPU time 61.13 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:52:59 PM PDT 24
Peak memory 218068 kb
Host smart-bd993482-584a-4c5d-9ca2-11f3256e32dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412955892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.412955892
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.344361953
Short name T148
Test name
Test status
Simulation time 248545669 ps
CPU time 9.66 seconds
Started Aug 17 04:41:12 PM PDT 24
Finished Aug 17 04:41:22 PM PDT 24
Peak memory 214476 kb
Host smart-217632d1-60a2-4aa4-ac38-06c132a53bfc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344361953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.344361953
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2448046049
Short name T144
Test name
Test status
Simulation time 529426205 ps
CPU time 9.52 seconds
Started Aug 17 04:41:03 PM PDT 24
Finished Aug 17 04:41:13 PM PDT 24
Peak memory 217144 kb
Host smart-5baee401-1f33-4629-a056-c78a199aefd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448046049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2448046049
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1748327253
Short name T155
Test name
Test status
Simulation time 180890712 ps
CPU time 5.45 seconds
Started Aug 17 04:41:15 PM PDT 24
Finished Aug 17 04:41:21 PM PDT 24
Peak memory 214480 kb
Host smart-14855f8d-26f9-4fd4-92d2-b5f57cdb2b0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748327253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1748327253
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2793399947
Short name T169
Test name
Test status
Simulation time 1142629204 ps
CPU time 3.3 seconds
Started Aug 17 04:50:00 PM PDT 24
Finished Aug 17 04:50:03 PM PDT 24
Peak memory 214744 kb
Host smart-8e6e32b0-b819-445c-a73c-9ba45da0356d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793399947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2793399947
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1675557312
Short name T254
Test name
Test status
Simulation time 102728821 ps
CPU time 2.01 seconds
Started Aug 17 04:52:01 PM PDT 24
Finished Aug 17 04:52:03 PM PDT 24
Peak memory 214656 kb
Host smart-f04fa24a-1985-4930-b8bf-afa5b17bcfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675557312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1675557312
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.669642072
Short name T375
Test name
Test status
Simulation time 886452911 ps
CPU time 4.66 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 211248 kb
Host smart-1aac0e01-6409-4179-91eb-c9d9e0e2bd8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669642072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.669642072
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1042061622
Short name T150
Test name
Test status
Simulation time 1046721840 ps
CPU time 10.42 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:27 PM PDT 24
Peak memory 216864 kb
Host smart-91403134-62c1-4ad7-a0da-7e4ee1b5d9ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042061622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1042061622
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2235864506
Short name T146
Test name
Test status
Simulation time 448152065 ps
CPU time 5.1 seconds
Started Aug 17 04:41:25 PM PDT 24
Finished Aug 17 04:41:30 PM PDT 24
Peak memory 216064 kb
Host smart-c6f71f40-c520-4be8-b3d6-ed7c6e4f1b26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235864506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2235864506
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3267909341
Short name T154
Test name
Test status
Simulation time 165481941 ps
CPU time 6.13 seconds
Started Aug 17 04:41:03 PM PDT 24
Finished Aug 17 04:41:09 PM PDT 24
Peak memory 214660 kb
Host smart-8993fc60-c711-4122-8d3e-fd04a847561a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267909341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3267909341
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.18371025
Short name T115
Test name
Test status
Simulation time 488078346 ps
CPU time 3.61 seconds
Started Aug 17 04:51:20 PM PDT 24
Finished Aug 17 04:51:24 PM PDT 24
Peak memory 218744 kb
Host smart-a96a1e25-ba82-4ecb-806a-f440b320233a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18371025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.18371025
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1948441290
Short name T122
Test name
Test status
Simulation time 310232443 ps
CPU time 5.35 seconds
Started Aug 17 04:52:32 PM PDT 24
Finished Aug 17 04:52:38 PM PDT 24
Peak memory 218824 kb
Host smart-7bd40e2e-1096-4469-869a-d740bfb13249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948441290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1948441290
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.4251307666
Short name T21
Test name
Test status
Simulation time 496071516 ps
CPU time 5.81 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 222796 kb
Host smart-f758a68f-0a6f-4d40-8878-e42b18d794dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251307666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.4251307666
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2254517173
Short name T290
Test name
Test status
Simulation time 139551337 ps
CPU time 3.42 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:50:54 PM PDT 24
Peak memory 214740 kb
Host smart-053d181a-7e1b-4ed6-902d-d7c9aa93ea84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254517173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2254517173
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2659104171
Short name T79
Test name
Test status
Simulation time 53445526 ps
CPU time 3.91 seconds
Started Aug 17 04:51:34 PM PDT 24
Finished Aug 17 04:51:38 PM PDT 24
Peak memory 215588 kb
Host smart-5f345eda-4716-4b80-a11b-5452f10aca18
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2659104171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2659104171
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.4106704179
Short name T316
Test name
Test status
Simulation time 127837311 ps
CPU time 3.23 seconds
Started Aug 17 04:51:42 PM PDT 24
Finished Aug 17 04:51:45 PM PDT 24
Peak memory 214692 kb
Host smart-4cf0bfab-8c93-4332-8f31-2009b34e34db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106704179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.4106704179
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2786657828
Short name T219
Test name
Test status
Simulation time 2160209272 ps
CPU time 43.77 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:52:37 PM PDT 24
Peak memory 221468 kb
Host smart-6147e930-8f37-4218-896b-df90c9ea9406
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786657828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2786657828
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2761553047
Short name T257
Test name
Test status
Simulation time 442966383 ps
CPU time 3.91 seconds
Started Aug 17 04:52:24 PM PDT 24
Finished Aug 17 04:52:28 PM PDT 24
Peak memory 214644 kb
Host smart-66f0595c-c65e-4825-ad44-e97f68240693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761553047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2761553047
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.687335486
Short name T299
Test name
Test status
Simulation time 437960279 ps
CPU time 4.23 seconds
Started Aug 17 04:50:40 PM PDT 24
Finished Aug 17 04:50:45 PM PDT 24
Peak memory 209424 kb
Host smart-2d18ae45-c568-4701-83f8-6cad3e406c02
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687335486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.687335486
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1862984246
Short name T120
Test name
Test status
Simulation time 83771817 ps
CPU time 2.18 seconds
Started Aug 17 04:51:07 PM PDT 24
Finished Aug 17 04:51:09 PM PDT 24
Peak memory 217660 kb
Host smart-a937f3ec-d631-4aba-ab49-71fb7e1f0086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862984246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1862984246
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3159504664
Short name T119
Test name
Test status
Simulation time 190013157 ps
CPU time 4.97 seconds
Started Aug 17 04:50:33 PM PDT 24
Finished Aug 17 04:50:38 PM PDT 24
Peak memory 223120 kb
Host smart-04431720-3366-485c-ad86-570db24967e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159504664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3159504664
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.4074406813
Short name T118
Test name
Test status
Simulation time 174657959 ps
CPU time 2.43 seconds
Started Aug 17 04:50:34 PM PDT 24
Finished Aug 17 04:50:36 PM PDT 24
Peak memory 218012 kb
Host smart-5b7b91c4-53dc-4018-8fe8-a04c5be9d132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074406813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.4074406813
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1888841986
Short name T279
Test name
Test status
Simulation time 36581713 ps
CPU time 2.52 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 208936 kb
Host smart-e9b260ed-6f24-4554-88dc-20edcf139794
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888841986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1888841986
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2657245161
Short name T309
Test name
Test status
Simulation time 234972031 ps
CPU time 2.91 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 207420 kb
Host smart-c004d688-d848-4184-8b5e-0b9c3450f6ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657245161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2657245161
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2258078096
Short name T302
Test name
Test status
Simulation time 3437550974 ps
CPU time 52.1 seconds
Started Aug 17 04:51:13 PM PDT 24
Finished Aug 17 04:52:05 PM PDT 24
Peak memory 214800 kb
Host smart-77efd08b-77a9-4a16-8fe4-8905caa71ef8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2258078096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2258078096
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2644901859
Short name T165
Test name
Test status
Simulation time 314124444 ps
CPU time 7.57 seconds
Started Aug 17 04:51:30 PM PDT 24
Finished Aug 17 04:51:42 PM PDT 24
Peak memory 222936 kb
Host smart-355919cf-8edc-47ec-a828-a0eb5ff3b919
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644901859 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2644901859
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3381833344
Short name T243
Test name
Test status
Simulation time 256905452 ps
CPU time 2.38 seconds
Started Aug 17 04:51:43 PM PDT 24
Finished Aug 17 04:51:45 PM PDT 24
Peak memory 215124 kb
Host smart-c913f09d-86a2-4114-96fe-47549456a710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381833344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3381833344
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3791315720
Short name T394
Test name
Test status
Simulation time 814637915 ps
CPU time 11.39 seconds
Started Aug 17 04:51:52 PM PDT 24
Finished Aug 17 04:52:04 PM PDT 24
Peak memory 215816 kb
Host smart-5024b860-a987-459b-9319-3d2cff62ee19
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3791315720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3791315720
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3936965511
Short name T181
Test name
Test status
Simulation time 472885878 ps
CPU time 6.52 seconds
Started Aug 17 04:52:25 PM PDT 24
Finished Aug 17 04:52:32 PM PDT 24
Peak memory 209356 kb
Host smart-d88759ce-c437-4ea4-9621-4f9bb571a337
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936965511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3936965511
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2324453057
Short name T867
Test name
Test status
Simulation time 11294035836 ps
CPU time 28.61 seconds
Started Aug 17 04:52:10 PM PDT 24
Finished Aug 17 04:52:39 PM PDT 24
Peak memory 222140 kb
Host smart-a19c38ad-6b51-44a6-af9c-b2546f5271cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324453057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2324453057
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.2288416780
Short name T89
Test name
Test status
Simulation time 332982613 ps
CPU time 16.05 seconds
Started Aug 17 04:52:25 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 223000 kb
Host smart-744917df-a4c9-4c16-b3ac-e60b3f4e5774
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288416780 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.2288416780
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3672932542
Short name T156
Test name
Test status
Simulation time 232319624 ps
CPU time 4.57 seconds
Started Aug 17 04:41:08 PM PDT 24
Finished Aug 17 04:41:13 PM PDT 24
Peak memory 206540 kb
Host smart-b6995ecb-7824-47fe-a34b-817eca878053
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672932542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3672932542
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4118648109
Short name T9
Test name
Test status
Simulation time 2771504423 ps
CPU time 9.36 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:18 PM PDT 24
Peak memory 232012 kb
Host smart-c9ccb6e6-1d99-435e-a421-aaea45ae33ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118648109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4118648109
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1925308603
Short name T55
Test name
Test status
Simulation time 159297050 ps
CPU time 3.11 seconds
Started Aug 17 04:50:42 PM PDT 24
Finished Aug 17 04:50:45 PM PDT 24
Peak memory 210900 kb
Host smart-fcbaa902-1045-449d-b0f9-31bd916f354f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925308603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1925308603
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.4216196651
Short name T47
Test name
Test status
Simulation time 108744660 ps
CPU time 2.51 seconds
Started Aug 17 04:50:36 PM PDT 24
Finished Aug 17 04:50:39 PM PDT 24
Peak memory 221508 kb
Host smart-094f2df4-7e4d-4580-abeb-afa337ee5130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216196651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.4216196651
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1296785329
Short name T112
Test name
Test status
Simulation time 63838346 ps
CPU time 2.52 seconds
Started Aug 17 04:50:52 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 217244 kb
Host smart-bf8c5b3d-1480-47e5-a844-bd461ff3b5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296785329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1296785329
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.4100091430
Short name T121
Test name
Test status
Simulation time 164754154 ps
CPU time 3.31 seconds
Started Aug 17 04:51:48 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 218480 kb
Host smart-1f2f94c0-43e4-4387-b69c-ec1d4b7a383b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100091430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.4100091430
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1200885570
Short name T149
Test name
Test status
Simulation time 131600809 ps
CPU time 5.38 seconds
Started Aug 17 04:41:14 PM PDT 24
Finished Aug 17 04:41:19 PM PDT 24
Peak memory 214456 kb
Host smart-bb6747de-4d79-46d1-811a-2d6f5fbf9b26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200885570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1200885570
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.703038280
Short name T489
Test name
Test status
Simulation time 102822083 ps
CPU time 2.86 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 207352 kb
Host smart-e42fb513-5ed5-41eb-a794-ae96d1db207e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703038280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.703038280
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.201057825
Short name T334
Test name
Test status
Simulation time 705009633 ps
CPU time 5.4 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 214692 kb
Host smart-1de48b1c-2931-4593-8055-efc1bef75d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201057825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.201057825
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1199952673
Short name T620
Test name
Test status
Simulation time 1828511407 ps
CPU time 5.22 seconds
Started Aug 17 04:50:51 PM PDT 24
Finished Aug 17 04:50:57 PM PDT 24
Peak memory 208376 kb
Host smart-eceae015-f692-44a2-a978-4c6f90364e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199952673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1199952673
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.348065795
Short name T231
Test name
Test status
Simulation time 203720458 ps
CPU time 3.73 seconds
Started Aug 17 04:50:48 PM PDT 24
Finished Aug 17 04:50:52 PM PDT 24
Peak memory 210352 kb
Host smart-2771ab9b-fce0-4d54-887b-06d12361b24f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348065795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.348065795
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1752847770
Short name T190
Test name
Test status
Simulation time 237230777 ps
CPU time 4.25 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:51:01 PM PDT 24
Peak memory 208068 kb
Host smart-5544c183-e36c-4d6e-a67c-38494924ba71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752847770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1752847770
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3315162145
Short name T204
Test name
Test status
Simulation time 282073165 ps
CPU time 3.39 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:13 PM PDT 24
Peak memory 219160 kb
Host smart-2aa15ee8-360a-4cc2-a3d6-06b24cccd077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315162145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3315162145
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2949541236
Short name T222
Test name
Test status
Simulation time 1915848020 ps
CPU time 3.91 seconds
Started Aug 17 04:51:20 PM PDT 24
Finished Aug 17 04:51:24 PM PDT 24
Peak memory 218836 kb
Host smart-1ed0ae1b-9d94-4818-977f-5863328149b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949541236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2949541236
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1628530868
Short name T234
Test name
Test status
Simulation time 111221520 ps
CPU time 3.81 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 215928 kb
Host smart-d28d5b2b-f652-40a3-9e6a-a845f5323991
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1628530868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1628530868
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.451017954
Short name T225
Test name
Test status
Simulation time 2618208025 ps
CPU time 26.77 seconds
Started Aug 17 04:51:31 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 223040 kb
Host smart-04d3bb64-b2f6-4193-a259-384a81692080
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451017954 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.451017954
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1626024418
Short name T866
Test name
Test status
Simulation time 77713051 ps
CPU time 3.78 seconds
Started Aug 17 04:51:37 PM PDT 24
Finished Aug 17 04:51:41 PM PDT 24
Peak memory 209440 kb
Host smart-d2ea9175-cd31-42aa-9cda-c5f2fcc69d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626024418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1626024418
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1295337659
Short name T99
Test name
Test status
Simulation time 318188437 ps
CPU time 2.91 seconds
Started Aug 17 04:51:37 PM PDT 24
Finished Aug 17 04:51:40 PM PDT 24
Peak memory 214680 kb
Host smart-9ab48ccb-1e02-4dcf-9661-1e342b2bdee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295337659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1295337659
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2962455597
Short name T367
Test name
Test status
Simulation time 485346180 ps
CPU time 5.94 seconds
Started Aug 17 04:51:37 PM PDT 24
Finished Aug 17 04:51:43 PM PDT 24
Peak memory 214736 kb
Host smart-23092f97-2065-4000-b87c-88eb18892fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962455597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2962455597
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.2695665770
Short name T278
Test name
Test status
Simulation time 75093945 ps
CPU time 4.61 seconds
Started Aug 17 04:50:12 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 215652 kb
Host smart-79e4518a-d778-4a68-bb77-9a2ac686e3ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2695665770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.2695665770
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2808717566
Short name T203
Test name
Test status
Simulation time 88463237 ps
CPU time 3.29 seconds
Started Aug 17 04:52:21 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 223244 kb
Host smart-f41cf148-ad7c-411d-acaa-ee1126e8c32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808717566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2808717566
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.171980121
Short name T208
Test name
Test status
Simulation time 755197014 ps
CPU time 5.26 seconds
Started Aug 17 04:50:34 PM PDT 24
Finished Aug 17 04:50:40 PM PDT 24
Peak memory 223052 kb
Host smart-ac23b39a-47e3-475a-8be6-4724a6e1de42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171980121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.171980121
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3107896465
Short name T335
Test name
Test status
Simulation time 80673534 ps
CPU time 1.92 seconds
Started Aug 17 04:50:33 PM PDT 24
Finished Aug 17 04:50:35 PM PDT 24
Peak memory 214668 kb
Host smart-cc1e5e0f-3ebc-47f5-828c-79993339b1ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107896465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3107896465
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.149720599
Short name T1041
Test name
Test status
Simulation time 3960837958 ps
CPU time 11.86 seconds
Started Aug 17 04:41:02 PM PDT 24
Finished Aug 17 04:41:14 PM PDT 24
Peak memory 206376 kb
Host smart-0c001e70-199a-4646-a451-5af3d9b6d670
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149720599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.149720599
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1314275262
Short name T1033
Test name
Test status
Simulation time 499396114 ps
CPU time 14.28 seconds
Started Aug 17 04:40:59 PM PDT 24
Finished Aug 17 04:41:13 PM PDT 24
Peak memory 206196 kb
Host smart-f9af8e96-0907-40a6-bce6-38086813aa09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314275262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
314275262
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3934701805
Short name T907
Test name
Test status
Simulation time 54937289 ps
CPU time 1.15 seconds
Started Aug 17 04:41:05 PM PDT 24
Finished Aug 17 04:41:06 PM PDT 24
Peak memory 206120 kb
Host smart-80cdf85f-11af-427a-a23a-0dcabdf89d52
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934701805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
934701805
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3331837513
Short name T974
Test name
Test status
Simulation time 52157887 ps
CPU time 1.76 seconds
Started Aug 17 04:41:04 PM PDT 24
Finished Aug 17 04:41:06 PM PDT 24
Peak memory 214520 kb
Host smart-9a1b0bc1-7d2c-4386-a77b-a28233d1dd59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331837513 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3331837513
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2219002911
Short name T110
Test name
Test status
Simulation time 64257783 ps
CPU time 0.95 seconds
Started Aug 17 04:41:02 PM PDT 24
Finished Aug 17 04:41:04 PM PDT 24
Peak memory 206104 kb
Host smart-2adc1c37-0981-4ba4-829f-d84439671423
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219002911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2219002911
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3844276764
Short name T951
Test name
Test status
Simulation time 13470243 ps
CPU time 0.75 seconds
Started Aug 17 04:41:05 PM PDT 24
Finished Aug 17 04:41:06 PM PDT 24
Peak memory 206040 kb
Host smart-aa638909-2fd0-4933-ac16-fccd95a3303e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844276764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3844276764
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2414050648
Short name T1000
Test name
Test status
Simulation time 122086080 ps
CPU time 4.32 seconds
Started Aug 17 04:41:05 PM PDT 24
Finished Aug 17 04:41:09 PM PDT 24
Peak memory 206260 kb
Host smart-04779bf8-9698-49c6-b061-e9cd02976e22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414050648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2414050648
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3742060155
Short name T1031
Test name
Test status
Simulation time 293013052 ps
CPU time 1.84 seconds
Started Aug 17 04:40:58 PM PDT 24
Finished Aug 17 04:41:00 PM PDT 24
Peak memory 214880 kb
Host smart-bdc52e45-da2c-4f5b-ba2b-981ef441a0fa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742060155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3742060155
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1061196808
Short name T86
Test name
Test status
Simulation time 825502100 ps
CPU time 9.36 seconds
Started Aug 17 04:41:00 PM PDT 24
Finished Aug 17 04:41:09 PM PDT 24
Peak memory 214832 kb
Host smart-9a3dd95f-1e19-4b11-817f-85f392399390
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061196808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1061196808
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2426522299
Short name T927
Test name
Test status
Simulation time 145521280 ps
CPU time 1.85 seconds
Started Aug 17 04:41:05 PM PDT 24
Finished Aug 17 04:41:07 PM PDT 24
Peak memory 206312 kb
Host smart-e573c723-0dc4-4493-99ed-ddf42b6538ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426522299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2426522299
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3824932590
Short name T376
Test name
Test status
Simulation time 62364671 ps
CPU time 2.59 seconds
Started Aug 17 04:40:57 PM PDT 24
Finished Aug 17 04:41:00 PM PDT 24
Peak memory 214536 kb
Host smart-55f70f1e-2dc4-4d6e-a1a5-4c2f8934c95b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824932590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3824932590
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1743464283
Short name T945
Test name
Test status
Simulation time 4147882353 ps
CPU time 7.57 seconds
Started Aug 17 04:41:00 PM PDT 24
Finished Aug 17 04:41:08 PM PDT 24
Peak memory 206368 kb
Host smart-923fef67-aa77-4c79-941a-3c174a6d7651
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743464283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
743464283
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2764195632
Short name T1001
Test name
Test status
Simulation time 139664339 ps
CPU time 6.58 seconds
Started Aug 17 04:41:05 PM PDT 24
Finished Aug 17 04:41:12 PM PDT 24
Peak memory 206236 kb
Host smart-78db2b59-e801-42f9-b638-ac94fdd5abc1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764195632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
764195632
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3543652631
Short name T977
Test name
Test status
Simulation time 22545660 ps
CPU time 0.91 seconds
Started Aug 17 04:41:01 PM PDT 24
Finished Aug 17 04:41:02 PM PDT 24
Peak memory 206076 kb
Host smart-03ca0520-2632-41f0-a948-4ebcaa4732d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543652631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
543652631
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.205366906
Short name T1069
Test name
Test status
Simulation time 82031331 ps
CPU time 2.36 seconds
Started Aug 17 04:41:10 PM PDT 24
Finished Aug 17 04:41:12 PM PDT 24
Peak memory 214616 kb
Host smart-72f6b90d-1ebe-4531-9102-d122505c1bae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205366906 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.205366906
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2525825339
Short name T1060
Test name
Test status
Simulation time 16404388 ps
CPU time 1.21 seconds
Started Aug 17 04:40:59 PM PDT 24
Finished Aug 17 04:41:00 PM PDT 24
Peak memory 206324 kb
Host smart-34340eaf-f222-4ce8-990e-415a6747fd6a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525825339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2525825339
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2365756376
Short name T1040
Test name
Test status
Simulation time 15377042 ps
CPU time 0.7 seconds
Started Aug 17 04:41:01 PM PDT 24
Finished Aug 17 04:41:01 PM PDT 24
Peak memory 205972 kb
Host smart-10628bb3-aa7b-46a4-a57c-59823c3d010a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365756376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2365756376
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1448229196
Short name T978
Test name
Test status
Simulation time 352184397 ps
CPU time 2.38 seconds
Started Aug 17 04:41:11 PM PDT 24
Finished Aug 17 04:41:13 PM PDT 24
Peak memory 206212 kb
Host smart-fc97a1e8-1c98-45c8-9d7a-b03317d57658
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448229196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1448229196
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.1856716180
Short name T1075
Test name
Test status
Simulation time 57944952 ps
CPU time 1.7 seconds
Started Aug 17 04:40:58 PM PDT 24
Finished Aug 17 04:41:00 PM PDT 24
Peak memory 214800 kb
Host smart-4197dd90-c9ad-49fb-b52b-0bed93bcce3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856716180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.1856716180
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3729431473
Short name T1064
Test name
Test status
Simulation time 1789055315 ps
CPU time 9.81 seconds
Started Aug 17 04:41:02 PM PDT 24
Finished Aug 17 04:41:12 PM PDT 24
Peak memory 222964 kb
Host smart-b9f9eccf-b162-44ab-846c-a3c85710e4cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729431473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3729431473
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.616740943
Short name T1024
Test name
Test status
Simulation time 79489251 ps
CPU time 1.85 seconds
Started Aug 17 04:41:13 PM PDT 24
Finished Aug 17 04:41:15 PM PDT 24
Peak memory 214480 kb
Host smart-841eccea-8d93-481f-8ec7-eb07b8161df5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616740943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.616740943
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.844527715
Short name T913
Test name
Test status
Simulation time 92881472 ps
CPU time 1.75 seconds
Started Aug 17 04:41:04 PM PDT 24
Finished Aug 17 04:41:06 PM PDT 24
Peak memory 214516 kb
Host smart-549769aa-fa6f-4dbd-a7e0-f879b058d67f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844527715 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.844527715
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1333940966
Short name T985
Test name
Test status
Simulation time 59164165 ps
CPU time 1.05 seconds
Started Aug 17 04:41:15 PM PDT 24
Finished Aug 17 04:41:16 PM PDT 24
Peak memory 206232 kb
Host smart-d41a969c-e0df-4bff-b3b6-4d9df3ffe301
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333940966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1333940966
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2446292102
Short name T967
Test name
Test status
Simulation time 213621908 ps
CPU time 0.95 seconds
Started Aug 17 04:41:15 PM PDT 24
Finished Aug 17 04:41:16 PM PDT 24
Peak memory 206116 kb
Host smart-e77fe97b-7da4-43b0-ab8e-7aed53192c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446292102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2446292102
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2225744631
Short name T920
Test name
Test status
Simulation time 34585441 ps
CPU time 2.7 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:20 PM PDT 24
Peak memory 206304 kb
Host smart-4019b664-5eb0-4250-8c07-01729eaa9fd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225744631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2225744631
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3110906255
Short name T1005
Test name
Test status
Simulation time 740256638 ps
CPU time 3.76 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:22 PM PDT 24
Peak memory 214816 kb
Host smart-810278e4-2d90-43c6-8ff4-7733ae9b13b2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110906255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3110906255
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.446376797
Short name T953
Test name
Test status
Simulation time 239104356 ps
CPU time 5.51 seconds
Started Aug 17 04:41:12 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 214716 kb
Host smart-266f938a-1aac-4c96-ad39-d666490fd818
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446376797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.446376797
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.680938884
Short name T1003
Test name
Test status
Simulation time 79511308 ps
CPU time 3.26 seconds
Started Aug 17 04:41:15 PM PDT 24
Finished Aug 17 04:41:19 PM PDT 24
Peak memory 217564 kb
Host smart-7ea564ed-fe20-4dfe-adcb-1722011181d1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680938884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.680938884
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2993209050
Short name T959
Test name
Test status
Simulation time 452220229 ps
CPU time 1.15 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:17 PM PDT 24
Peak memory 214500 kb
Host smart-a4651a1a-f02c-4d1f-82c5-c8e1a0c51df3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993209050 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2993209050
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1519990395
Short name T106
Test name
Test status
Simulation time 26553517 ps
CPU time 1.22 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 206244 kb
Host smart-1698c375-7a69-4111-9dc1-0ce0af151ac7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519990395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1519990395
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2065209874
Short name T972
Test name
Test status
Simulation time 11155580 ps
CPU time 0.68 seconds
Started Aug 17 04:41:04 PM PDT 24
Finished Aug 17 04:41:05 PM PDT 24
Peak memory 206000 kb
Host smart-148856de-d2a2-4471-989f-d3a96a17a7c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065209874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2065209874
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.727428373
Short name T966
Test name
Test status
Simulation time 182383244 ps
CPU time 3.68 seconds
Started Aug 17 04:41:14 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 206196 kb
Host smart-6c8daf66-8d88-4223-bdd3-2e302f783e36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727428373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.727428373
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2415532825
Short name T82
Test name
Test status
Simulation time 121313733 ps
CPU time 2.97 seconds
Started Aug 17 04:41:06 PM PDT 24
Finished Aug 17 04:41:09 PM PDT 24
Peak memory 214728 kb
Host smart-afe09dc7-b5b6-4718-80cb-47f80db5a032
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415532825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2415532825
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3819716481
Short name T989
Test name
Test status
Simulation time 230863400 ps
CPU time 8.28 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:25 PM PDT 24
Peak memory 220456 kb
Host smart-4cba9352-0586-4ffb-9b46-d86a10a2cf30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819716481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3819716481
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2174366482
Short name T958
Test name
Test status
Simulation time 58187758 ps
CPU time 2.26 seconds
Started Aug 17 04:41:08 PM PDT 24
Finished Aug 17 04:41:10 PM PDT 24
Peak memory 214564 kb
Host smart-ab75264d-188e-4fa9-b52b-94490b71c28f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174366482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2174366482
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.380971046
Short name T909
Test name
Test status
Simulation time 178454859 ps
CPU time 1.62 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:19 PM PDT 24
Peak memory 214556 kb
Host smart-bb095150-903a-4fa0-a395-de9ba7065194
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380971046 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.380971046
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.252294933
Short name T996
Test name
Test status
Simulation time 35538452 ps
CPU time 1.17 seconds
Started Aug 17 04:41:20 PM PDT 24
Finished Aug 17 04:41:21 PM PDT 24
Peak memory 206144 kb
Host smart-dd3104e6-3434-4652-83e0-f982d1f46af5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252294933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.252294933
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3708561650
Short name T906
Test name
Test status
Simulation time 39744008 ps
CPU time 0.8 seconds
Started Aug 17 04:41:20 PM PDT 24
Finished Aug 17 04:41:21 PM PDT 24
Peak memory 205940 kb
Host smart-382be41f-0ef2-41cc-943b-fec00fc3ba2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708561650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3708561650
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1914814426
Short name T1062
Test name
Test status
Simulation time 393566911 ps
CPU time 2.45 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:20 PM PDT 24
Peak memory 206256 kb
Host smart-736ca704-5941-47d4-acad-7aba26afca0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914814426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1914814426
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2646441118
Short name T1006
Test name
Test status
Simulation time 100215183 ps
CPU time 2.25 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 214768 kb
Host smart-4879a123-2172-4da6-ad5e-a887d557390c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646441118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2646441118
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3113804866
Short name T1056
Test name
Test status
Simulation time 452560897 ps
CPU time 9.44 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:26 PM PDT 24
Peak memory 221200 kb
Host smart-7cb586a4-3bad-4dc1-9840-ffc0a6047297
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113804866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3113804866
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2273929805
Short name T926
Test name
Test status
Simulation time 45689457 ps
CPU time 2.61 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:21 PM PDT 24
Peak memory 214612 kb
Host smart-bdda610b-636c-4073-b0c8-81c3d25d42e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273929805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2273929805
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1327656726
Short name T969
Test name
Test status
Simulation time 367853137 ps
CPU time 3.11 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:22 PM PDT 24
Peak memory 215516 kb
Host smart-bb4213b7-ec73-402c-b925-f9c1cf3adff6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327656726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1327656726
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3953721094
Short name T923
Test name
Test status
Simulation time 141547084 ps
CPU time 1.67 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 214596 kb
Host smart-3e34eee0-c913-4ad3-99df-b81ee7baac13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953721094 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3953721094
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1593571865
Short name T1045
Test name
Test status
Simulation time 18552758 ps
CPU time 0.85 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:17 PM PDT 24
Peak memory 206056 kb
Host smart-8fe6d26d-48bd-4b60-9e35-e40021af4df8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593571865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1593571865
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2614908087
Short name T943
Test name
Test status
Simulation time 49053874 ps
CPU time 0.85 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:19 PM PDT 24
Peak memory 206000 kb
Host smart-1ad184bb-788d-4e32-923c-af717a363f6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614908087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2614908087
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1718607712
Short name T949
Test name
Test status
Simulation time 52890107 ps
CPU time 2.47 seconds
Started Aug 17 04:41:23 PM PDT 24
Finished Aug 17 04:41:26 PM PDT 24
Peak memory 206336 kb
Host smart-9cf840e1-92ee-43d2-80ce-9be4df0d1a83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718607712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1718607712
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3253710794
Short name T1019
Test name
Test status
Simulation time 466122374 ps
CPU time 3.9 seconds
Started Aug 17 04:41:14 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 214800 kb
Host smart-df670212-824d-48ce-b3d1-00edb5acf788
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253710794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3253710794
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2640732168
Short name T1051
Test name
Test status
Simulation time 151073319 ps
CPU time 3.74 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:22 PM PDT 24
Peak memory 220828 kb
Host smart-d76b24b0-e334-4490-9867-e24448e7ae2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640732168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2640732168
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2951148473
Short name T998
Test name
Test status
Simulation time 75824462 ps
CPU time 3.18 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:20 PM PDT 24
Peak memory 214500 kb
Host smart-6dd60a2d-025b-4e65-8ea0-ec9137bc71fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951148473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2951148473
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2694483353
Short name T1008
Test name
Test status
Simulation time 100648935 ps
CPU time 1.33 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 206368 kb
Host smart-8e88e402-5ab0-407b-a815-3916aa1423dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694483353 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2694483353
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1880795843
Short name T976
Test name
Test status
Simulation time 64959352 ps
CPU time 1.24 seconds
Started Aug 17 04:41:15 PM PDT 24
Finished Aug 17 04:41:16 PM PDT 24
Peak memory 206152 kb
Host smart-2699e8e1-eac0-4025-b364-7bc7c127e009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880795843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1880795843
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1447088270
Short name T930
Test name
Test status
Simulation time 11526914 ps
CPU time 0.7 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:17 PM PDT 24
Peak memory 206008 kb
Host smart-49d80a4e-6b4c-4278-b76e-7d987083f2a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447088270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1447088270
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4052880387
Short name T109
Test name
Test status
Simulation time 245115071 ps
CPU time 2.28 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:19 PM PDT 24
Peak memory 206292 kb
Host smart-0b28807c-2174-477a-82c4-32e634fcb1db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052880387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4052880387
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.315185801
Short name T1020
Test name
Test status
Simulation time 349423525 ps
CPU time 4.84 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:21 PM PDT 24
Peak memory 214764 kb
Host smart-b5da09c8-d737-4a2d-85a8-c6aa48460275
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315185801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.315185801
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.581946142
Short name T991
Test name
Test status
Simulation time 995581789 ps
CPU time 8.06 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:26 PM PDT 24
Peak memory 214788 kb
Host smart-bf404a40-6fdc-4ccd-bfd6-4a441de580d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581946142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.581946142
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2762782423
Short name T995
Test name
Test status
Simulation time 86614439 ps
CPU time 2.69 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:19 PM PDT 24
Peak memory 217044 kb
Host smart-7c739c7e-0ed9-4b9d-b58d-b0407d8cd4b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762782423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2762782423
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2309388184
Short name T935
Test name
Test status
Simulation time 161930617 ps
CPU time 1.54 seconds
Started Aug 17 04:41:19 PM PDT 24
Finished Aug 17 04:41:21 PM PDT 24
Peak memory 214564 kb
Host smart-b5639c13-956b-4941-b138-e9ddcb35bbdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309388184 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2309388184
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.537229312
Short name T955
Test name
Test status
Simulation time 237222699 ps
CPU time 1.54 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:19 PM PDT 24
Peak memory 206216 kb
Host smart-4258be07-7510-4287-a97c-b0e02332cb49
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537229312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.537229312
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2111753938
Short name T1044
Test name
Test status
Simulation time 10554475 ps
CPU time 0.69 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:17 PM PDT 24
Peak memory 206104 kb
Host smart-dd9bcc95-9ce6-4d6e-974f-e88a5993b9d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111753938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2111753938
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1417350063
Short name T956
Test name
Test status
Simulation time 57161587 ps
CPU time 2.13 seconds
Started Aug 17 04:41:21 PM PDT 24
Finished Aug 17 04:41:23 PM PDT 24
Peak memory 206188 kb
Host smart-cbdb9486-8b9d-4802-926a-d0d4a7ee4bab
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417350063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1417350063
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3015556999
Short name T74
Test name
Test status
Simulation time 122351644 ps
CPU time 1.62 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:20 PM PDT 24
Peak memory 214752 kb
Host smart-24669748-a53d-4c44-b1a4-d696fc635cbb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015556999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3015556999
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1364383911
Short name T973
Test name
Test status
Simulation time 246163521 ps
CPU time 8.37 seconds
Started Aug 17 04:41:13 PM PDT 24
Finished Aug 17 04:41:21 PM PDT 24
Peak memory 214740 kb
Host smart-9bf44daf-1bcb-40c6-a902-392746a30165
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364383911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1364383911
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3637591412
Short name T916
Test name
Test status
Simulation time 32548798 ps
CPU time 1.73 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 214572 kb
Host smart-6f77f1c5-5ded-4780-9d59-749e46c13091
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637591412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3637591412
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1228113744
Short name T152
Test name
Test status
Simulation time 317705352 ps
CPU time 6.61 seconds
Started Aug 17 04:41:15 PM PDT 24
Finished Aug 17 04:41:22 PM PDT 24
Peak memory 214404 kb
Host smart-39662cbf-33bc-4530-805e-8b9b53e7908f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228113744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1228113744
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.514107867
Short name T1026
Test name
Test status
Simulation time 87797482 ps
CPU time 1.4 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 214468 kb
Host smart-6b348bf4-3e9d-4485-951f-cf00e84a26d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514107867 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.514107867
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.252129995
Short name T1028
Test name
Test status
Simulation time 77231538 ps
CPU time 0.99 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 206164 kb
Host smart-2a011b91-0c9f-4764-bffd-8fb94b439c99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252129995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.252129995
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1822485542
Short name T1042
Test name
Test status
Simulation time 27201856 ps
CPU time 0.78 seconds
Started Aug 17 04:41:20 PM PDT 24
Finished Aug 17 04:41:21 PM PDT 24
Peak memory 205924 kb
Host smart-be805534-b936-41d5-ba4f-f79a84f2c762
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822485542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1822485542
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3948242346
Short name T1018
Test name
Test status
Simulation time 627213593 ps
CPU time 2.22 seconds
Started Aug 17 04:41:15 PM PDT 24
Finished Aug 17 04:41:17 PM PDT 24
Peak memory 206560 kb
Host smart-7d2df7c5-2a64-4d5d-aa0b-6213984dfae9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948242346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3948242346
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.4292628407
Short name T78
Test name
Test status
Simulation time 265140622 ps
CPU time 2.37 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:20 PM PDT 24
Peak memory 214724 kb
Host smart-c044ab93-8425-4bb6-9dc1-651139d9040c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292628407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.4292628407
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1059479835
Short name T1004
Test name
Test status
Simulation time 1490807717 ps
CPU time 13.26 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:30 PM PDT 24
Peak memory 221080 kb
Host smart-091674af-436c-4252-8f9c-9610de0ac34e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059479835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1059479835
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1763055829
Short name T1027
Test name
Test status
Simulation time 202607804 ps
CPU time 3.07 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:20 PM PDT 24
Peak memory 214484 kb
Host smart-e95b86a7-fb93-42c3-a0f0-e696c7a36d93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763055829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1763055829
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2458498541
Short name T145
Test name
Test status
Simulation time 253134946 ps
CPU time 7.02 seconds
Started Aug 17 04:41:20 PM PDT 24
Finished Aug 17 04:41:27 PM PDT 24
Peak memory 214436 kb
Host smart-a9a6d958-8bd1-4bb8-a231-8c5f989dcd15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458498541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2458498541
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1858007795
Short name T910
Test name
Test status
Simulation time 270239592 ps
CPU time 1.39 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 206396 kb
Host smart-ab31bfdf-8320-444e-9c4d-4aca7d41cdec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858007795 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1858007795
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3788661448
Short name T982
Test name
Test status
Simulation time 57279453 ps
CPU time 1.22 seconds
Started Aug 17 04:41:20 PM PDT 24
Finished Aug 17 04:41:22 PM PDT 24
Peak memory 206248 kb
Host smart-20cda2a4-bba7-4ed7-b336-470bc496ce2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788661448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3788661448
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.2540970788
Short name T993
Test name
Test status
Simulation time 10757043 ps
CPU time 0.74 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:17 PM PDT 24
Peak memory 206092 kb
Host smart-ddb68dbc-3a3a-4a38-822a-d4f50109927c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540970788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.2540970788
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.3602061891
Short name T939
Test name
Test status
Simulation time 103489698 ps
CPU time 2.49 seconds
Started Aug 17 04:41:12 PM PDT 24
Finished Aug 17 04:41:15 PM PDT 24
Peak memory 206264 kb
Host smart-6fc09144-e790-4bcf-910e-446604126d5d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602061891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.3602061891
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3511107869
Short name T81
Test name
Test status
Simulation time 161014282 ps
CPU time 2.89 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:21 PM PDT 24
Peak memory 214916 kb
Host smart-ae162651-6736-42fd-929b-9b123077dab3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511107869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3511107869
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3091449950
Short name T76
Test name
Test status
Simulation time 1208529265 ps
CPU time 8.94 seconds
Started Aug 17 04:41:15 PM PDT 24
Finished Aug 17 04:41:24 PM PDT 24
Peak memory 214840 kb
Host smart-7692215f-0273-4e25-97ba-d1de484f511f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091449950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3091449950
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3746650560
Short name T1037
Test name
Test status
Simulation time 1131978702 ps
CPU time 2.29 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:19 PM PDT 24
Peak memory 214560 kb
Host smart-bbd4cb0b-3fea-4c9b-9d0e-ecd187ac3c68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746650560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3746650560
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1129868312
Short name T151
Test name
Test status
Simulation time 172958119 ps
CPU time 6.65 seconds
Started Aug 17 04:41:14 PM PDT 24
Finished Aug 17 04:41:21 PM PDT 24
Peak memory 214516 kb
Host smart-c385ffc6-4a15-4948-8b7d-b642d7febbb9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129868312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1129868312
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1267304024
Short name T1016
Test name
Test status
Simulation time 70316613 ps
CPU time 1.13 seconds
Started Aug 17 04:41:30 PM PDT 24
Finished Aug 17 04:41:32 PM PDT 24
Peak memory 206400 kb
Host smart-00d3d763-82fd-4252-b802-e07150503f1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267304024 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1267304024
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3887128807
Short name T1055
Test name
Test status
Simulation time 9801040 ps
CPU time 0.94 seconds
Started Aug 17 04:41:29 PM PDT 24
Finished Aug 17 04:41:30 PM PDT 24
Peak memory 206052 kb
Host smart-4fb077ec-0762-4ac4-9dcc-717367bcd78e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887128807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3887128807
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1980566505
Short name T1010
Test name
Test status
Simulation time 19339462 ps
CPU time 0.82 seconds
Started Aug 17 04:41:22 PM PDT 24
Finished Aug 17 04:41:23 PM PDT 24
Peak memory 206020 kb
Host smart-b257c984-2222-4861-90c2-70b7f08cee30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980566505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1980566505
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2417559360
Short name T1007
Test name
Test status
Simulation time 125495713 ps
CPU time 1.96 seconds
Started Aug 17 04:41:24 PM PDT 24
Finished Aug 17 04:41:26 PM PDT 24
Peak memory 206264 kb
Host smart-7f9d118c-b0b4-4c14-9ace-59c8629b494d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417559360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2417559360
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3091630516
Short name T1015
Test name
Test status
Simulation time 861915292 ps
CPU time 2.07 seconds
Started Aug 17 04:41:30 PM PDT 24
Finished Aug 17 04:41:32 PM PDT 24
Peak memory 214924 kb
Host smart-648f7793-c88c-4406-86e4-0d4f875347ee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091630516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.3091630516
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.854354458
Short name T983
Test name
Test status
Simulation time 1509210619 ps
CPU time 12.62 seconds
Started Aug 17 04:41:27 PM PDT 24
Finished Aug 17 04:41:40 PM PDT 24
Peak memory 221168 kb
Host smart-c5954fd3-0da2-428e-8521-337841bcfe4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854354458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.854354458
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2566866420
Short name T1025
Test name
Test status
Simulation time 31873006 ps
CPU time 2.17 seconds
Started Aug 17 04:41:32 PM PDT 24
Finished Aug 17 04:41:35 PM PDT 24
Peak memory 214564 kb
Host smart-828be14a-63c3-4b48-8cd7-b7ce993d18c6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566866420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2566866420
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3345466001
Short name T1023
Test name
Test status
Simulation time 187248786 ps
CPU time 4.66 seconds
Started Aug 17 04:41:30 PM PDT 24
Finished Aug 17 04:41:35 PM PDT 24
Peak memory 206244 kb
Host smart-6783932d-45b4-4d69-b5e9-fb87b09cec16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345466001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3345466001
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.505644729
Short name T1017
Test name
Test status
Simulation time 216442740 ps
CPU time 1.69 seconds
Started Aug 17 04:41:32 PM PDT 24
Finished Aug 17 04:41:34 PM PDT 24
Peak memory 214552 kb
Host smart-82375ddd-0347-4b59-abef-54af29bb9c81
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505644729 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.505644729
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2936561165
Short name T1058
Test name
Test status
Simulation time 15541299 ps
CPU time 1.06 seconds
Started Aug 17 04:41:27 PM PDT 24
Finished Aug 17 04:41:28 PM PDT 24
Peak memory 206236 kb
Host smart-458f61d4-024c-4a21-a6b6-f1866e84c3c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936561165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2936561165
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4028833450
Short name T1054
Test name
Test status
Simulation time 23915720 ps
CPU time 0.81 seconds
Started Aug 17 04:41:26 PM PDT 24
Finished Aug 17 04:41:27 PM PDT 24
Peak memory 206044 kb
Host smart-99ed9cce-4160-4e0a-8b5a-4ee023148f7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028833450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.4028833450
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1395085335
Short name T929
Test name
Test status
Simulation time 20715477 ps
CPU time 1.66 seconds
Started Aug 17 04:41:23 PM PDT 24
Finished Aug 17 04:41:25 PM PDT 24
Peak memory 206336 kb
Host smart-a9fdfebb-52cc-4013-975b-f9c73409194f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395085335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1395085335
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.4176845051
Short name T963
Test name
Test status
Simulation time 196574532 ps
CPU time 3.46 seconds
Started Aug 17 04:41:27 PM PDT 24
Finished Aug 17 04:41:30 PM PDT 24
Peak memory 214812 kb
Host smart-0df3dd88-a2ce-4498-a70d-d6abb153ddd4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176845051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.4176845051
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.58612188
Short name T994
Test name
Test status
Simulation time 191280743 ps
CPU time 7.17 seconds
Started Aug 17 04:41:26 PM PDT 24
Finished Aug 17 04:41:33 PM PDT 24
Peak memory 214832 kb
Host smart-0de22f6f-0f8c-409f-a384-45f4c4d041e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58612188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.k
eymgr_shadow_reg_errors_with_csr_rw.58612188
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2078552425
Short name T1043
Test name
Test status
Simulation time 124736903 ps
CPU time 3.21 seconds
Started Aug 17 04:41:29 PM PDT 24
Finished Aug 17 04:41:32 PM PDT 24
Peak memory 214428 kb
Host smart-10b87510-5981-4162-ae7d-5769ad0fb63d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078552425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2078552425
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.908524134
Short name T1021
Test name
Test status
Simulation time 137341694 ps
CPU time 8.61 seconds
Started Aug 17 04:41:03 PM PDT 24
Finished Aug 17 04:41:12 PM PDT 24
Peak memory 206300 kb
Host smart-c70285a5-3722-4dfa-9dba-a6ff31415e01
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908524134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.908524134
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1159275707
Short name T1039
Test name
Test status
Simulation time 2312941542 ps
CPU time 16.09 seconds
Started Aug 17 04:40:59 PM PDT 24
Finished Aug 17 04:41:15 PM PDT 24
Peak memory 206388 kb
Host smart-61541451-918b-4ae5-9f14-0cbb331b1fca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159275707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
159275707
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2547002101
Short name T1029
Test name
Test status
Simulation time 22930630 ps
CPU time 0.96 seconds
Started Aug 17 04:41:09 PM PDT 24
Finished Aug 17 04:41:10 PM PDT 24
Peak memory 206020 kb
Host smart-b2751acf-5cdb-40ca-93de-8d18abea3efe
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547002101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
547002101
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1061140174
Short name T981
Test name
Test status
Simulation time 32654345 ps
CPU time 1.64 seconds
Started Aug 17 04:40:58 PM PDT 24
Finished Aug 17 04:41:00 PM PDT 24
Peak memory 214556 kb
Host smart-fc603f1c-5045-4a55-8a60-fdadae8ed9a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061140174 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1061140174
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.4119360359
Short name T971
Test name
Test status
Simulation time 41393119 ps
CPU time 1.56 seconds
Started Aug 17 04:41:00 PM PDT 24
Finished Aug 17 04:41:02 PM PDT 24
Peak memory 206160 kb
Host smart-62ba6557-0a0b-44d9-a657-6d91d9689fb6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119360359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.4119360359
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.829752667
Short name T984
Test name
Test status
Simulation time 29462115 ps
CPU time 0.68 seconds
Started Aug 17 04:41:01 PM PDT 24
Finished Aug 17 04:41:02 PM PDT 24
Peak memory 205912 kb
Host smart-b6c79da0-1057-4d22-8d09-b3f10c161eb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829752667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.829752667
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3703815285
Short name T1071
Test name
Test status
Simulation time 115703152 ps
CPU time 3.61 seconds
Started Aug 17 04:41:06 PM PDT 24
Finished Aug 17 04:41:10 PM PDT 24
Peak memory 206232 kb
Host smart-f70bad23-8bcc-4bc4-b017-300d50d23b63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703815285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3703815285
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1633645222
Short name T919
Test name
Test status
Simulation time 1013928978 ps
CPU time 2.39 seconds
Started Aug 17 04:41:02 PM PDT 24
Finished Aug 17 04:41:04 PM PDT 24
Peak memory 214820 kb
Host smart-1a5db173-6d29-4e46-9289-7fb4f55a937d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633645222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1633645222
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.4254822439
Short name T1046
Test name
Test status
Simulation time 1327529254 ps
CPU time 8.08 seconds
Started Aug 17 04:41:02 PM PDT 24
Finished Aug 17 04:41:11 PM PDT 24
Peak memory 214844 kb
Host smart-e257c0d8-4c9b-486b-a1a9-e188c240fd97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254822439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.4254822439
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.265220336
Short name T979
Test name
Test status
Simulation time 636382750 ps
CPU time 4.07 seconds
Started Aug 17 04:40:59 PM PDT 24
Finished Aug 17 04:41:03 PM PDT 24
Peak memory 214528 kb
Host smart-d526d6c2-e4d3-4a39-b43b-1fde968d8aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265220336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.265220336
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2945353784
Short name T147
Test name
Test status
Simulation time 115236243 ps
CPU time 4.85 seconds
Started Aug 17 04:41:04 PM PDT 24
Finished Aug 17 04:41:09 PM PDT 24
Peak memory 214472 kb
Host smart-6635b28b-1cc5-4dcc-a6b2-c23bee75ef57
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945353784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2945353784
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.974249093
Short name T946
Test name
Test status
Simulation time 34003803 ps
CPU time 0.77 seconds
Started Aug 17 04:41:32 PM PDT 24
Finished Aug 17 04:41:33 PM PDT 24
Peak memory 206052 kb
Host smart-b27361fb-90a6-4aa5-91f2-c06eb0ad980c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=974249093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.974249093
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.338276809
Short name T942
Test name
Test status
Simulation time 9010345 ps
CPU time 0.78 seconds
Started Aug 17 04:41:26 PM PDT 24
Finished Aug 17 04:41:27 PM PDT 24
Peak memory 206028 kb
Host smart-ba453082-e4e0-4733-8daa-a205b7668d26
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338276809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.338276809
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2097295933
Short name T1074
Test name
Test status
Simulation time 15114761 ps
CPU time 0.69 seconds
Started Aug 17 04:41:26 PM PDT 24
Finished Aug 17 04:41:27 PM PDT 24
Peak memory 205936 kb
Host smart-4c72027d-d70d-4c58-9350-4de6fa025859
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097295933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2097295933
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.527783509
Short name T1013
Test name
Test status
Simulation time 49607969 ps
CPU time 0.71 seconds
Started Aug 17 04:41:25 PM PDT 24
Finished Aug 17 04:41:26 PM PDT 24
Peak memory 206020 kb
Host smart-6c9a525d-f7d1-4496-a2c9-1dd3126eb4a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527783509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.527783509
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2490586726
Short name T915
Test name
Test status
Simulation time 24372889 ps
CPU time 0.84 seconds
Started Aug 17 04:41:24 PM PDT 24
Finished Aug 17 04:41:25 PM PDT 24
Peak memory 205936 kb
Host smart-b2d90ab3-cf8b-4960-b477-a784c12e230a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490586726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2490586726
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1187178903
Short name T1009
Test name
Test status
Simulation time 57716508 ps
CPU time 0.81 seconds
Started Aug 17 04:41:27 PM PDT 24
Finished Aug 17 04:41:28 PM PDT 24
Peak memory 206068 kb
Host smart-c5a9e475-3ab5-4269-9c1b-fbf4171a42e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1187178903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1187178903
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2431718286
Short name T1073
Test name
Test status
Simulation time 39136449 ps
CPU time 0.71 seconds
Started Aug 17 04:41:24 PM PDT 24
Finished Aug 17 04:41:24 PM PDT 24
Peak memory 206036 kb
Host smart-990516a7-947e-4495-afe4-f032a0f9655f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431718286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2431718286
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1656865281
Short name T1061
Test name
Test status
Simulation time 10531684 ps
CPU time 0.81 seconds
Started Aug 17 04:41:27 PM PDT 24
Finished Aug 17 04:41:28 PM PDT 24
Peak memory 206080 kb
Host smart-65ce173f-3cbe-40b9-8e79-cf868b5fc890
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656865281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1656865281
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2029585206
Short name T918
Test name
Test status
Simulation time 62560104 ps
CPU time 0.87 seconds
Started Aug 17 04:41:24 PM PDT 24
Finished Aug 17 04:41:25 PM PDT 24
Peak memory 205964 kb
Host smart-6af87fb9-4103-4906-a1e9-260a7652a3e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029585206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2029585206
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4071120347
Short name T938
Test name
Test status
Simulation time 235231812 ps
CPU time 0.83 seconds
Started Aug 17 04:41:27 PM PDT 24
Finished Aug 17 04:41:27 PM PDT 24
Peak memory 206080 kb
Host smart-8fb1fccb-d6fb-48d6-939a-2b6930a29b5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071120347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4071120347
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1708445717
Short name T940
Test name
Test status
Simulation time 371380415 ps
CPU time 9.18 seconds
Started Aug 17 04:41:09 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 206280 kb
Host smart-06a81ffd-966e-4ad7-992b-7bfb824a7a8c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708445717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
708445717
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3939910175
Short name T990
Test name
Test status
Simulation time 5120706416 ps
CPU time 23.79 seconds
Started Aug 17 04:41:04 PM PDT 24
Finished Aug 17 04:41:28 PM PDT 24
Peak memory 206364 kb
Host smart-41d663ec-6faa-4202-a120-f49a1771abdc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939910175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
939910175
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.151874964
Short name T1036
Test name
Test status
Simulation time 182345847 ps
CPU time 1.11 seconds
Started Aug 17 04:41:01 PM PDT 24
Finished Aug 17 04:41:02 PM PDT 24
Peak memory 206344 kb
Host smart-884688e5-bd67-4d4e-a8ce-7f10257c6dab
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151874964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.151874964
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3216854391
Short name T917
Test name
Test status
Simulation time 45770685 ps
CPU time 1.09 seconds
Started Aug 17 04:41:03 PM PDT 24
Finished Aug 17 04:41:04 PM PDT 24
Peak memory 206280 kb
Host smart-510b1714-1ead-4f95-8dd7-5189c5451e55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216854391 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3216854391
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.226244411
Short name T1022
Test name
Test status
Simulation time 55411955 ps
CPU time 1.55 seconds
Started Aug 17 04:41:02 PM PDT 24
Finished Aug 17 04:41:04 PM PDT 24
Peak memory 206248 kb
Host smart-537241f8-54d8-4bd5-930c-5fca77eabe25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226244411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.226244411
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3023139034
Short name T975
Test name
Test status
Simulation time 86057361 ps
CPU time 0.8 seconds
Started Aug 17 04:41:01 PM PDT 24
Finished Aug 17 04:41:02 PM PDT 24
Peak memory 205912 kb
Host smart-72c6c586-4236-45c2-be06-7485ea0cd30b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023139034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3023139034
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2265954710
Short name T1050
Test name
Test status
Simulation time 67344032 ps
CPU time 1.62 seconds
Started Aug 17 04:40:59 PM PDT 24
Finished Aug 17 04:41:00 PM PDT 24
Peak memory 206276 kb
Host smart-32414e0f-08cc-4e73-a59e-a9b42c003be6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265954710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2265954710
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.4024239879
Short name T947
Test name
Test status
Simulation time 94281270 ps
CPU time 2.74 seconds
Started Aug 17 04:41:10 PM PDT 24
Finished Aug 17 04:41:13 PM PDT 24
Peak memory 214816 kb
Host smart-c00d3645-edf1-412a-b498-c442eefc89d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024239879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.4024239879
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2700730946
Short name T980
Test name
Test status
Simulation time 182610397 ps
CPU time 3.68 seconds
Started Aug 17 04:41:11 PM PDT 24
Finished Aug 17 04:41:14 PM PDT 24
Peak memory 214416 kb
Host smart-d7c57c7d-44b5-4ce6-a25e-c07ae1d3c374
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700730946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2700730946
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.1097117916
Short name T157
Test name
Test status
Simulation time 233452254 ps
CPU time 4.46 seconds
Started Aug 17 04:41:01 PM PDT 24
Finished Aug 17 04:41:05 PM PDT 24
Peak memory 214360 kb
Host smart-36ea1ace-83d7-43e7-a2a5-4330494ef06c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097117916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.1097117916
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.536090468
Short name T912
Test name
Test status
Simulation time 48231226 ps
CPU time 0.76 seconds
Started Aug 17 04:41:25 PM PDT 24
Finished Aug 17 04:41:26 PM PDT 24
Peak memory 205896 kb
Host smart-ae0986fd-44d7-4ca9-9512-49bff2d04836
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536090468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.536090468
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.369936714
Short name T968
Test name
Test status
Simulation time 19895461 ps
CPU time 0.66 seconds
Started Aug 17 04:41:26 PM PDT 24
Finished Aug 17 04:41:27 PM PDT 24
Peak memory 206012 kb
Host smart-7afe30e4-ca85-4231-a8e6-e01f5591cc02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369936714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.369936714
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1189779456
Short name T987
Test name
Test status
Simulation time 21952262 ps
CPU time 0.83 seconds
Started Aug 17 04:41:25 PM PDT 24
Finished Aug 17 04:41:26 PM PDT 24
Peak memory 206008 kb
Host smart-a58dc68d-1674-462b-8cbe-59e069cde9c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189779456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1189779456
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.4081807908
Short name T1038
Test name
Test status
Simulation time 43108704 ps
CPU time 0.87 seconds
Started Aug 17 04:41:29 PM PDT 24
Finished Aug 17 04:41:31 PM PDT 24
Peak memory 205964 kb
Host smart-5b2253a5-df23-4223-bb1d-305f8ea99908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081807908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.4081807908
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3442646355
Short name T1049
Test name
Test status
Simulation time 29461473 ps
CPU time 0.73 seconds
Started Aug 17 04:41:26 PM PDT 24
Finished Aug 17 04:41:27 PM PDT 24
Peak memory 206020 kb
Host smart-d3967658-e394-4317-a852-131d15c9f87a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442646355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3442646355
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1371033062
Short name T924
Test name
Test status
Simulation time 27362473 ps
CPU time 0.84 seconds
Started Aug 17 04:41:27 PM PDT 24
Finished Aug 17 04:41:28 PM PDT 24
Peak memory 206068 kb
Host smart-d7ec7243-36db-4c5c-8cf8-650a10140717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371033062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1371033062
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3540800635
Short name T932
Test name
Test status
Simulation time 63029338 ps
CPU time 0.92 seconds
Started Aug 17 04:41:30 PM PDT 24
Finished Aug 17 04:41:31 PM PDT 24
Peak memory 205948 kb
Host smart-65c5eade-ca94-4dba-9fb1-e506e8326ee3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540800635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3540800635
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.697989547
Short name T931
Test name
Test status
Simulation time 12993557 ps
CPU time 0.73 seconds
Started Aug 17 04:41:29 PM PDT 24
Finished Aug 17 04:41:30 PM PDT 24
Peak memory 205916 kb
Host smart-04407a10-2f46-4c66-9986-4552e82de875
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697989547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.697989547
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1351464211
Short name T950
Test name
Test status
Simulation time 24638194 ps
CPU time 0.75 seconds
Started Aug 17 04:41:27 PM PDT 24
Finished Aug 17 04:41:28 PM PDT 24
Peak memory 206036 kb
Host smart-88134585-c05f-4d6d-b485-e9e59f97244b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351464211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1351464211
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1633299219
Short name T933
Test name
Test status
Simulation time 11938723 ps
CPU time 0.85 seconds
Started Aug 17 04:41:29 PM PDT 24
Finished Aug 17 04:41:30 PM PDT 24
Peak memory 206040 kb
Host smart-2e030eff-f209-48cc-ad47-8e7eb585682f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1633299219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1633299219
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.154887644
Short name T922
Test name
Test status
Simulation time 563660073 ps
CPU time 4.72 seconds
Started Aug 17 04:41:10 PM PDT 24
Finished Aug 17 04:41:15 PM PDT 24
Peak memory 206256 kb
Host smart-ae694a92-c989-453e-ba25-58f4b260e7f5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154887644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.154887644
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2841764978
Short name T952
Test name
Test status
Simulation time 18397367133 ps
CPU time 20.34 seconds
Started Aug 17 04:41:04 PM PDT 24
Finished Aug 17 04:41:24 PM PDT 24
Peak memory 206412 kb
Host smart-d9ae00ce-593e-409b-8f05-323532c9187b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841764978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
841764978
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2916933374
Short name T142
Test name
Test status
Simulation time 39450704 ps
CPU time 1.34 seconds
Started Aug 17 04:41:04 PM PDT 24
Finished Aug 17 04:41:05 PM PDT 24
Peak memory 206276 kb
Host smart-436a9e6b-9edb-42f7-bf35-2104d4cfd3ba
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916933374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
916933374
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3438725112
Short name T1048
Test name
Test status
Simulation time 41112634 ps
CPU time 1.07 seconds
Started Aug 17 04:41:11 PM PDT 24
Finished Aug 17 04:41:12 PM PDT 24
Peak memory 206104 kb
Host smart-f0c8d856-2bcc-4813-9372-ff3a66c1430d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438725112 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3438725112
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3090709347
Short name T108
Test name
Test status
Simulation time 48133070 ps
CPU time 1.04 seconds
Started Aug 17 04:41:02 PM PDT 24
Finished Aug 17 04:41:03 PM PDT 24
Peak memory 206188 kb
Host smart-ef54b86b-3af1-4172-8d56-e7962c07caf4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090709347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3090709347
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2087258184
Short name T925
Test name
Test status
Simulation time 34450109 ps
CPU time 0.83 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:17 PM PDT 24
Peak memory 205968 kb
Host smart-1c277400-177d-49cb-9c46-5095353a9849
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087258184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2087258184
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3880549679
Short name T107
Test name
Test status
Simulation time 130425042 ps
CPU time 2.34 seconds
Started Aug 17 04:41:02 PM PDT 24
Finished Aug 17 04:41:04 PM PDT 24
Peak memory 206204 kb
Host smart-ba64877f-9dd5-404f-9630-a030ad1e90b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880549679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3880549679
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1481170133
Short name T936
Test name
Test status
Simulation time 109181594 ps
CPU time 1.8 seconds
Started Aug 17 04:41:02 PM PDT 24
Finished Aug 17 04:41:04 PM PDT 24
Peak memory 214824 kb
Host smart-a644b748-d191-48ae-99ea-d7b033e1e3ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481170133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1481170133
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.4271454598
Short name T1011
Test name
Test status
Simulation time 229153527 ps
CPU time 3.01 seconds
Started Aug 17 04:41:08 PM PDT 24
Finished Aug 17 04:41:11 PM PDT 24
Peak memory 214524 kb
Host smart-131b6450-bbfa-461f-8d4d-87ed01c7585c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271454598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.4271454598
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.665679338
Short name T948
Test name
Test status
Simulation time 11392169 ps
CPU time 0.77 seconds
Started Aug 17 04:41:31 PM PDT 24
Finished Aug 17 04:41:32 PM PDT 24
Peak memory 206052 kb
Host smart-24988609-77b2-4fa3-b16d-6cdd6b8bc3e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665679338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.665679338
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.594777459
Short name T997
Test name
Test status
Simulation time 32258204 ps
CPU time 0.72 seconds
Started Aug 17 04:41:24 PM PDT 24
Finished Aug 17 04:41:25 PM PDT 24
Peak memory 205960 kb
Host smart-2d30fd6f-4e30-48df-a45a-82634f3f9f85
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594777459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.594777459
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.286488518
Short name T1047
Test name
Test status
Simulation time 19257280 ps
CPU time 0.81 seconds
Started Aug 17 04:41:29 PM PDT 24
Finished Aug 17 04:41:30 PM PDT 24
Peak memory 205964 kb
Host smart-0b0310a0-7b58-4a93-b7dc-61943f13c98f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286488518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.286488518
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3440169415
Short name T1063
Test name
Test status
Simulation time 48509575 ps
CPU time 0.76 seconds
Started Aug 17 04:41:32 PM PDT 24
Finished Aug 17 04:41:32 PM PDT 24
Peak memory 205976 kb
Host smart-e39c548c-a571-4da8-b2fd-0b074d683f06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440169415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3440169415
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1431287147
Short name T1067
Test name
Test status
Simulation time 28007752 ps
CPU time 0.71 seconds
Started Aug 17 04:41:27 PM PDT 24
Finished Aug 17 04:41:28 PM PDT 24
Peak memory 206020 kb
Host smart-a76dd328-08a0-4398-a941-d5182e5f7c97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431287147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1431287147
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3745628987
Short name T914
Test name
Test status
Simulation time 67001839 ps
CPU time 0.88 seconds
Started Aug 17 04:41:24 PM PDT 24
Finished Aug 17 04:41:25 PM PDT 24
Peak memory 206020 kb
Host smart-fbab66ca-40c8-4b25-a8da-ec8cd1ae6cdc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745628987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3745628987
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3815713797
Short name T1059
Test name
Test status
Simulation time 10548922 ps
CPU time 0.79 seconds
Started Aug 17 04:41:24 PM PDT 24
Finished Aug 17 04:41:25 PM PDT 24
Peak memory 205928 kb
Host smart-a33df3ce-1270-48dc-8f2c-e8e9c67071ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815713797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3815713797
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2256040801
Short name T911
Test name
Test status
Simulation time 7240326 ps
CPU time 0.79 seconds
Started Aug 17 04:41:25 PM PDT 24
Finished Aug 17 04:41:26 PM PDT 24
Peak memory 205872 kb
Host smart-ecbd316d-a6de-4ff9-9c01-0a43de255847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256040801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2256040801
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1131653787
Short name T1072
Test name
Test status
Simulation time 13158671 ps
CPU time 0.9 seconds
Started Aug 17 04:41:25 PM PDT 24
Finished Aug 17 04:41:26 PM PDT 24
Peak memory 206040 kb
Host smart-cb14ba38-249b-4d0d-8e4f-517a7635c19e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131653787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1131653787
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4232969065
Short name T970
Test name
Test status
Simulation time 8761231 ps
CPU time 0.7 seconds
Started Aug 17 04:41:36 PM PDT 24
Finished Aug 17 04:41:37 PM PDT 24
Peak memory 206016 kb
Host smart-a487fee0-b662-431e-8a4e-cd50195b62c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232969065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4232969065
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2864013350
Short name T1068
Test name
Test status
Simulation time 105672563 ps
CPU time 1.9 seconds
Started Aug 17 04:40:59 PM PDT 24
Finished Aug 17 04:41:01 PM PDT 24
Peak memory 222676 kb
Host smart-88b95011-3c63-48b2-94e3-712f6ba9398d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864013350 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2864013350
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1992899934
Short name T961
Test name
Test status
Simulation time 33200006 ps
CPU time 0.99 seconds
Started Aug 17 04:41:05 PM PDT 24
Finished Aug 17 04:41:06 PM PDT 24
Peak memory 205920 kb
Host smart-2f794d24-88d1-4d5c-8a36-7f63e6f328f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992899934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1992899934
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1940554683
Short name T965
Test name
Test status
Simulation time 23949780 ps
CPU time 0.85 seconds
Started Aug 17 04:41:09 PM PDT 24
Finished Aug 17 04:41:10 PM PDT 24
Peak memory 205960 kb
Host smart-7d0c7b62-0395-4c04-820a-993d9cb87191
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940554683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1940554683
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.967591681
Short name T934
Test name
Test status
Simulation time 95822131 ps
CPU time 1.45 seconds
Started Aug 17 04:41:02 PM PDT 24
Finished Aug 17 04:41:04 PM PDT 24
Peak memory 206276 kb
Host smart-1c2edf4d-bcce-40c4-8356-d2ae1c7a9eb0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967591681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.967591681
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1700616997
Short name T84
Test name
Test status
Simulation time 144896330 ps
CPU time 1.55 seconds
Started Aug 17 04:41:01 PM PDT 24
Finished Aug 17 04:41:03 PM PDT 24
Peak memory 214792 kb
Host smart-3e2dd43f-b5b4-420b-a316-b03ab074ed42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700616997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1700616997
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1920994419
Short name T986
Test name
Test status
Simulation time 1250114800 ps
CPU time 8.79 seconds
Started Aug 17 04:41:03 PM PDT 24
Finished Aug 17 04:41:11 PM PDT 24
Peak memory 214840 kb
Host smart-dd481617-656c-4a8d-a6ca-8e2ca3efa21a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920994419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1920994419
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2265779348
Short name T928
Test name
Test status
Simulation time 28840200 ps
CPU time 1.82 seconds
Started Aug 17 04:41:04 PM PDT 24
Finished Aug 17 04:41:06 PM PDT 24
Peak memory 214656 kb
Host smart-93da868f-65f7-4190-ae8c-ac1bb9e91837
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265779348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2265779348
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.508576066
Short name T908
Test name
Test status
Simulation time 1479411051 ps
CPU time 8.99 seconds
Started Aug 17 04:41:02 PM PDT 24
Finished Aug 17 04:41:11 PM PDT 24
Peak memory 214432 kb
Host smart-7820fbf0-7621-48ec-b001-d2a1fe39b102
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508576066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
508576066
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2080437567
Short name T988
Test name
Test status
Simulation time 71526092 ps
CPU time 1.15 seconds
Started Aug 17 04:41:13 PM PDT 24
Finished Aug 17 04:41:15 PM PDT 24
Peak memory 214624 kb
Host smart-01e3ba45-b5d1-421a-bc52-20ea11e9aad6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080437567 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2080437567
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1323569715
Short name T1032
Test name
Test status
Simulation time 26431598 ps
CPU time 1.47 seconds
Started Aug 17 04:41:03 PM PDT 24
Finished Aug 17 04:41:04 PM PDT 24
Peak memory 206320 kb
Host smart-adad86a9-f028-4180-9e3b-0a323c5a3d07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323569715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1323569715
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1748157388
Short name T1066
Test name
Test status
Simulation time 49803221 ps
CPU time 0.81 seconds
Started Aug 17 04:41:00 PM PDT 24
Finished Aug 17 04:41:01 PM PDT 24
Peak memory 205936 kb
Host smart-6ea0e5f9-5276-4491-b625-77eeac931674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748157388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1748157388
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1067949847
Short name T944
Test name
Test status
Simulation time 79342097 ps
CPU time 1.58 seconds
Started Aug 17 04:41:14 PM PDT 24
Finished Aug 17 04:41:15 PM PDT 24
Peak memory 206212 kb
Host smart-347c5316-5086-4929-a91e-a05e016c03a7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067949847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1067949847
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3651691071
Short name T80
Test name
Test status
Simulation time 133407383 ps
CPU time 2.93 seconds
Started Aug 17 04:41:01 PM PDT 24
Finished Aug 17 04:41:04 PM PDT 24
Peak memory 214940 kb
Host smart-b0f09631-0268-4e18-bf34-d69517f20568
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651691071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3651691071
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3762422047
Short name T992
Test name
Test status
Simulation time 3518477934 ps
CPU time 10.58 seconds
Started Aug 17 04:41:09 PM PDT 24
Finished Aug 17 04:41:20 PM PDT 24
Peak memory 214936 kb
Host smart-aede9d7f-a965-40eb-9f2a-924aa2a04ffc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762422047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3762422047
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.796189650
Short name T1052
Test name
Test status
Simulation time 213142738 ps
CPU time 1.67 seconds
Started Aug 17 04:41:10 PM PDT 24
Finished Aug 17 04:41:12 PM PDT 24
Peak memory 214596 kb
Host smart-3d5c9990-bb3c-4df9-92f6-0bc14111e247
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796189650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.796189650
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1558076999
Short name T1014
Test name
Test status
Simulation time 43084782 ps
CPU time 1.33 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:19 PM PDT 24
Peak memory 214560 kb
Host smart-dc1de68f-6e80-40cc-9a27-c389c0657a78
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558076999 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1558076999
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2823999071
Short name T954
Test name
Test status
Simulation time 171118355 ps
CPU time 1.09 seconds
Started Aug 17 04:41:07 PM PDT 24
Finished Aug 17 04:41:08 PM PDT 24
Peak memory 206272 kb
Host smart-b28761dd-5f4c-4de9-b0e3-415c6698c7f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823999071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2823999071
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.4036655093
Short name T1057
Test name
Test status
Simulation time 13381547 ps
CPU time 0.73 seconds
Started Aug 17 04:41:05 PM PDT 24
Finished Aug 17 04:41:06 PM PDT 24
Peak memory 206020 kb
Host smart-57dd31db-6176-4fee-aec9-99ee456efdd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036655093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.4036655093
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1141333504
Short name T111
Test name
Test status
Simulation time 681731479 ps
CPU time 1.81 seconds
Started Aug 17 04:41:16 PM PDT 24
Finished Aug 17 04:41:17 PM PDT 24
Peak memory 206268 kb
Host smart-821bfbcb-1c0e-425e-9fa7-3013c7056720
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141333504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1141333504
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3241222210
Short name T1012
Test name
Test status
Simulation time 60616195 ps
CPU time 1.46 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:19 PM PDT 24
Peak memory 214816 kb
Host smart-013ac02e-2f17-4b3c-8db8-0735692137f0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241222210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3241222210
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1508107793
Short name T75
Test name
Test status
Simulation time 736154689 ps
CPU time 4.82 seconds
Started Aug 17 04:41:06 PM PDT 24
Finished Aug 17 04:41:11 PM PDT 24
Peak memory 214804 kb
Host smart-daea3202-702e-42b6-9845-90c789557259
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508107793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1508107793
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.559917725
Short name T957
Test name
Test status
Simulation time 297099324 ps
CPU time 5.07 seconds
Started Aug 17 04:41:06 PM PDT 24
Finished Aug 17 04:41:11 PM PDT 24
Peak memory 216892 kb
Host smart-515dd40d-2b2b-4eab-8d0b-97e71a2a6e1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559917725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.559917725
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.3477579454
Short name T153
Test name
Test status
Simulation time 202916865 ps
CPU time 3.01 seconds
Started Aug 17 04:41:06 PM PDT 24
Finished Aug 17 04:41:09 PM PDT 24
Peak memory 214756 kb
Host smart-dd207658-b961-40f5-b23e-f7be9e44ab88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477579454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.3477579454
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1431400071
Short name T1053
Test name
Test status
Simulation time 25780462 ps
CPU time 1.51 seconds
Started Aug 17 04:41:11 PM PDT 24
Finished Aug 17 04:41:12 PM PDT 24
Peak memory 214568 kb
Host smart-4aeff154-1272-4063-9370-f1b1f41dc08e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431400071 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1431400071
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3454439341
Short name T1035
Test name
Test status
Simulation time 176987617 ps
CPU time 0.88 seconds
Started Aug 17 04:41:15 PM PDT 24
Finished Aug 17 04:41:16 PM PDT 24
Peak memory 205996 kb
Host smart-8b4193b8-8e9c-455f-a424-1c8fd6da3f05
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454439341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3454439341
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4006007293
Short name T960
Test name
Test status
Simulation time 67694035 ps
CPU time 0.72 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:18 PM PDT 24
Peak memory 206028 kb
Host smart-7b94e02c-b1b1-4104-8463-53bd56cd2222
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006007293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4006007293
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2900614260
Short name T941
Test name
Test status
Simulation time 405898568 ps
CPU time 2.6 seconds
Started Aug 17 04:41:08 PM PDT 24
Finished Aug 17 04:41:11 PM PDT 24
Peak memory 206188 kb
Host smart-41043782-914b-4ebe-b12b-f9e2971cf390
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900614260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2900614260
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3402218563
Short name T962
Test name
Test status
Simulation time 211113377 ps
CPU time 1.5 seconds
Started Aug 17 04:41:13 PM PDT 24
Finished Aug 17 04:41:15 PM PDT 24
Peak memory 214868 kb
Host smart-01389d82-a8ea-4efe-8b65-2fa0f4a7df5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402218563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3402218563
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1537017750
Short name T1034
Test name
Test status
Simulation time 227910016 ps
CPU time 8.4 seconds
Started Aug 17 04:41:04 PM PDT 24
Finished Aug 17 04:41:13 PM PDT 24
Peak memory 214788 kb
Host smart-65b8a5e0-de04-413d-9e42-2e90bcbf5461
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537017750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1537017750
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1939378879
Short name T1030
Test name
Test status
Simulation time 145333412 ps
CPU time 2.98 seconds
Started Aug 17 04:41:19 PM PDT 24
Finished Aug 17 04:41:23 PM PDT 24
Peak memory 214524 kb
Host smart-1b061a97-d067-4348-b0ba-161a366e5d90
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939378879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1939378879
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2163017175
Short name T1065
Test name
Test status
Simulation time 120496658 ps
CPU time 1.25 seconds
Started Aug 17 04:41:06 PM PDT 24
Finished Aug 17 04:41:08 PM PDT 24
Peak memory 214524 kb
Host smart-7e60966d-c4da-42cd-9a4a-33e5c40c27c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163017175 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2163017175
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2997964636
Short name T1070
Test name
Test status
Simulation time 22703958 ps
CPU time 1.39 seconds
Started Aug 17 04:41:18 PM PDT 24
Finished Aug 17 04:41:19 PM PDT 24
Peak memory 206280 kb
Host smart-be64d26a-d7db-4dcc-afac-8d4dfe5f61a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997964636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2997964636
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1559222751
Short name T921
Test name
Test status
Simulation time 11159068 ps
CPU time 0.83 seconds
Started Aug 17 04:41:04 PM PDT 24
Finished Aug 17 04:41:05 PM PDT 24
Peak memory 206012 kb
Host smart-384b10cd-d8e0-48bc-94c7-baabc5ff6967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559222751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1559222751
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.1742342759
Short name T964
Test name
Test status
Simulation time 129771564 ps
CPU time 2.29 seconds
Started Aug 17 04:41:06 PM PDT 24
Finished Aug 17 04:41:09 PM PDT 24
Peak memory 206300 kb
Host smart-d772c8c4-e859-49d0-9c8d-612e772bdccb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742342759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.1742342759
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.338022009
Short name T999
Test name
Test status
Simulation time 159556926 ps
CPU time 2.44 seconds
Started Aug 17 04:41:17 PM PDT 24
Finished Aug 17 04:41:19 PM PDT 24
Peak memory 214804 kb
Host smart-6cdf53bd-19a1-4200-be04-7e3101a4fffa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338022009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.338022009
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.4214452104
Short name T937
Test name
Test status
Simulation time 786197288 ps
CPU time 7.49 seconds
Started Aug 17 04:41:06 PM PDT 24
Finished Aug 17 04:41:14 PM PDT 24
Peak memory 214768 kb
Host smart-803fe224-8efe-431d-96d9-9785c0d0fa49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4214452104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.4214452104
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1040625557
Short name T1002
Test name
Test status
Simulation time 111662969 ps
CPU time 3.04 seconds
Started Aug 17 04:41:06 PM PDT 24
Finished Aug 17 04:41:09 PM PDT 24
Peak memory 222676 kb
Host smart-b8a2fa3a-af60-4e7c-a10e-70070a364aab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040625557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1040625557
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1341375288
Short name T158
Test name
Test status
Simulation time 251069026 ps
CPU time 6.14 seconds
Started Aug 17 04:41:08 PM PDT 24
Finished Aug 17 04:41:15 PM PDT 24
Peak memory 214588 kb
Host smart-cf9d6dac-1e8d-4f06-99e6-79fe6b788bfb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341375288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1341375288
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.479230273
Short name T435
Test name
Test status
Simulation time 44551095 ps
CPU time 0.72 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:10 PM PDT 24
Peak memory 206384 kb
Host smart-b86ecd99-f822-4d3d-8d6a-73a7a8fb1b47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479230273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.479230273
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2478848195
Short name T406
Test name
Test status
Simulation time 168517016 ps
CPU time 3.12 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 214756 kb
Host smart-298ab288-ed87-456b-9bcb-ccfe5ad11592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478848195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2478848195
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2031929809
Short name T213
Test name
Test status
Simulation time 475322684 ps
CPU time 4.12 seconds
Started Aug 17 04:50:01 PM PDT 24
Finished Aug 17 04:50:05 PM PDT 24
Peak memory 218192 kb
Host smart-843c6d0d-a5da-48a3-ac0d-92657666030e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031929809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2031929809
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2589128713
Short name T253
Test name
Test status
Simulation time 67846501 ps
CPU time 2.32 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:11 PM PDT 24
Peak memory 208824 kb
Host smart-ebe8e384-ce6e-4186-a2bd-2ffd5937f1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589128713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2589128713
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1947226289
Short name T553
Test name
Test status
Simulation time 496063951 ps
CPU time 10.54 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:20 PM PDT 24
Peak memory 210064 kb
Host smart-05816adc-f648-4c3e-8d2e-266c7391249d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947226289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1947226289
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.575259888
Short name T223
Test name
Test status
Simulation time 53664212 ps
CPU time 3.36 seconds
Started Aug 17 04:49:59 PM PDT 24
Finished Aug 17 04:50:02 PM PDT 24
Peak memory 220788 kb
Host smart-401e2e7c-d327-4f64-a0fd-3fade988a139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575259888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.575259888
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.1855848583
Short name T304
Test name
Test status
Simulation time 213015334 ps
CPU time 3.49 seconds
Started Aug 17 04:50:13 PM PDT 24
Finished Aug 17 04:50:16 PM PDT 24
Peak memory 208164 kb
Host smart-823027bd-d827-4f9c-a6f5-f96ef09e33c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855848583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1855848583
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.4282653898
Short name T552
Test name
Test status
Simulation time 556839789 ps
CPU time 4.14 seconds
Started Aug 17 04:49:57 PM PDT 24
Finished Aug 17 04:50:01 PM PDT 24
Peak memory 208968 kb
Host smart-f6bd26c6-bedf-408c-80d1-4394db6049c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282653898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.4282653898
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3161072115
Short name T649
Test name
Test status
Simulation time 283356431 ps
CPU time 4.53 seconds
Started Aug 17 04:50:02 PM PDT 24
Finished Aug 17 04:50:07 PM PDT 24
Peak memory 208868 kb
Host smart-992f339c-bd57-4b54-a6a8-fec9faa1a969
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161072115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3161072115
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2061991741
Short name T534
Test name
Test status
Simulation time 72609460 ps
CPU time 2.85 seconds
Started Aug 17 04:50:08 PM PDT 24
Finished Aug 17 04:50:11 PM PDT 24
Peak memory 208080 kb
Host smart-b88075d0-be12-4f56-a151-0e1815b7e35b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061991741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2061991741
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3572560046
Short name T472
Test name
Test status
Simulation time 70107584 ps
CPU time 2.32 seconds
Started Aug 17 04:50:04 PM PDT 24
Finished Aug 17 04:50:06 PM PDT 24
Peak memory 207192 kb
Host smart-fd5b3dd4-f8c3-49ae-8ee5-854065abf449
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572560046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3572560046
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3041574675
Short name T502
Test name
Test status
Simulation time 238639432 ps
CPU time 2.46 seconds
Started Aug 17 04:50:07 PM PDT 24
Finished Aug 17 04:50:09 PM PDT 24
Peak memory 207664 kb
Host smart-b7b330d4-98eb-4ded-8210-b2a0ac9e1172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041574675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3041574675
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3507801084
Short name T449
Test name
Test status
Simulation time 412553029 ps
CPU time 9.64 seconds
Started Aug 17 04:50:04 PM PDT 24
Finished Aug 17 04:50:14 PM PDT 24
Peak memory 208684 kb
Host smart-0f439546-476c-4eae-addc-921ed77d8686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507801084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3507801084
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.419886191
Short name T179
Test name
Test status
Simulation time 343565538 ps
CPU time 13.17 seconds
Started Aug 17 04:50:07 PM PDT 24
Finished Aug 17 04:50:21 PM PDT 24
Peak memory 217636 kb
Host smart-82f98f95-ad7f-4f96-884b-ff97be28da31
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419886191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.419886191
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.547360656
Short name T799
Test name
Test status
Simulation time 2614425726 ps
CPU time 10.69 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:22 PM PDT 24
Peak memory 214928 kb
Host smart-ad7ca3b3-0fa9-44c5-b4c4-2b8855fa75cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547360656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.547360656
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2640616350
Short name T850
Test name
Test status
Simulation time 75449236 ps
CPU time 3 seconds
Started Aug 17 04:50:12 PM PDT 24
Finished Aug 17 04:50:15 PM PDT 24
Peak memory 210716 kb
Host smart-2f53ad13-8eed-44e3-992c-c1b6a9254005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640616350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2640616350
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2335460735
Short name T646
Test name
Test status
Simulation time 46070430 ps
CPU time 0.87 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:11 PM PDT 24
Peak memory 206360 kb
Host smart-76daf295-1c2e-4105-af2d-b09950f5b4f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335460735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2335460735
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3421908126
Short name T377
Test name
Test status
Simulation time 32693478 ps
CPU time 2.61 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:13 PM PDT 24
Peak memory 214732 kb
Host smart-a6b159f0-326b-42a9-a30c-1f3e159a1d61
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421908126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3421908126
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1202347349
Short name T810
Test name
Test status
Simulation time 143784428 ps
CPU time 5.34 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:16 PM PDT 24
Peak memory 223188 kb
Host smart-0fa9a4b7-6ffe-4f4e-bd03-0a41ad88e7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202347349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1202347349
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1799507931
Short name T241
Test name
Test status
Simulation time 78321796 ps
CPU time 2.08 seconds
Started Aug 17 04:50:13 PM PDT 24
Finished Aug 17 04:50:15 PM PDT 24
Peak memory 209520 kb
Host smart-0cc1967f-55c3-43f5-8f3f-969365f116a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799507931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1799507931
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2647009795
Short name T288
Test name
Test status
Simulation time 210817725 ps
CPU time 1.84 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:11 PM PDT 24
Peak memory 214804 kb
Host smart-4da38f82-2274-404d-9aec-540be3723c26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647009795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2647009795
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3579599865
Short name T777
Test name
Test status
Simulation time 343573205 ps
CPU time 3.75 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:14 PM PDT 24
Peak memory 208436 kb
Host smart-7b213179-38f7-4708-a98b-5945dfbf47bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579599865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3579599865
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2545772728
Short name T900
Test name
Test status
Simulation time 568845114 ps
CPU time 5.14 seconds
Started Aug 17 04:50:13 PM PDT 24
Finished Aug 17 04:50:18 PM PDT 24
Peak memory 214744 kb
Host smart-eaeb977b-5326-4752-be9e-51a5bdd53e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545772728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2545772728
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.762437694
Short name T338
Test name
Test status
Simulation time 751927053 ps
CPU time 18.11 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:34 PM PDT 24
Peak memory 209244 kb
Host smart-fd083450-b67a-4150-b5e5-3a938f2469aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762437694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.762437694
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3665185712
Short name T503
Test name
Test status
Simulation time 32564457 ps
CPU time 2.31 seconds
Started Aug 17 04:50:16 PM PDT 24
Finished Aug 17 04:50:18 PM PDT 24
Peak memory 207180 kb
Host smart-a8c5ed2e-db82-4cc1-81ac-1f6f43677ebc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665185712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3665185712
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1601524333
Short name T683
Test name
Test status
Simulation time 758432369 ps
CPU time 2.56 seconds
Started Aug 17 04:50:06 PM PDT 24
Finished Aug 17 04:50:09 PM PDT 24
Peak memory 208988 kb
Host smart-3451319b-936a-4516-b25e-baba007059a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601524333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1601524333
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1208113264
Short name T625
Test name
Test status
Simulation time 312867808 ps
CPU time 2.79 seconds
Started Aug 17 04:50:29 PM PDT 24
Finished Aug 17 04:50:32 PM PDT 24
Peak memory 207400 kb
Host smart-595b5e40-8578-4099-b22a-ab779e80d635
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208113264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1208113264
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1252831558
Short name T676
Test name
Test status
Simulation time 305381797 ps
CPU time 1.91 seconds
Started Aug 17 04:50:08 PM PDT 24
Finished Aug 17 04:50:10 PM PDT 24
Peak memory 216156 kb
Host smart-0b5ce761-6bf5-4f92-95ab-dc3c7f753743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252831558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1252831558
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1060340677
Short name T827
Test name
Test status
Simulation time 1053330556 ps
CPU time 3.66 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:14 PM PDT 24
Peak memory 208832 kb
Host smart-b6b7a700-f704-4ca2-a571-2d314c62f34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060340677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1060340677
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1492460340
Short name T263
Test name
Test status
Simulation time 106342466 ps
CPU time 4.49 seconds
Started Aug 17 04:50:15 PM PDT 24
Finished Aug 17 04:50:19 PM PDT 24
Peak memory 214732 kb
Host smart-28591e27-370d-449d-a30f-365f512662a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1492460340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1492460340
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.354705369
Short name T374
Test name
Test status
Simulation time 318226544 ps
CPU time 3.55 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:14 PM PDT 24
Peak memory 210660 kb
Host smart-34cde22a-dda2-4dab-89b8-64e6ebf28e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354705369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.354705369
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1540719979
Short name T563
Test name
Test status
Simulation time 26926679 ps
CPU time 0.79 seconds
Started Aug 17 04:50:46 PM PDT 24
Finished Aug 17 04:50:47 PM PDT 24
Peak memory 206604 kb
Host smart-fc849406-de0d-4e1e-a0f0-a636e1fce1a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540719979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1540719979
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2793053251
Short name T138
Test name
Test status
Simulation time 256292341 ps
CPU time 4.51 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 208744 kb
Host smart-475ca51a-fb77-45f8-bf40-dffff8bf57d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793053251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2793053251
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2147358930
Short name T366
Test name
Test status
Simulation time 288016135 ps
CPU time 8.59 seconds
Started Aug 17 04:50:41 PM PDT 24
Finished Aug 17 04:50:50 PM PDT 24
Peak memory 214668 kb
Host smart-e4191de4-249b-46c2-bf47-adccd1b35eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147358930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2147358930
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2914347361
Short name T487
Test name
Test status
Simulation time 64166285 ps
CPU time 3.18 seconds
Started Aug 17 04:50:42 PM PDT 24
Finished Aug 17 04:50:46 PM PDT 24
Peak memory 214484 kb
Host smart-c2ff01b3-91c5-4865-91ca-08de668b4fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914347361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2914347361
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2394125669
Short name T7
Test name
Test status
Simulation time 354576604 ps
CPU time 4.34 seconds
Started Aug 17 04:50:45 PM PDT 24
Finished Aug 17 04:50:49 PM PDT 24
Peak memory 220260 kb
Host smart-acdbba9f-683c-49ae-b761-a3d5e5b4a6e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394125669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2394125669
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1007708800
Short name T301
Test name
Test status
Simulation time 417952426 ps
CPU time 4.79 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 209548 kb
Host smart-98cd1f57-8630-4613-b149-96c71576349f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007708800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1007708800
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3021872407
Short name T239
Test name
Test status
Simulation time 102041725 ps
CPU time 3.07 seconds
Started Aug 17 04:50:45 PM PDT 24
Finished Aug 17 04:50:48 PM PDT 24
Peak memory 207500 kb
Host smart-209fbfff-0a65-4186-aaec-760ffbbf5f4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021872407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3021872407
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3950599445
Short name T856
Test name
Test status
Simulation time 204154052 ps
CPU time 7.76 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:50:58 PM PDT 24
Peak memory 208748 kb
Host smart-91e56735-ca36-45ce-adab-3b043bfd16b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950599445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3950599445
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.793000822
Short name T590
Test name
Test status
Simulation time 210933784 ps
CPU time 5.5 seconds
Started Aug 17 04:50:54 PM PDT 24
Finished Aug 17 04:51:00 PM PDT 24
Peak memory 208388 kb
Host smart-3d8dd19b-e363-43cc-8634-9a6b38703b23
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793000822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.793000822
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.707124811
Short name T354
Test name
Test status
Simulation time 67859506 ps
CPU time 3.26 seconds
Started Aug 17 04:50:43 PM PDT 24
Finished Aug 17 04:50:46 PM PDT 24
Peak memory 208804 kb
Host smart-a9158833-c94a-4385-8fc7-e2bafdfd65a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707124811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.707124811
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1604348271
Short name T184
Test name
Test status
Simulation time 164278140 ps
CPU time 2.96 seconds
Started Aug 17 04:50:44 PM PDT 24
Finished Aug 17 04:50:47 PM PDT 24
Peak memory 209536 kb
Host smart-c30d19b8-34f4-4f41-928c-c3b45e4e95b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604348271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1604348271
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2273913051
Short name T332
Test name
Test status
Simulation time 1492835346 ps
CPU time 6.57 seconds
Started Aug 17 04:50:45 PM PDT 24
Finished Aug 17 04:50:52 PM PDT 24
Peak memory 210380 kb
Host smart-ff37325a-44d0-443d-9006-7ac08e1bfcfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273913051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2273913051
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.559311190
Short name T397
Test name
Test status
Simulation time 178999342 ps
CPU time 3.4 seconds
Started Aug 17 04:50:47 PM PDT 24
Finished Aug 17 04:50:50 PM PDT 24
Peak memory 215524 kb
Host smart-589e66c9-4ac7-49b5-a50e-78e1530143ed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=559311190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.559311190
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1321142995
Short name T20
Test name
Test status
Simulation time 87950450 ps
CPU time 2.85 seconds
Started Aug 17 04:50:34 PM PDT 24
Finished Aug 17 04:50:37 PM PDT 24
Peak memory 209844 kb
Host smart-d2e52c82-7641-4fee-a30d-963dd1eac70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321142995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1321142995
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3667042109
Short name T128
Test name
Test status
Simulation time 54167411 ps
CPU time 3.56 seconds
Started Aug 17 04:50:52 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 222860 kb
Host smart-80615bc0-856e-4710-9a53-a878cd3307fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667042109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3667042109
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.803809059
Short name T202
Test name
Test status
Simulation time 294842916 ps
CPU time 1.98 seconds
Started Aug 17 04:50:55 PM PDT 24
Finished Aug 17 04:50:57 PM PDT 24
Peak memory 214800 kb
Host smart-de97d7a3-da74-444e-b364-d1886872cffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803809059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.803809059
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.1941292893
Short name T281
Test name
Test status
Simulation time 186612246 ps
CPU time 5.52 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:50:58 PM PDT 24
Peak memory 210072 kb
Host smart-33493af8-3423-459a-a203-8c846f434c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941292893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.1941292893
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2897200299
Short name T461
Test name
Test status
Simulation time 139764536 ps
CPU time 2.27 seconds
Started Aug 17 04:50:49 PM PDT 24
Finished Aug 17 04:50:51 PM PDT 24
Peak memory 207476 kb
Host smart-7cc46ea9-33d8-4adf-aae4-a1e3d32f1582
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897200299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2897200299
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.797334930
Short name T746
Test name
Test status
Simulation time 809783942 ps
CPU time 5.45 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 208692 kb
Host smart-671afe47-eb2c-4797-aafa-b4c8e06c950d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797334930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.797334930
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2493617251
Short name T551
Test name
Test status
Simulation time 65096517 ps
CPU time 3.27 seconds
Started Aug 17 04:50:47 PM PDT 24
Finished Aug 17 04:50:51 PM PDT 24
Peak memory 207284 kb
Host smart-40b624c1-e0fc-4a9d-b2eb-c5426fc5801d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493617251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2493617251
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3579464323
Short name T694
Test name
Test status
Simulation time 117635272 ps
CPU time 3.27 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 214824 kb
Host smart-432b2ccc-0b7e-4990-ab6b-854b13bafb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579464323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3579464323
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1224756155
Short name T172
Test name
Test status
Simulation time 173273959 ps
CPU time 3.7 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:50:54 PM PDT 24
Peak memory 208852 kb
Host smart-1ed1c229-ace9-41fc-ae9f-82cb073cd6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224756155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1224756155
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1866462961
Short name T787
Test name
Test status
Simulation time 370349965 ps
CPU time 8.96 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 207744 kb
Host smart-cac6ed40-9239-4d2a-a37a-e56cb98d81cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866462961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1866462961
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3536668582
Short name T599
Test name
Test status
Simulation time 252777723 ps
CPU time 3.53 seconds
Started Aug 17 04:50:52 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 208020 kb
Host smart-61c2ec3f-26b0-491a-a7c1-db170c98dad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536668582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3536668582
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3800776660
Short name T485
Test name
Test status
Simulation time 37034049 ps
CPU time 1.83 seconds
Started Aug 17 04:50:49 PM PDT 24
Finished Aug 17 04:50:51 PM PDT 24
Peak memory 210564 kb
Host smart-69b7c289-6bc3-4446-a4b1-3ba014dda6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800776660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3800776660
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.446740545
Short name T796
Test name
Test status
Simulation time 14500600 ps
CPU time 0.93 seconds
Started Aug 17 04:51:04 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 206468 kb
Host smart-918d987f-986f-43a1-bedb-d095fce4340a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446740545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.446740545
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2677159962
Short name T414
Test name
Test status
Simulation time 659231684 ps
CPU time 3.44 seconds
Started Aug 17 04:50:51 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 214644 kb
Host smart-5fae4d75-d99a-4f08-ac52-dd0062d7fe7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2677159962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2677159962
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2990638704
Short name T266
Test name
Test status
Simulation time 69850585 ps
CPU time 3.41 seconds
Started Aug 17 04:50:47 PM PDT 24
Finished Aug 17 04:50:51 PM PDT 24
Peak memory 219036 kb
Host smart-5c606068-ab66-4d42-b1ce-ec732bcf2f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990638704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2990638704
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.4105300540
Short name T194
Test name
Test status
Simulation time 85362970 ps
CPU time 2.2 seconds
Started Aug 17 04:50:48 PM PDT 24
Finished Aug 17 04:50:50 PM PDT 24
Peak memory 210160 kb
Host smart-888e803f-54cc-4da9-802d-a1cb0d6588dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105300540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.4105300540
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.646121816
Short name T807
Test name
Test status
Simulation time 97466148 ps
CPU time 4.22 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:50:57 PM PDT 24
Peak memory 215040 kb
Host smart-92e0b291-2701-4dee-b1a8-cf93efeef0f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646121816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.646121816
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.681558174
Short name T242
Test name
Test status
Simulation time 343937092 ps
CPU time 3.63 seconds
Started Aug 17 04:50:56 PM PDT 24
Finished Aug 17 04:50:59 PM PDT 24
Peak memory 219116 kb
Host smart-ffff3260-cc9f-4fa8-8cb2-dde10a67b9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681558174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.681558174
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.3991283380
Short name T58
Test name
Test status
Simulation time 36591707 ps
CPU time 2.41 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:50:53 PM PDT 24
Peak memory 210312 kb
Host smart-18d510cc-a512-468b-abdd-138f9dd07d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991283380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3991283380
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2193903605
Short name T734
Test name
Test status
Simulation time 71153704 ps
CPU time 3.11 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 208820 kb
Host smart-15d6930a-b1bc-4833-99e1-64283aea73d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193903605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2193903605
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2980776116
Short name T453
Test name
Test status
Simulation time 135979186 ps
CPU time 3.19 seconds
Started Aug 17 04:50:42 PM PDT 24
Finished Aug 17 04:50:45 PM PDT 24
Peak memory 208836 kb
Host smart-40a2cb8a-92f7-45e6-9db2-aed203ed1303
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980776116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2980776116
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.656269880
Short name T674
Test name
Test status
Simulation time 180192777 ps
CPU time 2.73 seconds
Started Aug 17 04:50:48 PM PDT 24
Finished Aug 17 04:50:51 PM PDT 24
Peak memory 207464 kb
Host smart-1250aa82-51bc-4a47-852f-ac4a2c808a6b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=656269880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.656269880
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2217035486
Short name T505
Test name
Test status
Simulation time 184930733 ps
CPU time 4.78 seconds
Started Aug 17 04:50:34 PM PDT 24
Finished Aug 17 04:50:39 PM PDT 24
Peak memory 210244 kb
Host smart-adc0a845-5b71-441c-95b4-b2108c22a804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217035486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2217035486
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2383719678
Short name T92
Test name
Test status
Simulation time 125183908 ps
CPU time 2.47 seconds
Started Aug 17 04:50:37 PM PDT 24
Finished Aug 17 04:50:40 PM PDT 24
Peak memory 207168 kb
Host smart-b27d8b37-34d9-4fb4-b8f4-7479b7bf577b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383719678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2383719678
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.350069450
Short name T879
Test name
Test status
Simulation time 880086033 ps
CPU time 10.47 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 208008 kb
Host smart-849c5898-9a87-41a3-933e-86ac832ee876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350069450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.350069450
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3780499215
Short name T504
Test name
Test status
Simulation time 192677109 ps
CPU time 2.21 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 210636 kb
Host smart-0a273556-f81e-47a6-8977-5bc4595e9d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780499215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3780499215
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2065495047
Short name T581
Test name
Test status
Simulation time 34220016 ps
CPU time 0.8 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:50:51 PM PDT 24
Peak memory 206344 kb
Host smart-d0f86d2b-3869-441c-944f-07daa0d040a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065495047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2065495047
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.102344393
Short name T27
Test name
Test status
Simulation time 129275889 ps
CPU time 3.12 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 217120 kb
Host smart-0493c78e-cb77-48f1-a1a6-c6db6eb8ed01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102344393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.102344393
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.4181627156
Short name T705
Test name
Test status
Simulation time 89518935 ps
CPU time 1.83 seconds
Started Aug 17 04:50:54 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 214720 kb
Host smart-c8769ceb-208b-454f-a896-5bbdab20dd60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181627156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.4181627156
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.369734020
Short name T901
Test name
Test status
Simulation time 103619558 ps
CPU time 2.84 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:01 PM PDT 24
Peak memory 214900 kb
Host smart-2541665e-753e-4252-85ba-020aa9b3ea9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369734020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.369734020
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.275996116
Short name T276
Test name
Test status
Simulation time 34728433 ps
CPU time 2.34 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 214656 kb
Host smart-5e1ebc61-dc73-4918-a338-6171d33ad925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275996116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.275996116
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1188012773
Short name T548
Test name
Test status
Simulation time 197414560 ps
CPU time 5.73 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 219476 kb
Host smart-c3e44e07-b610-47f4-a9f2-0a0ac96ce351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188012773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1188012773
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3478961497
Short name T559
Test name
Test status
Simulation time 1189697736 ps
CPU time 3.97 seconds
Started Aug 17 04:50:52 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 209764 kb
Host smart-28e308ba-9eb3-4f8d-97ae-184c7a5a51f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478961497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3478961497
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.472145260
Short name T297
Test name
Test status
Simulation time 349953969 ps
CPU time 5.72 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 209020 kb
Host smart-2c994367-d0ed-4b83-9cf0-f8f4a76579a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472145260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.472145260
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3965311089
Short name T269
Test name
Test status
Simulation time 255098057 ps
CPU time 3.22 seconds
Started Aug 17 04:50:55 PM PDT 24
Finished Aug 17 04:50:58 PM PDT 24
Peak memory 207200 kb
Host smart-5efaf1f2-77ba-4369-adb3-25a91563cb6b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965311089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3965311089
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1371139771
Short name T785
Test name
Test status
Simulation time 287751208 ps
CPU time 3.74 seconds
Started Aug 17 04:51:08 PM PDT 24
Finished Aug 17 04:51:12 PM PDT 24
Peak memory 209028 kb
Host smart-c1b1e089-5033-4563-b768-2440f3e4e44e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371139771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1371139771
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3589995595
Short name T776
Test name
Test status
Simulation time 960511291 ps
CPU time 6.48 seconds
Started Aug 17 04:50:56 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 209184 kb
Host smart-cd17ba67-159c-4b36-b1e2-e0fdc9dca611
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589995595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3589995595
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.66789393
Short name T786
Test name
Test status
Simulation time 52336820 ps
CPU time 2.68 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 208492 kb
Host smart-0dbfd878-418a-4295-b0b0-ff1dceaa43a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66789393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.66789393
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1885545918
Short name T437
Test name
Test status
Simulation time 40014121 ps
CPU time 1.77 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 207324 kb
Host smart-24dea067-e80c-40d1-8f1c-a66dc532ed15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885545918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1885545918
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2087809161
Short name T544
Test name
Test status
Simulation time 2602916787 ps
CPU time 23.2 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:26 PM PDT 24
Peak memory 217192 kb
Host smart-b5bd595a-33e3-4e9e-9d05-50f34a443b7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087809161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2087809161
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2377350826
Short name T852
Test name
Test status
Simulation time 180334044 ps
CPU time 6.68 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 218812 kb
Host smart-b13dffa2-8bc5-4960-bc06-53eb5252259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377350826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2377350826
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3491578451
Short name T814
Test name
Test status
Simulation time 583634826 ps
CPU time 3.59 seconds
Started Aug 17 04:51:09 PM PDT 24
Finished Aug 17 04:51:13 PM PDT 24
Peak memory 211044 kb
Host smart-745a6291-6190-4d2a-b167-81118f086bdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491578451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3491578451
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2252208001
Short name T445
Test name
Test status
Simulation time 46488861 ps
CPU time 0.76 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:00 PM PDT 24
Peak memory 206400 kb
Host smart-1b98cbf5-8911-4a52-a57a-378be5526fe3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252208001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2252208001
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.386541744
Short name T391
Test name
Test status
Simulation time 129536069 ps
CPU time 2.76 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:00 PM PDT 24
Peak memory 214700 kb
Host smart-5555d317-aaba-4dd7-af3e-d28e8cbf73b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386541744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.386541744
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1819494279
Short name T766
Test name
Test status
Simulation time 402741290 ps
CPU time 3.92 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 218992 kb
Host smart-bb04b7c7-020e-4a51-94f6-583373980cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819494279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1819494279
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1579354412
Short name T688
Test name
Test status
Simulation time 91338726 ps
CPU time 1.73 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:50:52 PM PDT 24
Peak memory 209192 kb
Host smart-87d32e95-a109-4dc9-a094-6110555c4fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579354412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1579354412
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2191936286
Short name T806
Test name
Test status
Simulation time 33896888 ps
CPU time 2.19 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 214756 kb
Host smart-34a77f8e-9e71-4635-8a6c-5897b485cc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191936286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2191936286
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3088272148
Short name T831
Test name
Test status
Simulation time 134687675 ps
CPU time 4.31 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 211864 kb
Host smart-a2e3927a-57fc-43ce-9c84-b84b58cb30a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088272148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3088272148
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.599851380
Short name T598
Test name
Test status
Simulation time 58470031 ps
CPU time 2.7 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:51:00 PM PDT 24
Peak memory 222752 kb
Host smart-1f42c9d9-d5ef-48f0-a5fe-1932661a87e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599851380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.599851380
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2255200262
Short name T793
Test name
Test status
Simulation time 198333546 ps
CPU time 2.91 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 210708 kb
Host smart-49e85fab-059d-4e9d-8f26-cc2b161054ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255200262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2255200262
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2170002182
Short name T577
Test name
Test status
Simulation time 1668565229 ps
CPU time 41.78 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:51:39 PM PDT 24
Peak memory 208688 kb
Host smart-a8dae4ca-f7ea-4638-bda7-fed27acc4c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170002182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2170002182
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2045536886
Short name T346
Test name
Test status
Simulation time 116766190 ps
CPU time 2.76 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:01 PM PDT 24
Peak memory 207336 kb
Host smart-71c49f76-9da5-4016-81d8-566c74b20a55
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045536886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2045536886
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.384375699
Short name T742
Test name
Test status
Simulation time 50292368 ps
CPU time 1.98 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:50:59 PM PDT 24
Peak memory 209100 kb
Host smart-41d09d62-4ded-4f70-ae08-d173a3bf9dfe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384375699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.384375699
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.581281970
Short name T701
Test name
Test status
Simulation time 261166407 ps
CPU time 2.8 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:51:00 PM PDT 24
Peak memory 209052 kb
Host smart-116b4708-d279-4d6b-b95d-f766db1d18d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581281970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.581281970
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.696358212
Short name T408
Test name
Test status
Simulation time 490268284 ps
CPU time 2.85 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:51:00 PM PDT 24
Peak memory 220592 kb
Host smart-fb54ab36-da01-4391-9274-2e558001cbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=696358212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.696358212
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3131442424
Short name T521
Test name
Test status
Simulation time 7541990670 ps
CPU time 35.62 seconds
Started Aug 17 04:50:54 PM PDT 24
Finished Aug 17 04:51:29 PM PDT 24
Peak memory 209012 kb
Host smart-46b558e7-c438-4eed-9b63-70aec3bc3d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131442424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3131442424
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2633901408
Short name T268
Test name
Test status
Simulation time 844766923 ps
CPU time 16.96 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:51:14 PM PDT 24
Peak memory 222944 kb
Host smart-a10cdc7f-4d05-465a-9ff2-405344b92bfb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633901408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2633901408
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3446083144
Short name T710
Test name
Test status
Simulation time 599487623 ps
CPU time 7 seconds
Started Aug 17 04:51:04 PM PDT 24
Finished Aug 17 04:51:11 PM PDT 24
Peak memory 214768 kb
Host smart-8c86c212-c1a1-4ad3-b65f-90077fa142ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446083144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3446083144
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.587319212
Short name T709
Test name
Test status
Simulation time 35521371 ps
CPU time 1.91 seconds
Started Aug 17 04:50:52 PM PDT 24
Finished Aug 17 04:50:54 PM PDT 24
Peak memory 210600 kb
Host smart-d9e374d5-ca6b-4aef-9788-1546ca4a257a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587319212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.587319212
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.966940171
Short name T765
Test name
Test status
Simulation time 108209720 ps
CPU time 0.83 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:50:58 PM PDT 24
Peak memory 206372 kb
Host smart-09312158-e83b-4c1f-857b-33227fccc519
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966940171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.966940171
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2799368665
Short name T307
Test name
Test status
Simulation time 197137446 ps
CPU time 3.76 seconds
Started Aug 17 04:51:06 PM PDT 24
Finished Aug 17 04:51:10 PM PDT 24
Peak memory 215708 kb
Host smart-4b67b75b-d938-42f9-b6c8-1395bf352ddd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2799368665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2799368665
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1980533977
Short name T209
Test name
Test status
Simulation time 127590088 ps
CPU time 1.8 seconds
Started Aug 17 04:51:08 PM PDT 24
Finished Aug 17 04:51:10 PM PDT 24
Peak memory 208512 kb
Host smart-f1b62bd1-b5f3-4fc6-bd74-8e3360ba56a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980533977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1980533977
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.548177297
Short name T347
Test name
Test status
Simulation time 558421232 ps
CPU time 2.75 seconds
Started Aug 17 04:50:54 PM PDT 24
Finished Aug 17 04:50:57 PM PDT 24
Peak memory 214744 kb
Host smart-0dac353e-7e71-4b4e-9fb3-f2d3bbf19cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548177297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.548177297
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2600741907
Short name T53
Test name
Test status
Simulation time 1152709432 ps
CPU time 7.44 seconds
Started Aug 17 04:51:06 PM PDT 24
Finished Aug 17 04:51:13 PM PDT 24
Peak memory 214704 kb
Host smart-80bef10d-34a8-4710-b123-da99b0cf1961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600741907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2600741907
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.630601279
Short name T518
Test name
Test status
Simulation time 35160133 ps
CPU time 2.71 seconds
Started Aug 17 04:50:54 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 220744 kb
Host smart-42837b77-1958-4f56-8e91-82e731a7c928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630601279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.630601279
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.2654701726
Short name T451
Test name
Test status
Simulation time 98087136 ps
CPU time 4.81 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 208220 kb
Host smart-9965ceba-be3c-4425-b430-a93712b2337a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2654701726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.2654701726
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3792836659
Short name T539
Test name
Test status
Simulation time 1122734009 ps
CPU time 14.02 seconds
Started Aug 17 04:50:54 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 208496 kb
Host smart-b95cf7a9-1f29-4849-b2aa-1be290b0fa46
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3792836659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3792836659
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2047255914
Short name T853
Test name
Test status
Simulation time 499380518 ps
CPU time 4.57 seconds
Started Aug 17 04:50:56 PM PDT 24
Finished Aug 17 04:51:01 PM PDT 24
Peak memory 209148 kb
Host smart-35531b6e-22bb-4f37-bac4-fc0c7823b5f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047255914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2047255914
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3515960849
Short name T767
Test name
Test status
Simulation time 80794823 ps
CPU time 3.63 seconds
Started Aug 17 04:51:04 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 208520 kb
Host smart-252ca58b-8408-4b61-8127-1c81d02054e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515960849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3515960849
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2957190810
Short name T617
Test name
Test status
Simulation time 186990947 ps
CPU time 3.43 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 208624 kb
Host smart-98faf3d2-3b99-40fd-83ce-9034bd3baf9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957190810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2957190810
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.853766889
Short name T692
Test name
Test status
Simulation time 45392856 ps
CPU time 2.21 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:00 PM PDT 24
Peak memory 208916 kb
Host smart-94c80890-1176-4c77-b100-010e94d84576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853766889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.853766889
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3186711150
Short name T325
Test name
Test status
Simulation time 2133588424 ps
CPU time 9.48 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 218868 kb
Host smart-371a41f3-5413-47e3-a7c4-d90d0f726064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186711150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3186711150
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.291566433
Short name T192
Test name
Test status
Simulation time 102395344 ps
CPU time 2.83 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 210616 kb
Host smart-4183db54-7f29-49e6-adbf-6ce3b1f50e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291566433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.291566433
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.150359430
Short name T442
Test name
Test status
Simulation time 30211894 ps
CPU time 0.81 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:50:58 PM PDT 24
Peak memory 206412 kb
Host smart-a350e01d-5386-4f5d-a23b-82be74fe892e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150359430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.150359430
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.4022558571
Short name T25
Test name
Test status
Simulation time 253965152 ps
CPU time 2.28 seconds
Started Aug 17 04:50:56 PM PDT 24
Finished Aug 17 04:50:58 PM PDT 24
Peak memory 223248 kb
Host smart-41125d83-d26a-4d43-af68-27cfe4013e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022558571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.4022558571
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.958614730
Short name T126
Test name
Test status
Simulation time 39076744 ps
CPU time 1.58 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:00 PM PDT 24
Peak memory 208688 kb
Host smart-fa8d2834-c2d9-4e61-b89e-c3921055eb5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958614730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.958614730
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.598058894
Short name T249
Test name
Test status
Simulation time 68740709 ps
CPU time 3.57 seconds
Started Aug 17 04:50:55 PM PDT 24
Finished Aug 17 04:50:59 PM PDT 24
Peak memory 220132 kb
Host smart-dfdb5499-ab8b-4138-9697-f1f4727a9649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598058894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.598058894
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3520386019
Short name T294
Test name
Test status
Simulation time 421926151 ps
CPU time 3.6 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 214800 kb
Host smart-3e7b14bc-0598-4d89-bc0e-a7d92f9d6427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520386019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3520386019
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1762760917
Short name T216
Test name
Test status
Simulation time 265468019 ps
CPU time 3.54 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 214760 kb
Host smart-7998f5eb-27cf-4b7c-9ec4-98a55682db0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762760917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1762760917
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.295065349
Short name T456
Test name
Test status
Simulation time 892662426 ps
CPU time 6.6 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 207232 kb
Host smart-052f1be1-573a-400e-a760-6f9cedf9d354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295065349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.295065349
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2742950231
Short name T195
Test name
Test status
Simulation time 231133025 ps
CPU time 4.92 seconds
Started Aug 17 04:50:54 PM PDT 24
Finished Aug 17 04:50:59 PM PDT 24
Peak memory 208944 kb
Host smart-6bde3621-2e51-4c35-86c4-884dd6d22e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742950231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2742950231
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2126008195
Short name T671
Test name
Test status
Simulation time 21017965 ps
CPU time 1.86 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 207696 kb
Host smart-7b59c152-ed72-4d67-8a11-2be786656998
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126008195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2126008195
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1675135166
Short name T431
Test name
Test status
Simulation time 538599574 ps
CPU time 3.96 seconds
Started Aug 17 04:51:07 PM PDT 24
Finished Aug 17 04:51:11 PM PDT 24
Peak memory 209204 kb
Host smart-8b3a78a0-9861-40de-ab94-31e456a5fc2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675135166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1675135166
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.474212622
Short name T747
Test name
Test status
Simulation time 611514250 ps
CPU time 6.23 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 208444 kb
Host smart-bff27814-e37a-4b5f-9ae8-565441355d7b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474212622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.474212622
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1301492670
Short name T201
Test name
Test status
Simulation time 99374522 ps
CPU time 2.72 seconds
Started Aug 17 04:50:55 PM PDT 24
Finished Aug 17 04:50:58 PM PDT 24
Peak memory 210288 kb
Host smart-76230ac0-a795-4680-80a0-808a0d9e09c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301492670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1301492670
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2963806725
Short name T903
Test name
Test status
Simulation time 99258536 ps
CPU time 2.77 seconds
Started Aug 17 04:50:53 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 207348 kb
Host smart-628a84e3-bd5c-4af3-8d88-df92b145c490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963806725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2963806725
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.4253440167
Short name T210
Test name
Test status
Simulation time 10839376516 ps
CPU time 103.66 seconds
Started Aug 17 04:51:01 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 222988 kb
Host smart-f71f82b0-de00-4415-88a7-ab9caa6648ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253440167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.4253440167
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2783387136
Short name T687
Test name
Test status
Simulation time 100051970 ps
CPU time 3.92 seconds
Started Aug 17 04:51:15 PM PDT 24
Finished Aug 17 04:51:19 PM PDT 24
Peak memory 207800 kb
Host smart-4833f9ea-6ea8-4894-947c-60aae66410cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783387136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2783387136
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.905623396
Short name T629
Test name
Test status
Simulation time 206690938 ps
CPU time 3.52 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 210968 kb
Host smart-31cfe153-53f0-422a-84a0-8b2bc57df117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905623396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.905623396
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2502255400
Short name T836
Test name
Test status
Simulation time 17235274 ps
CPU time 0.79 seconds
Started Aug 17 04:51:06 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 206272 kb
Host smart-7c15289f-d920-4703-b5fe-9a0eb638b13b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502255400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2502255400
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1588207876
Short name T393
Test name
Test status
Simulation time 189818453 ps
CPU time 3.07 seconds
Started Aug 17 04:51:09 PM PDT 24
Finished Aug 17 04:51:12 PM PDT 24
Peak memory 215904 kb
Host smart-fc06a4f6-9c43-462e-ae4d-e508dba23890
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1588207876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1588207876
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.934929720
Short name T895
Test name
Test status
Simulation time 55541573 ps
CPU time 1.99 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:50:59 PM PDT 24
Peak memory 214856 kb
Host smart-8bef483f-b516-4bf8-9d20-ab2250a4a673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934929720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.934929720
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2899311830
Short name T800
Test name
Test status
Simulation time 143033779 ps
CPU time 2.64 seconds
Started Aug 17 04:51:05 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 206648 kb
Host smart-9f4b8ef6-e30a-4d58-93f9-34982e86714d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899311830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2899311830
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2703810351
Short name T320
Test name
Test status
Simulation time 109302440 ps
CPU time 3.59 seconds
Started Aug 17 04:51:13 PM PDT 24
Finished Aug 17 04:51:17 PM PDT 24
Peak memory 222800 kb
Host smart-25305a59-e6e3-4594-adc8-502deaaa87d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703810351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2703810351
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3556514626
Short name T271
Test name
Test status
Simulation time 500352548 ps
CPU time 5.7 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 209200 kb
Host smart-9f4b69b8-5be0-4f0c-9caa-5fdcb37f1e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556514626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3556514626
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.4216113716
Short name T641
Test name
Test status
Simulation time 2840831860 ps
CPU time 26.46 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:27 PM PDT 24
Peak memory 209304 kb
Host smart-c775ea54-16a5-48ef-b61d-cdb85750a63e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216113716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.4216113716
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1591598699
Short name T869
Test name
Test status
Simulation time 123002280 ps
CPU time 3.13 seconds
Started Aug 17 04:51:04 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 207464 kb
Host smart-104e07fc-f537-40ec-a1ca-35e5b6c12732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591598699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1591598699
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1921330653
Short name T847
Test name
Test status
Simulation time 93445240 ps
CPU time 4.02 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 209076 kb
Host smart-423e85bd-f106-4aa5-9938-9b54867dbce1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921330653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1921330653
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2833999697
Short name T481
Test name
Test status
Simulation time 55014272 ps
CPU time 2.7 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 208744 kb
Host smart-fca21a70-d84c-4612-9f86-22ea6df11e0f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833999697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2833999697
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2085204816
Short name T788
Test name
Test status
Simulation time 631465415 ps
CPU time 4.96 seconds
Started Aug 17 04:51:01 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 209304 kb
Host smart-d2fe6342-ef2c-44d1-b72a-ca447cf452f7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2085204816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2085204816
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.764617350
Short name T778
Test name
Test status
Simulation time 295346490 ps
CPU time 4.9 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 209224 kb
Host smart-0d1f87b3-bba5-4a79-b7e1-c9f10bfa5039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764617350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.764617350
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.508496806
Short name T864
Test name
Test status
Simulation time 175138925 ps
CPU time 3.65 seconds
Started Aug 17 04:50:55 PM PDT 24
Finished Aug 17 04:50:58 PM PDT 24
Peak memory 208380 kb
Host smart-e708328a-c69a-41e2-99ae-146bb6b83418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508496806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.508496806
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1606727231
Short name T183
Test name
Test status
Simulation time 4811720491 ps
CPU time 24.53 seconds
Started Aug 17 04:51:04 PM PDT 24
Finished Aug 17 04:51:29 PM PDT 24
Peak memory 208600 kb
Host smart-ef5542cd-a2a8-4534-bcca-4f2742708634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606727231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1606727231
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2927330339
Short name T860
Test name
Test status
Simulation time 346065219 ps
CPU time 1.92 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 210348 kb
Host smart-819c2e6c-b6bc-45e5-8ad3-3b4c1d8d06aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927330339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2927330339
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.938767001
Short name T57
Test name
Test status
Simulation time 72503809 ps
CPU time 0.75 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:01 PM PDT 24
Peak memory 206316 kb
Host smart-51fe7d85-5b54-4465-928c-5bff498c5c60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938767001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.938767001
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.599713533
Short name T233
Test name
Test status
Simulation time 227001101 ps
CPU time 2.44 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 214748 kb
Host smart-542a850d-b5d6-4120-a89b-4d23462428f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=599713533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.599713533
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2624983221
Short name T29
Test name
Test status
Simulation time 183922331 ps
CPU time 2.68 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 210584 kb
Host smart-302c8ccc-3a46-4d84-9371-5ba3e68f88bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624983221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2624983221
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.375026984
Short name T868
Test name
Test status
Simulation time 37776970 ps
CPU time 1.72 seconds
Started Aug 17 04:51:08 PM PDT 24
Finished Aug 17 04:51:10 PM PDT 24
Peak memory 207380 kb
Host smart-c75e0985-0882-44fa-9846-a9652ef508de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375026984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.375026984
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.3132825463
Short name T52
Test name
Test status
Simulation time 115395789 ps
CPU time 2.5 seconds
Started Aug 17 04:51:12 PM PDT 24
Finished Aug 17 04:51:14 PM PDT 24
Peak memory 209532 kb
Host smart-19527cf6-3755-4f87-b7b5-be2094a1ad60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132825463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.3132825463
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2307573363
Short name T45
Test name
Test status
Simulation time 48647264 ps
CPU time 2.67 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 214696 kb
Host smart-1dce58a7-42b1-45aa-bcc3-948cba1163af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307573363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2307573363
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1278435616
Short name T511
Test name
Test status
Simulation time 125805220 ps
CPU time 3.96 seconds
Started Aug 17 04:51:01 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 211032 kb
Host smart-8d9a2d7e-6285-4e1e-a522-702f0a42684e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278435616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1278435616
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3400161136
Short name T602
Test name
Test status
Simulation time 239383259 ps
CPU time 4.42 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 210288 kb
Host smart-0da64abf-592c-4b78-bc8b-f8318c41c222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400161136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3400161136
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1816666632
Short name T444
Test name
Test status
Simulation time 131406239 ps
CPU time 2.29 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 207472 kb
Host smart-3d1654a8-5440-44c5-ae5b-81d3f0a12ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816666632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1816666632
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1182805199
Short name T589
Test name
Test status
Simulation time 239112964 ps
CPU time 3.7 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 209032 kb
Host smart-76e87525-720e-4cd5-b54c-2e7520de2f0d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182805199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1182805199
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.4059332337
Short name T697
Test name
Test status
Simulation time 431072098 ps
CPU time 5.49 seconds
Started Aug 17 04:51:04 PM PDT 24
Finished Aug 17 04:51:09 PM PDT 24
Peak memory 208680 kb
Host smart-1a6d191a-725e-4111-9bcb-e3a7ca0f315b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059332337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4059332337
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1413535387
Short name T554
Test name
Test status
Simulation time 48461292 ps
CPU time 2.14 seconds
Started Aug 17 04:51:19 PM PDT 24
Finished Aug 17 04:51:26 PM PDT 24
Peak memory 208940 kb
Host smart-7b9963a6-19d0-43e5-8e51-0ecfef4af8a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413535387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1413535387
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2918248847
Short name T401
Test name
Test status
Simulation time 41865621 ps
CPU time 1.86 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 208632 kb
Host smart-f204b958-8940-45a4-9837-5d8dfee4433c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918248847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2918248847
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3806454004
Short name T556
Test name
Test status
Simulation time 82473257 ps
CPU time 3.32 seconds
Started Aug 17 04:51:06 PM PDT 24
Finished Aug 17 04:51:09 PM PDT 24
Peak memory 209136 kb
Host smart-be1fb0d5-7278-4cb9-8cf6-5c2cc7712b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806454004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3806454004
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.128206497
Short name T139
Test name
Test status
Simulation time 428985699 ps
CPU time 11.58 seconds
Started Aug 17 04:51:01 PM PDT 24
Finished Aug 17 04:51:12 PM PDT 24
Peak memory 216592 kb
Host smart-f6461b38-5f1c-441e-be28-b782f62cbf1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128206497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.128206497
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1067029671
Short name T173
Test name
Test status
Simulation time 208343612 ps
CPU time 2.28 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 210384 kb
Host smart-6aeed8fd-500d-4d33-926e-a3bbeac8cc8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067029671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1067029671
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3443338175
Short name T889
Test name
Test status
Simulation time 18082221 ps
CPU time 0.83 seconds
Started Aug 17 04:51:20 PM PDT 24
Finished Aug 17 04:51:21 PM PDT 24
Peak memory 206388 kb
Host smart-0f5117b8-bd0e-41fa-ba46-b386d62d8051
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443338175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3443338175
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1385637031
Short name T360
Test name
Test status
Simulation time 161061353 ps
CPU time 3.39 seconds
Started Aug 17 04:51:04 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 215584 kb
Host smart-85d325c1-2bb6-4d9c-9a28-136e5081b6d1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1385637031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1385637031
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.167264693
Short name T26
Test name
Test status
Simulation time 259286893 ps
CPU time 3.24 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 210440 kb
Host smart-a8fa9916-569d-41eb-998e-1ed0071ec591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167264693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.167264693
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1806571279
Short name T818
Test name
Test status
Simulation time 60148988 ps
CPU time 2.74 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 218624 kb
Host smart-103bc0a5-19ea-44c8-9ea6-b20495ab47b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806571279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1806571279
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3116707136
Short name T364
Test name
Test status
Simulation time 189494944 ps
CPU time 5.76 seconds
Started Aug 17 04:51:01 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 214744 kb
Host smart-0dab461a-dee1-4ef9-84fc-492f1875f880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116707136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3116707136
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3523480257
Short name T293
Test name
Test status
Simulation time 587433339 ps
CPU time 3.81 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 222828 kb
Host smart-d2d8d770-fff8-4b36-8639-87dba53eeae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523480257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3523480257
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.662492250
Short name T811
Test name
Test status
Simulation time 174804668 ps
CPU time 1.99 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:01 PM PDT 24
Peak memory 222796 kb
Host smart-14585fa9-8908-4899-8db8-1446bc1b937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=662492250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.662492250
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1132268529
Short name T546
Test name
Test status
Simulation time 221540907 ps
CPU time 6.04 seconds
Started Aug 17 04:51:16 PM PDT 24
Finished Aug 17 04:51:22 PM PDT 24
Peak memory 214748 kb
Host smart-54dd828e-d174-441e-8eda-03ecfc4cf366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132268529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1132268529
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3583107940
Short name T841
Test name
Test status
Simulation time 64291677 ps
CPU time 2.37 seconds
Started Aug 17 04:51:07 PM PDT 24
Finished Aug 17 04:51:09 PM PDT 24
Peak memory 207320 kb
Host smart-0fe7185f-b0a8-4ed0-83fd-7ec653107406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583107940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3583107940
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1439795836
Short name T384
Test name
Test status
Simulation time 19335873 ps
CPU time 1.82 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:01 PM PDT 24
Peak memory 207332 kb
Host smart-ea877542-82fe-4bed-90ca-901c3b34ac4d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439795836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1439795836
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3001992804
Short name T522
Test name
Test status
Simulation time 104771704 ps
CPU time 4.52 seconds
Started Aug 17 04:51:12 PM PDT 24
Finished Aug 17 04:51:17 PM PDT 24
Peak memory 209092 kb
Host smart-e6c21927-657b-456e-8551-d7312eabbc62
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001992804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3001992804
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2791116249
Short name T508
Test name
Test status
Simulation time 143695642 ps
CPU time 1.83 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 207276 kb
Host smart-6c5151d6-787e-4440-bbbd-a58db42bd2b9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791116249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2791116249
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1000422486
Short name T718
Test name
Test status
Simulation time 45177322 ps
CPU time 2.42 seconds
Started Aug 17 04:51:06 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 209368 kb
Host smart-5586a31d-2848-48f5-a5a9-db0d860db4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000422486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1000422486
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2384592839
Short name T419
Test name
Test status
Simulation time 73424152 ps
CPU time 3.12 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 208840 kb
Host smart-d25987d9-13d4-40cb-a07c-495b5e818010
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384592839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2384592839
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3161861983
Short name T174
Test name
Test status
Simulation time 640974200 ps
CPU time 24.37 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:23 PM PDT 24
Peak memory 221324 kb
Host smart-2f596709-5452-4ab3-9c8d-3109af7f0dab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161861983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3161861983
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2948063353
Short name T12
Test name
Test status
Simulation time 371751437 ps
CPU time 13.37 seconds
Started Aug 17 04:51:11 PM PDT 24
Finished Aug 17 04:51:25 PM PDT 24
Peak memory 222952 kb
Host smart-166f0461-efd5-4037-b1ba-3ccc72437c32
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948063353 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2948063353
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1235804973
Short name T791
Test name
Test status
Simulation time 263623490 ps
CPU time 6.64 seconds
Started Aug 17 04:51:07 PM PDT 24
Finished Aug 17 04:51:19 PM PDT 24
Peak memory 209300 kb
Host smart-01a5851d-8f5b-4f32-a64b-d1af06ca8a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235804973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1235804973
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3530328454
Short name T730
Test name
Test status
Simulation time 19978978 ps
CPU time 0.75 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 206344 kb
Host smart-62595068-02ab-44c7-b6d4-c16df76ef951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530328454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3530328454
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2451512082
Short name T594
Test name
Test status
Simulation time 269862255 ps
CPU time 4 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:14 PM PDT 24
Peak memory 223128 kb
Host smart-9a3ebe31-233c-4211-9202-45c5eae47617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451512082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2451512082
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2145836930
Short name T439
Test name
Test status
Simulation time 106892157 ps
CPU time 1.66 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:11 PM PDT 24
Peak memory 207880 kb
Host smart-8a18c69e-41b2-40ad-8d7a-95258b9536d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145836930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2145836930
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3870888788
Short name T496
Test name
Test status
Simulation time 67849765 ps
CPU time 2.36 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:14 PM PDT 24
Peak memory 214764 kb
Host smart-63b7b5a7-7dd7-4b42-ad07-83242a2f0d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870888788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3870888788
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2534299258
Short name T275
Test name
Test status
Simulation time 1228933208 ps
CPU time 2.67 seconds
Started Aug 17 04:50:07 PM PDT 24
Finished Aug 17 04:50:10 PM PDT 24
Peak memory 214764 kb
Host smart-205ea156-47a9-401d-b0cb-01b2a7d637b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534299258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2534299258
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.4015398597
Short name T353
Test name
Test status
Simulation time 1153918743 ps
CPU time 5.8 seconds
Started Aug 17 04:50:06 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 209500 kb
Host smart-a927df1f-7ef6-4953-a55b-f5925ece8de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015398597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.4015398597
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.983711367
Short name T10
Test name
Test status
Simulation time 956200442 ps
CPU time 17.62 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:29 PM PDT 24
Peak memory 235652 kb
Host smart-1c5e3107-63cf-43cd-80c2-2f805baf94f9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983711367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.983711367
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.824603287
Short name T584
Test name
Test status
Simulation time 206275211 ps
CPU time 2.9 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 207420 kb
Host smart-98e027da-c994-473a-aeb9-9f38a4bff500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824603287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.824603287
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2053502224
Short name T466
Test name
Test status
Simulation time 30387102 ps
CPU time 2.33 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 207944 kb
Host smart-ac9c8dcd-21bf-45f0-900b-f117c2cfb27e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2053502224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2053502224
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3732105742
Short name T700
Test name
Test status
Simulation time 187919591 ps
CPU time 3.22 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:14 PM PDT 24
Peak memory 208444 kb
Host smart-8cb2a84a-2f4c-437c-90b1-804acd09fed4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732105742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3732105742
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.2610603522
Short name T761
Test name
Test status
Simulation time 92078853 ps
CPU time 2.68 seconds
Started Aug 17 04:50:07 PM PDT 24
Finished Aug 17 04:50:10 PM PDT 24
Peak memory 207224 kb
Host smart-c70be5de-938f-4850-a968-59d63d331898
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610603522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.2610603522
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3783241352
Short name T826
Test name
Test status
Simulation time 170773813 ps
CPU time 1.6 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:10 PM PDT 24
Peak memory 208472 kb
Host smart-0de115c3-d7aa-4480-8247-da925d966f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783241352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3783241352
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3376814578
Short name T484
Test name
Test status
Simulation time 899104957 ps
CPU time 15.3 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:25 PM PDT 24
Peak memory 208300 kb
Host smart-6991519c-a2b8-49c5-b371-4790cc04f4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376814578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3376814578
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1189776533
Short name T333
Test name
Test status
Simulation time 261637024 ps
CPU time 13.33 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:23 PM PDT 24
Peak memory 221748 kb
Host smart-e2122a38-a022-4294-a45e-e52a74f56789
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189776533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1189776533
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1412270030
Short name T163
Test name
Test status
Simulation time 197493669 ps
CPU time 6.85 seconds
Started Aug 17 04:50:13 PM PDT 24
Finished Aug 17 04:50:20 PM PDT 24
Peak memory 222948 kb
Host smart-a84c7ef0-8b5d-4e98-ab88-91e2ab01a841
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412270030 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1412270030
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2056730919
Short name T660
Test name
Test status
Simulation time 1610478107 ps
CPU time 6.98 seconds
Started Aug 17 04:50:14 PM PDT 24
Finished Aug 17 04:50:21 PM PDT 24
Peak memory 208740 kb
Host smart-cd76ca72-6ce2-479f-863e-d96566d75d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056730919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2056730919
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1732925073
Short name T558
Test name
Test status
Simulation time 11318623 ps
CPU time 0.67 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:50:58 PM PDT 24
Peak memory 206376 kb
Host smart-c4f17d1c-3fbc-4b9f-8025-02af30c5d14d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732925073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1732925073
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1857052054
Short name T103
Test name
Test status
Simulation time 129249280 ps
CPU time 3.98 seconds
Started Aug 17 04:50:57 PM PDT 24
Finished Aug 17 04:51:01 PM PDT 24
Peak memory 214708 kb
Host smart-2254eec1-b518-4f66-87ca-d8244e3da39a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1857052054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1857052054
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3042979090
Short name T886
Test name
Test status
Simulation time 31958874 ps
CPU time 1.93 seconds
Started Aug 17 04:51:05 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 208532 kb
Host smart-0c0a4e10-40af-4208-b02d-81c8efeba84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042979090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3042979090
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1493136760
Short name T471
Test name
Test status
Simulation time 180424689 ps
CPU time 2.19 seconds
Started Aug 17 04:50:56 PM PDT 24
Finished Aug 17 04:50:58 PM PDT 24
Peak memory 209140 kb
Host smart-15ba0d88-4498-4ea2-8f76-89b8dd11b521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493136760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1493136760
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1965602214
Short name T315
Test name
Test status
Simulation time 117034209 ps
CPU time 3.15 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 214808 kb
Host smart-41f6f49e-87d3-49db-94e1-312980217839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965602214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1965602214
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.1951248619
Short name T319
Test name
Test status
Simulation time 107925600 ps
CPU time 2.07 seconds
Started Aug 17 04:51:10 PM PDT 24
Finished Aug 17 04:51:12 PM PDT 24
Peak memory 214732 kb
Host smart-c40e587d-63ca-40ea-bab7-97698e0b8877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1951248619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.1951248619
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2076250252
Short name T669
Test name
Test status
Simulation time 48251720 ps
CPU time 1.32 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:00 PM PDT 24
Peak memory 205456 kb
Host smart-7bb05941-eccb-4519-8a7a-9061bdbd536b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076250252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2076250252
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.246907368
Short name T773
Test name
Test status
Simulation time 54487994 ps
CPU time 2.52 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 208488 kb
Host smart-29abde3d-be2b-429c-ad63-7c340b17ad7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246907368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.246907368
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2264228226
Short name T543
Test name
Test status
Simulation time 53012795 ps
CPU time 2.57 seconds
Started Aug 17 04:51:04 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 206320 kb
Host smart-bb03a1e1-cd34-4f44-8a72-77b4ebc7bb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264228226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2264228226
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1039450115
Short name T523
Test name
Test status
Simulation time 707422413 ps
CPU time 16.49 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:29 PM PDT 24
Peak memory 209392 kb
Host smart-5ff74d7d-c8df-470d-b413-df35fe76e6db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039450115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1039450115
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.4072868362
Short name T330
Test name
Test status
Simulation time 224548258 ps
CPU time 5.79 seconds
Started Aug 17 04:51:16 PM PDT 24
Finished Aug 17 04:51:22 PM PDT 24
Peak memory 209156 kb
Host smart-97f14958-4d70-4754-adc7-f452b875cf2a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072868362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.4072868362
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1663000584
Short name T717
Test name
Test status
Simulation time 76706676 ps
CPU time 2.61 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 209104 kb
Host smart-a45b670b-d133-4557-8e0c-af4cc01f22a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663000584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1663000584
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3993576391
Short name T631
Test name
Test status
Simulation time 211654661 ps
CPU time 2.74 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:01 PM PDT 24
Peak memory 207984 kb
Host smart-41c93d80-9d70-48d9-8be0-dd064eb7e781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993576391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3993576391
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2467728627
Short name T457
Test name
Test status
Simulation time 146198233 ps
CPU time 3.24 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 207776 kb
Host smart-70de352a-574b-41bb-addb-39a08f18b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467728627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2467728627
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.135068888
Short name T164
Test name
Test status
Simulation time 3081552511 ps
CPU time 27.62 seconds
Started Aug 17 04:50:58 PM PDT 24
Finished Aug 17 04:51:26 PM PDT 24
Peak memory 223104 kb
Host smart-8260cb1c-699b-43aa-bd2c-404abf59eec2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135068888 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.135068888
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2858467593
Short name T486
Test name
Test status
Simulation time 283493886 ps
CPU time 3.81 seconds
Started Aug 17 04:51:25 PM PDT 24
Finished Aug 17 04:51:34 PM PDT 24
Peak memory 207380 kb
Host smart-6324462c-1a44-4f95-8b0a-845f9bdca272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858467593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2858467593
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1247909614
Short name T728
Test name
Test status
Simulation time 81366404 ps
CPU time 2.34 seconds
Started Aug 17 04:51:07 PM PDT 24
Finished Aug 17 04:51:14 PM PDT 24
Peak memory 210680 kb
Host smart-7ae5fe05-e9cb-46f8-845f-9442a3b25a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247909614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1247909614
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.454261530
Short name T516
Test name
Test status
Simulation time 101149210 ps
CPU time 0.89 seconds
Started Aug 17 04:51:16 PM PDT 24
Finished Aug 17 04:51:16 PM PDT 24
Peak memory 206332 kb
Host smart-7c06fef7-a15b-4506-a72b-1805d33078cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454261530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.454261530
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3288697516
Short name T883
Test name
Test status
Simulation time 86849223 ps
CPU time 3.58 seconds
Started Aug 17 04:51:04 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 209184 kb
Host smart-991dabc0-2af2-44d8-bab9-86d4af01d895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288697516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3288697516
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3779044690
Short name T784
Test name
Test status
Simulation time 55350995 ps
CPU time 1.91 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 214784 kb
Host smart-868b12ee-2aa8-4e8d-a2fe-7f55284e6b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779044690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3779044690
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1464727346
Short name T291
Test name
Test status
Simulation time 252085694 ps
CPU time 2.01 seconds
Started Aug 17 04:51:13 PM PDT 24
Finished Aug 17 04:51:15 PM PDT 24
Peak memory 214648 kb
Host smart-61f4e53a-28a0-4f64-8cf7-5dcbdb1b55ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464727346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1464727346
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1015192712
Short name T821
Test name
Test status
Simulation time 220331679 ps
CPU time 4.3 seconds
Started Aug 17 04:51:01 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 210376 kb
Host smart-7e085c23-b816-46b6-bf9e-c845cc677571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015192712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1015192712
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3771213124
Short name T67
Test name
Test status
Simulation time 525873945 ps
CPU time 17.83 seconds
Started Aug 17 04:51:08 PM PDT 24
Finished Aug 17 04:51:26 PM PDT 24
Peak memory 213740 kb
Host smart-fc52e035-e658-4db0-8896-9d65f373843c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771213124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3771213124
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2025828293
Short name T199
Test name
Test status
Simulation time 526305136 ps
CPU time 7.43 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:11 PM PDT 24
Peak memory 208884 kb
Host smart-5785602d-dcea-4ebd-a70d-747ff362d4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025828293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2025828293
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1261397897
Short name T834
Test name
Test status
Simulation time 73879863 ps
CPU time 3.36 seconds
Started Aug 17 04:51:21 PM PDT 24
Finished Aug 17 04:51:25 PM PDT 24
Peak memory 209080 kb
Host smart-6a8782b4-9dfb-4484-adac-4a2c79aa63cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261397897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1261397897
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3427118646
Short name T187
Test name
Test status
Simulation time 377041949 ps
CPU time 5.42 seconds
Started Aug 17 04:50:56 PM PDT 24
Finished Aug 17 04:51:01 PM PDT 24
Peak memory 208284 kb
Host smart-7a12f75a-7f03-4226-afd8-104d8303e2a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427118646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3427118646
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3542129866
Short name T712
Test name
Test status
Simulation time 472324958 ps
CPU time 2.82 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 209168 kb
Host smart-edb27107-1608-460d-8dfb-28bfbd6207f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542129866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3542129866
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1189814635
Short name T597
Test name
Test status
Simulation time 56183754 ps
CPU time 2.71 seconds
Started Aug 17 04:51:01 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 209196 kb
Host smart-09dca7cb-8006-4806-8483-f10f777e7af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189814635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1189814635
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3216923776
Short name T759
Test name
Test status
Simulation time 668995403 ps
CPU time 10.93 seconds
Started Aug 17 04:51:01 PM PDT 24
Finished Aug 17 04:51:12 PM PDT 24
Peak memory 209016 kb
Host smart-55efd734-2910-4c4d-9036-2eb1e65de74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216923776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3216923776
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.143046559
Short name T865
Test name
Test status
Simulation time 362608237 ps
CPU time 4.84 seconds
Started Aug 17 04:51:04 PM PDT 24
Finished Aug 17 04:51:09 PM PDT 24
Peak memory 214976 kb
Host smart-c90769ec-2050-4fed-9096-65e63d9b237d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143046559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.143046559
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1577100751
Short name T96
Test name
Test status
Simulation time 66410659 ps
CPU time 2.39 seconds
Started Aug 17 04:51:19 PM PDT 24
Finished Aug 17 04:51:21 PM PDT 24
Peak memory 210496 kb
Host smart-f23f2e34-1a03-4a0f-9d4e-cefdb2df5832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577100751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1577100751
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1969901859
Short name T861
Test name
Test status
Simulation time 10708537 ps
CPU time 0.81 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 206384 kb
Host smart-095d7e56-b046-44fd-b049-78f404c00d02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969901859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1969901859
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2892516638
Short name T378
Test name
Test status
Simulation time 118736832 ps
CPU time 2.74 seconds
Started Aug 17 04:51:08 PM PDT 24
Finished Aug 17 04:51:11 PM PDT 24
Peak memory 214768 kb
Host smart-49141868-f02e-40de-bf9e-8ef9e6cb95e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2892516638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2892516638
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3852525979
Short name T579
Test name
Test status
Simulation time 228992597 ps
CPU time 1.87 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 214740 kb
Host smart-10c0d0a4-93a7-4fc4-b825-e504a2815dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852525979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3852525979
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.310235743
Short name T71
Test name
Test status
Simulation time 404016003 ps
CPU time 3.43 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 218540 kb
Host smart-159d8e0f-848c-439d-a3a7-1b828de1ba69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310235743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.310235743
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3579266186
Short name T780
Test name
Test status
Simulation time 146316894 ps
CPU time 2.72 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 214744 kb
Host smart-f5ac117b-3538-4cfe-860f-93e3006719b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579266186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3579266186
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3944871622
Short name T255
Test name
Test status
Simulation time 52975029 ps
CPU time 1.91 seconds
Started Aug 17 04:51:14 PM PDT 24
Finished Aug 17 04:51:16 PM PDT 24
Peak memory 218916 kb
Host smart-07e37e55-ffcc-46b4-9d29-d25bd94bc94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944871622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3944871622
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2881688387
Short name T298
Test name
Test status
Simulation time 230884419 ps
CPU time 3.97 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 220900 kb
Host smart-f701f73c-969d-4e69-85e1-0e2e3d0e0445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881688387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2881688387
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2613361176
Short name T428
Test name
Test status
Simulation time 3863221741 ps
CPU time 23.74 seconds
Started Aug 17 04:51:11 PM PDT 24
Finished Aug 17 04:51:35 PM PDT 24
Peak memory 208716 kb
Host smart-aec2b1ac-2353-4aed-9d28-d3cdbd50986b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613361176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2613361176
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1388988241
Short name T265
Test name
Test status
Simulation time 2740352504 ps
CPU time 52.05 seconds
Started Aug 17 04:51:15 PM PDT 24
Finished Aug 17 04:52:07 PM PDT 24
Peak memory 209532 kb
Host smart-947954cc-e0ef-4e24-9e12-aa89eca8d774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388988241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1388988241
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3551647662
Short name T62
Test name
Test status
Simulation time 57635439 ps
CPU time 2.97 seconds
Started Aug 17 04:51:15 PM PDT 24
Finished Aug 17 04:51:18 PM PDT 24
Peak memory 209048 kb
Host smart-78e2a7c2-faea-43b8-a41f-e757bac2d5e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551647662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3551647662
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2922713653
Short name T648
Test name
Test status
Simulation time 155449568 ps
CPU time 4.5 seconds
Started Aug 17 04:51:05 PM PDT 24
Finished Aug 17 04:51:14 PM PDT 24
Peak memory 208248 kb
Host smart-d6d12807-61c6-4601-b23e-2bd4445fbf5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922713653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2922713653
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.245229281
Short name T287
Test name
Test status
Simulation time 39441949 ps
CPU time 2.45 seconds
Started Aug 17 04:51:05 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 207500 kb
Host smart-fa01dfad-cf4d-4830-9b98-ec6d37699978
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245229281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.245229281
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3233628450
Short name T538
Test name
Test status
Simulation time 103338536 ps
CPU time 1.91 seconds
Started Aug 17 04:51:04 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 207688 kb
Host smart-bbb311fb-ea4e-41e9-99d0-0477b38d2a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233628450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3233628450
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1787240593
Short name T452
Test name
Test status
Simulation time 408649867 ps
CPU time 4 seconds
Started Aug 17 04:51:43 PM PDT 24
Finished Aug 17 04:51:47 PM PDT 24
Peak memory 207760 kb
Host smart-45edb333-8e51-4ab8-a17f-6d4fea0c5a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787240593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1787240593
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3466301527
Short name T789
Test name
Test status
Simulation time 9972023340 ps
CPU time 234.45 seconds
Started Aug 17 04:51:07 PM PDT 24
Finished Aug 17 04:55:02 PM PDT 24
Peak memory 222956 kb
Host smart-6dc67af9-e3ae-4ea3-bb5a-0ac1d0d8956f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466301527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3466301527
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1567255887
Short name T592
Test name
Test status
Simulation time 132079379 ps
CPU time 4.17 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 208348 kb
Host smart-e5069f16-0ca7-4baa-bb31-a2974a1f951b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567255887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1567255887
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3255181661
Short name T645
Test name
Test status
Simulation time 56194318 ps
CPU time 2.01 seconds
Started Aug 17 04:51:18 PM PDT 24
Finished Aug 17 04:51:20 PM PDT 24
Peak memory 210712 kb
Host smart-533393f2-6880-4e42-adad-abbd24b1a947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255181661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3255181661
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3328129327
Short name T642
Test name
Test status
Simulation time 10830467 ps
CPU time 0.73 seconds
Started Aug 17 04:51:05 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 206460 kb
Host smart-b62bdd3a-44d8-4e72-8f0e-708ea2907d13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328129327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3328129327
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.256882602
Short name T664
Test name
Test status
Simulation time 57145404 ps
CPU time 2.25 seconds
Started Aug 17 04:51:14 PM PDT 24
Finished Aug 17 04:51:17 PM PDT 24
Peak memory 208736 kb
Host smart-8dcf622f-af4b-4a82-9157-0e1bebdc81b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256882602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.256882602
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3233785517
Short name T876
Test name
Test status
Simulation time 311017489 ps
CPU time 3.29 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 214736 kb
Host smart-fd98d6c1-0918-41d1-b5a9-e2986c85e5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233785517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3233785517
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3969867405
Short name T535
Test name
Test status
Simulation time 93713937 ps
CPU time 3.51 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 210352 kb
Host smart-778d568b-535c-4896-a56f-7e5f63760265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969867405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3969867405
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3721179058
Short name T341
Test name
Test status
Simulation time 192773523 ps
CPU time 3.39 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 207284 kb
Host smart-d16c37b6-73b0-4280-91c9-36260bcb45ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721179058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3721179058
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.4106546107
Short name T531
Test name
Test status
Simulation time 107069918 ps
CPU time 2.66 seconds
Started Aug 17 04:51:11 PM PDT 24
Finished Aug 17 04:51:14 PM PDT 24
Peak memory 207280 kb
Host smart-1880870c-3a35-445d-8e2f-1b8424086d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106546107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.4106546107
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3002432906
Short name T615
Test name
Test status
Simulation time 463329680 ps
CPU time 4.01 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 207488 kb
Host smart-4dc00839-8b52-4bbc-b2ef-451da64b1082
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002432906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3002432906
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3455993307
Short name T626
Test name
Test status
Simulation time 185754107 ps
CPU time 5.83 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:13 PM PDT 24
Peak memory 208404 kb
Host smart-a8a757c1-8e13-473d-b1b8-2244f50d16a7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455993307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3455993307
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3253112414
Short name T606
Test name
Test status
Simulation time 61364086 ps
CPU time 2.78 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:03 PM PDT 24
Peak memory 209040 kb
Host smart-8341b470-f02c-4cf1-9d80-9baf2c76b19f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3253112414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3253112414
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.62332835
Short name T699
Test name
Test status
Simulation time 196369132 ps
CPU time 2.77 seconds
Started Aug 17 04:51:08 PM PDT 24
Finished Aug 17 04:51:11 PM PDT 24
Peak memory 216004 kb
Host smart-77360310-049c-4d17-9dea-0f6b6b6f5db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62332835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.62332835
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2761606077
Short name T744
Test name
Test status
Simulation time 32866754 ps
CPU time 2.13 seconds
Started Aug 17 04:51:36 PM PDT 24
Finished Aug 17 04:51:38 PM PDT 24
Peak memory 207412 kb
Host smart-cea51a95-4e24-4772-a479-82921e38ca56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761606077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2761606077
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.92791244
Short name T215
Test name
Test status
Simulation time 2741157437 ps
CPU time 35.77 seconds
Started Aug 17 04:51:25 PM PDT 24
Finished Aug 17 04:52:01 PM PDT 24
Peak memory 216612 kb
Host smart-4c8cf03f-42d9-4ed8-a4b3-e8b8860dfafb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92791244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.92791244
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2535393730
Short name T161
Test name
Test status
Simulation time 584612283 ps
CPU time 10.55 seconds
Started Aug 17 04:51:31 PM PDT 24
Finished Aug 17 04:51:42 PM PDT 24
Peak memory 223000 kb
Host smart-a72087c2-10d3-466b-9dee-c9d8cd6ce1f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535393730 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2535393730
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3167500489
Short name T327
Test name
Test status
Simulation time 137327370 ps
CPU time 2.41 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 218672 kb
Host smart-c96a82c4-0a2a-40c9-ae7f-baf9ef6935f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167500489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3167500489
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3386446166
Short name T623
Test name
Test status
Simulation time 102444795 ps
CPU time 2.3 seconds
Started Aug 17 04:51:00 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 210748 kb
Host smart-bce81bde-0d97-4770-bf81-f4235773c4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386446166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3386446166
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1410267346
Short name T429
Test name
Test status
Simulation time 11934846 ps
CPU time 0.71 seconds
Started Aug 17 04:51:06 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 206308 kb
Host smart-4173cb59-5e1a-470e-88d2-c3eb5f9f63ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410267346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1410267346
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.466344274
Short name T236
Test name
Test status
Simulation time 175246017 ps
CPU time 2.9 seconds
Started Aug 17 04:51:30 PM PDT 24
Finished Aug 17 04:51:33 PM PDT 24
Peak memory 214692 kb
Host smart-0be714b7-e80f-4a20-9b41-fb6884c0ddb0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=466344274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.466344274
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1279171872
Short name T823
Test name
Test status
Simulation time 102293867 ps
CPU time 3.25 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 218884 kb
Host smart-c3c5de95-09fe-42cb-a9d1-2b882dbe6481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279171872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1279171872
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3571319383
Short name T848
Test name
Test status
Simulation time 32763639 ps
CPU time 2.24 seconds
Started Aug 17 04:51:10 PM PDT 24
Finished Aug 17 04:51:12 PM PDT 24
Peak memory 220964 kb
Host smart-ef100fc3-658a-474f-bad6-4661edbb075c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571319383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3571319383
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2755917254
Short name T321
Test name
Test status
Simulation time 75167868 ps
CPU time 2.54 seconds
Started Aug 17 04:51:38 PM PDT 24
Finished Aug 17 04:51:41 PM PDT 24
Peak memory 214624 kb
Host smart-09936778-3905-41c3-97e9-82a3fd8e416f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755917254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2755917254
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2133841308
Short name T702
Test name
Test status
Simulation time 124527069 ps
CPU time 2.39 seconds
Started Aug 17 04:51:23 PM PDT 24
Finished Aug 17 04:51:26 PM PDT 24
Peak memory 209284 kb
Host smart-61d2c458-137d-4ad5-bf77-cb3ffc56aa5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133841308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2133841308
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3886668452
Short name T627
Test name
Test status
Simulation time 266311635 ps
CPU time 3.55 seconds
Started Aug 17 04:51:27 PM PDT 24
Finished Aug 17 04:51:31 PM PDT 24
Peak memory 209268 kb
Host smart-4f4ce43b-0ce8-49a0-8f68-96369d8da35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886668452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3886668452
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2011387854
Short name T575
Test name
Test status
Simulation time 63189386 ps
CPU time 2.81 seconds
Started Aug 17 04:51:11 PM PDT 24
Finished Aug 17 04:51:14 PM PDT 24
Peak memory 207292 kb
Host smart-1e07cb2a-8d7f-4f7f-b058-8a64b5c0ce89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011387854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2011387854
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.285671711
Short name T383
Test name
Test status
Simulation time 909759208 ps
CPU time 6.39 seconds
Started Aug 17 04:51:01 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 209204 kb
Host smart-65b0ba66-cc50-4f84-8ee6-2f20b3e226ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285671711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.285671711
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4268011753
Short name T743
Test name
Test status
Simulation time 535274983 ps
CPU time 4.03 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 209076 kb
Host smart-5a2e5a48-aa8d-4973-89d0-0d826fe43219
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268011753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4268011753
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2423581859
Short name T296
Test name
Test status
Simulation time 188770758 ps
CPU time 5.69 seconds
Started Aug 17 04:51:21 PM PDT 24
Finished Aug 17 04:51:27 PM PDT 24
Peak memory 209452 kb
Host smart-f9bcbc1f-581f-48da-ac40-4e0c99260a63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423581859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2423581859
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1167381386
Short name T458
Test name
Test status
Simulation time 105956499 ps
CPU time 4.04 seconds
Started Aug 17 04:51:27 PM PDT 24
Finished Aug 17 04:51:31 PM PDT 24
Peak memory 209700 kb
Host smart-ae8dd95d-15a9-4138-b519-9b35fc85aac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167381386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1167381386
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.839240442
Short name T892
Test name
Test status
Simulation time 184244773 ps
CPU time 2.44 seconds
Started Aug 17 04:51:03 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 207216 kb
Host smart-817ce27f-64cc-4d86-9291-26c9ec68ebbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839240442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.839240442
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.255170508
Short name T162
Test name
Test status
Simulation time 605529612 ps
CPU time 10.82 seconds
Started Aug 17 04:51:06 PM PDT 24
Finished Aug 17 04:51:16 PM PDT 24
Peak memory 222948 kb
Host smart-180f427b-365c-445c-80f8-72fa6adbfe94
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255170508 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.255170508
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.686733039
Short name T632
Test name
Test status
Simulation time 963001900 ps
CPU time 22.4 seconds
Started Aug 17 04:51:23 PM PDT 24
Finished Aug 17 04:51:46 PM PDT 24
Peak memory 214752 kb
Host smart-01786af4-a607-4c8d-8457-96c92ea975ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686733039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.686733039
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.2200096415
Short name T420
Test name
Test status
Simulation time 35370191 ps
CPU time 1.51 seconds
Started Aug 17 04:51:05 PM PDT 24
Finished Aug 17 04:51:07 PM PDT 24
Peak memory 210060 kb
Host smart-ad93b2fd-9f21-46d5-9676-b83c1b643820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200096415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2200096415
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2851183949
Short name T424
Test name
Test status
Simulation time 20766861 ps
CPU time 0.74 seconds
Started Aug 17 04:51:37 PM PDT 24
Finished Aug 17 04:51:38 PM PDT 24
Peak memory 206384 kb
Host smart-388f3eeb-e313-451f-b837-23766f73753a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851183949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2851183949
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2087934186
Short name T555
Test name
Test status
Simulation time 346502570 ps
CPU time 2.52 seconds
Started Aug 17 04:51:20 PM PDT 24
Finished Aug 17 04:51:23 PM PDT 24
Peak memory 221836 kb
Host smart-2366a021-e033-4d69-a265-a5ed11c9e68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087934186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2087934186
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1840552353
Short name T407
Test name
Test status
Simulation time 60699391 ps
CPU time 2.55 seconds
Started Aug 17 04:51:07 PM PDT 24
Finished Aug 17 04:51:10 PM PDT 24
Peak memory 208068 kb
Host smart-2133633b-b18f-4ee1-9f44-51641abcbda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840552353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1840552353
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.496926206
Short name T857
Test name
Test status
Simulation time 102133834 ps
CPU time 2.23 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 209392 kb
Host smart-d1b650d1-36ca-4b1d-9cc0-8858f4981b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496926206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.496926206
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.783566518
Short name T647
Test name
Test status
Simulation time 277600646 ps
CPU time 3.07 seconds
Started Aug 17 04:51:27 PM PDT 24
Finished Aug 17 04:51:31 PM PDT 24
Peak memory 221996 kb
Host smart-ead0b34f-d4e9-4001-920e-7a60044c3b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783566518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.783566518
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1825819086
Short name T259
Test name
Test status
Simulation time 101394766 ps
CPU time 4.26 seconds
Started Aug 17 04:51:07 PM PDT 24
Finished Aug 17 04:51:11 PM PDT 24
Peak memory 222764 kb
Host smart-00e1fa71-db57-43f4-915a-26558d3d4619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825819086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1825819086
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.4039776695
Short name T672
Test name
Test status
Simulation time 439816823 ps
CPU time 14.34 seconds
Started Aug 17 04:51:31 PM PDT 24
Finished Aug 17 04:51:46 PM PDT 24
Peak memory 222892 kb
Host smart-ea909a78-0a46-4761-9cd9-52878cb49a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039776695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.4039776695
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.4049249434
Short name T448
Test name
Test status
Simulation time 600499479 ps
CPU time 5.87 seconds
Started Aug 17 04:51:27 PM PDT 24
Finished Aug 17 04:51:33 PM PDT 24
Peak memory 207396 kb
Host smart-47f39dfb-831b-4717-ab8b-306e2bb87738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049249434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.4049249434
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2141121645
Short name T715
Test name
Test status
Simulation time 175669306 ps
CPU time 3.21 seconds
Started Aug 17 04:51:30 PM PDT 24
Finished Aug 17 04:51:33 PM PDT 24
Peak memory 207404 kb
Host smart-c3793380-5095-480f-8f8a-4da431a69ee4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141121645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2141121645
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1304942003
Short name T93
Test name
Test status
Simulation time 124257278 ps
CPU time 2.73 seconds
Started Aug 17 04:51:02 PM PDT 24
Finished Aug 17 04:51:05 PM PDT 24
Peak memory 207436 kb
Host smart-79c38298-a7b3-46f1-85bd-2e0ef7cf4b00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304942003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1304942003
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2427251446
Short name T469
Test name
Test status
Simulation time 1835614983 ps
CPU time 40.47 seconds
Started Aug 17 04:51:30 PM PDT 24
Finished Aug 17 04:52:11 PM PDT 24
Peak memory 208920 kb
Host smart-741e2da2-483a-4f57-b872-ed9c30f592fb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427251446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2427251446
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.521398727
Short name T14
Test name
Test status
Simulation time 615201770 ps
CPU time 5.68 seconds
Started Aug 17 04:51:05 PM PDT 24
Finished Aug 17 04:51:11 PM PDT 24
Peak memory 208104 kb
Host smart-7571bb3d-21c2-4a10-bdf4-05967d4fdf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521398727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.521398727
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3332299271
Short name T422
Test name
Test status
Simulation time 418370168 ps
CPU time 2.75 seconds
Started Aug 17 04:51:37 PM PDT 24
Finished Aug 17 04:51:40 PM PDT 24
Peak memory 207216 kb
Host smart-ecea88a0-5d1c-427f-a746-2d8a916af83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3332299271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3332299271
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2270930188
Short name T312
Test name
Test status
Simulation time 1375052363 ps
CPU time 15.18 seconds
Started Aug 17 04:51:04 PM PDT 24
Finished Aug 17 04:51:19 PM PDT 24
Peak memory 221296 kb
Host smart-28bcb2e2-965b-47da-977e-b99368ecbf37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270930188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2270930188
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2216607912
Short name T668
Test name
Test status
Simulation time 179497269 ps
CPU time 4.39 seconds
Started Aug 17 04:51:08 PM PDT 24
Finished Aug 17 04:51:12 PM PDT 24
Peak memory 208040 kb
Host smart-8674a888-1be4-4954-abf0-fe68c8616c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216607912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2216607912
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3134535794
Short name T870
Test name
Test status
Simulation time 617694982 ps
CPU time 3.21 seconds
Started Aug 17 04:51:11 PM PDT 24
Finished Aug 17 04:51:14 PM PDT 24
Peak memory 210828 kb
Host smart-0697999e-69d0-4bf1-bc9b-ce7f675e2f96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134535794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3134535794
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3101190137
Short name T433
Test name
Test status
Simulation time 15533120 ps
CPU time 0.82 seconds
Started Aug 17 04:51:31 PM PDT 24
Finished Aug 17 04:51:32 PM PDT 24
Peak memory 206392 kb
Host smart-744220fd-5faa-4d38-9681-ba4d51816bae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101190137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3101190137
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.999048250
Short name T390
Test name
Test status
Simulation time 185648818 ps
CPU time 3.85 seconds
Started Aug 17 04:51:33 PM PDT 24
Finished Aug 17 04:51:37 PM PDT 24
Peak memory 216216 kb
Host smart-8fd676df-3b14-4e0e-899c-2612931e14ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=999048250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.999048250
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.743110881
Short name T667
Test name
Test status
Simulation time 1464340253 ps
CPU time 7.5 seconds
Started Aug 17 04:51:19 PM PDT 24
Finished Aug 17 04:51:27 PM PDT 24
Peak memory 215044 kb
Host smart-15c5bc9c-36f7-4837-a6ad-5b10a9a0242c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743110881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.743110881
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3147750236
Short name T872
Test name
Test status
Simulation time 1737350330 ps
CPU time 4.9 seconds
Started Aug 17 04:51:23 PM PDT 24
Finished Aug 17 04:51:29 PM PDT 24
Peak memory 214708 kb
Host smart-40863235-d39b-4434-8eb7-35b6f534908e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147750236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3147750236
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3835053914
Short name T808
Test name
Test status
Simulation time 1222303529 ps
CPU time 3.87 seconds
Started Aug 17 04:51:33 PM PDT 24
Finished Aug 17 04:51:37 PM PDT 24
Peak memory 220220 kb
Host smart-89b7f398-6044-45c7-9df8-9031e83fe9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835053914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3835053914
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.4167688924
Short name T331
Test name
Test status
Simulation time 119923117 ps
CPU time 3.92 seconds
Started Aug 17 04:51:42 PM PDT 24
Finished Aug 17 04:51:46 PM PDT 24
Peak memory 214724 kb
Host smart-44b6ce01-498f-422c-aae2-3abfc05c4939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4167688924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.4167688924
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3152456393
Short name T497
Test name
Test status
Simulation time 110976043 ps
CPU time 2.97 seconds
Started Aug 17 04:51:27 PM PDT 24
Finished Aug 17 04:51:30 PM PDT 24
Peak memory 207360 kb
Host smart-7310834a-7ddd-4bff-91a5-9e2024457797
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152456393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3152456393
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2885120387
Short name T495
Test name
Test status
Simulation time 64691114 ps
CPU time 3.2 seconds
Started Aug 17 04:51:26 PM PDT 24
Finished Aug 17 04:51:29 PM PDT 24
Peak memory 208936 kb
Host smart-8a5dcd14-b305-4a9a-b4f9-ff515578ecfa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885120387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2885120387
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.290274647
Short name T200
Test name
Test status
Simulation time 66952088 ps
CPU time 2.4 seconds
Started Aug 17 04:51:15 PM PDT 24
Finished Aug 17 04:51:18 PM PDT 24
Peak memory 207348 kb
Host smart-c370edc6-66b2-43e8-8e1f-784be3a02a0f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290274647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.290274647
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3247666568
Short name T560
Test name
Test status
Simulation time 198050854 ps
CPU time 3.78 seconds
Started Aug 17 04:51:17 PM PDT 24
Finished Aug 17 04:51:21 PM PDT 24
Peak memory 222796 kb
Host smart-e2d8acee-3199-4798-b20f-eb0a43dcb752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247666568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3247666568
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2435778261
Short name T580
Test name
Test status
Simulation time 539473286 ps
CPU time 2.93 seconds
Started Aug 17 04:51:20 PM PDT 24
Finished Aug 17 04:51:23 PM PDT 24
Peak memory 209224 kb
Host smart-247ddbf6-9f6a-4017-8e66-472d0c770395
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435778261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2435778261
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.995805737
Short name T212
Test name
Test status
Simulation time 13295442195 ps
CPU time 141.34 seconds
Started Aug 17 04:51:24 PM PDT 24
Finished Aug 17 04:53:46 PM PDT 24
Peak memory 219668 kb
Host smart-1da5f018-8b00-44dd-95b1-973b8a1b8b5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995805737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.995805737
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.314394241
Short name T819
Test name
Test status
Simulation time 1585522897 ps
CPU time 23.31 seconds
Started Aug 17 04:51:33 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 223020 kb
Host smart-f16bb1ec-54cb-4d7e-b0f6-7853de3750d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314394241 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.314394241
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.720068017
Short name T605
Test name
Test status
Simulation time 221110454 ps
CPU time 5.33 seconds
Started Aug 17 04:51:14 PM PDT 24
Finished Aug 17 04:51:19 PM PDT 24
Peak memory 208784 kb
Host smart-9e9d6402-38cd-4bdd-9cb2-8e39d0b3baeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720068017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.720068017
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1136770538
Short name T434
Test name
Test status
Simulation time 67597050 ps
CPU time 1.79 seconds
Started Aug 17 04:51:36 PM PDT 24
Finished Aug 17 04:51:38 PM PDT 24
Peak memory 209248 kb
Host smart-968420b9-7228-4ec6-a718-5e0e2560bf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136770538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1136770538
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.892675141
Short name T817
Test name
Test status
Simulation time 9283838 ps
CPU time 0.73 seconds
Started Aug 17 04:51:26 PM PDT 24
Finished Aug 17 04:51:27 PM PDT 24
Peak memory 206360 kb
Host smart-0c1dc57f-d226-4787-80d1-0e11859d8d5b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892675141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.892675141
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.4028698174
Short name T588
Test name
Test status
Simulation time 1207766194 ps
CPU time 2.69 seconds
Started Aug 17 04:51:27 PM PDT 24
Finished Aug 17 04:51:30 PM PDT 24
Peak memory 217004 kb
Host smart-57a5f7ea-efe5-444b-91c9-658053167005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028698174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.4028698174
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.449842119
Short name T585
Test name
Test status
Simulation time 370164917 ps
CPU time 3.31 seconds
Started Aug 17 04:51:35 PM PDT 24
Finished Aug 17 04:51:38 PM PDT 24
Peak memory 222924 kb
Host smart-a29f0b94-a3df-4424-adcb-5d1835b82deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449842119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.449842119
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2854403403
Short name T245
Test name
Test status
Simulation time 220147638 ps
CPU time 2.56 seconds
Started Aug 17 04:51:33 PM PDT 24
Finished Aug 17 04:51:36 PM PDT 24
Peak memory 214668 kb
Host smart-27409228-8f44-4725-a497-eefa510943bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854403403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2854403403
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2736711096
Short name T256
Test name
Test status
Simulation time 238259728 ps
CPU time 3.54 seconds
Started Aug 17 04:51:32 PM PDT 24
Finished Aug 17 04:51:36 PM PDT 24
Peak memory 214704 kb
Host smart-014e5b49-ab5e-485f-8b83-471ed32a391b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736711096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2736711096
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2408708977
Short name T399
Test name
Test status
Simulation time 464235032 ps
CPU time 2.88 seconds
Started Aug 17 04:51:41 PM PDT 24
Finished Aug 17 04:51:45 PM PDT 24
Peak memory 214724 kb
Host smart-ba102cd9-3bc0-4e6f-8f4a-91c3a69f0661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408708977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2408708977
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1662908074
Short name T379
Test name
Test status
Simulation time 457583649 ps
CPU time 5.31 seconds
Started Aug 17 04:51:20 PM PDT 24
Finished Aug 17 04:51:25 PM PDT 24
Peak memory 208040 kb
Host smart-f729f049-c86a-4632-b386-ac8cd6d7bf89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662908074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1662908074
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3945949266
Short name T295
Test name
Test status
Simulation time 106488345 ps
CPU time 2.99 seconds
Started Aug 17 04:51:24 PM PDT 24
Finished Aug 17 04:51:27 PM PDT 24
Peak memory 208792 kb
Host smart-a79aca5a-281c-466d-b3c7-8fd55e322636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945949266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3945949266
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.591605795
Short name T474
Test name
Test status
Simulation time 554906535 ps
CPU time 6.54 seconds
Started Aug 17 04:51:23 PM PDT 24
Finished Aug 17 04:51:30 PM PDT 24
Peak memory 208944 kb
Host smart-c7275956-c6fd-4651-b8e0-f7b88e8bba9d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591605795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.591605795
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.77130336
Short name T888
Test name
Test status
Simulation time 194963815 ps
CPU time 2.81 seconds
Started Aug 17 04:51:42 PM PDT 24
Finished Aug 17 04:51:45 PM PDT 24
Peak memory 209160 kb
Host smart-8e7f2a20-84ae-41ef-88ec-6a133572ce13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77130336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.77130336
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1473333080
Short name T454
Test name
Test status
Simulation time 252412200 ps
CPU time 4.2 seconds
Started Aug 17 04:51:23 PM PDT 24
Finished Aug 17 04:51:27 PM PDT 24
Peak memory 207224 kb
Host smart-e3629d98-ae0c-43a9-b534-acfb30cf75ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473333080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1473333080
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_smoke.10501042
Short name T686
Test name
Test status
Simulation time 3877718040 ps
CPU time 16.4 seconds
Started Aug 17 04:51:24 PM PDT 24
Finished Aug 17 04:51:41 PM PDT 24
Peak memory 208788 kb
Host smart-989a9d54-17e0-4bd5-b995-dd4d1b266848
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10501042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.10501042
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1944427300
Short name T794
Test name
Test status
Simulation time 462231220 ps
CPU time 5.58 seconds
Started Aug 17 04:51:35 PM PDT 24
Finished Aug 17 04:51:41 PM PDT 24
Peak memory 215824 kb
Host smart-616b70fb-a427-4ae1-9d55-3e98b39e96e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944427300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1944427300
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2254073600
Short name T666
Test name
Test status
Simulation time 165791337 ps
CPU time 3.81 seconds
Started Aug 17 04:51:38 PM PDT 24
Finished Aug 17 04:51:42 PM PDT 24
Peak memory 210252 kb
Host smart-f212169b-7c64-4e63-9c0b-bf74f13a13d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254073600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2254073600
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.837950926
Short name T527
Test name
Test status
Simulation time 504140304 ps
CPU time 3.52 seconds
Started Aug 17 04:51:48 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 210884 kb
Host smart-50761680-462a-4af0-82e6-f1be5bc5a934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837950926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.837950926
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.542622240
Short name T905
Test name
Test status
Simulation time 23356806 ps
CPU time 1.06 seconds
Started Aug 17 04:51:30 PM PDT 24
Finished Aug 17 04:51:31 PM PDT 24
Peak memory 206512 kb
Host smart-0f3eba28-11f3-4363-8e85-40c696b72326
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542622240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.542622240
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2722930999
Short name T832
Test name
Test status
Simulation time 564329523 ps
CPU time 5.5 seconds
Started Aug 17 04:51:29 PM PDT 24
Finished Aug 17 04:51:35 PM PDT 24
Peak memory 221696 kb
Host smart-b05acd29-9bbe-4463-844b-daffc61e8de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722930999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2722930999
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2585624876
Short name T567
Test name
Test status
Simulation time 284538072 ps
CPU time 2.71 seconds
Started Aug 17 04:51:35 PM PDT 24
Finished Aug 17 04:51:38 PM PDT 24
Peak memory 209768 kb
Host smart-8bb8a4b8-1b0d-489b-b230-1f42b642317b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585624876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2585624876
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3748751309
Short name T630
Test name
Test status
Simulation time 52022468 ps
CPU time 3.25 seconds
Started Aug 17 04:51:33 PM PDT 24
Finished Aug 17 04:51:37 PM PDT 24
Peak memory 215024 kb
Host smart-db0e8f3d-dc53-4019-8d94-416750bf33d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3748751309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3748751309
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_random.1815531652
Short name T517
Test name
Test status
Simulation time 108167912 ps
CPU time 4.41 seconds
Started Aug 17 04:51:36 PM PDT 24
Finished Aug 17 04:51:41 PM PDT 24
Peak memory 209012 kb
Host smart-ddfb4df3-942a-415c-8f01-395450bec339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815531652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1815531652
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2888929189
Short name T822
Test name
Test status
Simulation time 68531301 ps
CPU time 2.88 seconds
Started Aug 17 04:51:30 PM PDT 24
Finished Aug 17 04:51:33 PM PDT 24
Peak memory 208656 kb
Host smart-45f6a7a3-29bb-4b92-b00d-36db39a83bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888929189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2888929189
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1400933140
Short name T614
Test name
Test status
Simulation time 85426603 ps
CPU time 3.18 seconds
Started Aug 17 04:51:40 PM PDT 24
Finished Aug 17 04:51:43 PM PDT 24
Peak memory 207400 kb
Host smart-00c32356-7e01-4aab-8206-bd32d2c797f1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400933140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1400933140
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1089851983
Short name T514
Test name
Test status
Simulation time 38962015 ps
CPU time 2.43 seconds
Started Aug 17 04:51:36 PM PDT 24
Finished Aug 17 04:51:39 PM PDT 24
Peak memory 207296 kb
Host smart-3b12f8a4-068c-4bd1-b9d1-f2fe57f35e35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089851983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1089851983
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.4287445165
Short name T657
Test name
Test status
Simulation time 213010253 ps
CPU time 3.15 seconds
Started Aug 17 04:51:35 PM PDT 24
Finished Aug 17 04:51:38 PM PDT 24
Peak memory 207820 kb
Host smart-baf6bf2f-ce58-4894-8161-4573b4da94a1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287445165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.4287445165
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4021505826
Short name T775
Test name
Test status
Simulation time 150428056 ps
CPU time 2.32 seconds
Started Aug 17 04:51:37 PM PDT 24
Finished Aug 17 04:51:39 PM PDT 24
Peak memory 210280 kb
Host smart-b5ea71f7-4718-45c8-93de-b6838e40bb0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021505826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4021505826
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3232204175
Short name T633
Test name
Test status
Simulation time 628382695 ps
CPU time 3.79 seconds
Started Aug 17 04:51:41 PM PDT 24
Finished Aug 17 04:51:45 PM PDT 24
Peak memory 207100 kb
Host smart-e198c5ef-11a6-4666-ac8e-12cb9964cab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232204175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3232204175
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.212464755
Short name T141
Test name
Test status
Simulation time 704187799 ps
CPU time 16.75 seconds
Started Aug 17 04:51:39 PM PDT 24
Finished Aug 17 04:51:56 PM PDT 24
Peak memory 215380 kb
Host smart-98623b0c-e445-4e94-aaf2-9c41dc6c2c86
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212464755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.212464755
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.855903967
Short name T622
Test name
Test status
Simulation time 39297128 ps
CPU time 2.78 seconds
Started Aug 17 04:51:34 PM PDT 24
Finished Aug 17 04:51:37 PM PDT 24
Peak memory 218736 kb
Host smart-cb81c1b0-502f-4d06-a1a0-7b86aa91930c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855903967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.855903967
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3923593714
Short name T65
Test name
Test status
Simulation time 13733526 ps
CPU time 0.91 seconds
Started Aug 17 04:51:24 PM PDT 24
Finished Aug 17 04:51:25 PM PDT 24
Peak memory 206500 kb
Host smart-61528eb3-edf1-4d7d-b904-98f950c7715d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3923593714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3923593714
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.139374886
Short name T396
Test name
Test status
Simulation time 144562490 ps
CPU time 3 seconds
Started Aug 17 04:51:38 PM PDT 24
Finished Aug 17 04:51:41 PM PDT 24
Peak memory 214620 kb
Host smart-6b7e7257-c963-4bed-827e-f741aaf06fef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139374886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.139374886
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2162218806
Short name T132
Test name
Test status
Simulation time 231881685 ps
CPU time 2.76 seconds
Started Aug 17 04:51:37 PM PDT 24
Finished Aug 17 04:51:40 PM PDT 24
Peak memory 214824 kb
Host smart-9e7db08f-aa33-45e7-a32e-bf4a78a2075b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162218806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2162218806
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.55424551
Short name T324
Test name
Test status
Simulation time 422337524 ps
CPU time 3.8 seconds
Started Aug 17 04:51:35 PM PDT 24
Finished Aug 17 04:51:39 PM PDT 24
Peak memory 210008 kb
Host smart-58d55a3a-f145-4e61-ba20-2035da52923a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55424551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.55424551
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3834458346
Short name T684
Test name
Test status
Simulation time 951603346 ps
CPU time 3.76 seconds
Started Aug 17 04:51:33 PM PDT 24
Finished Aug 17 04:51:37 PM PDT 24
Peak memory 214620 kb
Host smart-d0f7ff4b-0b90-4f51-be66-0946965691c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834458346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3834458346
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3265547038
Short name T724
Test name
Test status
Simulation time 169352779 ps
CPU time 2.64 seconds
Started Aug 17 04:51:32 PM PDT 24
Finished Aug 17 04:51:34 PM PDT 24
Peak memory 208024 kb
Host smart-7d5952c3-37be-479c-8358-acbe4f5e4983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265547038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3265547038
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2069191360
Short name T528
Test name
Test status
Simulation time 38872577 ps
CPU time 2.54 seconds
Started Aug 17 04:51:38 PM PDT 24
Finished Aug 17 04:51:40 PM PDT 24
Peak memory 210084 kb
Host smart-42fd6ea2-eab2-4af9-811f-c52e40466e6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069191360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2069191360
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3716903380
Short name T515
Test name
Test status
Simulation time 228613139 ps
CPU time 6.28 seconds
Started Aug 17 04:51:38 PM PDT 24
Finished Aug 17 04:51:45 PM PDT 24
Peak memory 208608 kb
Host smart-0e648111-f559-4a6b-bf8d-8c820d897446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716903380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3716903380
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2137020536
Short name T512
Test name
Test status
Simulation time 27492106 ps
CPU time 1.99 seconds
Started Aug 17 04:51:45 PM PDT 24
Finished Aug 17 04:51:47 PM PDT 24
Peak memory 209004 kb
Host smart-e06f9cec-277d-4dca-aa08-7d89fdc846e6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137020536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2137020536
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.1224163795
Short name T467
Test name
Test status
Simulation time 109965857 ps
CPU time 3.35 seconds
Started Aug 17 04:51:46 PM PDT 24
Finished Aug 17 04:51:49 PM PDT 24
Peak memory 207444 kb
Host smart-395455a8-9210-490e-899b-0b03efdf1275
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224163795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.1224163795
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4252796106
Short name T898
Test name
Test status
Simulation time 1827149198 ps
CPU time 24.85 seconds
Started Aug 17 04:51:45 PM PDT 24
Finished Aug 17 04:52:10 PM PDT 24
Peak memory 208388 kb
Host smart-d15e35ef-8eaa-477c-81b6-434d2f798641
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252796106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4252796106
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.563513591
Short name T550
Test name
Test status
Simulation time 58604611 ps
CPU time 2.89 seconds
Started Aug 17 04:51:39 PM PDT 24
Finished Aug 17 04:51:42 PM PDT 24
Peak memory 209204 kb
Host smart-29ca5547-aef8-4e59-b421-4faf29bdd2ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563513591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.563513591
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2413675880
Short name T760
Test name
Test status
Simulation time 329619517 ps
CPU time 2.94 seconds
Started Aug 17 04:51:30 PM PDT 24
Finished Aug 17 04:51:33 PM PDT 24
Peak memory 207132 kb
Host smart-0f93d457-822e-4b7e-b288-c612afc86e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413675880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2413675880
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3600187206
Short name T363
Test name
Test status
Simulation time 221744822 ps
CPU time 12.51 seconds
Started Aug 17 04:51:40 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 223008 kb
Host smart-cc1aa513-d48c-4aa6-9e31-aa1ac91a881f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600187206 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3600187206
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1722330137
Short name T691
Test name
Test status
Simulation time 151004896 ps
CPU time 4.42 seconds
Started Aug 17 04:51:39 PM PDT 24
Finished Aug 17 04:51:43 PM PDT 24
Peak memory 208888 kb
Host smart-6ed019ba-5d88-440f-af87-3c0a2df84467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722330137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1722330137
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2500620268
Short name T191
Test name
Test status
Simulation time 100045569 ps
CPU time 2.32 seconds
Started Aug 17 04:51:48 PM PDT 24
Finished Aug 17 04:52:01 PM PDT 24
Peak memory 210288 kb
Host smart-f649c979-5f0a-4e4b-882a-64eb767ae102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500620268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2500620268
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.877036163
Short name T56
Test name
Test status
Simulation time 24464324 ps
CPU time 0.79 seconds
Started Aug 17 04:50:23 PM PDT 24
Finished Aug 17 04:50:24 PM PDT 24
Peak memory 206356 kb
Host smart-aa6fd00d-5a61-4fb6-92ca-46cd43051491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877036163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.877036163
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3636664383
Short name T323
Test name
Test status
Simulation time 137637463 ps
CPU time 3.76 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:15 PM PDT 24
Peak memory 214660 kb
Host smart-2f5d7007-ba2b-4ca8-b4af-833b6f076efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636664383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3636664383
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3062564944
Short name T40
Test name
Test status
Simulation time 40611370 ps
CPU time 2.8 seconds
Started Aug 17 04:50:22 PM PDT 24
Finished Aug 17 04:50:24 PM PDT 24
Peak memory 222180 kb
Host smart-af5a1b77-1fd4-47dd-b23d-c5c5fe5a96fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062564944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3062564944
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1251937621
Short name T124
Test name
Test status
Simulation time 101793248 ps
CPU time 2.98 seconds
Started Aug 17 04:50:28 PM PDT 24
Finished Aug 17 04:50:31 PM PDT 24
Peak memory 214820 kb
Host smart-7ee5f240-5e7e-4939-adf7-db3ad6e54ea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251937621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1251937621
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1814205365
Short name T837
Test name
Test status
Simulation time 115961040 ps
CPU time 3.98 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:13 PM PDT 24
Peak memory 214756 kb
Host smart-58fce58c-255c-4c6f-80d6-0b188b6be5c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814205365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1814205365
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3862073449
Short name T37
Test name
Test status
Simulation time 240090589 ps
CPU time 5.23 seconds
Started Aug 17 04:50:19 PM PDT 24
Finished Aug 17 04:50:24 PM PDT 24
Peak memory 237860 kb
Host smart-55d9862b-4ae6-433e-8db9-2894c97718f3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862073449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3862073449
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3379199254
Short name T358
Test name
Test status
Simulation time 52749088 ps
CPU time 2.62 seconds
Started Aug 17 04:50:11 PM PDT 24
Finished Aug 17 04:50:14 PM PDT 24
Peak memory 207304 kb
Host smart-a9afa0e1-8149-49b7-9f23-716108a645ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379199254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3379199254
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1699740645
Short name T677
Test name
Test status
Simulation time 50954683 ps
CPU time 2.83 seconds
Started Aug 17 04:50:09 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 207340 kb
Host smart-71bfe62e-10ad-494e-abc5-8fc73d6ddd82
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699740645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1699740645
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2915651952
Short name T904
Test name
Test status
Simulation time 74378300 ps
CPU time 1.73 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:17 PM PDT 24
Peak memory 207336 kb
Host smart-5c5d35e0-9779-4e7b-88f6-e0011274583b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915651952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2915651952
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3721503061
Short name T541
Test name
Test status
Simulation time 67877530 ps
CPU time 2.42 seconds
Started Aug 17 04:50:10 PM PDT 24
Finished Aug 17 04:50:12 PM PDT 24
Peak memory 207364 kb
Host smart-aceeccdc-77f1-495d-ae7c-7c34109f5d1c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721503061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3721503061
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1732109738
Short name T635
Test name
Test status
Simulation time 169296543 ps
CPU time 3.42 seconds
Started Aug 17 04:50:25 PM PDT 24
Finished Aug 17 04:50:29 PM PDT 24
Peak memory 216296 kb
Host smart-6e982acc-3e09-4bf5-a35b-fff5bd1709b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732109738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1732109738
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1605830346
Short name T726
Test name
Test status
Simulation time 67843644 ps
CPU time 1.98 seconds
Started Aug 17 04:50:08 PM PDT 24
Finished Aug 17 04:50:10 PM PDT 24
Peak memory 207204 kb
Host smart-bacabe74-43b2-4945-a3e1-e1c5c881edc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605830346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1605830346
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1415762788
Short name T843
Test name
Test status
Simulation time 551812854 ps
CPU time 13.52 seconds
Started Aug 17 04:50:30 PM PDT 24
Finished Aug 17 04:50:44 PM PDT 24
Peak memory 216896 kb
Host smart-492f3166-143e-4122-b028-b3f3db051d69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1415762788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1415762788
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2857079040
Short name T771
Test name
Test status
Simulation time 1401622139 ps
CPU time 30.47 seconds
Started Aug 17 04:50:28 PM PDT 24
Finished Aug 17 04:50:59 PM PDT 24
Peak memory 214856 kb
Host smart-d491b512-90f6-4ccb-9a2c-446b3b684161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857079040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2857079040
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.369259092
Short name T4
Test name
Test status
Simulation time 40352574 ps
CPU time 2.13 seconds
Started Aug 17 04:50:21 PM PDT 24
Finished Aug 17 04:50:23 PM PDT 24
Peak memory 210964 kb
Host smart-d5395ba5-e880-4888-8045-d8da3dcde51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369259092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.369259092
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1237384564
Short name T875
Test name
Test status
Simulation time 33258198 ps
CPU time 0.76 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 206320 kb
Host smart-fd449a9a-4d4c-4e31-b1c0-c566b71769d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237384564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1237384564
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.322340201
Short name T402
Test name
Test status
Simulation time 355561775 ps
CPU time 10.06 seconds
Started Aug 17 04:51:36 PM PDT 24
Finished Aug 17 04:51:46 PM PDT 24
Peak memory 215976 kb
Host smart-95a3f693-0abf-4af1-b507-5decb7559912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=322340201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.322340201
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2603395184
Short name T264
Test name
Test status
Simulation time 143432090 ps
CPU time 2.78 seconds
Started Aug 17 04:51:47 PM PDT 24
Finished Aug 17 04:51:50 PM PDT 24
Peak memory 210360 kb
Host smart-4427584b-d9d6-480d-8b9d-83ff0ea42abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603395184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2603395184
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1602706901
Short name T750
Test name
Test status
Simulation time 483786177 ps
CPU time 3.68 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 218788 kb
Host smart-656d6bfb-a763-441d-88ae-284dda93b5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602706901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1602706901
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3309988212
Short name T696
Test name
Test status
Simulation time 63915783 ps
CPU time 3.25 seconds
Started Aug 17 04:51:43 PM PDT 24
Finished Aug 17 04:51:46 PM PDT 24
Peak memory 220296 kb
Host smart-7240a5f3-c1ad-41f1-9d06-88708d7f53ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309988212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3309988212
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3915921408
Short name T386
Test name
Test status
Simulation time 396829808 ps
CPU time 4.29 seconds
Started Aug 17 04:51:47 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 209272 kb
Host smart-28a3e807-d5e2-45f3-b266-02aa5973af0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915921408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3915921408
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.981997525
Short name T476
Test name
Test status
Simulation time 40863421 ps
CPU time 2.76 seconds
Started Aug 17 04:51:38 PM PDT 24
Finished Aug 17 04:51:41 PM PDT 24
Peak memory 208948 kb
Host smart-9675479c-0c60-44eb-a2f2-c18c1b4a21d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981997525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.981997525
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.595551274
Short name T300
Test name
Test status
Simulation time 122946645 ps
CPU time 3.81 seconds
Started Aug 17 04:51:48 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 208832 kb
Host smart-cef3e2e3-7481-4d9e-9184-4684e2c9ddd4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595551274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.595551274
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2555347425
Short name T446
Test name
Test status
Simulation time 193457762 ps
CPU time 5.06 seconds
Started Aug 17 04:51:47 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 209060 kb
Host smart-1f16b8fb-33d2-40fc-909f-baabd7b310c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555347425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2555347425
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2585677934
Short name T616
Test name
Test status
Simulation time 49189380 ps
CPU time 2.48 seconds
Started Aug 17 04:51:42 PM PDT 24
Finished Aug 17 04:51:44 PM PDT 24
Peak memory 208520 kb
Host smart-24b3a0a7-ede6-4f76-a95e-a452841f8de2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585677934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2585677934
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.2443264703
Short name T859
Test name
Test status
Simulation time 408184369 ps
CPU time 3.62 seconds
Started Aug 17 04:51:43 PM PDT 24
Finished Aug 17 04:51:46 PM PDT 24
Peak memory 210312 kb
Host smart-ba9ad776-c8d6-4460-991b-baf8fbba496d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443264703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.2443264703
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.928625370
Short name T381
Test name
Test status
Simulation time 2415603685 ps
CPU time 9.64 seconds
Started Aug 17 04:51:38 PM PDT 24
Finished Aug 17 04:51:48 PM PDT 24
Peak memory 208292 kb
Host smart-df6ba6d2-ae4f-4cb5-b359-8bbf663cf90e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928625370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.928625370
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2473058599
Short name T825
Test name
Test status
Simulation time 4888111890 ps
CPU time 44.74 seconds
Started Aug 17 04:51:36 PM PDT 24
Finished Aug 17 04:52:20 PM PDT 24
Peak memory 223012 kb
Host smart-5ed818b5-7fea-47ce-918f-0741e8accfce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473058599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2473058599
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2903103162
Short name T123
Test name
Test status
Simulation time 1459687125 ps
CPU time 19.77 seconds
Started Aug 17 04:51:45 PM PDT 24
Finished Aug 17 04:52:05 PM PDT 24
Peak memory 222944 kb
Host smart-6160d984-7a43-469d-bbb9-2c80a9ee51ac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903103162 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2903103162
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.969145450
Short name T64
Test name
Test status
Simulation time 362360784 ps
CPU time 6.67 seconds
Started Aug 17 04:51:42 PM PDT 24
Finished Aug 17 04:51:49 PM PDT 24
Peak memory 208948 kb
Host smart-ef8600c4-27d7-405e-9490-f0d55baa10f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969145450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.969145450
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.685581634
Short name T129
Test name
Test status
Simulation time 192990335 ps
CPU time 6.39 seconds
Started Aug 17 04:51:36 PM PDT 24
Finished Aug 17 04:51:43 PM PDT 24
Peak memory 211408 kb
Host smart-943a76f7-84d2-4d0f-8c28-e77824c84432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=685581634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.685581634
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3213695468
Short name T873
Test name
Test status
Simulation time 40914737 ps
CPU time 0.82 seconds
Started Aug 17 04:51:44 PM PDT 24
Finished Aug 17 04:51:45 PM PDT 24
Peak memory 206400 kb
Host smart-b94165b2-bfcf-4bd7-9569-d9cda997c27e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213695468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3213695468
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1844514569
Short name T328
Test name
Test status
Simulation time 50778131 ps
CPU time 3.6 seconds
Started Aug 17 04:51:41 PM PDT 24
Finished Aug 17 04:51:45 PM PDT 24
Peak memory 214756 kb
Host smart-54ff991e-59af-4926-aa92-961d3359a597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1844514569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1844514569
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.968645247
Short name T68
Test name
Test status
Simulation time 223960642 ps
CPU time 3.87 seconds
Started Aug 17 04:51:35 PM PDT 24
Finished Aug 17 04:51:39 PM PDT 24
Peak memory 208740 kb
Host smart-d35d749d-a218-449f-a1b5-828e85ff6b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968645247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.968645247
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3231742894
Short name T43
Test name
Test status
Simulation time 33927641 ps
CPU time 1.82 seconds
Started Aug 17 04:51:45 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 214772 kb
Host smart-a3c9c2ab-3a41-4b88-afb8-3df87451dd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231742894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3231742894
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.375647705
Short name T317
Test name
Test status
Simulation time 808083707 ps
CPU time 5.01 seconds
Started Aug 17 04:51:37 PM PDT 24
Finished Aug 17 04:51:43 PM PDT 24
Peak memory 214772 kb
Host smart-11184c0d-7570-4cfc-99d6-08326a6f533e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375647705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.375647705
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.314371985
Short name T662
Test name
Test status
Simulation time 4611786065 ps
CPU time 19.92 seconds
Started Aug 17 04:51:37 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 209840 kb
Host smart-7ee4ca52-994e-4519-b7ba-2a803ab7c40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314371985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.314371985
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1539947410
Short name T193
Test name
Test status
Simulation time 169562685 ps
CPU time 6.84 seconds
Started Aug 17 04:51:42 PM PDT 24
Finished Aug 17 04:51:49 PM PDT 24
Peak memory 208468 kb
Host smart-fbcf4a4e-d69b-4f7a-856a-388db4815eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539947410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1539947410
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3656291872
Short name T659
Test name
Test status
Simulation time 23697756 ps
CPU time 2.1 seconds
Started Aug 17 04:51:41 PM PDT 24
Finished Aug 17 04:51:43 PM PDT 24
Peak memory 209216 kb
Host smart-75d42b70-644a-495a-9b07-f1b3a0d4b82f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656291872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3656291872
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.142921623
Short name T727
Test name
Test status
Simulation time 744026119 ps
CPU time 5.71 seconds
Started Aug 17 04:51:47 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 208524 kb
Host smart-7db66f0a-d389-40bc-882a-e1e728192fd3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142921623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.142921623
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2667425441
Short name T862
Test name
Test status
Simulation time 164530668 ps
CPU time 2.33 seconds
Started Aug 17 04:51:35 PM PDT 24
Finished Aug 17 04:51:38 PM PDT 24
Peak memory 207188 kb
Host smart-c1aa35a7-0a1d-466d-a478-b3ea95f9f0d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667425441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2667425441
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3134660512
Short name T685
Test name
Test status
Simulation time 213159956 ps
CPU time 5.64 seconds
Started Aug 17 04:51:42 PM PDT 24
Finished Aug 17 04:51:48 PM PDT 24
Peak memory 208220 kb
Host smart-1bca6d83-2d68-4119-8f54-05ab49e4ebe3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134660512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3134660512
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.4196019135
Short name T308
Test name
Test status
Simulation time 106219724 ps
CPU time 3.69 seconds
Started Aug 17 04:51:40 PM PDT 24
Finished Aug 17 04:51:44 PM PDT 24
Peak memory 222744 kb
Host smart-ae91b0c8-d347-4e02-8dfa-e6563b3afc28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196019135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.4196019135
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2159311734
Short name T493
Test name
Test status
Simulation time 130563448 ps
CPU time 2.16 seconds
Started Aug 17 04:51:41 PM PDT 24
Finished Aug 17 04:51:44 PM PDT 24
Peak memory 207352 kb
Host smart-16374ead-5bc4-454b-b957-f65961092143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159311734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2159311734
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3734959817
Short name T98
Test name
Test status
Simulation time 425533389 ps
CPU time 7.81 seconds
Started Aug 17 04:51:50 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 208820 kb
Host smart-6207adc5-ee30-4720-9e2a-565eb95afa55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734959817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3734959817
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.381967093
Short name T547
Test name
Test status
Simulation time 3791447101 ps
CPU time 35.65 seconds
Started Aug 17 04:51:41 PM PDT 24
Finished Aug 17 04:52:16 PM PDT 24
Peak memory 210260 kb
Host smart-53b4064a-38d4-4b72-acd9-e62520af9cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381967093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.381967093
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3835300294
Short name T570
Test name
Test status
Simulation time 99764308 ps
CPU time 1.59 seconds
Started Aug 17 04:51:41 PM PDT 24
Finished Aug 17 04:51:43 PM PDT 24
Peak memory 210276 kb
Host smart-618076a9-a937-4877-9bcf-8a6d99b828b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835300294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3835300294
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3556483324
Short name T603
Test name
Test status
Simulation time 38854867 ps
CPU time 0.87 seconds
Started Aug 17 04:51:39 PM PDT 24
Finished Aug 17 04:51:40 PM PDT 24
Peak memory 206304 kb
Host smart-ad4a3928-6e9c-44dd-86bb-89568c8f6902
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556483324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3556483324
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3917494030
Short name T846
Test name
Test status
Simulation time 1171771671 ps
CPU time 8.29 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:52:01 PM PDT 24
Peak memory 222212 kb
Host smart-35e4b287-1d0a-41d0-a755-7b4f6399c44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917494030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3917494030
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2921018825
Short name T166
Test name
Test status
Simulation time 98503440 ps
CPU time 3.06 seconds
Started Aug 17 04:51:44 PM PDT 24
Finished Aug 17 04:51:47 PM PDT 24
Peak memory 218756 kb
Host smart-e2579f8c-e83c-4d92-8ed5-ba9c947673c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921018825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2921018825
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.791504113
Short name T689
Test name
Test status
Simulation time 325670779 ps
CPU time 3.41 seconds
Started Aug 17 04:51:43 PM PDT 24
Finished Aug 17 04:51:46 PM PDT 24
Peak memory 214800 kb
Host smart-261f427b-05b3-4420-b353-127afea04194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791504113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.791504113
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.591543995
Short name T591
Test name
Test status
Simulation time 61608615 ps
CPU time 3.45 seconds
Started Aug 17 04:51:40 PM PDT 24
Finished Aug 17 04:51:43 PM PDT 24
Peak memory 221012 kb
Host smart-91fbce1a-047b-42ee-9878-393852833620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591543995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.591543995
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.3979327108
Short name T477
Test name
Test status
Simulation time 71196244 ps
CPU time 2 seconds
Started Aug 17 04:51:40 PM PDT 24
Finished Aug 17 04:51:42 PM PDT 24
Peak memory 220464 kb
Host smart-7cdd613b-2c2d-48b1-9dad-faa620c48424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979327108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3979327108
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2075676814
Short name T343
Test name
Test status
Simulation time 45808812 ps
CPU time 2.88 seconds
Started Aug 17 04:51:39 PM PDT 24
Finished Aug 17 04:51:42 PM PDT 24
Peak memory 210228 kb
Host smart-d9240dbe-7aac-4af8-9ac6-3c35a5ca8d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075676814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2075676814
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1611628438
Short name T737
Test name
Test status
Simulation time 121640563 ps
CPU time 2.19 seconds
Started Aug 17 04:51:46 PM PDT 24
Finished Aug 17 04:51:48 PM PDT 24
Peak memory 207672 kb
Host smart-ddefb6d0-c7ac-4149-956b-f0cdc16eee97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611628438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1611628438
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1311112955
Short name T251
Test name
Test status
Simulation time 62829521 ps
CPU time 2.77 seconds
Started Aug 17 04:51:38 PM PDT 24
Finished Aug 17 04:51:40 PM PDT 24
Peak memory 207392 kb
Host smart-2ff636dd-5dcf-4df3-8aaf-264a59d8b9d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311112955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1311112955
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.630604422
Short name T654
Test name
Test status
Simulation time 211939466 ps
CPU time 1.96 seconds
Started Aug 17 04:51:37 PM PDT 24
Finished Aug 17 04:51:40 PM PDT 24
Peak memory 207232 kb
Host smart-3373240a-7490-45a9-8a8c-7564b9a66c9e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630604422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.630604422
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3682862863
Short name T359
Test name
Test status
Simulation time 197280849 ps
CPU time 2.85 seconds
Started Aug 17 04:51:31 PM PDT 24
Finished Aug 17 04:51:34 PM PDT 24
Peak memory 207436 kb
Host smart-49b174f2-bd93-47d2-8db9-e84fb2cc7f8d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682862863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3682862863
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2764974612
Short name T258
Test name
Test status
Simulation time 274404916 ps
CPU time 3.98 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:51:59 PM PDT 24
Peak memory 218528 kb
Host smart-1874226e-f898-4370-a174-a5e78625ab31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764974612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2764974612
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3969994787
Short name T188
Test name
Test status
Simulation time 943595282 ps
CPU time 4.86 seconds
Started Aug 17 04:51:44 PM PDT 24
Finished Aug 17 04:51:49 PM PDT 24
Peak memory 208332 kb
Host smart-db432e98-adab-44c0-8f47-53b8aa01e4b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969994787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3969994787
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2900684802
Short name T329
Test name
Test status
Simulation time 3336433814 ps
CPU time 33.62 seconds
Started Aug 17 04:51:44 PM PDT 24
Finished Aug 17 04:52:18 PM PDT 24
Peak memory 216008 kb
Host smart-0f6a7539-a439-4c61-8c75-0b3e99d50665
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900684802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2900684802
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1493317080
Short name T283
Test name
Test status
Simulation time 625191711 ps
CPU time 5.18 seconds
Started Aug 17 04:51:45 PM PDT 24
Finished Aug 17 04:51:51 PM PDT 24
Peak memory 209548 kb
Host smart-6717b00b-b4cf-4335-9c94-24ba8048e779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493317080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1493317080
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.4031710999
Short name T369
Test name
Test status
Simulation time 35729978 ps
CPU time 1.46 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 210168 kb
Host smart-22c1acf0-1467-456a-9e4e-f51d8f9ca755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031710999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.4031710999
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.701966303
Short name T897
Test name
Test status
Simulation time 43678706 ps
CPU time 0.86 seconds
Started Aug 17 04:51:50 PM PDT 24
Finished Aug 17 04:51:51 PM PDT 24
Peak memory 206328 kb
Host smart-036ff413-f03c-4d52-a8ea-51139e808243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701966303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.701966303
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.769746352
Short name T342
Test name
Test status
Simulation time 112241335 ps
CPU time 2.44 seconds
Started Aug 17 04:51:43 PM PDT 24
Finished Aug 17 04:51:45 PM PDT 24
Peak memory 214748 kb
Host smart-fed6fcc8-c99b-4dbe-8c43-b4f1fa056240
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769746352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.769746352
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1024702447
Short name T159
Test name
Test status
Simulation time 390099969 ps
CPU time 2.21 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 221572 kb
Host smart-b36a2f7b-b52f-4356-a414-71632456b3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024702447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1024702447
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3475257364
Short name T468
Test name
Test status
Simulation time 295945879 ps
CPU time 2.91 seconds
Started Aug 17 04:51:41 PM PDT 24
Finished Aug 17 04:51:44 PM PDT 24
Peak memory 210376 kb
Host smart-57cef298-655f-4e32-87d8-0f35631b1d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475257364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3475257364
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2237083182
Short name T48
Test name
Test status
Simulation time 234021684 ps
CPU time 5.64 seconds
Started Aug 17 04:51:50 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 222816 kb
Host smart-fdba51d5-080a-49a5-bd5c-e21bdf3f7725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237083182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2237083182
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.932126050
Short name T362
Test name
Test status
Simulation time 48660465 ps
CPU time 3.41 seconds
Started Aug 17 04:51:49 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 214740 kb
Host smart-fcdc126b-4f0d-4e88-92ef-91d5f8a9da03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932126050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.932126050
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.372286854
Short name T272
Test name
Test status
Simulation time 154642437 ps
CPU time 5.48 seconds
Started Aug 17 04:51:50 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 222700 kb
Host smart-6a578f56-09a0-4f53-9040-fea87654ec6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372286854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.372286854
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3061598609
Short name T770
Test name
Test status
Simulation time 316753246 ps
CPU time 8.04 seconds
Started Aug 17 04:51:45 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 218772 kb
Host smart-279d744c-14ed-457c-b393-3fd6b7c24e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061598609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3061598609
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.3802545837
Short name T644
Test name
Test status
Simulation time 65003063 ps
CPU time 3.25 seconds
Started Aug 17 04:51:44 PM PDT 24
Finished Aug 17 04:51:47 PM PDT 24
Peak memory 208640 kb
Host smart-f16b9bdf-c1df-4447-9e08-7795e58c68cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802545837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3802545837
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1601072355
Short name T464
Test name
Test status
Simulation time 952654015 ps
CPU time 7.96 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:52:00 PM PDT 24
Peak memory 208428 kb
Host smart-a5cca888-2030-45b9-a53b-5bc9c25186de
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601072355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1601072355
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1461965575
Short name T732
Test name
Test status
Simulation time 185183259 ps
CPU time 6.5 seconds
Started Aug 17 04:51:44 PM PDT 24
Finished Aug 17 04:51:51 PM PDT 24
Peak memory 207352 kb
Host smart-65fe22b5-a4cf-49b2-b297-3abadf551b0a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461965575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1461965575
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3142807236
Short name T706
Test name
Test status
Simulation time 74701223 ps
CPU time 1.75 seconds
Started Aug 17 04:51:52 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 207244 kb
Host smart-e08a556c-4a5f-4fe2-bc2e-d47446a6ae4b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142807236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3142807236
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.4199627516
Short name T532
Test name
Test status
Simulation time 108401862 ps
CPU time 2.31 seconds
Started Aug 17 04:51:45 PM PDT 24
Finished Aug 17 04:51:47 PM PDT 24
Peak memory 214776 kb
Host smart-73834814-7026-4247-816c-d1f0e1227ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199627516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.4199627516
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.3981860928
Short name T842
Test name
Test status
Simulation time 326271848 ps
CPU time 5.72 seconds
Started Aug 17 04:51:37 PM PDT 24
Finished Aug 17 04:51:43 PM PDT 24
Peak memory 208336 kb
Host smart-35ba39e3-cb3f-4967-b3d8-4b8a3a679732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981860928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.3981860928
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.899925898
Short name T478
Test name
Test status
Simulation time 693181208 ps
CPU time 7.12 seconds
Started Aug 17 04:51:50 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 208032 kb
Host smart-ace8435f-93a4-44a9-839e-ed8204062d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899925898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.899925898
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.840087306
Short name T682
Test name
Test status
Simulation time 75677355 ps
CPU time 2.9 seconds
Started Aug 17 04:51:44 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 210636 kb
Host smart-fd2aa331-d3f8-4ff8-971e-c738bfcab605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840087306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.840087306
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.659234974
Short name T447
Test name
Test status
Simulation time 13661972 ps
CPU time 0.88 seconds
Started Aug 17 04:51:45 PM PDT 24
Finished Aug 17 04:51:46 PM PDT 24
Peak memory 206560 kb
Host smart-186d653a-dc60-4f04-b1ab-fb5b44069606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659234974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.659234974
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2508898163
Short name T757
Test name
Test status
Simulation time 6693762433 ps
CPU time 51.31 seconds
Started Aug 17 04:51:44 PM PDT 24
Finished Aug 17 04:52:36 PM PDT 24
Peak memory 219712 kb
Host smart-a8163fc0-3ae2-4942-b760-7ac33237816e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508898163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2508898163
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2328380004
Short name T182
Test name
Test status
Simulation time 90280526 ps
CPU time 2.43 seconds
Started Aug 17 04:51:47 PM PDT 24
Finished Aug 17 04:51:50 PM PDT 24
Peak memory 209940 kb
Host smart-c1292279-86b2-48d3-ac20-e1994ea41ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328380004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2328380004
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.528652541
Short name T51
Test name
Test status
Simulation time 325211918 ps
CPU time 2.32 seconds
Started Aug 17 04:51:44 PM PDT 24
Finished Aug 17 04:51:46 PM PDT 24
Peak memory 222844 kb
Host smart-766a5e57-7a35-4692-8cd4-14ba9231d2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528652541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.528652541
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3687362195
Short name T23
Test name
Test status
Simulation time 53418353 ps
CPU time 2.26 seconds
Started Aug 17 04:51:42 PM PDT 24
Finished Aug 17 04:51:44 PM PDT 24
Peak memory 221564 kb
Host smart-e8ec332c-767e-4d26-a530-7f0292971585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687362195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3687362195
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3680975580
Short name T206
Test name
Test status
Simulation time 436526413 ps
CPU time 3.79 seconds
Started Aug 17 04:51:46 PM PDT 24
Finished Aug 17 04:51:50 PM PDT 24
Peak memory 222832 kb
Host smart-19e3871c-6c72-4390-9ab8-1d33953d0a8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680975580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3680975580
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.140046886
Short name T491
Test name
Test status
Simulation time 1372406481 ps
CPU time 12.45 seconds
Started Aug 17 04:51:42 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 214680 kb
Host smart-528006b6-3275-49f4-9df1-f4ef901b1a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140046886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.140046886
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.165578166
Short name T572
Test name
Test status
Simulation time 192231740 ps
CPU time 3.86 seconds
Started Aug 17 04:51:49 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 207224 kb
Host smart-f30e851f-f0a7-4fb4-91e6-b16e9946b094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165578166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.165578166
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3267522908
Short name T100
Test name
Test status
Simulation time 646066115 ps
CPU time 4.96 seconds
Started Aug 17 04:51:46 PM PDT 24
Finished Aug 17 04:51:51 PM PDT 24
Peak memory 208920 kb
Host smart-bcccf7d7-384f-4fa9-973d-8d7b7b2e8fb1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267522908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3267522908
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3417307737
Short name T878
Test name
Test status
Simulation time 31868122 ps
CPU time 2.13 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 207416 kb
Host smart-d1461620-43fb-43c9-af1d-a8b651ecc3b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417307737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3417307737
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.419885763
Short name T593
Test name
Test status
Simulation time 2941547534 ps
CPU time 16.67 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:52:10 PM PDT 24
Peak memory 209140 kb
Host smart-a9f6db93-8825-45a3-91d5-4ef963a952c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419885763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.419885763
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.533169490
Short name T571
Test name
Test status
Simulation time 168116973 ps
CPU time 3.06 seconds
Started Aug 17 04:51:44 PM PDT 24
Finished Aug 17 04:51:47 PM PDT 24
Peak memory 209844 kb
Host smart-9a5e517f-e29f-4283-876b-da0867434ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533169490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.533169490
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2276816797
Short name T426
Test name
Test status
Simulation time 60882033 ps
CPU time 2.05 seconds
Started Aug 17 04:51:49 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 207368 kb
Host smart-661f80d3-50fa-4775-8385-cde5c0da803c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276816797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2276816797
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1160505703
Short name T340
Test name
Test status
Simulation time 226296306 ps
CPU time 8.83 seconds
Started Aug 17 04:51:46 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 220992 kb
Host smart-75748e98-5e45-42df-a40d-67fe981f5b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160505703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1160505703
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3307853681
Short name T801
Test name
Test status
Simulation time 6728412262 ps
CPU time 38.97 seconds
Started Aug 17 04:51:48 PM PDT 24
Finished Aug 17 04:52:28 PM PDT 24
Peak memory 214772 kb
Host smart-b6a5ad2d-8a4c-4bfb-a99c-a6107ae2420c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307853681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3307853681
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2954566595
Short name T600
Test name
Test status
Simulation time 76554314 ps
CPU time 2.18 seconds
Started Aug 17 04:51:38 PM PDT 24
Finished Aug 17 04:51:40 PM PDT 24
Peak memory 210804 kb
Host smart-1432a075-0843-435b-8578-00ad5cdacbf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954566595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2954566595
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2338638066
Short name T529
Test name
Test status
Simulation time 11645907 ps
CPU time 0.84 seconds
Started Aug 17 04:51:57 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 206352 kb
Host smart-1290218e-7cb2-440e-a2db-4d3ec2660599
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338638066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2338638066
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1755144517
Short name T415
Test name
Test status
Simulation time 423643784 ps
CPU time 2.9 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 214768 kb
Host smart-8f1aab72-6bb2-4fa5-8c78-b6fd9402fde8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1755144517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1755144517
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3083393081
Short name T32
Test name
Test status
Simulation time 76092012 ps
CPU time 2.87 seconds
Started Aug 17 04:51:47 PM PDT 24
Finished Aug 17 04:51:50 PM PDT 24
Peak memory 214652 kb
Host smart-063d9a1c-5f1d-4ca0-b3b2-97b585a75f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083393081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3083393081
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3841754567
Short name T704
Test name
Test status
Simulation time 462455810 ps
CPU time 2.02 seconds
Started Aug 17 04:51:47 PM PDT 24
Finished Aug 17 04:51:50 PM PDT 24
Peak memory 209292 kb
Host smart-15837452-1091-42ed-b4a6-25a62e9e64f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841754567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3841754567
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.471809616
Short name T795
Test name
Test status
Simulation time 399406335 ps
CPU time 4.67 seconds
Started Aug 17 04:52:09 PM PDT 24
Finished Aug 17 04:52:14 PM PDT 24
Peak memory 214868 kb
Host smart-4f016cd8-e4b8-46ea-8df4-5ca8502d4c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471809616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.471809616
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1551718770
Short name T224
Test name
Test status
Simulation time 72010691 ps
CPU time 3.55 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 219800 kb
Host smart-72713d54-b4d0-4dfd-83af-1e9286369b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551718770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1551718770
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3200438905
Short name T463
Test name
Test status
Simulation time 561219679 ps
CPU time 4.28 seconds
Started Aug 17 04:51:50 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 210300 kb
Host smart-b0e6e88e-7760-4c9d-b1bb-386d09d7e307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200438905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3200438905
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2288171323
Short name T670
Test name
Test status
Simulation time 90312362 ps
CPU time 2.71 seconds
Started Aug 17 04:51:43 PM PDT 24
Finished Aug 17 04:51:46 PM PDT 24
Peak memory 208984 kb
Host smart-34d88583-efda-4ae6-94a6-d5517d34f0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288171323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2288171323
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3822762471
Short name T499
Test name
Test status
Simulation time 50626882 ps
CPU time 2.43 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 207420 kb
Host smart-fa26fe1d-a461-4903-958c-78f56f380142
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822762471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3822762471
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1990159667
Short name T262
Test name
Test status
Simulation time 86544082 ps
CPU time 3.54 seconds
Started Aug 17 04:51:48 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 209168 kb
Host smart-02c2fc40-eb5f-4364-8549-1fcfe58ab9a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990159667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1990159667
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.775704526
Short name T586
Test name
Test status
Simulation time 224170971 ps
CPU time 3.46 seconds
Started Aug 17 04:51:37 PM PDT 24
Finished Aug 17 04:51:41 PM PDT 24
Peak memory 207332 kb
Host smart-f2dd8621-b94a-468a-8ca7-a136476e93a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775704526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.775704526
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.4048808554
Short name T621
Test name
Test status
Simulation time 14890751 ps
CPU time 1.39 seconds
Started Aug 17 04:52:06 PM PDT 24
Finished Aug 17 04:52:07 PM PDT 24
Peak memory 207992 kb
Host smart-c9003edf-46fc-4b08-932f-ced767fd957f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048808554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4048808554
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3496159225
Short name T613
Test name
Test status
Simulation time 36112187 ps
CPU time 2.26 seconds
Started Aug 17 04:51:45 PM PDT 24
Finished Aug 17 04:51:48 PM PDT 24
Peak memory 208872 kb
Host smart-dbef2705-b4d2-484c-ba2a-9f7121aadd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496159225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3496159225
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1657430374
Short name T812
Test name
Test status
Simulation time 4136656093 ps
CPU time 47.68 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:52:42 PM PDT 24
Peak memory 216368 kb
Host smart-87abcc84-7d93-47bd-8c78-719b86309502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657430374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1657430374
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3351274712
Short name T781
Test name
Test status
Simulation time 84464979 ps
CPU time 4.12 seconds
Started Aug 17 04:51:44 PM PDT 24
Finished Aug 17 04:51:49 PM PDT 24
Peak memory 208136 kb
Host smart-b130f7a0-d4fb-4c0f-ba6f-e0549ec4ef7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351274712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3351274712
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1427078432
Short name T368
Test name
Test status
Simulation time 167738709 ps
CPU time 2.33 seconds
Started Aug 17 04:51:49 PM PDT 24
Finished Aug 17 04:51:51 PM PDT 24
Peak memory 210400 kb
Host smart-749049f1-8793-47df-8998-69fd6a76679c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427078432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1427078432
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2744453050
Short name T436
Test name
Test status
Simulation time 10605586 ps
CPU time 0.88 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:59 PM PDT 24
Peak memory 206396 kb
Host smart-88bae600-2c40-43aa-aa6c-0f0262e1e4b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744453050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2744453050
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1916153315
Short name T250
Test name
Test status
Simulation time 69148878 ps
CPU time 4.38 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:59 PM PDT 24
Peak memory 214776 kb
Host smart-df48f8ad-20f0-4375-8ebc-b1d63848bbb5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1916153315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1916153315
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2413918463
Short name T218
Test name
Test status
Simulation time 202912354 ps
CPU time 3.22 seconds
Started Aug 17 04:51:52 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 222948 kb
Host smart-c9f43af1-909c-4bb5-8cad-b9b6f63568f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413918463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2413918463
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.242379370
Short name T136
Test name
Test status
Simulation time 78815283 ps
CPU time 2.17 seconds
Started Aug 17 04:51:47 PM PDT 24
Finished Aug 17 04:51:50 PM PDT 24
Peak memory 218876 kb
Host smart-5cf43d3a-27a6-43d7-b45b-73cefee6cbb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242379370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.242379370
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1969786248
Short name T349
Test name
Test status
Simulation time 345096389 ps
CPU time 4.24 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 214672 kb
Host smart-b4675da3-5621-4ca5-a088-47ed9ec1f3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969786248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1969786248
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.4208042317
Short name T277
Test name
Test status
Simulation time 86297073 ps
CPU time 2.69 seconds
Started Aug 17 04:52:02 PM PDT 24
Finished Aug 17 04:52:04 PM PDT 24
Peak memory 214700 kb
Host smart-efe738e7-60e9-4320-8328-4c269fbd98b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208042317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.4208042317
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3044788260
Short name T217
Test name
Test status
Simulation time 64668473 ps
CPU time 2.08 seconds
Started Aug 17 04:51:46 PM PDT 24
Finished Aug 17 04:51:48 PM PDT 24
Peak memory 220404 kb
Host smart-7deda660-5665-44cf-b133-dfa791067c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044788260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3044788260
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2565715294
Short name T720
Test name
Test status
Simulation time 613791491 ps
CPU time 10.56 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:52:05 PM PDT 24
Peak memory 209744 kb
Host smart-74ff08ef-8d60-42e5-bb1b-b7fdf1af43ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565715294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2565715294
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.799551585
Short name T352
Test name
Test status
Simulation time 52450900 ps
CPU time 2.76 seconds
Started Aug 17 04:51:48 PM PDT 24
Finished Aug 17 04:51:51 PM PDT 24
Peak memory 208740 kb
Host smart-fee6411d-7ad1-4dd8-87d0-3ba0bcc8de09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799551585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.799551585
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3929551076
Short name T896
Test name
Test status
Simulation time 148737381 ps
CPU time 2.49 seconds
Started Aug 17 04:51:43 PM PDT 24
Finished Aug 17 04:51:46 PM PDT 24
Peak memory 209076 kb
Host smart-79318b66-b6c2-4f19-ade7-23ddfb943248
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929551076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3929551076
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3104029331
Short name T634
Test name
Test status
Simulation time 853973570 ps
CPU time 3.01 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 209296 kb
Host smart-7d28148c-7a2e-4d1d-a499-a62e4f49d12e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104029331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3104029331
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2307483822
Short name T69
Test name
Test status
Simulation time 891903716 ps
CPU time 4.77 seconds
Started Aug 17 04:51:52 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 208480 kb
Host smart-d9a09b76-8f0d-4260-8c8b-7f935c0e8586
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307483822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2307483822
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2785258563
Short name T858
Test name
Test status
Simulation time 23328444 ps
CPU time 1.83 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:56 PM PDT 24
Peak memory 216616 kb
Host smart-73a5e6de-3ab4-48a7-bafb-b1e15008a0aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785258563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2785258563
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2455770998
Short name T675
Test name
Test status
Simulation time 45817764 ps
CPU time 2.23 seconds
Started Aug 17 04:52:07 PM PDT 24
Finished Aug 17 04:52:09 PM PDT 24
Peak memory 207324 kb
Host smart-e98cc0df-71a1-4c0f-952d-a2455fd42874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455770998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2455770998
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1216057944
Short name T87
Test name
Test status
Simulation time 602247672 ps
CPU time 12.08 seconds
Started Aug 17 04:51:42 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 223072 kb
Host smart-c9a290ed-f2d6-4dc3-a3d8-8ff31c638a3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216057944 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1216057944
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3139516203
Short name T755
Test name
Test status
Simulation time 1061770467 ps
CPU time 8.04 seconds
Started Aug 17 04:51:49 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 218928 kb
Host smart-8a6b64bf-1586-48c3-bfa0-d8823fcfda0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139516203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3139516203
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1201133347
Short name T749
Test name
Test status
Simulation time 1315047844 ps
CPU time 6.2 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 211336 kb
Host smart-dd832b01-5232-4698-b984-82eb37354464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201133347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1201133347
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.4156829171
Short name T714
Test name
Test status
Simulation time 53597954 ps
CPU time 0.87 seconds
Started Aug 17 04:51:52 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 206356 kb
Host smart-867b3f1a-a6fd-4daa-8805-4663bb4c7433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156829171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.4156829171
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3855748734
Short name T741
Test name
Test status
Simulation time 60773558 ps
CPU time 2.61 seconds
Started Aug 17 04:52:13 PM PDT 24
Finished Aug 17 04:52:16 PM PDT 24
Peak memory 214704 kb
Host smart-3faa1452-e2f3-4c48-a030-e9c907632d21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855748734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3855748734
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1557546337
Short name T131
Test name
Test status
Simulation time 1249582595 ps
CPU time 31.39 seconds
Started Aug 17 04:51:57 PM PDT 24
Finished Aug 17 04:52:28 PM PDT 24
Peak memory 218712 kb
Host smart-6680466d-2de2-48fb-b179-417b171da513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557546337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1557546337
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1966397701
Short name T835
Test name
Test status
Simulation time 82382384 ps
CPU time 2.9 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 210332 kb
Host smart-510e8a55-102b-4812-82d5-f38ab1fd78a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966397701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1966397701
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.747046549
Short name T738
Test name
Test status
Simulation time 396871217 ps
CPU time 2.5 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 219988 kb
Host smart-cef26a79-eb3e-44b9-af18-517da7f6277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747046549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.747046549
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1838469507
Short name T105
Test name
Test status
Simulation time 544260599 ps
CPU time 4.88 seconds
Started Aug 17 04:51:52 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 222844 kb
Host smart-e3885ed0-56ea-45d4-8707-ab33006799e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838469507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1838469507
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1370895845
Short name T286
Test name
Test status
Simulation time 1156862296 ps
CPU time 15.36 seconds
Started Aug 17 04:52:08 PM PDT 24
Finished Aug 17 04:52:23 PM PDT 24
Peak memory 209284 kb
Host smart-bad7152c-e80f-47c4-9424-e80d1bc11ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370895845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1370895845
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1514270756
Short name T643
Test name
Test status
Simulation time 2339440120 ps
CPU time 29.28 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:52:22 PM PDT 24
Peak memory 208628 kb
Host smart-9c6a26d3-8cd3-4fa8-b1d4-21a4459fe952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514270756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1514270756
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2312170736
Short name T530
Test name
Test status
Simulation time 30396336 ps
CPU time 2.06 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 207312 kb
Host smart-6de9619c-44fe-47d4-92d4-be2747a17bf7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312170736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2312170736
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2426800933
Short name T803
Test name
Test status
Simulation time 103360477 ps
CPU time 3.2 seconds
Started Aug 17 04:51:50 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 208984 kb
Host smart-64fee130-4b31-4257-85c3-3a2fbf65b0b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426800933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2426800933
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.4077252282
Short name T768
Test name
Test status
Simulation time 97310245 ps
CPU time 3.42 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 209064 kb
Host smart-162ed1e8-30a6-45ff-b309-e1f2a434d4ea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077252282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.4077252282
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.4141892781
Short name T719
Test name
Test status
Simulation time 3094140241 ps
CPU time 29.23 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 209180 kb
Host smart-1cae4c08-b3c3-4752-a3b6-b4155588a764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141892781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.4141892781
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.4153284392
Short name T380
Test name
Test status
Simulation time 337502034 ps
CPU time 4.65 seconds
Started Aug 17 04:52:08 PM PDT 24
Finished Aug 17 04:52:12 PM PDT 24
Peak memory 207176 kb
Host smart-389b7c60-916d-42ca-95da-8f62d794f42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153284392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.4153284392
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.4062082653
Short name T175
Test name
Test status
Simulation time 1017460781 ps
CPU time 37.21 seconds
Started Aug 17 04:51:56 PM PDT 24
Finished Aug 17 04:52:34 PM PDT 24
Peak memory 220752 kb
Host smart-d4c78996-5a07-4068-b896-19d737bddef0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062082653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.4062082653
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2539237379
Short name T160
Test name
Test status
Simulation time 600135173 ps
CPU time 22.09 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:52:16 PM PDT 24
Peak memory 222968 kb
Host smart-f6b90a0c-4e88-4add-b7d9-7371a4f8a3d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539237379 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2539237379
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2220812197
Short name T855
Test name
Test status
Simulation time 78634436 ps
CPU time 3.92 seconds
Started Aug 17 04:52:11 PM PDT 24
Finished Aug 17 04:52:15 PM PDT 24
Peak memory 214700 kb
Host smart-1bf6beba-937b-4f04-9e85-3adc4889430a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220812197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2220812197
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.2033387295
Short name T417
Test name
Test status
Simulation time 11744829 ps
CPU time 0.74 seconds
Started Aug 17 04:51:49 PM PDT 24
Finished Aug 17 04:51:50 PM PDT 24
Peak memory 206356 kb
Host smart-9ccb0276-9c4e-4eeb-adfc-c3dddb60e30c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033387295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.2033387295
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3299026335
Short name T398
Test name
Test status
Simulation time 171660364 ps
CPU time 3.26 seconds
Started Aug 17 04:51:47 PM PDT 24
Finished Aug 17 04:51:51 PM PDT 24
Peak memory 214756 kb
Host smart-ebb1477f-0dd8-49f1-927f-66dabc668735
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3299026335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3299026335
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3705338825
Short name T885
Test name
Test status
Simulation time 300929881 ps
CPU time 3.79 seconds
Started Aug 17 04:52:09 PM PDT 24
Finished Aug 17 04:52:13 PM PDT 24
Peak memory 214712 kb
Host smart-59f5404e-6313-4530-839d-fa0f21a13453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705338825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3705338825
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3435168686
Short name T49
Test name
Test status
Simulation time 298580424 ps
CPU time 4.95 seconds
Started Aug 17 04:52:07 PM PDT 24
Finished Aug 17 04:52:12 PM PDT 24
Peak memory 209916 kb
Host smart-7fdd6e87-ab58-49f8-af38-3e13523a3b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435168686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3435168686
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3241510571
Short name T639
Test name
Test status
Simulation time 143278720 ps
CPU time 2.73 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 222876 kb
Host smart-fbc5a4dc-96b6-4c3b-9d94-01e686316937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241510571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3241510571
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2568774101
Short name T229
Test name
Test status
Simulation time 112641591 ps
CPU time 5.28 seconds
Started Aug 17 04:51:57 PM PDT 24
Finished Aug 17 04:52:03 PM PDT 24
Peak memory 210680 kb
Host smart-bd8a499c-2c30-4751-a332-2fc02da9d727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568774101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2568774101
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1418947362
Short name T355
Test name
Test status
Simulation time 195800204 ps
CPU time 4.77 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 210256 kb
Host smart-bf850af4-9710-46aa-b37e-277073c63539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418947362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1418947362
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2692961270
Short name T525
Test name
Test status
Simulation time 110779778 ps
CPU time 1.69 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 207284 kb
Host smart-da143f21-e8db-49d6-a99c-29f8350edea2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692961270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2692961270
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3828497661
Short name T310
Test name
Test status
Simulation time 445814476 ps
CPU time 4.28 seconds
Started Aug 17 04:51:57 PM PDT 24
Finished Aug 17 04:52:02 PM PDT 24
Peak memory 207348 kb
Host smart-175b0741-9d51-4fa4-87dd-447cee746f63
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828497661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3828497661
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1430451922
Short name T540
Test name
Test status
Simulation time 161957892 ps
CPU time 4.5 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 209320 kb
Host smart-f9d9efa4-00bd-4d52-bf94-3dc384c8cb62
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430451922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1430451922
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1892526316
Short name T871
Test name
Test status
Simulation time 132450355 ps
CPU time 5.22 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:59 PM PDT 24
Peak memory 207368 kb
Host smart-3adcfcf0-35b2-475b-a95e-6813b6d147f1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892526316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1892526316
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1446306699
Short name T711
Test name
Test status
Simulation time 632284908 ps
CPU time 4.71 seconds
Started Aug 17 04:51:50 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 209288 kb
Host smart-0f6663e9-fb40-4b5e-8aee-891ca776c849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446306699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1446306699
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1694551184
Short name T772
Test name
Test status
Simulation time 25553088 ps
CPU time 1.79 seconds
Started Aug 17 04:51:48 PM PDT 24
Finished Aug 17 04:51:50 PM PDT 24
Peak memory 208792 kb
Host smart-ee076332-8bba-484a-9acf-77d8cdcd6d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694551184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1694551184
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2025796456
Short name T240
Test name
Test status
Simulation time 3067123633 ps
CPU time 28.09 seconds
Started Aug 17 04:51:57 PM PDT 24
Finished Aug 17 04:52:25 PM PDT 24
Peak memory 216952 kb
Host smart-e2a54fe4-9c59-4200-b875-9a5e7d5018bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025796456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2025796456
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1029633066
Short name T480
Test name
Test status
Simulation time 29697975 ps
CPU time 2.16 seconds
Started Aug 17 04:51:52 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 207004 kb
Host smart-32a4ecb4-e653-4f9b-9d01-f1910ab1d1f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029633066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1029633066
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3254053895
Short name T805
Test name
Test status
Simulation time 463939657 ps
CPU time 3.32 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 210536 kb
Host smart-9fe1082f-0fc3-4f15-b7ed-2561265c8608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254053895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3254053895
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2705648205
Short name T542
Test name
Test status
Simulation time 20948071 ps
CPU time 0.74 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 206408 kb
Host smart-57b2ea89-8d9b-4a95-bd69-61abcb257f2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705648205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2705648205
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.2881546199
Short name T356
Test name
Test status
Simulation time 158342913 ps
CPU time 2.45 seconds
Started Aug 17 04:52:05 PM PDT 24
Finished Aug 17 04:52:08 PM PDT 24
Peak memory 214748 kb
Host smart-fb0b84a8-7560-4241-92d2-169c6190707d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2881546199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.2881546199
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1433747894
Short name T681
Test name
Test status
Simulation time 639844639 ps
CPU time 7.48 seconds
Started Aug 17 04:51:48 PM PDT 24
Finished Aug 17 04:51:56 PM PDT 24
Peak memory 214780 kb
Host smart-111956e0-82df-4832-a44e-0a59f43737ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433747894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1433747894
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3364238858
Short name T656
Test name
Test status
Simulation time 29434602 ps
CPU time 2 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 208188 kb
Host smart-def9e447-1928-4f69-94fc-f1442ca6eb0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364238858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3364238858
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1157011443
Short name T783
Test name
Test status
Simulation time 138044140 ps
CPU time 3.47 seconds
Started Aug 17 04:51:49 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 214676 kb
Host smart-3ddf799c-abc1-4c58-9dbb-6e1d3e36d15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157011443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1157011443
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.515878111
Short name T460
Test name
Test status
Simulation time 67647306 ps
CPU time 2.53 seconds
Started Aug 17 04:51:46 PM PDT 24
Finished Aug 17 04:51:48 PM PDT 24
Peak memory 220400 kb
Host smart-ee3d0a8d-4d19-4983-9629-3961e2638bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515878111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.515878111
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.31942875
Short name T536
Test name
Test status
Simulation time 1182732674 ps
CPU time 6.67 seconds
Started Aug 17 04:51:52 PM PDT 24
Finished Aug 17 04:51:59 PM PDT 24
Peak memory 208792 kb
Host smart-a57545ef-dcd1-4d90-befe-8fb2ea8ee787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31942875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.31942875
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.307348245
Short name T545
Test name
Test status
Simulation time 344864236 ps
CPU time 3.76 seconds
Started Aug 17 04:52:05 PM PDT 24
Finished Aug 17 04:52:09 PM PDT 24
Peak memory 208868 kb
Host smart-4ef7c08b-2a0d-42c1-afbb-b90d079011eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307348245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.307348245
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.932398433
Short name T510
Test name
Test status
Simulation time 3257499375 ps
CPU time 30.67 seconds
Started Aug 17 04:52:03 PM PDT 24
Finished Aug 17 04:52:34 PM PDT 24
Peak memory 209744 kb
Host smart-7cdd5cfd-e66c-442a-b693-818631253c5b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932398433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.932398433
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3498101880
Short name T650
Test name
Test status
Simulation time 918209613 ps
CPU time 11.28 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:52:02 PM PDT 24
Peak memory 208340 kb
Host smart-cf9705ff-cacb-4cba-9cd6-02407f48066b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498101880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3498101880
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1227210850
Short name T557
Test name
Test status
Simulation time 64888998 ps
CPU time 2.53 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 207196 kb
Host smart-bab060cf-29e6-4a8d-8d23-ced6d52bf24d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227210850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1227210850
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1762025171
Short name T13
Test name
Test status
Simulation time 94421608 ps
CPU time 1.72 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 208424 kb
Host smart-e53f4ae6-4479-4ffe-b5f6-894b58051926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762025171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1762025171
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.734771062
Short name T894
Test name
Test status
Simulation time 219503539 ps
CPU time 3 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 208704 kb
Host smart-2ac97ce1-b056-4c6c-8a52-99d084f87730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734771062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.734771062
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1099787249
Short name T703
Test name
Test status
Simulation time 319729125 ps
CPU time 12.11 seconds
Started Aug 17 04:52:01 PM PDT 24
Finished Aug 17 04:52:14 PM PDT 24
Peak memory 219780 kb
Host smart-d97575f9-ecf7-45a6-9359-74a0cd550e48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099787249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1099787249
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.2625937143
Short name T473
Test name
Test status
Simulation time 170025173 ps
CPU time 2.94 seconds
Started Aug 17 04:52:07 PM PDT 24
Finished Aug 17 04:52:10 PM PDT 24
Peak memory 207680 kb
Host smart-83ee8ee4-60ee-4337-96e2-01e604096834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625937143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.2625937143
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3357138206
Short name T372
Test name
Test status
Simulation time 61667341 ps
CPU time 2.68 seconds
Started Aug 17 04:51:50 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 210732 kb
Host smart-9f9e24e1-2704-4581-86f3-144cfe8ee581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357138206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3357138206
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1864175347
Short name T673
Test name
Test status
Simulation time 41105804 ps
CPU time 0.72 seconds
Started Aug 17 04:50:17 PM PDT 24
Finished Aug 17 04:50:18 PM PDT 24
Peak memory 206432 kb
Host smart-1edad9f4-c4da-452d-ad17-7372da864fcf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864175347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1864175347
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1749355653
Short name T412
Test name
Test status
Simulation time 127292569 ps
CPU time 4.03 seconds
Started Aug 17 04:50:20 PM PDT 24
Finished Aug 17 04:50:24 PM PDT 24
Peak memory 214740 kb
Host smart-f8a73c2a-57a8-4821-a4bd-e291daf77c58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1749355653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1749355653
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.301662119
Short name T1
Test name
Test status
Simulation time 81123649 ps
CPU time 2.17 seconds
Started Aug 17 04:50:21 PM PDT 24
Finished Aug 17 04:50:23 PM PDT 24
Peak memory 209324 kb
Host smart-abe9e58e-34a4-4f17-99ac-a6e622132339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301662119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.301662119
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1917227411
Short name T739
Test name
Test status
Simulation time 65769277 ps
CPU time 1.95 seconds
Started Aug 17 04:50:33 PM PDT 24
Finished Aug 17 04:50:35 PM PDT 24
Peak memory 209092 kb
Host smart-066df3fa-ae83-4bf7-908e-ab4101caf0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917227411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1917227411
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3325165289
Short name T46
Test name
Test status
Simulation time 321677785 ps
CPU time 8.03 seconds
Started Aug 17 04:50:17 PM PDT 24
Finished Aug 17 04:50:25 PM PDT 24
Peak memory 214604 kb
Host smart-e05c2b41-b1f6-44d9-a78c-b14a95772abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325165289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3325165289
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1822368207
Short name T851
Test name
Test status
Simulation time 458514188 ps
CPU time 3.2 seconds
Started Aug 17 04:50:34 PM PDT 24
Finished Aug 17 04:50:37 PM PDT 24
Peak memory 214656 kb
Host smart-e154b791-a1a7-4604-9691-fe2c28f75ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822368207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1822368207
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2390056737
Short name T101
Test name
Test status
Simulation time 1375920971 ps
CPU time 34.06 seconds
Started Aug 17 04:50:20 PM PDT 24
Finished Aug 17 04:50:59 PM PDT 24
Peak memory 214748 kb
Host smart-72ccc322-f1e7-4379-9e09-c60847263b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390056737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2390056737
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1743244099
Short name T678
Test name
Test status
Simulation time 1228384819 ps
CPU time 23.62 seconds
Started Aug 17 04:50:22 PM PDT 24
Finished Aug 17 04:50:45 PM PDT 24
Peak memory 209572 kb
Host smart-4b36d44a-99a8-4ac2-93d4-76f71c46df91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743244099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1743244099
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.702837749
Short name T39
Test name
Test status
Simulation time 502075361 ps
CPU time 6.08 seconds
Started Aug 17 04:50:18 PM PDT 24
Finished Aug 17 04:50:24 PM PDT 24
Peak memory 237916 kb
Host smart-89768dd3-c26f-4c5b-8f8d-4f089dd2be5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702837749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.702837749
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.942977330
Short name T507
Test name
Test status
Simulation time 146147416 ps
CPU time 5.35 seconds
Started Aug 17 04:50:33 PM PDT 24
Finished Aug 17 04:50:38 PM PDT 24
Peak memory 208776 kb
Host smart-49dbf478-e413-4652-8466-a2e132b52f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942977330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.942977330
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3206663740
Short name T171
Test name
Test status
Simulation time 1212056602 ps
CPU time 5.52 seconds
Started Aug 17 04:50:40 PM PDT 24
Finished Aug 17 04:50:45 PM PDT 24
Peak memory 209304 kb
Host smart-83441779-a4d9-4ea4-96b0-91f5843e2c62
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206663740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3206663740
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1944295034
Short name T816
Test name
Test status
Simulation time 60985792 ps
CPU time 2.84 seconds
Started Aug 17 04:50:19 PM PDT 24
Finished Aug 17 04:50:21 PM PDT 24
Peak memory 209392 kb
Host smart-a3900e90-424f-4528-ba8f-e1093bd19579
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944295034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1944295034
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1124736500
Short name T863
Test name
Test status
Simulation time 240600068 ps
CPU time 3.35 seconds
Started Aug 17 04:50:20 PM PDT 24
Finished Aug 17 04:50:23 PM PDT 24
Peak memory 209188 kb
Host smart-052d3818-9e3e-4e1d-92c1-2535b2c122f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124736500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1124736500
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4271277594
Short name T400
Test name
Test status
Simulation time 575363134 ps
CPU time 3.06 seconds
Started Aug 17 04:50:17 PM PDT 24
Finished Aug 17 04:50:20 PM PDT 24
Peak memory 210108 kb
Host smart-6c04cbad-c118-4488-a7ed-29d9fae6b4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271277594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4271277594
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.345737419
Short name T797
Test name
Test status
Simulation time 133411587 ps
CPU time 3.19 seconds
Started Aug 17 04:50:36 PM PDT 24
Finished Aug 17 04:50:39 PM PDT 24
Peak memory 209088 kb
Host smart-37f48429-c3b5-4ba1-8b51-1455456d47d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345737419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.345737419
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2285300088
Short name T230
Test name
Test status
Simulation time 77605834 ps
CPU time 4.13 seconds
Started Aug 17 04:50:41 PM PDT 24
Finished Aug 17 04:50:46 PM PDT 24
Peak memory 217748 kb
Host smart-f2614fdd-0e93-4531-a04d-984a884b2447
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285300088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2285300088
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1509840349
Short name T604
Test name
Test status
Simulation time 258978725 ps
CPU time 4.34 seconds
Started Aug 17 04:50:19 PM PDT 24
Finished Aug 17 04:50:23 PM PDT 24
Peak memory 208632 kb
Host smart-b842aa49-569c-4f63-a293-0ffe2fd74eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509840349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1509840349
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.274248015
Short name T370
Test name
Test status
Simulation time 543804203 ps
CPU time 3.53 seconds
Started Aug 17 04:50:18 PM PDT 24
Finished Aug 17 04:50:22 PM PDT 24
Peak memory 210740 kb
Host smart-4e018e22-fcff-4551-8d20-9becbda776da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274248015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.274248015
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.342469154
Short name T479
Test name
Test status
Simulation time 42669771 ps
CPU time 0.87 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 206376 kb
Host smart-be18eeee-da84-440b-92d6-30b83f02c46b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342469154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.342469154
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.996064063
Short name T881
Test name
Test status
Simulation time 748128168 ps
CPU time 11.02 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:52:04 PM PDT 24
Peak memory 215712 kb
Host smart-3b49d442-9981-422a-bf41-073569606b2e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=996064063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.996064063
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3533166350
Short name T19
Test name
Test status
Simulation time 89298205 ps
CPU time 2.7 seconds
Started Aug 17 04:51:50 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 210916 kb
Host smart-27b49cee-db92-40a4-8022-a1012f7dfac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533166350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3533166350
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2588858386
Short name T618
Test name
Test status
Simulation time 152681221 ps
CPU time 3.82 seconds
Started Aug 17 04:51:49 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 210440 kb
Host smart-1e25a86b-7719-4f09-a2d2-b746b49a1d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588858386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2588858386
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2406517860
Short name T628
Test name
Test status
Simulation time 564791641 ps
CPU time 4.16 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 214760 kb
Host smart-8c8f8d29-e7be-438a-a091-76a1dd1dc13c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406517860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2406517860
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1779246178
Short name T619
Test name
Test status
Simulation time 155426951 ps
CPU time 3.48 seconds
Started Aug 17 04:51:47 PM PDT 24
Finished Aug 17 04:51:51 PM PDT 24
Peak memory 222752 kb
Host smart-23beb543-9a21-4024-882a-6f9dcfd17470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779246178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1779246178
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3191552580
Short name T829
Test name
Test status
Simulation time 98862300 ps
CPU time 2.75 seconds
Started Aug 17 04:51:48 PM PDT 24
Finished Aug 17 04:51:51 PM PDT 24
Peak memory 206520 kb
Host smart-96626654-418a-49dc-ae63-70c94c3f29a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191552580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3191552580
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2779905705
Short name T574
Test name
Test status
Simulation time 2387331976 ps
CPU time 16.27 seconds
Started Aug 17 04:52:02 PM PDT 24
Finished Aug 17 04:52:18 PM PDT 24
Peak memory 210520 kb
Host smart-9c481430-aa5f-46fd-9ddb-040d9318dae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2779905705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2779905705
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1947585493
Short name T636
Test name
Test status
Simulation time 286496855 ps
CPU time 2.96 seconds
Started Aug 17 04:51:48 PM PDT 24
Finished Aug 17 04:51:51 PM PDT 24
Peak memory 207108 kb
Host smart-93888658-a519-4f93-967b-fabd3f9562db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947585493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1947585493
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1770153107
Short name T893
Test name
Test status
Simulation time 318228446 ps
CPU time 6.31 seconds
Started Aug 17 04:52:10 PM PDT 24
Finished Aug 17 04:52:16 PM PDT 24
Peak memory 206436 kb
Host smart-9cdc8ac2-f854-491a-975f-32fb2fa0a0e0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770153107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1770153107
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.235160974
Short name T185
Test name
Test status
Simulation time 383690098 ps
CPU time 3.13 seconds
Started Aug 17 04:51:49 PM PDT 24
Finished Aug 17 04:51:52 PM PDT 24
Peak memory 209536 kb
Host smart-05e83e72-29fc-48c6-8034-b77fc37d5633
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235160974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.235160974
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1233739285
Short name T624
Test name
Test status
Simulation time 428554938 ps
CPU time 6.31 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 209280 kb
Host smart-4b45c3a1-d98f-4583-9e04-4cde3347f6c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233739285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1233739285
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.2448639884
Short name T351
Test name
Test status
Simulation time 86084168 ps
CPU time 2.03 seconds
Started Aug 17 04:51:59 PM PDT 24
Finished Aug 17 04:52:01 PM PDT 24
Peak memory 214748 kb
Host smart-e0540ba3-2a76-417d-a67f-ec25c736475d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448639884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.2448639884
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3450658892
Short name T509
Test name
Test status
Simulation time 165910006 ps
CPU time 5.28 seconds
Started Aug 17 04:51:46 PM PDT 24
Finished Aug 17 04:51:51 PM PDT 24
Peak memory 208896 kb
Host smart-e4748de4-dfb8-4482-8162-fefff23be2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450658892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3450658892
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1637434146
Short name T220
Test name
Test status
Simulation time 1686935810 ps
CPU time 52.81 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:52:48 PM PDT 24
Peak memory 216772 kb
Host smart-6b0ef823-1803-463e-b33c-87903a3f6aa5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637434146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1637434146
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2086055637
Short name T465
Test name
Test status
Simulation time 864096379 ps
CPU time 3.47 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 208476 kb
Host smart-18ae0295-1874-4de3-ac66-fae42fbebd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086055637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2086055637
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3753285337
Short name T34
Test name
Test status
Simulation time 319337406 ps
CPU time 3.22 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:52:01 PM PDT 24
Peak memory 210524 kb
Host smart-836d3048-b716-44c0-997e-eff258ccae73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753285337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3753285337
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.461553898
Short name T809
Test name
Test status
Simulation time 38430616 ps
CPU time 0.81 seconds
Started Aug 17 04:52:03 PM PDT 24
Finished Aug 17 04:52:04 PM PDT 24
Peak memory 206412 kb
Host smart-b1247405-035b-4cec-a642-e3fbb65a93e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461553898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.461553898
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3290933617
Short name T409
Test name
Test status
Simulation time 232402661 ps
CPU time 4.48 seconds
Started Aug 17 04:52:00 PM PDT 24
Finished Aug 17 04:52:04 PM PDT 24
Peak memory 222856 kb
Host smart-479b9402-fab6-4243-b132-526ca3125503
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290933617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3290933617
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2029162760
Short name T24
Test name
Test status
Simulation time 503614613 ps
CPU time 4.94 seconds
Started Aug 17 04:51:50 PM PDT 24
Finished Aug 17 04:51:56 PM PDT 24
Peak memory 215152 kb
Host smart-2362e2fd-b0e7-4ba4-8144-96881a1d5719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029162760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2029162760
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.115161901
Short name T754
Test name
Test status
Simulation time 451034028 ps
CPU time 3.24 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 209836 kb
Host smart-6e5a6345-f78d-4d9b-b376-46b24e4fa774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115161901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.115161901
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3647442484
Short name T708
Test name
Test status
Simulation time 99409268 ps
CPU time 3.3 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:56 PM PDT 24
Peak memory 214776 kb
Host smart-a5806bd3-8b92-497a-a38f-8cfed18875ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647442484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3647442484
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2213005018
Short name T566
Test name
Test status
Simulation time 275101310 ps
CPU time 3.64 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 214792 kb
Host smart-0b47db61-7a0c-4ce3-ab1b-a505cf79e997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213005018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2213005018
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.309566085
Short name T561
Test name
Test status
Simulation time 151927049 ps
CPU time 4.58 seconds
Started Aug 17 04:51:49 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 210044 kb
Host smart-8dc00dcf-6f9f-443c-9dac-cae28119bea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309566085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.309566085
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2002264112
Short name T168
Test name
Test status
Simulation time 710428240 ps
CPU time 6.21 seconds
Started Aug 17 04:51:57 PM PDT 24
Finished Aug 17 04:52:04 PM PDT 24
Peak memory 209328 kb
Host smart-e405c8a5-d421-4aa6-ad96-b16c30740f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002264112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2002264112
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3330163230
Short name T526
Test name
Test status
Simulation time 56450687 ps
CPU time 2.96 seconds
Started Aug 17 04:52:05 PM PDT 24
Finished Aug 17 04:52:08 PM PDT 24
Peak memory 207240 kb
Host smart-18c6a62f-0ed3-4bb7-b4df-a93cf59fcdf5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330163230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3330163230
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.314816517
Short name T693
Test name
Test status
Simulation time 707919604 ps
CPU time 7.37 seconds
Started Aug 17 04:51:50 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 208992 kb
Host smart-d2aebab0-af09-4ab4-8b7a-350d16284675
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314816517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.314816517
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1587848467
Short name T695
Test name
Test status
Simulation time 241666966 ps
CPU time 4.08 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:59 PM PDT 24
Peak memory 207280 kb
Host smart-78e5a1c4-7283-4eca-a2ab-6a6cfffc7a42
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587848467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1587848467
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1183175352
Short name T735
Test name
Test status
Simulation time 3713870781 ps
CPU time 34.43 seconds
Started Aug 17 04:52:09 PM PDT 24
Finished Aug 17 04:52:43 PM PDT 24
Peak memory 209152 kb
Host smart-17473092-0a97-4b8a-9098-cc497bbd170d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183175352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1183175352
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1907109118
Short name T637
Test name
Test status
Simulation time 33927889 ps
CPU time 2.11 seconds
Started Aug 17 04:51:52 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 208868 kb
Host smart-4ed583e0-b2b7-4665-9fab-8894f9d2ddaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907109118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1907109118
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3159240862
Short name T211
Test name
Test status
Simulation time 3682502052 ps
CPU time 50.56 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:52:50 PM PDT 24
Peak memory 223052 kb
Host smart-59f3bf34-f1b9-418a-b781-8287f36119cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159240862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3159240862
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1656191576
Short name T441
Test name
Test status
Simulation time 176458567 ps
CPU time 4.18 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 207860 kb
Host smart-2d36e79d-3aff-49ff-866f-09c9896b5b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656191576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1656191576
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1220585300
Short name T748
Test name
Test status
Simulation time 56510589 ps
CPU time 1.26 seconds
Started Aug 17 04:52:36 PM PDT 24
Finished Aug 17 04:52:37 PM PDT 24
Peak memory 209152 kb
Host smart-36c3f513-2f25-4590-aa9f-2a29095e6a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220585300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1220585300
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1092208318
Short name T490
Test name
Test status
Simulation time 56211249 ps
CPU time 0.81 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 206396 kb
Host smart-5c10a3af-3317-4b46-a66f-ff88a7b4dd85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092208318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1092208318
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1831818005
Short name T117
Test name
Test status
Simulation time 80745099 ps
CPU time 3.38 seconds
Started Aug 17 04:51:59 PM PDT 24
Finished Aug 17 04:52:03 PM PDT 24
Peak memory 217880 kb
Host smart-a2d04af5-b6b0-4caf-af6b-68a65dd70fd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831818005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1831818005
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1877803839
Short name T524
Test name
Test status
Simulation time 107669206 ps
CPU time 1.66 seconds
Started Aug 17 04:52:22 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 214740 kb
Host smart-837aa04f-48d6-499b-bea3-2e1355d163d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877803839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1877803839
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2415768682
Short name T519
Test name
Test status
Simulation time 533076782 ps
CPU time 6.65 seconds
Started Aug 17 04:51:57 PM PDT 24
Finished Aug 17 04:52:04 PM PDT 24
Peak memory 223148 kb
Host smart-eebd4b30-5207-4b2a-9d94-beddbdaca1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415768682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2415768682
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3974089016
Short name T802
Test name
Test status
Simulation time 149983319 ps
CPU time 2.06 seconds
Started Aug 17 04:52:15 PM PDT 24
Finished Aug 17 04:52:17 PM PDT 24
Peak memory 214680 kb
Host smart-f7df354c-57ae-491e-a431-fac27220b609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974089016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3974089016
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1476277175
Short name T228
Test name
Test status
Simulation time 663146755 ps
CPU time 9.96 seconds
Started Aug 17 04:52:20 PM PDT 24
Finished Aug 17 04:52:30 PM PDT 24
Peak memory 218652 kb
Host smart-dbc9d096-0e47-45eb-b682-1de8cdd23928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476277175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1476277175
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2599398147
Short name T167
Test name
Test status
Simulation time 146973964 ps
CPU time 5.41 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:59 PM PDT 24
Peak memory 209100 kb
Host smart-4a57e8c7-8398-4bbd-9a3f-ac20ad236aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599398147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2599398147
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3436264492
Short name T658
Test name
Test status
Simulation time 87174661 ps
CPU time 1.85 seconds
Started Aug 17 04:51:52 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 207324 kb
Host smart-d4b81b3c-0e1e-4e12-a0d6-c1e7f75c13a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436264492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3436264492
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3209648353
Short name T549
Test name
Test status
Simulation time 165990360 ps
CPU time 4 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 207508 kb
Host smart-56b3461e-9053-40b6-8ac6-324932aa21d8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209648353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3209648353
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3602000719
Short name T63
Test name
Test status
Simulation time 441753358 ps
CPU time 3.46 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 209240 kb
Host smart-14c5d439-94b6-4eb2-8230-91193b1971fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602000719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3602000719
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3041410796
Short name T764
Test name
Test status
Simulation time 186870215 ps
CPU time 2.67 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 207468 kb
Host smart-d56e93c8-bc14-4087-8e44-c893445d0c2a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041410796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3041410796
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1201931833
Short name T248
Test name
Test status
Simulation time 127580813 ps
CPU time 2.58 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 214688 kb
Host smart-292f5f4f-c9c7-4fef-a770-43bd1afab6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201931833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1201931833
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4003793410
Short name T513
Test name
Test status
Simulation time 2350891472 ps
CPU time 22.28 seconds
Started Aug 17 04:52:11 PM PDT 24
Finished Aug 17 04:52:33 PM PDT 24
Peak memory 208840 kb
Host smart-bbf1740c-f119-43ed-be1d-449b5f82a4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003793410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4003793410
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1100987754
Short name T178
Test name
Test status
Simulation time 909739133 ps
CPU time 34.89 seconds
Started Aug 17 04:52:06 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 215908 kb
Host smart-a605a106-54f4-45ae-bb7b-f3656ecb723a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100987754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1100987754
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1498626002
Short name T91
Test name
Test status
Simulation time 2665399915 ps
CPU time 29.69 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:52:27 PM PDT 24
Peak memory 221408 kb
Host smart-1501dd6d-c406-4b46-80b2-03e0736621c9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498626002 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1498626002
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1599021664
Short name T612
Test name
Test status
Simulation time 17906666822 ps
CPU time 41.34 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:52:36 PM PDT 24
Peak memory 209212 kb
Host smart-0b422b6d-2f40-4f22-a745-774d4eed773b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599021664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1599021664
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.165833528
Short name T94
Test name
Test status
Simulation time 45542149 ps
CPU time 2.51 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 210704 kb
Host smart-e87b9b41-1fc9-4f84-991b-938898f7774d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165833528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.165833528
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3521505040
Short name T568
Test name
Test status
Simulation time 33363772 ps
CPU time 0.71 seconds
Started Aug 17 04:51:52 PM PDT 24
Finished Aug 17 04:51:53 PM PDT 24
Peak memory 206408 kb
Host smart-f15d5f2f-3420-4663-802d-73358c8358a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521505040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3521505040
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3859449267
Short name T753
Test name
Test status
Simulation time 201424224 ps
CPU time 3.35 seconds
Started Aug 17 04:52:20 PM PDT 24
Finished Aug 17 04:52:23 PM PDT 24
Peak memory 219580 kb
Host smart-3c425601-fb8c-422d-914d-5bdefd5855d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859449267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3859449267
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1940700812
Short name T652
Test name
Test status
Simulation time 109493059 ps
CPU time 3.8 seconds
Started Aug 17 04:51:52 PM PDT 24
Finished Aug 17 04:51:56 PM PDT 24
Peak memory 208620 kb
Host smart-79462696-138a-4663-9c7b-f853403d3769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940700812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1940700812
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.196392364
Short name T365
Test name
Test status
Simulation time 45956327 ps
CPU time 3.11 seconds
Started Aug 17 04:52:18 PM PDT 24
Finished Aug 17 04:52:21 PM PDT 24
Peak memory 209640 kb
Host smart-8a053da0-733e-4419-99c6-e38d57d2151e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196392364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.196392364
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2221548536
Short name T731
Test name
Test status
Simulation time 601542390 ps
CPU time 2.63 seconds
Started Aug 17 04:52:16 PM PDT 24
Finished Aug 17 04:52:19 PM PDT 24
Peak memory 219076 kb
Host smart-9af42953-9518-4bf2-bea8-23601e8b98b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221548536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2221548536
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.4135869644
Short name T135
Test name
Test status
Simulation time 188812116 ps
CPU time 2.83 seconds
Started Aug 17 04:52:22 PM PDT 24
Finished Aug 17 04:52:25 PM PDT 24
Peak memory 209940 kb
Host smart-44391831-154c-4d1d-9ad7-84c1b1c7a55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135869644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.4135869644
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2566907471
Short name T198
Test name
Test status
Simulation time 283801718 ps
CPU time 7.61 seconds
Started Aug 17 04:52:15 PM PDT 24
Finished Aug 17 04:52:23 PM PDT 24
Peak memory 218652 kb
Host smart-b7fac4ed-785b-43f6-b2b3-2a0649805a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566907471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2566907471
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.4121507268
Short name T707
Test name
Test status
Simulation time 184057542 ps
CPU time 6.57 seconds
Started Aug 17 04:51:58 PM PDT 24
Finished Aug 17 04:52:04 PM PDT 24
Peak memory 208996 kb
Host smart-7a851244-4b99-4c92-abc1-b338a856284c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121507268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.4121507268
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4265257213
Short name T578
Test name
Test status
Simulation time 180359230 ps
CPU time 2.57 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 207416 kb
Host smart-1b79cbb6-4207-488e-8368-d872f36aba35
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265257213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4265257213
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3753560245
Short name T733
Test name
Test status
Simulation time 44099894 ps
CPU time 1.89 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 207704 kb
Host smart-9568d250-3ad4-4423-88f6-c316da854ac8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753560245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3753560245
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.3916340913
Short name T488
Test name
Test status
Simulation time 207533177 ps
CPU time 5.79 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 208336 kb
Host smart-21db5693-62e3-422f-ba87-eeb0d034f2ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916340913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3916340913
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2607069163
Short name T197
Test name
Test status
Simulation time 426443508 ps
CPU time 3.67 seconds
Started Aug 17 04:52:10 PM PDT 24
Finished Aug 17 04:52:14 PM PDT 24
Peak memory 218820 kb
Host smart-0b6a73d8-f880-41e8-b361-52067d424d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607069163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2607069163
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1680723815
Short name T382
Test name
Test status
Simulation time 53977424 ps
CPU time 2.57 seconds
Started Aug 17 04:51:51 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 208624 kb
Host smart-e25ac139-7154-4006-b95e-8aa1990dc5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680723815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1680723815
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1207373869
Short name T261
Test name
Test status
Simulation time 170773222 ps
CPU time 4.34 seconds
Started Aug 17 04:52:18 PM PDT 24
Finished Aug 17 04:52:23 PM PDT 24
Peak memory 218764 kb
Host smart-d58fdfc8-65c7-4596-b017-1bbedfe01b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207373869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1207373869
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.45120386
Short name T716
Test name
Test status
Simulation time 66445014 ps
CPU time 1.92 seconds
Started Aug 17 04:52:22 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 210908 kb
Host smart-a7ade8ff-13d1-4f8f-a125-e312c4e6d568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45120386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.45120386
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.792794092
Short name T820
Test name
Test status
Simulation time 44584334 ps
CPU time 0.7 seconds
Started Aug 17 04:51:56 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 206404 kb
Host smart-6a295e3c-4f64-4b8a-9a99-094018ea9c96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792794092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.792794092
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1268074765
Short name T403
Test name
Test status
Simulation time 122684274 ps
CPU time 2.56 seconds
Started Aug 17 04:52:15 PM PDT 24
Finished Aug 17 04:52:18 PM PDT 24
Peak memory 215680 kb
Host smart-16ef7dd0-220d-40da-9e22-ba2081493363
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1268074765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1268074765
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3547580832
Short name T18
Test name
Test status
Simulation time 207133122 ps
CPU time 2.88 seconds
Started Aug 17 04:52:08 PM PDT 24
Finished Aug 17 04:52:11 PM PDT 24
Peak memory 217196 kb
Host smart-061ce8b4-570f-4029-b0bf-15b8d2f33d60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547580832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3547580832
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.827776237
Short name T350
Test name
Test status
Simulation time 887709534 ps
CPU time 2.58 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:56 PM PDT 24
Peak memory 222900 kb
Host smart-0d3e3262-897e-4b27-ba7c-f60cb026f66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827776237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.827776237
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2448231628
Short name T339
Test name
Test status
Simulation time 623076449 ps
CPU time 5.13 seconds
Started Aug 17 04:52:11 PM PDT 24
Finished Aug 17 04:52:16 PM PDT 24
Peak memory 214756 kb
Host smart-c9fcfb75-7b18-48d9-a85c-4a2da20394f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448231628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2448231628
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3243105858
Short name T758
Test name
Test status
Simulation time 49078226 ps
CPU time 2.8 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:52:00 PM PDT 24
Peak memory 214740 kb
Host smart-4dd8a678-6e08-494d-a0e5-89f450215601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243105858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3243105858
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.861403258
Short name T127
Test name
Test status
Simulation time 105100530 ps
CPU time 4.54 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 211148 kb
Host smart-9ab6a34e-ac36-48a7-a1e6-d460eff7e8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861403258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.861403258
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2590183410
Short name T611
Test name
Test status
Simulation time 105997305 ps
CPU time 4 seconds
Started Aug 17 04:52:01 PM PDT 24
Finished Aug 17 04:52:05 PM PDT 24
Peak memory 209744 kb
Host smart-241ec0b4-54d9-47ac-85b3-e0746dfc6844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590183410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2590183410
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.749162078
Short name T769
Test name
Test status
Simulation time 385996992 ps
CPU time 4.8 seconds
Started Aug 17 04:52:12 PM PDT 24
Finished Aug 17 04:52:17 PM PDT 24
Peak memory 207180 kb
Host smart-857bb177-ff4e-4d4d-bb5e-852884e218c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749162078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.749162078
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3355610385
Short name T790
Test name
Test status
Simulation time 233946010 ps
CPU time 3.97 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 209284 kb
Host smart-0ce3263b-836e-4270-9415-36294f1bcb67
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355610385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3355610385
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.152942352
Short name T608
Test name
Test status
Simulation time 301953754 ps
CPU time 2.8 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 207304 kb
Host smart-9e5a780f-d44f-4104-b215-f3fc910349a3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152942352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.152942352
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.739106835
Short name T494
Test name
Test status
Simulation time 189862880 ps
CPU time 4.19 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:58 PM PDT 24
Peak memory 214772 kb
Host smart-aee90507-974d-4037-9469-4c29b38789e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739106835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.739106835
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1730733151
Short name T751
Test name
Test status
Simulation time 2024845251 ps
CPU time 12.74 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:52:08 PM PDT 24
Peak memory 208856 kb
Host smart-755564ce-d749-456c-a54f-3ee5f7cb7eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730733151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1730733151
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.2034726328
Short name T596
Test name
Test status
Simulation time 801834880 ps
CPU time 8.35 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:52:03 PM PDT 24
Peak memory 219508 kb
Host smart-b172f849-2815-4c1b-a18a-7fc972a23eb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034726328 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.2034726328
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.4202975474
Short name T66
Test name
Test status
Simulation time 65585861 ps
CPU time 3.07 seconds
Started Aug 17 04:52:03 PM PDT 24
Finished Aug 17 04:52:07 PM PDT 24
Peak memory 209812 kb
Host smart-84f2df97-60a6-4a16-8784-e5483102c80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202975474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.4202975474
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3103668887
Short name T698
Test name
Test status
Simulation time 97611787 ps
CPU time 3.42 seconds
Started Aug 17 04:52:01 PM PDT 24
Finished Aug 17 04:52:04 PM PDT 24
Peak memory 210364 kb
Host smart-62c76530-0f24-4b01-8ee4-29ec0d509fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103668887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3103668887
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3004014816
Short name T564
Test name
Test status
Simulation time 14709217 ps
CPU time 0.92 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:54 PM PDT 24
Peak memory 206532 kb
Host smart-29a8d20e-bd79-4829-b1a7-fde28f983f14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004014816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3004014816
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1629024669
Short name T282
Test name
Test status
Simulation time 833974180 ps
CPU time 10.18 seconds
Started Aug 17 04:51:57 PM PDT 24
Finished Aug 17 04:52:08 PM PDT 24
Peak memory 210560 kb
Host smart-d1034f6a-f71e-4321-8a35-ab656dc6c9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629024669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1629024669
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.751534216
Short name T877
Test name
Test status
Simulation time 30705045 ps
CPU time 1.98 seconds
Started Aug 17 04:52:14 PM PDT 24
Finished Aug 17 04:52:17 PM PDT 24
Peak memory 214960 kb
Host smart-4e9fa641-9282-4049-a735-bbffd783562c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751534216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.751534216
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1234058213
Short name T226
Test name
Test status
Simulation time 115376595 ps
CPU time 5.71 seconds
Started Aug 17 04:52:03 PM PDT 24
Finished Aug 17 04:52:09 PM PDT 24
Peak memory 210672 kb
Host smart-f290112d-e829-446a-a789-a159cdeb4cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234058213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1234058213
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.4007376258
Short name T492
Test name
Test status
Simulation time 758844684 ps
CPU time 4.8 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:59 PM PDT 24
Peak memory 209752 kb
Host smart-1b6b1b10-5fad-441a-9221-129119724f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007376258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.4007376258
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.528654615
Short name T284
Test name
Test status
Simulation time 98739993 ps
CPU time 2.63 seconds
Started Aug 17 04:51:57 PM PDT 24
Finished Aug 17 04:51:59 PM PDT 24
Peak memory 207308 kb
Host smart-fdbb98a5-21b6-4467-bef8-e90ccd37e681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528654615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.528654615
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2802038551
Short name T385
Test name
Test status
Simulation time 201110199 ps
CPU time 3.05 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:56 PM PDT 24
Peak memory 207340 kb
Host smart-48a29a15-aad0-4947-bbea-199745ff0c61
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802038551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2802038551
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2103024209
Short name T690
Test name
Test status
Simulation time 131375944 ps
CPU time 4.83 seconds
Started Aug 17 04:52:19 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 208812 kb
Host smart-7fb909de-eaa4-4b53-924c-3d92ccd21616
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103024209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2103024209
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.288761094
Short name T70
Test name
Test status
Simulation time 48961324 ps
CPU time 2.16 seconds
Started Aug 17 04:51:53 PM PDT 24
Finished Aug 17 04:51:55 PM PDT 24
Peak memory 209100 kb
Host smart-67f4bf72-f260-487a-ba29-ef40af96ff68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288761094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.288761094
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2574026270
Short name T326
Test name
Test status
Simulation time 109221635 ps
CPU time 3.62 seconds
Started Aug 17 04:51:56 PM PDT 24
Finished Aug 17 04:51:59 PM PDT 24
Peak memory 209892 kb
Host smart-c6e01dc7-5390-4442-af49-d071f70c517b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574026270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2574026270
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2094716455
Short name T189
Test name
Test status
Simulation time 344336772 ps
CPU time 3.76 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:52:01 PM PDT 24
Peak memory 207332 kb
Host smart-c1ff08d8-d32f-45bb-924a-d8be2a51c76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094716455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2094716455
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2566472263
Short name T890
Test name
Test status
Simulation time 3523957403 ps
CPU time 23.16 seconds
Started Aug 17 04:51:55 PM PDT 24
Finished Aug 17 04:52:18 PM PDT 24
Peak memory 210152 kb
Host smart-7a90c7db-548e-4ab2-9404-b5badefc5bfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566472263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2566472263
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3868540338
Short name T73
Test name
Test status
Simulation time 155269848 ps
CPU time 3.1 seconds
Started Aug 17 04:51:54 PM PDT 24
Finished Aug 17 04:51:57 PM PDT 24
Peak memory 210976 kb
Host smart-83e22ef2-a075-4086-abbb-5e3e733e5dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868540338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3868540338
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.435644139
Short name T423
Test name
Test status
Simulation time 10246426 ps
CPU time 0.77 seconds
Started Aug 17 04:52:15 PM PDT 24
Finished Aug 17 04:52:16 PM PDT 24
Peak memory 206384 kb
Host smart-80ba72bc-877e-48fa-8c9c-e3722e271a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435644139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.435644139
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.994296529
Short name T411
Test name
Test status
Simulation time 342534722 ps
CPU time 5.11 seconds
Started Aug 17 04:52:25 PM PDT 24
Finished Aug 17 04:52:30 PM PDT 24
Peak memory 215880 kb
Host smart-58c87b92-9490-4f0d-977a-8278de9670a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=994296529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.994296529
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2512932359
Short name T828
Test name
Test status
Simulation time 482747567 ps
CPU time 2.42 seconds
Started Aug 17 04:52:27 PM PDT 24
Finished Aug 17 04:52:29 PM PDT 24
Peak memory 208164 kb
Host smart-6357aedf-1151-40dd-988e-da83963bda42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512932359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2512932359
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2771216821
Short name T763
Test name
Test status
Simulation time 80781040 ps
CPU time 4.26 seconds
Started Aug 17 04:52:19 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 214900 kb
Host smart-4d597e12-1446-4643-b3ce-151221d01863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771216821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2771216821
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2004280613
Short name T721
Test name
Test status
Simulation time 104634727 ps
CPU time 2.33 seconds
Started Aug 17 04:52:04 PM PDT 24
Finished Aug 17 04:52:07 PM PDT 24
Peak memory 220640 kb
Host smart-36f38c65-e8e1-4671-aa30-ef9abbea141d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004280613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2004280613
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1903338324
Short name T655
Test name
Test status
Simulation time 141858376 ps
CPU time 3.6 seconds
Started Aug 17 04:52:14 PM PDT 24
Finished Aug 17 04:52:18 PM PDT 24
Peak memory 209872 kb
Host smart-553b640d-789e-46df-be67-03c420b02b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903338324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1903338324
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.4026105722
Short name T361
Test name
Test status
Simulation time 2001160843 ps
CPU time 7.13 seconds
Started Aug 17 04:52:15 PM PDT 24
Finished Aug 17 04:52:22 PM PDT 24
Peak memory 208912 kb
Host smart-61afbc82-8db4-4fe5-a973-b35db79ef7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026105722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.4026105722
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.4107853907
Short name T170
Test name
Test status
Simulation time 25443913 ps
CPU time 2.07 seconds
Started Aug 17 04:52:03 PM PDT 24
Finished Aug 17 04:52:05 PM PDT 24
Peak memory 209080 kb
Host smart-16fdf4d2-f834-4438-8643-10f4c94bf292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107853907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.4107853907
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2171745727
Short name T440
Test name
Test status
Simulation time 90467082 ps
CPU time 2.16 seconds
Started Aug 17 04:52:13 PM PDT 24
Finished Aug 17 04:52:15 PM PDT 24
Peak memory 208920 kb
Host smart-ccfe8e4e-ab3f-4a6f-a21c-90d84ad94dad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171745727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2171745727
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1153412968
Short name T874
Test name
Test status
Simulation time 1253817409 ps
CPU time 27.37 seconds
Started Aug 17 04:52:13 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 209100 kb
Host smart-79ab86e4-efc8-4213-aa51-08b1ed94f528
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153412968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1153412968
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2504816566
Short name T237
Test name
Test status
Simulation time 57044758 ps
CPU time 2.4 seconds
Started Aug 17 04:52:23 PM PDT 24
Finished Aug 17 04:52:26 PM PDT 24
Peak memory 209308 kb
Host smart-331b6f08-3f34-469e-adf7-df0d9c35249e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2504816566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2504816566
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2929099355
Short name T483
Test name
Test status
Simulation time 52160880 ps
CPU time 2.85 seconds
Started Aug 17 04:52:20 PM PDT 24
Finished Aug 17 04:52:23 PM PDT 24
Peak memory 216260 kb
Host smart-77c993ab-ab47-41c9-843f-421a733ab489
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929099355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2929099355
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2379197781
Short name T653
Test name
Test status
Simulation time 2341259973 ps
CPU time 12.98 seconds
Started Aug 17 04:51:58 PM PDT 24
Finished Aug 17 04:52:11 PM PDT 24
Peak memory 209316 kb
Host smart-63f03172-fa04-4c92-8961-76280591454c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379197781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2379197781
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2522565526
Short name T177
Test name
Test status
Simulation time 12522315406 ps
CPU time 56.81 seconds
Started Aug 17 04:52:22 PM PDT 24
Finished Aug 17 04:53:19 PM PDT 24
Peak memory 221256 kb
Host smart-a7b4cc8e-a1ce-4fae-bc04-75ec19b9859b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522565526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2522565526
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3995731116
Short name T729
Test name
Test status
Simulation time 9222605833 ps
CPU time 30.76 seconds
Started Aug 17 04:52:20 PM PDT 24
Finished Aug 17 04:52:51 PM PDT 24
Peak memory 210076 kb
Host smart-1547305c-2838-4591-88e9-f3120fd82884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995731116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3995731116
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.4187697970
Short name T35
Test name
Test status
Simulation time 161395062 ps
CPU time 1.61 seconds
Started Aug 17 04:52:15 PM PDT 24
Finished Aug 17 04:52:16 PM PDT 24
Peak memory 210752 kb
Host smart-1e47f495-ce88-4a7d-a088-d9721de88d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187697970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.4187697970
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3651388140
Short name T418
Test name
Test status
Simulation time 11893246 ps
CPU time 0.9 seconds
Started Aug 17 04:52:23 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 206256 kb
Host smart-5a85c9f6-1b10-40f6-8443-32647336494a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651388140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3651388140
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.647114575
Short name T311
Test name
Test status
Simulation time 173803395 ps
CPU time 3.62 seconds
Started Aug 17 04:52:12 PM PDT 24
Finished Aug 17 04:52:16 PM PDT 24
Peak memory 215636 kb
Host smart-63ed07cc-8423-4ecc-be7f-f12f698d378d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=647114575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.647114575
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.43097471
Short name T238
Test name
Test status
Simulation time 172262072 ps
CPU time 3.84 seconds
Started Aug 17 04:52:18 PM PDT 24
Finished Aug 17 04:52:21 PM PDT 24
Peak memory 210264 kb
Host smart-e7039423-f594-4409-9894-ba5bffa37f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43097471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.43097471
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.66895341
Short name T455
Test name
Test status
Simulation time 3188877237 ps
CPU time 22.29 seconds
Started Aug 17 04:52:20 PM PDT 24
Finished Aug 17 04:52:43 PM PDT 24
Peak memory 214808 kb
Host smart-5b4db7bf-9c9b-4618-9cb0-2c5e1a718465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66895341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.66895341
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2200423739
Short name T44
Test name
Test status
Simulation time 381887156 ps
CPU time 4.57 seconds
Started Aug 17 04:52:14 PM PDT 24
Finished Aug 17 04:52:19 PM PDT 24
Peak memory 222856 kb
Host smart-96173919-2caa-421d-b59a-30262011b620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200423739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2200423739
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1615343626
Short name T348
Test name
Test status
Simulation time 60695080 ps
CPU time 3.27 seconds
Started Aug 17 04:52:22 PM PDT 24
Finished Aug 17 04:52:26 PM PDT 24
Peak memory 222276 kb
Host smart-655422c7-be97-431d-9caa-4a7e4abf1d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615343626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1615343626
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2328726772
Short name T97
Test name
Test status
Simulation time 720305619 ps
CPU time 5.4 seconds
Started Aug 17 04:52:26 PM PDT 24
Finished Aug 17 04:52:32 PM PDT 24
Peak memory 210956 kb
Host smart-a844719f-28ef-4fa8-986c-ff5eac2c95b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328726772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2328726772
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.382245007
Short name T713
Test name
Test status
Simulation time 2229420845 ps
CPU time 10.92 seconds
Started Aug 17 04:52:19 PM PDT 24
Finished Aug 17 04:52:30 PM PDT 24
Peak memory 218768 kb
Host smart-3088aa2d-d69f-4e42-976f-ee30dc4c6127
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382245007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.382245007
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2991182009
Short name T565
Test name
Test status
Simulation time 452401728 ps
CPU time 4.28 seconds
Started Aug 17 04:52:21 PM PDT 24
Finished Aug 17 04:52:25 PM PDT 24
Peak memory 208968 kb
Host smart-642a27f1-c2b4-42ea-8ab6-e2cfb0bb7d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991182009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2991182009
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.262893215
Short name T804
Test name
Test status
Simulation time 300683698 ps
CPU time 4.71 seconds
Started Aug 17 04:52:19 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 208952 kb
Host smart-52b6f50e-17a7-4b0a-b290-94321d7e72ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262893215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.262893215
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1200318306
Short name T537
Test name
Test status
Simulation time 189114930 ps
CPU time 2.55 seconds
Started Aug 17 04:52:16 PM PDT 24
Finished Aug 17 04:52:19 PM PDT 24
Peak memory 207396 kb
Host smart-c44f8f30-974a-4218-b644-dba01b80d8c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200318306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1200318306
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3262128561
Short name T756
Test name
Test status
Simulation time 93692310 ps
CPU time 2.1 seconds
Started Aug 17 04:52:22 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 208900 kb
Host smart-8d280d4e-8946-4734-bda5-a78005ddd0e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262128561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3262128561
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3472596225
Short name T38
Test name
Test status
Simulation time 56868576 ps
CPU time 2.08 seconds
Started Aug 17 04:52:25 PM PDT 24
Finished Aug 17 04:52:27 PM PDT 24
Peak memory 214716 kb
Host smart-5c0b4064-b7fd-4315-999c-e9fe724389c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472596225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3472596225
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.447593590
Short name T438
Test name
Test status
Simulation time 248269822 ps
CPU time 2.96 seconds
Started Aug 17 04:52:22 PM PDT 24
Finished Aug 17 04:52:25 PM PDT 24
Peak memory 209152 kb
Host smart-0cc62d45-1319-44fe-8f69-4040d5deff5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447593590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.447593590
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2006064578
Short name T140
Test name
Test status
Simulation time 735603543 ps
CPU time 20.84 seconds
Started Aug 17 04:52:28 PM PDT 24
Finished Aug 17 04:52:48 PM PDT 24
Peak memory 220456 kb
Host smart-7afb8408-c041-4cd0-ad89-057171980cac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006064578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2006064578
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1963204243
Short name T609
Test name
Test status
Simulation time 730775787 ps
CPU time 7.54 seconds
Started Aug 17 04:52:12 PM PDT 24
Finished Aug 17 04:52:19 PM PDT 24
Peak memory 208400 kb
Host smart-2a415491-0646-4234-9e60-2bd3f9a2495f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963204243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1963204243
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3892110001
Short name T798
Test name
Test status
Simulation time 805449111 ps
CPU time 2.65 seconds
Started Aug 17 04:52:26 PM PDT 24
Finished Aug 17 04:52:28 PM PDT 24
Peak memory 210504 kb
Host smart-e371fdbb-7f24-484e-a0ab-b088d614489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892110001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3892110001
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3284535347
Short name T482
Test name
Test status
Simulation time 13880497 ps
CPU time 0.78 seconds
Started Aug 17 04:52:23 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 206368 kb
Host smart-b1686574-ee7f-476c-b1a4-f1ba6504e96f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284535347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3284535347
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.211076805
Short name T736
Test name
Test status
Simulation time 2421033775 ps
CPU time 13.01 seconds
Started Aug 17 04:52:24 PM PDT 24
Finished Aug 17 04:52:37 PM PDT 24
Peak memory 218968 kb
Host smart-9c6e9c92-fe69-4c20-a752-42e355343258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=211076805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.211076805
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2363966669
Short name T244
Test name
Test status
Simulation time 29904769 ps
CPU time 2.12 seconds
Started Aug 17 04:52:32 PM PDT 24
Finished Aug 17 04:52:34 PM PDT 24
Peak memory 214688 kb
Host smart-085b6325-c910-458d-b7e8-596c9a127095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363966669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2363966669
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3781758353
Short name T232
Test name
Test status
Simulation time 1712164615 ps
CPU time 7.74 seconds
Started Aug 17 04:52:23 PM PDT 24
Finished Aug 17 04:52:31 PM PDT 24
Peak memory 214724 kb
Host smart-0c999974-334d-4472-aa54-09d07bd6a417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781758353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3781758353
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1925985477
Short name T345
Test name
Test status
Simulation time 434013710 ps
CPU time 9.35 seconds
Started Aug 17 04:52:19 PM PDT 24
Finished Aug 17 04:52:28 PM PDT 24
Peak memory 210532 kb
Host smart-a149b381-bf1f-43e8-8ba1-bb54a167d18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925985477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1925985477
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.4097404518
Short name T430
Test name
Test status
Simulation time 135660849 ps
CPU time 2.45 seconds
Started Aug 17 04:52:18 PM PDT 24
Finished Aug 17 04:52:20 PM PDT 24
Peak memory 207272 kb
Host smart-08afde13-d720-44ea-b7a0-e27c129010c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097404518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4097404518
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2796023384
Short name T679
Test name
Test status
Simulation time 3292170829 ps
CPU time 14.14 seconds
Started Aug 17 04:52:19 PM PDT 24
Finished Aug 17 04:52:33 PM PDT 24
Peak memory 209188 kb
Host smart-a497aca4-c911-494f-8ef7-bb47a9897e6f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796023384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2796023384
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3788376064
Short name T427
Test name
Test status
Simulation time 2162686013 ps
CPU time 19.84 seconds
Started Aug 17 04:52:25 PM PDT 24
Finished Aug 17 04:52:45 PM PDT 24
Peak memory 208444 kb
Host smart-86c72a2d-157e-447b-b8ca-488a69759a35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788376064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3788376064
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3848041420
Short name T638
Test name
Test status
Simulation time 70653360 ps
CPU time 2.14 seconds
Started Aug 17 04:52:35 PM PDT 24
Finished Aug 17 04:52:37 PM PDT 24
Peak memory 207176 kb
Host smart-d2218511-cf2e-4fd4-b9fd-1708ef104ef9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848041420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3848041420
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.154790915
Short name T595
Test name
Test status
Simulation time 1370307850 ps
CPU time 24.76 seconds
Started Aug 17 04:52:22 PM PDT 24
Finished Aug 17 04:52:46 PM PDT 24
Peak memory 209576 kb
Host smart-47bef6bb-3c36-4944-9107-2f380ab184fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154790915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.154790915
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.4180504070
Short name T31
Test name
Test status
Simulation time 1368629660 ps
CPU time 19.66 seconds
Started Aug 17 04:52:14 PM PDT 24
Finished Aug 17 04:52:33 PM PDT 24
Peak memory 208320 kb
Host smart-e395fb3d-daf0-473d-8a64-fad786f4c907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180504070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.4180504070
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.863900758
Short name T267
Test name
Test status
Simulation time 1224624792 ps
CPU time 22.53 seconds
Started Aug 17 04:52:29 PM PDT 24
Finished Aug 17 04:52:52 PM PDT 24
Peak memory 214992 kb
Host smart-72618ee9-60fe-488d-9024-140e9f22d6ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863900758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.863900758
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1008867648
Short name T833
Test name
Test status
Simulation time 274909719 ps
CPU time 6.67 seconds
Started Aug 17 04:52:25 PM PDT 24
Finished Aug 17 04:52:32 PM PDT 24
Peak memory 223004 kb
Host smart-761fcee5-5b2b-420a-be4d-bd955f4ae378
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008867648 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1008867648
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.738318764
Short name T651
Test name
Test status
Simulation time 255297175 ps
CPU time 4.78 seconds
Started Aug 17 04:52:34 PM PDT 24
Finished Aug 17 04:52:38 PM PDT 24
Peak memory 210056 kb
Host smart-050c0957-3c27-4c58-85c5-3695f85a9917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738318764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.738318764
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2660185670
Short name T186
Test name
Test status
Simulation time 146256873 ps
CPU time 3.14 seconds
Started Aug 17 04:52:14 PM PDT 24
Finished Aug 17 04:52:17 PM PDT 24
Peak memory 210792 kb
Host smart-b254b21f-5e78-493e-b530-be0c25441e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660185670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2660185670
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2950376562
Short name T573
Test name
Test status
Simulation time 31501772 ps
CPU time 0.75 seconds
Started Aug 17 04:52:39 PM PDT 24
Finished Aug 17 04:52:40 PM PDT 24
Peak memory 206400 kb
Host smart-cdd8dc5d-5a1e-463c-a63b-0be798d943be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950376562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2950376562
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3021083990
Short name T405
Test name
Test status
Simulation time 41427007 ps
CPU time 2.93 seconds
Started Aug 17 04:52:24 PM PDT 24
Finished Aug 17 04:52:27 PM PDT 24
Peak memory 214956 kb
Host smart-8507e8f1-7566-4983-9e71-32b7f7231d2d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3021083990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3021083990
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.421077603
Short name T459
Test name
Test status
Simulation time 78093357 ps
CPU time 1.51 seconds
Started Aug 17 04:52:14 PM PDT 24
Finished Aug 17 04:52:16 PM PDT 24
Peak memory 210184 kb
Host smart-98b495a4-96f6-45df-b363-7ace3116aa43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421077603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.421077603
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2345760720
Short name T314
Test name
Test status
Simulation time 678483112 ps
CPU time 4.98 seconds
Started Aug 17 04:52:20 PM PDT 24
Finished Aug 17 04:52:25 PM PDT 24
Peak memory 214748 kb
Host smart-10897a29-e56c-4973-bd19-7f6a78888dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2345760720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2345760720
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1335156833
Short name T723
Test name
Test status
Simulation time 179118042 ps
CPU time 2.56 seconds
Started Aug 17 04:52:21 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 214716 kb
Host smart-7c9b9e01-4972-4fdb-9a02-fb9058c347f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335156833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1335156833
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2130175626
Short name T774
Test name
Test status
Simulation time 91352888 ps
CPU time 3.44 seconds
Started Aug 17 04:52:38 PM PDT 24
Finished Aug 17 04:52:41 PM PDT 24
Peak memory 214656 kb
Host smart-72dc4ec4-9fce-4c82-a3fe-6c6bbb0e874a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130175626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2130175626
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1040547297
Short name T840
Test name
Test status
Simulation time 111458180 ps
CPU time 2.86 seconds
Started Aug 17 04:52:29 PM PDT 24
Finished Aug 17 04:52:32 PM PDT 24
Peak memory 223012 kb
Host smart-c6022fd2-534a-4ec7-a5ec-71c2ee4abe6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040547297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1040547297
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.291864901
Short name T11
Test name
Test status
Simulation time 412001859 ps
CPU time 3.91 seconds
Started Aug 17 04:52:29 PM PDT 24
Finished Aug 17 04:52:34 PM PDT 24
Peak memory 214820 kb
Host smart-be14101a-5e0b-4d4d-83be-8e4338b6ab73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291864901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.291864901
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.731434026
Short name T260
Test name
Test status
Simulation time 62016270 ps
CPU time 3.14 seconds
Started Aug 17 04:52:23 PM PDT 24
Finished Aug 17 04:52:26 PM PDT 24
Peak memory 208648 kb
Host smart-8e8c9efc-98bf-42f2-a128-35e148d09e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731434026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.731434026
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2580014397
Short name T562
Test name
Test status
Simulation time 173436723 ps
CPU time 4.79 seconds
Started Aug 17 04:52:21 PM PDT 24
Finished Aug 17 04:52:26 PM PDT 24
Peak memory 207364 kb
Host smart-73681ebf-a98f-4123-8c5c-b9280bf47bc1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580014397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2580014397
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1541881186
Short name T815
Test name
Test status
Simulation time 41079145 ps
CPU time 1.89 seconds
Started Aug 17 04:52:27 PM PDT 24
Finished Aug 17 04:52:29 PM PDT 24
Peak memory 209232 kb
Host smart-08fd191c-b8b6-43ee-9c54-ee43be474c46
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541881186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1541881186
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.668500907
Short name T887
Test name
Test status
Simulation time 114879000 ps
CPU time 2.21 seconds
Started Aug 17 04:52:23 PM PDT 24
Finished Aug 17 04:52:25 PM PDT 24
Peak memory 207372 kb
Host smart-f85210f8-9a21-43a3-af8d-1a66e8285407
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668500907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.668500907
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1741095571
Short name T844
Test name
Test status
Simulation time 63191240 ps
CPU time 2.38 seconds
Started Aug 17 04:52:21 PM PDT 24
Finished Aug 17 04:52:24 PM PDT 24
Peak memory 208760 kb
Host smart-9930f2dd-dedf-499d-acff-4420a472ebf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741095571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1741095571
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3112555283
Short name T443
Test name
Test status
Simulation time 325258999 ps
CPU time 6.69 seconds
Started Aug 17 04:52:31 PM PDT 24
Finished Aug 17 04:52:37 PM PDT 24
Peak memory 208432 kb
Host smart-dec17b05-0145-4797-9ee3-d5966a52101a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112555283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3112555283
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3781714982
Short name T176
Test name
Test status
Simulation time 9952195855 ps
CPU time 146.34 seconds
Started Aug 17 04:52:19 PM PDT 24
Finished Aug 17 04:54:46 PM PDT 24
Peak memory 217704 kb
Host smart-5d1dc6f7-1165-499b-a3b8-3474ba2249cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781714982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3781714982
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.3982284500
Short name T95
Test name
Test status
Simulation time 330068862 ps
CPU time 14.61 seconds
Started Aug 17 04:52:41 PM PDT 24
Finished Aug 17 04:52:56 PM PDT 24
Peak memory 222976 kb
Host smart-38c5e8b4-a339-445f-a4db-c55e5b227f83
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982284500 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.3982284500
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3511317367
Short name T663
Test name
Test status
Simulation time 118729013 ps
CPU time 4.3 seconds
Started Aug 17 04:52:25 PM PDT 24
Finished Aug 17 04:52:29 PM PDT 24
Peak memory 207748 kb
Host smart-c4c769e4-9c1e-42e2-aad1-e6adb30a7301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511317367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3511317367
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.555770143
Short name T371
Test name
Test status
Simulation time 132560520 ps
CPU time 2.2 seconds
Started Aug 17 04:52:29 PM PDT 24
Finished Aug 17 04:52:31 PM PDT 24
Peak memory 210360 kb
Host smart-fbdf8060-f023-4108-ab3b-4a1e40dbe81b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555770143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.555770143
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1622828851
Short name T899
Test name
Test status
Simulation time 50845405 ps
CPU time 0.81 seconds
Started Aug 17 04:50:32 PM PDT 24
Finished Aug 17 04:50:33 PM PDT 24
Peak memory 206408 kb
Host smart-ba359b06-0901-4aee-a4d1-a2ebb532b88c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622828851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1622828851
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.430596128
Short name T357
Test name
Test status
Simulation time 75616852 ps
CPU time 2.99 seconds
Started Aug 17 04:50:17 PM PDT 24
Finished Aug 17 04:50:20 PM PDT 24
Peak memory 215736 kb
Host smart-c271ec59-1f6a-4530-bd9e-6f96139159ac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=430596128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.430596128
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.4240931622
Short name T576
Test name
Test status
Simulation time 84090243 ps
CPU time 1.8 seconds
Started Aug 17 04:50:31 PM PDT 24
Finished Aug 17 04:50:33 PM PDT 24
Peak memory 209152 kb
Host smart-1db5017d-f448-4e84-aa61-51eeed669bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240931622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.4240931622
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1873726967
Short name T824
Test name
Test status
Simulation time 329902048 ps
CPU time 9.16 seconds
Started Aug 17 04:50:27 PM PDT 24
Finished Aug 17 04:50:37 PM PDT 24
Peak memory 218284 kb
Host smart-4717628b-f7be-4f50-8aa4-1ee9527691ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873726967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1873726967
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3128107833
Short name T292
Test name
Test status
Simulation time 97318149 ps
CPU time 2.56 seconds
Started Aug 17 04:50:25 PM PDT 24
Finished Aug 17 04:50:28 PM PDT 24
Peak memory 214604 kb
Host smart-1c79f153-0c84-4f68-8c23-92655690fb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128107833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3128107833
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_random.2177646660
Short name T745
Test name
Test status
Simulation time 854609122 ps
CPU time 8.55 seconds
Started Aug 17 04:50:32 PM PDT 24
Finished Aug 17 04:50:40 PM PDT 24
Peak memory 207740 kb
Host smart-63cc577e-8c3b-4459-9708-da9bbe9def51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177646660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2177646660
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2884227736
Short name T680
Test name
Test status
Simulation time 373537867 ps
CPU time 5.24 seconds
Started Aug 17 04:50:33 PM PDT 24
Finished Aug 17 04:50:38 PM PDT 24
Peak memory 209048 kb
Host smart-9f4566e6-d595-4974-bbbc-0d96f9ff7dca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884227736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2884227736
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3074774585
Short name T432
Test name
Test status
Simulation time 50148923 ps
CPU time 2.63 seconds
Started Aug 17 04:50:17 PM PDT 24
Finished Aug 17 04:50:20 PM PDT 24
Peak memory 207292 kb
Host smart-ca24ff79-b13d-45ce-ace8-5d2933c06419
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074774585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3074774585
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.133613879
Short name T640
Test name
Test status
Simulation time 94624473 ps
CPU time 3.16 seconds
Started Aug 17 04:50:44 PM PDT 24
Finished Aug 17 04:50:47 PM PDT 24
Peak memory 207432 kb
Host smart-a34e9c43-5452-4e20-b238-35cba41af427
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133613879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.133613879
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.56665737
Short name T884
Test name
Test status
Simulation time 2553224489 ps
CPU time 7.35 seconds
Started Aug 17 04:50:17 PM PDT 24
Finished Aug 17 04:50:25 PM PDT 24
Peak memory 209312 kb
Host smart-443417f2-4cbb-4f28-a2f0-4a14c511582a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56665737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.56665737
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1766975235
Short name T305
Test name
Test status
Simulation time 45117029 ps
CPU time 1.93 seconds
Started Aug 17 04:50:33 PM PDT 24
Finished Aug 17 04:50:35 PM PDT 24
Peak memory 208480 kb
Host smart-af1724d5-377a-464a-b97f-edeb5efc964c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766975235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1766975235
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2437121477
Short name T425
Test name
Test status
Simulation time 51048988 ps
CPU time 2.5 seconds
Started Aug 17 04:50:19 PM PDT 24
Finished Aug 17 04:50:21 PM PDT 24
Peak memory 207316 kb
Host smart-78ea0094-a6d2-4a23-a298-ca253db43612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437121477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2437121477
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.398973938
Short name T587
Test name
Test status
Simulation time 282820757 ps
CPU time 14.36 seconds
Started Aug 17 04:50:20 PM PDT 24
Finished Aug 17 04:50:35 PM PDT 24
Peak memory 223196 kb
Host smart-4f01dd0b-9bf8-49ea-ae70-984ee7a49511
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398973938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.398973938
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.702303509
Short name T88
Test name
Test status
Simulation time 943338732 ps
CPU time 10.49 seconds
Started Aug 17 04:50:20 PM PDT 24
Finished Aug 17 04:50:31 PM PDT 24
Peak memory 223208 kb
Host smart-4f55a299-09ad-4134-8430-03e4f43a92f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702303509 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.702303509
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.222601103
Short name T61
Test name
Test status
Simulation time 178196018 ps
CPU time 5.65 seconds
Started Aug 17 04:50:35 PM PDT 24
Finished Aug 17 04:50:41 PM PDT 24
Peak memory 210580 kb
Host smart-1f6957a4-a04b-46e0-bc0a-b056e28d6ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222601103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.222601103
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3235843884
Short name T373
Test name
Test status
Simulation time 186126874 ps
CPU time 2.5 seconds
Started Aug 17 04:50:28 PM PDT 24
Finished Aug 17 04:50:30 PM PDT 24
Peak memory 210508 kb
Host smart-46c4c9de-b142-40f7-8355-dc784b346263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235843884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3235843884
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.4170769594
Short name T849
Test name
Test status
Simulation time 9904047 ps
CPU time 0.85 seconds
Started Aug 17 04:50:42 PM PDT 24
Finished Aug 17 04:50:43 PM PDT 24
Peak memory 206236 kb
Host smart-e19b9361-c40a-46aa-a5fc-db8a23b73a01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170769594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.4170769594
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2957452795
Short name T273
Test name
Test status
Simulation time 188693189 ps
CPU time 4.11 seconds
Started Aug 17 04:50:29 PM PDT 24
Finished Aug 17 04:50:33 PM PDT 24
Peak memory 214668 kb
Host smart-3e4704e7-0c1d-4a5c-aef6-9ab027092708
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2957452795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2957452795
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.503650746
Short name T5
Test name
Test status
Simulation time 320190924 ps
CPU time 6.5 seconds
Started Aug 17 04:50:42 PM PDT 24
Finished Aug 17 04:50:49 PM PDT 24
Peak memory 207764 kb
Host smart-306ca9a8-1160-4bba-8f95-5985579bb99c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503650746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.503650746
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2067299255
Short name T54
Test name
Test status
Simulation time 124770848 ps
CPU time 5.27 seconds
Started Aug 17 04:50:44 PM PDT 24
Finished Aug 17 04:50:49 PM PDT 24
Peak memory 209572 kb
Host smart-914d8b9a-4228-4a18-a24d-eb952f2807b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2067299255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2067299255
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.509007743
Short name T274
Test name
Test status
Simulation time 244137214 ps
CPU time 1.97 seconds
Started Aug 17 04:50:37 PM PDT 24
Finished Aug 17 04:50:39 PM PDT 24
Peak memory 214708 kb
Host smart-b4ad733e-0a17-41d6-896f-1ae3ab8dbe3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509007743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.509007743
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.942658208
Short name T227
Test name
Test status
Simulation time 138700951 ps
CPU time 6.3 seconds
Started Aug 17 04:50:51 PM PDT 24
Finished Aug 17 04:50:58 PM PDT 24
Peak memory 211232 kb
Host smart-02ed6acc-e70a-4219-b0a6-6162846d843f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942658208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.942658208
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.313693251
Short name T582
Test name
Test status
Simulation time 716891585 ps
CPU time 8.13 seconds
Started Aug 17 04:50:47 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 209428 kb
Host smart-343cd3a4-1f2a-4536-96af-49f3eb40a0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313693251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.313693251
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.189345222
Short name T501
Test name
Test status
Simulation time 196160672 ps
CPU time 2.44 seconds
Started Aug 17 04:50:33 PM PDT 24
Finished Aug 17 04:50:36 PM PDT 24
Peak memory 207480 kb
Host smart-2b565b1b-f7f9-4c51-83a3-79e069d95a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189345222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.189345222
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1360159223
Short name T285
Test name
Test status
Simulation time 36487712 ps
CPU time 2.46 seconds
Started Aug 17 04:50:34 PM PDT 24
Finished Aug 17 04:50:37 PM PDT 24
Peak memory 208952 kb
Host smart-ba070439-7116-4cb1-9dcc-a352fa3ed42b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360159223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1360159223
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.36481483
Short name T661
Test name
Test status
Simulation time 203936722 ps
CPU time 4.57 seconds
Started Aug 17 04:50:42 PM PDT 24
Finished Aug 17 04:50:47 PM PDT 24
Peak memory 208396 kb
Host smart-b3f6b619-e823-45fb-9aae-e71565acd10f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36481483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.36481483
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3190561190
Short name T583
Test name
Test status
Simulation time 94707324 ps
CPU time 4.23 seconds
Started Aug 17 04:50:34 PM PDT 24
Finished Aug 17 04:50:39 PM PDT 24
Peak memory 209268 kb
Host smart-e063484b-a7b7-43a3-9532-0cac4c138b93
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190561190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3190561190
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1798488623
Short name T387
Test name
Test status
Simulation time 56057761 ps
CPU time 2.24 seconds
Started Aug 17 04:50:38 PM PDT 24
Finished Aug 17 04:50:41 PM PDT 24
Peak memory 208632 kb
Host smart-9f5f142f-9809-4fdb-b6f0-1c580ad68db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798488623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1798488623
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3352282205
Short name T838
Test name
Test status
Simulation time 317182558 ps
CPU time 2.24 seconds
Started Aug 17 04:50:18 PM PDT 24
Finished Aug 17 04:50:20 PM PDT 24
Peak memory 208696 kb
Host smart-4bff682d-f11c-4d3d-b250-0efc6a4578c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352282205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3352282205
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1959873323
Short name T221
Test name
Test status
Simulation time 1868023028 ps
CPU time 30.14 seconds
Started Aug 17 04:50:32 PM PDT 24
Finished Aug 17 04:51:02 PM PDT 24
Peak memory 220448 kb
Host smart-84997a8c-d6e9-4fdc-8c31-20be34cc899a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959873323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1959873323
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3120389927
Short name T782
Test name
Test status
Simulation time 328400386 ps
CPU time 4.25 seconds
Started Aug 17 04:50:34 PM PDT 24
Finished Aug 17 04:50:38 PM PDT 24
Peak memory 214692 kb
Host smart-ef7b42d3-5cc1-41fc-8f7a-2f940df2ce5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120389927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3120389927
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2947650806
Short name T740
Test name
Test status
Simulation time 120426647 ps
CPU time 2.16 seconds
Started Aug 17 04:50:38 PM PDT 24
Finished Aug 17 04:50:40 PM PDT 24
Peak memory 210436 kb
Host smart-f103cc62-d5d2-431e-8ba6-be4e8b26fec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947650806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2947650806
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1566870753
Short name T792
Test name
Test status
Simulation time 24798154 ps
CPU time 0.92 seconds
Started Aug 17 04:50:44 PM PDT 24
Finished Aug 17 04:50:45 PM PDT 24
Peak memory 206408 kb
Host smart-661e47cc-5065-499c-9e64-d903a8c636ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566870753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1566870753
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1146603245
Short name T404
Test name
Test status
Simulation time 176893994 ps
CPU time 3.03 seconds
Started Aug 17 04:50:41 PM PDT 24
Finished Aug 17 04:50:44 PM PDT 24
Peak memory 214744 kb
Host smart-94de180c-7e7c-44b7-b06f-a43a7bcaf5e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1146603245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1146603245
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1299028145
Short name T30
Test name
Test status
Simulation time 115836627 ps
CPU time 3.48 seconds
Started Aug 17 04:50:36 PM PDT 24
Finished Aug 17 04:50:39 PM PDT 24
Peak memory 223260 kb
Host smart-bde41a39-4306-46c9-b5b0-e6b39e7c7976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1299028145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1299028145
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3493244566
Short name T180
Test name
Test status
Simulation time 80544914 ps
CPU time 1.5 seconds
Started Aug 17 04:50:32 PM PDT 24
Finished Aug 17 04:50:33 PM PDT 24
Peak memory 207392 kb
Host smart-9be074f6-9a14-41b6-973c-d09b07a19a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493244566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3493244566
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3593645259
Short name T854
Test name
Test status
Simulation time 1071865466 ps
CPU time 5.88 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 214784 kb
Host smart-4483e792-05d9-40df-b984-163903d24a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3593645259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3593645259
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3978544948
Short name T289
Test name
Test status
Simulation time 94046417 ps
CPU time 3.41 seconds
Started Aug 17 04:50:41 PM PDT 24
Finished Aug 17 04:50:45 PM PDT 24
Peak memory 214672 kb
Host smart-6883163f-50db-4196-9ea2-fda3797d7d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978544948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3978544948
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.614677049
Short name T752
Test name
Test status
Simulation time 205776000 ps
CPU time 3.54 seconds
Started Aug 17 04:50:46 PM PDT 24
Finished Aug 17 04:50:50 PM PDT 24
Peak memory 209028 kb
Host smart-7f04d200-2ee5-4642-8a9f-6f0e513bc25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=614677049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.614677049
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1587833868
Short name T902
Test name
Test status
Simulation time 117601243 ps
CPU time 3.79 seconds
Started Aug 17 04:50:35 PM PDT 24
Finished Aug 17 04:50:39 PM PDT 24
Peak memory 210248 kb
Host smart-e7c9013f-e915-42f9-b631-25e7abd3429b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587833868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1587833868
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.405601004
Short name T882
Test name
Test status
Simulation time 205031793 ps
CPU time 5.28 seconds
Started Aug 17 04:50:49 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 207212 kb
Host smart-28be2c5c-ee38-4deb-b19e-ea9ce118ec69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405601004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.405601004
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2867488352
Short name T462
Test name
Test status
Simulation time 191540729 ps
CPU time 3.88 seconds
Started Aug 17 04:50:47 PM PDT 24
Finished Aug 17 04:50:51 PM PDT 24
Peak memory 209084 kb
Host smart-3d0c0418-c305-4534-8315-2d4e1eea52f1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867488352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2867488352
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.377779973
Short name T569
Test name
Test status
Simulation time 50131648 ps
CPU time 2.89 seconds
Started Aug 17 04:50:39 PM PDT 24
Finished Aug 17 04:50:42 PM PDT 24
Peak memory 207484 kb
Host smart-0011703d-deef-4eaf-b4aa-620a3baa1b4c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377779973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.377779973
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4074276574
Short name T779
Test name
Test status
Simulation time 1220789230 ps
CPU time 6.45 seconds
Started Aug 17 04:50:42 PM PDT 24
Finished Aug 17 04:50:48 PM PDT 24
Peak memory 220864 kb
Host smart-544c9695-e0e7-4274-9529-5ad5e63bea93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074276574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4074276574
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2699513823
Short name T520
Test name
Test status
Simulation time 291419048 ps
CPU time 3.29 seconds
Started Aug 17 04:50:43 PM PDT 24
Finished Aug 17 04:50:47 PM PDT 24
Peak memory 208548 kb
Host smart-81e33d4c-7171-4ce5-ad2d-03f806b64830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699513823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2699513823
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.4237162909
Short name T72
Test name
Test status
Simulation time 326395868 ps
CPU time 11.49 seconds
Started Aug 17 04:50:43 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 222668 kb
Host smart-4ce6f32a-a87c-4360-91b0-22c083e42ff2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237162909 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.4237162909
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2755527033
Short name T500
Test name
Test status
Simulation time 3411070307 ps
CPU time 60.09 seconds
Started Aug 17 04:50:42 PM PDT 24
Finished Aug 17 04:51:43 PM PDT 24
Peak memory 214808 kb
Host smart-81a015a8-9be7-45ae-8ec2-353ecb451e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755527033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2755527033
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1386241382
Short name T601
Test name
Test status
Simulation time 114536703 ps
CPU time 1.18 seconds
Started Aug 17 04:50:32 PM PDT 24
Finished Aug 17 04:50:34 PM PDT 24
Peak memory 206508 kb
Host smart-be9b0c8c-e066-4a8e-b805-5fd5415fef62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386241382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1386241382
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2424689219
Short name T392
Test name
Test status
Simulation time 4384062420 ps
CPU time 54.88 seconds
Started Aug 17 04:50:39 PM PDT 24
Finished Aug 17 04:51:34 PM PDT 24
Peak memory 215256 kb
Host smart-f32c35b5-7398-4c7d-bf30-19f2ce106b22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424689219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2424689219
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1849342747
Short name T246
Test name
Test status
Simulation time 115454375 ps
CPU time 2.16 seconds
Started Aug 17 04:50:36 PM PDT 24
Finished Aug 17 04:50:39 PM PDT 24
Peak memory 209588 kb
Host smart-040c3255-dc25-4613-8bbe-873418f2e9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849342747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1849342747
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1374299726
Short name T845
Test name
Test status
Simulation time 1946000470 ps
CPU time 4.99 seconds
Started Aug 17 04:50:41 PM PDT 24
Finished Aug 17 04:50:46 PM PDT 24
Peak memory 219660 kb
Host smart-31b9fe51-06f9-474c-ad3e-453167c1e976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374299726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1374299726
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1746484569
Short name T104
Test name
Test status
Simulation time 667048612 ps
CPU time 17.13 seconds
Started Aug 17 04:50:30 PM PDT 24
Finished Aug 17 04:50:47 PM PDT 24
Peak memory 214748 kb
Host smart-7eda0c98-3d35-4b26-81fa-44cfd27a2d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746484569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1746484569
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1395255427
Short name T891
Test name
Test status
Simulation time 2355022439 ps
CPU time 37.16 seconds
Started Aug 17 04:50:29 PM PDT 24
Finished Aug 17 04:51:06 PM PDT 24
Peak memory 209900 kb
Host smart-f7bf210d-f8a4-4d9c-a496-1dee9bc77813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395255427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1395255427
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2242223598
Short name T475
Test name
Test status
Simulation time 39904794 ps
CPU time 2.7 seconds
Started Aug 17 04:50:42 PM PDT 24
Finished Aug 17 04:50:44 PM PDT 24
Peak memory 209156 kb
Host smart-63ffd726-0333-42ab-8d46-62b90f29d657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242223598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2242223598
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2165688769
Short name T839
Test name
Test status
Simulation time 359569855 ps
CPU time 4.76 seconds
Started Aug 17 04:50:38 PM PDT 24
Finished Aug 17 04:50:43 PM PDT 24
Peak memory 209088 kb
Host smart-c91eedf4-d02c-42f1-b252-97c821f0996c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165688769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2165688769
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3566484116
Short name T533
Test name
Test status
Simulation time 659745674 ps
CPU time 5.22 seconds
Started Aug 17 04:50:37 PM PDT 24
Finished Aug 17 04:50:42 PM PDT 24
Peak memory 209240 kb
Host smart-e0b38bfc-b346-416d-9246-0bc6833467af
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566484116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3566484116
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.39607451
Short name T498
Test name
Test status
Simulation time 62306665 ps
CPU time 2.72 seconds
Started Aug 17 04:50:46 PM PDT 24
Finished Aug 17 04:50:49 PM PDT 24
Peak memory 207428 kb
Host smart-e2be663f-3ccd-4f5a-99fd-8c6323923e58
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39607451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.39607451
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1855876876
Short name T506
Test name
Test status
Simulation time 1847338514 ps
CPU time 5.07 seconds
Started Aug 17 04:50:36 PM PDT 24
Finished Aug 17 04:50:41 PM PDT 24
Peak memory 208956 kb
Host smart-61540208-120e-487b-ac90-2b9c8ad4c4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855876876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1855876876
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1028107421
Short name T450
Test name
Test status
Simulation time 2209033390 ps
CPU time 19.99 seconds
Started Aug 17 04:50:36 PM PDT 24
Finished Aug 17 04:50:56 PM PDT 24
Peak memory 209388 kb
Host smart-152a65bd-fede-4e77-9a09-8d547a7ce520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028107421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1028107421
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3832520369
Short name T762
Test name
Test status
Simulation time 1059942927 ps
CPU time 37.74 seconds
Started Aug 17 04:50:30 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 222936 kb
Host smart-d09196ef-44f8-442b-aa64-873ea0301c98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832520369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3832520369
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2551502172
Short name T880
Test name
Test status
Simulation time 1136324620 ps
CPU time 4.9 seconds
Started Aug 17 04:50:47 PM PDT 24
Finished Aug 17 04:50:52 PM PDT 24
Peak memory 209568 kb
Host smart-7d36d960-729b-4308-80c6-34e1735134fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551502172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2551502172
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2828271157
Short name T665
Test name
Test status
Simulation time 509674310 ps
CPU time 5.29 seconds
Started Aug 17 04:50:37 PM PDT 24
Finished Aug 17 04:50:43 PM PDT 24
Peak memory 211456 kb
Host smart-93987cac-52a9-4414-b313-52ad2465e36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828271157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2828271157
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3426339033
Short name T2
Test name
Test status
Simulation time 49062419 ps
CPU time 0.96 seconds
Started Aug 17 04:50:45 PM PDT 24
Finished Aug 17 04:50:46 PM PDT 24
Peak memory 206436 kb
Host smart-9c5828db-c521-4bd7-9cd0-8c0b8a753c0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426339033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3426339033
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1231626428
Short name T252
Test name
Test status
Simulation time 108466680 ps
CPU time 2.26 seconds
Started Aug 17 04:50:52 PM PDT 24
Finished Aug 17 04:50:54 PM PDT 24
Peak memory 214732 kb
Host smart-79cf920e-21fa-4e9b-9c5d-4af8dae27aa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1231626428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1231626428
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1665146692
Short name T607
Test name
Test status
Simulation time 88303864 ps
CPU time 2.13 seconds
Started Aug 17 04:50:38 PM PDT 24
Finished Aug 17 04:50:40 PM PDT 24
Peak memory 208596 kb
Host smart-37b6f7d1-e23f-4fab-abe8-869ffe43d86d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665146692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1665146692
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.251694687
Short name T725
Test name
Test status
Simulation time 355328814 ps
CPU time 3.17 seconds
Started Aug 17 04:50:46 PM PDT 24
Finished Aug 17 04:50:49 PM PDT 24
Peak memory 209204 kb
Host smart-7630d84f-a40f-4214-9a8f-7d524b263ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251694687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.251694687
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3041007145
Short name T336
Test name
Test status
Simulation time 210710512 ps
CPU time 2.95 seconds
Started Aug 17 04:50:56 PM PDT 24
Finished Aug 17 04:50:59 PM PDT 24
Peak memory 214764 kb
Host smart-fc69dd31-5d7a-4242-adee-06bb861ec953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041007145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3041007145
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3227830596
Short name T337
Test name
Test status
Simulation time 115759305 ps
CPU time 5.16 seconds
Started Aug 17 04:50:54 PM PDT 24
Finished Aug 17 04:50:59 PM PDT 24
Peak memory 221684 kb
Host smart-f8368b62-ab13-43a5-8a13-94ddd3f7f4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227830596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3227830596
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_random.870467565
Short name T196
Test name
Test status
Simulation time 181918225 ps
CPU time 4.19 seconds
Started Aug 17 04:50:55 PM PDT 24
Finished Aug 17 04:50:59 PM PDT 24
Peak memory 209680 kb
Host smart-0be337d9-eb42-454d-b2cf-b7588d8a91e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870467565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.870467565
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4262190266
Short name T722
Test name
Test status
Simulation time 58066264 ps
CPU time 2.3 seconds
Started Aug 17 04:51:01 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 207556 kb
Host smart-7680ce5e-fa9c-44a0-8fb5-7f722f0d9a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262190266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4262190266
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1204303745
Short name T470
Test name
Test status
Simulation time 2399942159 ps
CPU time 24.31 seconds
Started Aug 17 04:50:59 PM PDT 24
Finished Aug 17 04:51:28 PM PDT 24
Peak memory 208904 kb
Host smart-03a0fe7a-b73e-4fd3-950b-46f8549c4b81
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204303745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1204303745
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1977383149
Short name T270
Test name
Test status
Simulation time 115076551 ps
CPU time 2.44 seconds
Started Aug 17 04:50:49 PM PDT 24
Finished Aug 17 04:50:51 PM PDT 24
Peak memory 207332 kb
Host smart-93aecc00-515f-400f-ab75-e4d98453cc6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977383149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1977383149
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3884697334
Short name T830
Test name
Test status
Simulation time 79029288 ps
CPU time 3.09 seconds
Started Aug 17 04:50:56 PM PDT 24
Finished Aug 17 04:51:04 PM PDT 24
Peak memory 208872 kb
Host smart-c2e06306-19b4-4faf-92c1-0b8dea9602dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884697334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3884697334
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.668206807
Short name T421
Test name
Test status
Simulation time 143449673 ps
CPU time 4.12 seconds
Started Aug 17 04:50:50 PM PDT 24
Finished Aug 17 04:50:55 PM PDT 24
Peak memory 207500 kb
Host smart-df7b2da8-1f9d-4382-b2d2-5b6059117541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668206807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.668206807
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2407070105
Short name T813
Test name
Test status
Simulation time 84913663 ps
CPU time 1.81 seconds
Started Aug 17 04:50:33 PM PDT 24
Finished Aug 17 04:50:35 PM PDT 24
Peak memory 207536 kb
Host smart-a97c90ad-ac1a-4f77-8ff4-61ce7ef1d114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407070105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2407070105
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.807847355
Short name T303
Test name
Test status
Simulation time 12296633456 ps
CPU time 94.1 seconds
Started Aug 17 04:50:49 PM PDT 24
Finished Aug 17 04:52:28 PM PDT 24
Peak memory 222816 kb
Host smart-4c9c0c27-dd8a-4b37-9cc2-614f2b8329a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807847355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.807847355
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3099465440
Short name T313
Test name
Test status
Simulation time 789108717 ps
CPU time 16.08 seconds
Started Aug 17 04:50:51 PM PDT 24
Finished Aug 17 04:51:08 PM PDT 24
Peak memory 209948 kb
Host smart-07a6ba57-c290-4070-bcd8-3088dfb4f995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099465440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3099465440
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.4279247893
Short name T133
Test name
Test status
Simulation time 61812453 ps
CPU time 2.05 seconds
Started Aug 17 04:50:47 PM PDT 24
Finished Aug 17 04:50:49 PM PDT 24
Peak memory 210532 kb
Host smart-bb87e0eb-2a4a-4497-8d95-d41d0179ac04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279247893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4279247893
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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