Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	14	35	71.43

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	13	22	62.86	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	45	1			T91	1		T119	1		T112	1
auto[OpGenId]	10	1			T190	1		T10	1		T191	1
auto[OpGenSwOut]	24	1			T58	1		T131	1		T192	1
auto[OpGenHwOut]	17	1			T28	1		T7	1		T18	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1617	1			T12	180		T63	1		T64	2
auto[StInit]	75	1			T25	1		T67	1		T7	2
auto[StCreatorRootKey]	54	1			T91	1		T64	1		T7	1
auto[StOwnerIntKey]	50	1			T36	1		T128	2		T130	1
auto[StOwnerKey]	32	1			T64	1		T7	1		T37	1
auto[StDisabled]	410	1			T25	6		T65	1		T28	1
auto[StInvalid]	49	1			T15	1		T35	1		T47	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3270

1

T1

1

T2

1

T3

1

auto[1]

96

1

T28

1

T91

1

T7

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1608	1			T12	180		T63	1		T64	2
auto[StReset]	auto[1]	9	1			T120	1		T18	1		T121	1
auto[StInit]	auto[0]	41	1			T25	1		T67	1		T7	2
auto[StInit]	auto[1]	34	1			T8	1		T131	1		T193	1
auto[StCreatorRootKey]	auto[0]	37	1			T64	1		T7	1		T128	1
auto[StCreatorRootKey]	auto[1]	17	1			T91	1		T38	1		T194	1
auto[StOwnerIntKey]	auto[0]	36	1			T36	1		T128	2		T130	1
auto[StOwnerIntKey]	auto[1]	14	1			T27	1		T87	1		T195	1
auto[StOwnerKey]	auto[0]	24	1			T64	1		T7	1		T37	1
auto[StOwnerKey]	auto[1]	8	1			T119	1		T192	1		T196	1
auto[StDisabled]	auto[0]	396	1			T25	6		T65	1		T63	4
auto[StDisabled]	auto[1]	14	1			T28	1		T7	1		T112	1
auto[StInvalid]	auto[0]	49	1			T15	1		T35	1		T47	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	13	22	62.86	13

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut]]	--	--	2
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	5

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	8	1			T120	1		T121	1		T122	1
auto[StReset]	auto[OpGenHwOut]	1	1			T18	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	15	1			T197	1		T122	1		T198	1
auto[StInit]	auto[OpGenId]	4	1			T10	1		T191	1		T199	1
auto[StInit]	auto[OpGenSwOut]	12	1			T131	1		T193	1		T191	1
auto[StInit]	auto[OpGenHwOut]	3	1			T8	1		T200	1		T201	1
auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T91	1		T194	1		T202	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T203	1		T204	1		T205	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T206	1		T207	1		T208	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	5	1			T38	1		T209	1		T210	1
auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T27	1		T87	1		T211	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T212	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T195	1		T213	1		T214	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T9	1		T141	1		T215	1
auto[StOwnerKey]	auto[OpAdvance]	3	1			T119	1		T196	1		T216	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T217	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T192	1		T218	1		T219	1
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T220	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	6	1			T112	1		T40	1		T216	1
auto[StDisabled]	auto[OpGenId]	1	1			T190	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	3	1			T58	1		T221	1		T222	1
auto[StDisabled]	auto[OpGenHwOut]	4	1			T28	1		T7	1		T202	1