Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4512

1

T1

12

T2

9

T3

8

auto[1]

568

1

T4

1

T34

1

T25

7

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4512

1

T1

12

T2

9

T3

8

auto[1]

568

1

T4

1

T34

1

T25

7

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4600

1

T1

12

T2

5

T3

8

auto[1]

480

1

T2

4

T4

1

T17

2

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4600

1

T1

12

T2

5

T3

8

auto[1]

480

1

T2

4

T4

1

T17

2

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	395	1			T15	1		T33	1		T25	4
auto[OpGenId]	1032	1			T4	1		T5	1		T6	3
auto[OpGenSwOut]	1097	1			T4	2		T15	1		T5	1
auto[OpGenHwOut]	2502	1			T1	12		T2	9		T3	8
auto[OpDisable]	54	1			T68	1		T72	1		T66	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	395	1			T15	1		T33	1		T25	4
auto[OpGenId]	1032	1			T4	1		T5	1		T6	3
auto[OpGenSwOut]	1097	1			T4	2		T15	1		T5	1
auto[OpGenHwOut]	2502	1			T1	12		T2	9		T3	8
auto[OpDisable]	54	1			T68	1		T72	1		T66	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4550

1

T1

9

T2

9

T3

5

auto[1]

530

1

T1

3

T3

3

T16

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4550

1

T1

9

T2

9

T3

5

auto[1]

530

1

T1

3

T3

3

T16

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4845

1

T1

12

T2

9

T3

8

auto[1]

235

1

T79

3

T96

9

T97

8

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1651	1			T1	3		T2	3		T3	2
auto[1]	654	1			T1	2		T3	1		T15	1
auto[2]	730	1			T2	1		T3	1		T4	1
auto[3]	657	1			T1	2		T2	2		T16	3
auto[4]	352	1			T1	1		T2	1		T17	2
auto[5]	347	1			T1	1		T2	1		T3	2
auto[6]	357	1			T2	1		T3	2		T15	1
auto[7]	332	1			T1	3		T16	1		T17	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1388	1			T1	5		T2	3		T3	4
clear_one[1]	654	1			T1	2		T3	1		T15	1
clear_one[2]	730	1			T2	1		T3	1		T4	1
clear_one[3]	657	1			T1	2		T2	2		T16	3
clear_none	1651	1			T1	3		T2	3		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	946	1			T1	4		T2	1		T17	1
auto[StInit]	614	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	523	1			T1	1		T2	1		T3	1
auto[StOwnerIntKey]	506	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	447	1			T1	1		T2	1		T3	1
auto[StDisabled]	1784	1			T1	4		T2	4		T3	4
auto[StInvalid]	260	1			T15	3		T35	3		T47	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	946	1			T1	4		T2	1		T17	1
auto[StInit]	614	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	523	1			T1	1		T2	1		T3	1
auto[StOwnerIntKey]	506	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	447	1			T1	1		T2	1		T3	1
auto[StDisabled]	1784	1			T1	4		T2	4		T3	4
auto[StInvalid]	260	1			T15	3		T35	3		T47	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[0]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[0]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[2] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[2] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpGenId]	132	1			T94	1		T63	3		T64	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	148	1			T5	1		T94	1		T47	2
auto[0]	auto[StReset]	auto[OpGenHwOut]	250	1			T1	1		T2	1		T17	1
auto[0]	auto[StInit]	auto[OpAdvance]	32	1			T33	1		T7	1		T58	1
auto[0]	auto[StInit]	auto[OpGenId]	81	1			T25	1		T64	1		T7	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	89	1			T65	1		T28	1		T63	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	178	1			T1	1		T3	1		T16	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	16	1			T91	1		T7	1		T66	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	38	1			T4	1		T34	1		T63	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	46	1			T25	1		T64	2		T58	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	67	1			T72	1		T7	1		T223	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T79	1		T224	1		T131	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	27	1			T25	1		T132	1		T131	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	28	1			T146	1		T224	1		T179	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	64	1			T25	1		T65	1		T225	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T97	1		T224	1		T226	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	19	1			T113	2		T227	1		T86	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T71	1		T228	1		T229	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T2	1		T25	1		T64	2
auto[0]	auto[StDisabled]	auto[OpAdvance]	16	1			T25	1		T113	1		T230	1
auto[0]	auto[StDisabled]	auto[OpGenId]	42	1			T25	2		T79	2		T66	2
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	47	1			T4	1		T66	1		T231	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T1	1		T2	1		T3	1
auto[0]	auto[StDisabled]	auto[OpDisable]	15	1			T68	1		T232	1		T233	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	10	1			T15	1		T234	1		T235	1
auto[0]	auto[StInvalid]	auto[OpGenId]	19	1			T92	1		T236	1		T59	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T35	1		T92	1		T237	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	19	1			T177	1		T238	1		T239	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T97	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	24	1			T64	1		T49	1		T86	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	21	1			T6	1		T63	1		T131	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	37	1			T240	1		T147	1		T149	1
auto[1]	auto[StInit]	auto[OpAdvance]	4	1			T97	1		T241	1		T242	1
auto[1]	auto[StInit]	auto[OpGenId]	8	1			T63	1		T93	1		T58	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T71	1		T243	1		T244	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	22	1			T95	1		T66	1		T245	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T87	1		T246	1		T199	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T50	1		T85	1		T131	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T66	1		T86	1		T179	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T1	1		T240	1		T128	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T99	1		T131	1		T247	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T227	1		T99	1		T248	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T98	1		T233	1		T249	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T1	1		T250	1		T251	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T227	1		T252	1		T253	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	15	1			T58	1		T98	1		T247	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T79	3		T72	1		T146	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	28	1			T66	1		T250	1		T86	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	21	1			T128	1		T146	1		T48	1
auto[1]	auto[StDisabled]	auto[OpGenId]	46	1			T6	1		T52	1		T58	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	52	1			T84	1		T85	1		T251	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	149	1			T3	1		T16	2		T17	1
auto[1]	auto[StDisabled]	auto[OpDisable]	6	1			T254	1		T255	1		T139	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	8	1			T256	1		T257	1		T46	1
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T47	1		T258	1		T259	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T15	1		T125	1		T258	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T35	1		T236	2		T260	1
auto[2]	auto[StReset]	auto[OpGenId]	15	1			T66	1		T131	1		T261	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	21	1			T64	1		T149	1		T132	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	46	1			T47	1		T147	1		T148	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T50	1		T48	1		T218	1
auto[2]	auto[StInit]	auto[OpGenId]	12	1			T6	1		T66	1		T87	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	10	1			T63	1		T128	1		T132	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	17	1			T17	1		T262	1		T263	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T264	1		T265	1		T218	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T128	1		T266	1		T139	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T64	1		T66	1		T267	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	39	1			T16	1		T25	1		T225	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T128	1		T102	1		T264	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T34	1		T268	1		T88	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T28	1		T128	1		T84	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T148	1		T269	1		T85	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T270	1		T184	1		T271	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	15	1			T58	1		T272	1		T122	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T28	1		T63	1		T7	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T3	1		T95	1		T66	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	29	1			T25	2		T63	1		T49	1
auto[2]	auto[StDisabled]	auto[OpGenId]	56	1			T64	2		T97	2		T58	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	73	1			T4	1		T71	1		T66	5
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	169	1			T2	1		T25	1		T72	2
auto[2]	auto[StDisabled]	auto[OpDisable]	11	1			T72	1		T175	1		T122	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T125	1		T273	1		T274	1
auto[2]	auto[StInvalid]	auto[OpGenId]	19	1			T92	1		T275	2		T276	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T256	1		T277	1		T258	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T59	1		T237	1		T257	1
auto[3]	auto[StReset]	auto[OpGenId]	19	1			T97	1		T18	1		T99	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	23	1			T66	1		T128	1		T89	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	33	1			T1	1		T240	1		T278	1
auto[3]	auto[StInit]	auto[OpAdvance]	4	1			T279	1		T280	1		T281	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T72	1		T57	1		T86	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	13	1			T122	1		T282	1		T283	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	24	1			T240	1		T147	1		T278	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T131	1		T192	1		T196	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T89	1		T284	1		T285	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T128	1		T227	1		T232	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T2	1		T93	1		T147	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T100	1		T180	1		T286	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T68	1		T7	1		T58	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T58	1		T232	1		T131	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	38	1			T16	1		T287	1		T48	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T66	1		T288	1		T289	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	12	1			T63	1		T50	1		T290	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	16	1			T128	1		T84	1		T86	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	31	1			T16	1		T70	1		T291	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	29	1			T65	1		T227	1		T100	1
auto[3]	auto[StDisabled]	auto[OpGenId]	50	1			T6	1		T71	1		T66	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T34	1		T63	1		T64	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	148	1			T1	1		T2	1		T16	1
auto[3]	auto[StDisabled]	auto[OpDisable]	5	1			T124	1		T128	1		T292	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	7	1			T45	1		T275	1		T257	1
auto[3]	auto[StInvalid]	auto[OpGenId]	3	1			T125	1		T256	1		T293	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T35	1		T45	1		T239	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	17	1			T47	2		T256	1		T276	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T100	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	14	1			T227	1		T294	1		T248	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	7	1			T8	1		T295	1		T258	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	22	1			T1	1		T148	1		T278	2
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T192	1		T296	1		T297	1
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T94	1		T101	1		T298	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	6	1			T67	1		T24	1		T299	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	12	1			T2	1		T300	1		T181	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T301	1		T302	1		T303	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T5	1		T100	1		T304	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T25	1		T99	1		T85	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T17	1		T227	1		T305	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T63	1		T112	1		T247	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T64	1		T306	1		T301	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T296	1		T307	1		T191	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	14	1			T308	1		T309	1		T310	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T266	1		T311	1		T199	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	8	1			T312	1		T279	1		T184	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T131	1		T121	1		T313	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T86	1		T314	1		T315	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	16	1			T25	1		T95	1		T58	1
auto[4]	auto[StDisabled]	auto[OpGenId]	33	1			T34	1		T65	1		T64	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	20	1			T64	1		T128	1		T224	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T17	1		T66	1		T287	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T66	1		T137	1		T179	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	1	1			T276	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	5	1			T47	1		T59	1		T316	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T239	1		T258	1		T317	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T177	1		T238	1		T318	2
auto[5]	auto[StReset]	auto[OpGenId]	9	1			T47	1		T66	1		T30	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	12	1			T18	1		T130	1		T87	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	28	1			T147	1		T85	1		T263	1
auto[5]	auto[StInit]	auto[OpAdvance]	6	1			T227	1		T226	1		T295	2
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T25	1		T248	1		T199	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	4	1			T319	1		T139	1		T24	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T70	1		T250	1		T24	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T320	1		-	-		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T48	1		T181	1		T321	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T131	1		T243	1		T295	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T3	1		T70	1		T322	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T130	1		T191	1		T56	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T66	1		T323	1		T131	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T58	1		T227	1		T285	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T2	1		T95	1		T223	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T48	1		T324	1		T325	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	4	1			T84	1		T326	1		T327	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T328	1		T131	1		T22	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T25	1		T278	1		T329	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T58	1		T131	1		T270	1
auto[5]	auto[StDisabled]	auto[OpGenId]	22	1			T227	1		T87	1		T181	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T71	1		T49	1		T330	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	70	1			T1	1		T3	1		T17	1
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T138	1		T141	1		T280	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T294	2		T331	1		T332	1
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T277	1		T257	1		T294	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T294	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T47	1		T333	1		T334	1
auto[6]	auto[StReset]	auto[OpGenId]	12	1			T86	1		T181	1		T335	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	5	1			T248	1		T298	1		T336	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	24	1			T227	1		T337	1		T250	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T64	1		T338	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	6	1			T267	1		T56	1		T339	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	4	1			T335	1		T340	1		T341	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	6	1			T342	1		T343	1		T344	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T345	1		T346	1		T347	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T66	1		T88	1		T324	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T63	1		T52	1		T348	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	11	1			T7	1		T329	1		T349	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T96	4		T233	1		T142	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T49	1		T233	1		T312	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T25	1		T175	1		T27	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T3	1		T240	1		T227	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T96	3		T322	1		T335	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	1	1			T350	1		-	-		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T195	1		T351	1		T352	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T17	1		T147	1		T353	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	10	1			T79	1		T184	1		T354	1
auto[6]	auto[StDisabled]	auto[OpGenId]	37	1			T66	1		T96	3		T49	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	37	1			T25	1		T66	2		T85	3
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T2	1		T3	1		T25	1
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T140	1		T171	1		T142	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T275	1		T355	1		T356	1
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T92	1		T177	1		T294	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T125	1		T259	1		T235	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T15	1		T235	1		T355	1
auto[7]	auto[StReset]	auto[OpGenId]	6	1			T47	1		T120	1		T190	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	12	1			T97	1		T86	1		T226	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	24	1			T1	1		T278	1		T250	1
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T357	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	3	1			T40	1		T297	2		-	-
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T227	1		T266	1		T324	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	11	1			T227	1		T337	1		T358	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T85	1		T359	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T180	1		T354	1		T185	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T64	1		T84	1		T360	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T7	1		T49	1		T361	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T362	1		T363	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T284	1		T121	1		T122	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T63	1		T66	1		T348	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T17	1		T70	1		T305	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T65	1		T64	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T364	1		T191	2		T280	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T58	1		T227	1		T365	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T1	1		T287	1		T366	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	13	1			T180	1		T328	2		T348	1
auto[7]	auto[StDisabled]	auto[OpGenId]	26	1			T66	1		T58	1		T227	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	20	1			T72	1		T84	1		T122	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T1	1		T16	1		T66	1
auto[7]	auto[StDisabled]	auto[OpDisable]	1	1			T367	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpAdvance]	4	1			T45	1		T125	1		T368	1
auto[7]	auto[StInvalid]	auto[OpGenId]	6	1			T45	2		T238	1		T260	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T92	1		T258	1		T369	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T45	1		T177	1		T237	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1388

1

T1

5

T2

3

T3

4

clear_one[1]

auto[0]

auto[0]

auto[0]

386

1

T15

1

T6

1

T35

1

clear_one[1]

auto[0]

auto[0]

auto[1]

112

1

T1

2

T3

1

T16

2

clear_one[1]

auto[0]

auto[1]

auto[0]

127

1

T17

1

T6

2

T79

3

clear_one[1]

auto[0]

auto[1]

auto[1]

29

1

T58

3

T251

1

T131

2

clear_one[2]

auto[0]

auto[0]

auto[0]

412

1

T2

1

T17

1

T6

1

clear_one[2]

auto[0]

auto[0]

auto[1]

139

1

T3

1

T16

1

T25

1

clear_one[2]

auto[1]

auto[0]

auto[0]

133

1

T4

1

T25

2

T28

2

clear_one[2]

auto[1]

auto[0]

auto[1]

46

1

T58

2

T269

1

T102

4

clear_one[3]

auto[0]

auto[0]

auto[0]

399

1

T1

2

T16

3

T35

1

clear_one[3]

auto[0]

auto[1]

auto[0]

100

1

T2

2

T6

1

T66

1

clear_one[3]

auto[1]

auto[0]

auto[0]

131

1

T34

1

T68

1

T65

1

clear_one[3]

auto[1]

auto[1]

auto[0]

27

1

T64

1

T93

1

T66

1

clear_none

auto[0]

auto[0]

auto[0]

1162

1

T1

2

T2

1

T3

1

clear_none

auto[0]

auto[0]

auto[1]

119

1

T1

1

T3

1

T7

1

clear_none

auto[0]

auto[1]

auto[0]

117

1

T2

2

T4

1

T17

1

clear_none

auto[0]

auto[1]

auto[1]

22

1

T113

3

T370

1

T131

1

clear_none

auto[1]

auto[0]

auto[0]

137

1

T25

1

T68

1

T70

1

clear_none

auto[1]

auto[0]

auto[1]

36

1

T25

3

T64

2

T58

1

clear_none

auto[1]

auto[1]

auto[0]

31

1

T25

1

T79

1

T224

1

clear_none

auto[1]

auto[1]

auto[1]

27

1

T224

1

T370

1

T286

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1304	1			T1	5		T2	3		T3	4
clear_all	auto[1]	84	1			T96	9		T100	4		T328	5
clear_one[1]	auto[0]	630	1			T1	2		T3	1		T15	1
clear_one[1]	auto[1]	24	1			T79	2		T97	1		T99	5
clear_one[2]	auto[0]	671	1			T2	1		T3	1		T4	1
clear_one[2]	auto[1]	59	1			T97	4		T102	7		T247	1
clear_one[3]	auto[0]	632	1			T1	2		T2	2		T16	3
clear_one[3]	auto[1]	25	1			T79	1		T100	4		T328	1
clear_none	auto[0]	1608	1			T1	3		T2	3		T3	2
clear_none	auto[1]	43	1			T97	3		T113	1		T328	1