Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10646

1

T1

15

T2

3

T3

3

auto[Attestation]

7235

1

T1

2

T2

6

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2592	1			T4	2		T5	2		T6	7
auto[Aes]	3296	1			T4	2		T5	5		T6	3
auto[Kmac]	3223	1			T2	9		T4	3		T17	10
auto[Otbn]	3208	1			T1	17		T3	8		T4	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7342	1			T1	8		T2	8		T3	8
auto[OpGenId]	5562	1			T4	10		T5	3		T6	12
auto[OpGenSwOut]	5624	1			T4	4		T5	6		T6	9
auto[OpGenHwOut]	6695	1			T1	17		T2	9		T3	8
auto[OpDisable]	125	1			T5	1		T25	1		T68	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10111

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

15237

1

T1

17

T2

9

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6057	1			T1	10		T2	2		T3	1
auto[StInit]	3667	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3017	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2609	1			T1	2		T2	2		T3	2
auto[StOwnerKey]	2371	1			T1	2		T2	2		T3	2
auto[StDisabled]	7627	1			T1	7		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	289	1			T25	2		T94	1		T95	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	83	1			T68	1		T67	1		T66	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	71	1			T63	1		T64	2		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	50	1			T6	1		T25	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	72	1			T25	1		T71	1		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	220	1			T6	1		T25	1		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	294	1			T5	2		T25	2		T95	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	117	1			T4	1		T91	2		T64	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	82	1			T25	1		T65	1		T64	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	73	1			T25	1		T93	1		T66	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	60	1			T6	1		T63	1		T79	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	194	1			T68	1		T65	2		T95	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	332	1			T5	1		T6	1		T25	5
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	95	1			T25	1		T64	2		T7	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	78	1			T25	1		T64	1		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T25	1		T63	1		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	61	1			T64	1		T7	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	193	1			T6	1		T34	1		T25	6
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	311	1			T25	2		T94	2		T95	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	117	1			T64	3		T72	1		T124	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	69	1			T5	1		T25	1		T64	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	79	1			T25	1		T7	2		T84	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	63	1			T7	1		T93	2		T66	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	203	1			T71	1		T95	1		T64	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	84	1			T63	4		T64	2		T66	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	113	1			T25	1		T28	1		T63	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T36	1		T28	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	64	1			T5	1		T6	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	61	1			T95	1		T28	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	210	1			T4	1		T6	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	67	1			T64	3		T7	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	117	1			T25	4		T28	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	91	1			T25	1		T79	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	75	1			T25	1		T64	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	56	1			T95	1		T66	1		T96	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	214	1			T6	1		T25	1		T64	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	64	1			T63	1		T64	3		T58	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	92	1			T25	1		T65	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T33	1		T68	1		T64	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	59	1			T5	1		T64	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	52	1			T25	1		T79	1		T72	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	199	1			T65	1		T63	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	83	1			T63	1		T64	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	100	1			T4	1		T71	1		T63	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	72	1			T6	1		T94	1		T66	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	57	1			T25	1		T28	1		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	61	1			T95	1		T63	1		T79	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	201	1			T4	1		T64	2		T189	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	230	1			T6	1		T25	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	90	1			T5	1		T35	1		T94	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	73	1			T4	1		T25	2		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	63	1			T68	1		T65	1		T95	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	54	1			T25	1		T95	1		T96	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	188	1			T25	1		T68	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	464	1			T5	1		T25	3		T70	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	116	1			T34	1		T25	1		T63	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	118	1			T68	1		T36	1		T64	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	96	1			T70	1		T64	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	72	1			T64	2		T93	1		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	270	1			T6	1		T25	6		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	469	1			T2	1		T17	2		T6	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	119	1			T7	2		T66	1		T128	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	114	1			T17	1		T6	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	80	1			T17	1		T6	1		T64	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	72	1			T2	1		T17	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	306	1			T2	1		T4	1		T17	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	434	1			T1	9		T5	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	114	1			T16	1		T94	1		T63	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	118	1			T1	1		T3	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	87	1			T1	1		T16	1		T94	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	79	1			T1	1		T16	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	248	1			T1	3		T3	2		T16	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	60	1			T64	6		T7	3		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	79	1			T91	1		T66	2		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	55	1			T6	1		T37	1		T128	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T64	2		T66	1		T128	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	53	1			T25	1		T66	2		T132	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	194	1			T6	1		T25	2		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	62	1			T63	1		T64	2		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	111	1			T70	1		T36	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	101	1			T5	1		T33	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	72	1			T28	1		T7	1		T93	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	91	1			T34	1		T70	1		T64	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	283	1			T4	1		T5	1		T25	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	40	1			T63	2		T64	4		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	122	1			T2	1		T4	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T2	1		T25	1		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T2	1		T5	1		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	80	1			T93	2		T66	1		T128	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	249	1			T2	3		T4	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	52	1			T63	2		T64	6		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	90	1			T1	1		T3	1		T95	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	103	1			T16	1		T33	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	99	1			T3	1		T25	1		T94	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	88	1			T3	1		T25	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	280	1			T1	1		T3	2		T5	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	183	1			T6	1		T25	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	602	1			T6	1		T25	4		T68	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	203	1			T6	1		T25	2		T65	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	617	1			T4	1		T5	2		T25	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	201	1			T25	2		T63	1		T64	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	637	1			T5	1		T6	2		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	191	1			T5	1		T25	2		T7	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	651	1			T25	2		T71	1		T94	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	182	1			T5	1		T6	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	423	1			T4	1		T6	1		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	211	1			T25	2		T95	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	409	1			T6	1		T25	5		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	172	1			T5	1		T33	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	368	1			T25	2		T65	2		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	170	1			T25	1		T94	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	404	1			T4	2		T6	1		T71	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	175	1			T4	1		T25	2		T68	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	523	1			T5	1		T6	1		T25	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	268	1			T68	1		T70	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	868	1			T5	1		T6	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	243	1			T2	1		T17	3		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	917	1			T2	2		T4	1		T17	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	270	1			T1	3		T3	1		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	810	1			T1	12		T3	2		T16	5
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	153	1			T25	1		T64	1		T66	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	351	1			T6	2		T25	2		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	252	1			T5	1		T33	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	468	1			T4	1		T5	1		T25	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	267	1			T2	2		T5	1		T25	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	418	1			T2	4		T4	2		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	273	1			T3	2		T16	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	439	1			T1	2		T3	3		T5	1