Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31017

1

T1

31

T2

21

T3

22

auto[1]

229

1

T79

1

T96

8

T97

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31028	1			T1	31		T2	21		T3	22
auto[134217728:268435455]	5	1			T96	1		T97	1		T264	1
auto[268435456:402653183]	7	1			T113	1		T264	1		T401	1
auto[402653184:536870911]	6	1			T100	1		T264	2		T401	1
auto[536870912:671088639]	4	1			T102	1		T402	1		T297	1
auto[671088640:805306367]	7	1			T96	1		T403	1		T404	1
auto[805306368:939524095]	9	1			T100	1		T384	1		T404	1
auto[939524096:1073741823]	10	1			T97	1		T328	1		T265	1
auto[1073741824:1207959551]	13	1			T96	1		T97	1		T328	1
auto[1207959552:1342177279]	11	1			T99	1		T247	1		T265	1
auto[1342177280:1476395007]	7	1			T79	1		T247	1		T264	1
auto[1476395008:1610612735]	4	1			T288	1		T401	1		T297	1
auto[1610612736:1744830463]	4	1			T96	1		T403	1		T288	1
auto[1744830464:1879048191]	7	1			T328	1		T247	1		T288	1
auto[1879048192:2013265919]	7	1			T102	1		T383	1		T384	1
auto[2013265920:2147483647]	2	1			T384	2		-	-		-	-
auto[2147483648:2281701375]	11	1			T97	1		T113	1		T99	1
auto[2281701376:2415919103]	9	1			T285	1		T384	1		T401	1
auto[2415919104:2550136831]	6	1			T295	1		T264	1		T401	1
auto[2550136832:2684354559]	7	1			T405	1		T297	1		T406	1
auto[2684354560:2818572287]	7	1			T96	2		T99	2		T404	1
auto[2818572288:2952790015]	7	1			T247	1		T264	2		T384	1
auto[2952790016:3087007743]	8	1			T401	1		T404	2		T386	1
auto[3087007744:3221225471]	6	1			T247	1		T401	2		T405	1
auto[3221225472:3355443199]	1	1			T402	1		-	-		-	-
auto[3355443200:3489660927]	8	1			T405	1		T386	1		T406	2
auto[3489660928:3623878655]	7	1			T96	1		T99	1		T102	1
auto[3623878656:3758096383]	7	1			T403	1		T288	1		T401	1
auto[3758096384:3892314111]	12	1			T96	1		T99	1		T295	1
auto[3892314112:4026531839]	9	1			T328	1		T264	1		T401	1
auto[4026531840:4160749567]	6	1			T264	1		T403	1		T288	1
auto[4160749568:4294967295]	4	1			T97	2		T288	1		T404	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31017	1			T1	31		T2	21		T3	22
auto[0:134217727]	auto[1]	11	1			T328	1		T102	1		T264	2
auto[134217728:268435455]	auto[1]	5	1			T96	1		T97	1		T264	1
auto[268435456:402653183]	auto[1]	7	1			T113	1		T264	1		T401	1
auto[402653184:536870911]	auto[1]	6	1			T100	1		T264	2		T401	1
auto[536870912:671088639]	auto[1]	4	1			T102	1		T402	1		T297	1
auto[671088640:805306367]	auto[1]	7	1			T96	1		T403	1		T404	1
auto[805306368:939524095]	auto[1]	9	1			T100	1		T384	1		T404	1
auto[939524096:1073741823]	auto[1]	10	1			T97	1		T328	1		T265	1
auto[1073741824:1207959551]	auto[1]	13	1			T96	1		T97	1		T328	1
auto[1207959552:1342177279]	auto[1]	11	1			T99	1		T247	1		T265	1
auto[1342177280:1476395007]	auto[1]	7	1			T79	1		T247	1		T264	1
auto[1476395008:1610612735]	auto[1]	4	1			T288	1		T401	1		T297	1
auto[1610612736:1744830463]	auto[1]	4	1			T96	1		T403	1		T288	1
auto[1744830464:1879048191]	auto[1]	7	1			T328	1		T247	1		T288	1
auto[1879048192:2013265919]	auto[1]	7	1			T102	1		T383	1		T384	1
auto[2013265920:2147483647]	auto[1]	2	1			T384	2		-	-		-	-
auto[2147483648:2281701375]	auto[1]	11	1			T97	1		T113	1		T99	1
auto[2281701376:2415919103]	auto[1]	9	1			T285	1		T384	1		T401	1
auto[2415919104:2550136831]	auto[1]	6	1			T295	1		T264	1		T401	1
auto[2550136832:2684354559]	auto[1]	7	1			T405	1		T297	1		T406	1
auto[2684354560:2818572287]	auto[1]	7	1			T96	2		T99	2		T404	1
auto[2818572288:2952790015]	auto[1]	7	1			T247	1		T264	2		T384	1
auto[2952790016:3087007743]	auto[1]	8	1			T401	1		T404	2		T386	1
auto[3087007744:3221225471]	auto[1]	6	1			T247	1		T401	2		T405	1
auto[3221225472:3355443199]	auto[1]	1	1			T402	1		-	-		-	-
auto[3355443200:3489660927]	auto[1]	8	1			T405	1		T386	1		T406	2
auto[3489660928:3623878655]	auto[1]	7	1			T96	1		T99	1		T102	1
auto[3623878656:3758096383]	auto[1]	7	1			T403	1		T288	1		T401	1
auto[3758096384:3892314111]	auto[1]	12	1			T96	1		T99	1		T295	1
auto[3892314112:4026531839]	auto[1]	9	1			T328	1		T264	1		T401	1
auto[4026531840:4160749567]	auto[1]	6	1			T264	1		T403	1		T288	1
auto[4160749568:4294967295]	auto[1]	4	1			T97	2		T288	1		T404	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1480

1

T4

1

T15

4

T5

2

auto[1]

1672

1

T4

4

T15

1

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	97	1			T25	1		T91	1		T64	1
auto[134217728:268435455]	101	1			T25	2		T95	1		T64	1
auto[268435456:402653183]	100	1			T4	2		T64	1		T93	1
auto[402653184:536870911]	105	1			T5	2		T25	1		T91	1
auto[536870912:671088639]	95	1			T79	1		T64	2		T7	2
auto[671088640:805306367]	95	1			T25	1		T47	1		T64	1
auto[805306368:939524095]	86	1			T15	1		T6	1		T25	1
auto[939524096:1073741823]	95	1			T7	1		T66	1		T128	1
auto[1073741824:1207959551]	105	1			T4	2		T25	2		T94	1
auto[1207959552:1342177279]	84	1			T95	1		T64	1		T66	1
auto[1342177280:1476395007]	105	1			T68	1		T66	1		T49	1
auto[1476395008:1610612735]	111	1			T25	2		T63	2		T79	1
auto[1610612736:1744830463]	89	1			T25	2		T64	1		T92	1
auto[1744830464:1879048191]	101	1			T15	2		T5	1		T47	1
auto[1879048192:2013265919]	110	1			T35	1		T94	1		T63	1
auto[2013265920:2147483647]	96	1			T47	1		T79	1		T64	1
auto[2147483648:2281701375]	99	1			T35	1		T64	2		T92	1
auto[2281701376:2415919103]	102	1			T63	2		T64	2		T66	1
auto[2415919104:2550136831]	84	1			T15	1		T25	1		T67	1
auto[2550136832:2684354559]	91	1			T25	2		T28	1		T64	1
auto[2684354560:2818572287]	92	1			T25	2		T63	3		T67	1
auto[2818572288:2952790015]	97	1			T7	1		T66	2		T128	1
auto[2952790016:3087007743]	93	1			T4	1		T95	1		T28	1
auto[3087007744:3221225471]	110	1			T25	1		T94	1		T47	1
auto[3221225472:3355443199]	104	1			T25	2		T47	1		T67	1
auto[3355443200:3489660927]	106	1			T6	1		T68	1		T65	1
auto[3489660928:3623878655]	115	1			T5	1		T6	1		T33	1
auto[3623878656:3758096383]	114	1			T95	1		T63	1		T66	1
auto[3758096384:3892314111]	84	1			T25	2		T47	1		T7	1
auto[3892314112:4026531839]	78	1			T15	1		T7	1		T50	1
auto[4026531840:4160749567]	105	1			T25	2		T64	2		T66	1
auto[4160749568:4294967295]	103	1			T6	1		T25	1		T65	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	46	1			T25	1		T64	1		T7	1
auto[0:134217727]	auto[1]	51	1			T91	1		T92	1		T128	1
auto[134217728:268435455]	auto[0]	50	1			T95	1		T58	1		T120	1
auto[134217728:268435455]	auto[1]	51	1			T25	2		T64	1		T67	1
auto[268435456:402653183]	auto[0]	50	1			T64	1		T128	2		T132	1
auto[268435456:402653183]	auto[1]	50	1			T4	2		T93	1		T84	1
auto[402653184:536870911]	auto[0]	55	1			T5	1		T72	1		T66	3
auto[402653184:536870911]	auto[1]	50	1			T5	1		T25	1		T91	1
auto[536870912:671088639]	auto[0]	48	1			T64	1		T7	2		T227	1
auto[536870912:671088639]	auto[1]	47	1			T79	1		T64	1		T66	1
auto[671088640:805306367]	auto[0]	53	1			T25	1		T47	1		T7	2
auto[671088640:805306367]	auto[1]	42	1			T64	1		T72	1		T84	1
auto[805306368:939524095]	auto[0]	44	1			T15	1		T6	1		T25	1
auto[805306368:939524095]	auto[1]	42	1			T65	1		T64	1		T96	1
auto[939524096:1073741823]	auto[0]	38	1			T128	1		T52	1		T48	1
auto[939524096:1073741823]	auto[1]	57	1			T7	1		T66	1		T224	1
auto[1073741824:1207959551]	auto[0]	48	1			T7	1		T236	1		T48	1
auto[1073741824:1207959551]	auto[1]	57	1			T4	2		T25	2		T94	1
auto[1207959552:1342177279]	auto[0]	41	1			T95	1		T64	1		T58	1
auto[1207959552:1342177279]	auto[1]	43	1			T66	1		T96	1		T370	1
auto[1342177280:1476395007]	auto[0]	46	1			T68	1		T48	1		T27	1
auto[1342177280:1476395007]	auto[1]	59	1			T66	1		T49	1		T50	1
auto[1476395008:1610612735]	auto[0]	52	1			T63	1		T79	1		T64	1
auto[1476395008:1610612735]	auto[1]	59	1			T25	2		T63	1		T64	1
auto[1610612736:1744830463]	auto[0]	49	1			T92	1		T7	1		T93	1
auto[1610612736:1744830463]	auto[1]	40	1			T25	2		T64	1		T227	1
auto[1744830464:1879048191]	auto[0]	40	1			T15	2		T52	1		T330	1
auto[1744830464:1879048191]	auto[1]	61	1			T5	1		T47	1		T63	1
auto[1879048192:2013265919]	auto[0]	54	1			T94	1		T64	1		T66	1
auto[1879048192:2013265919]	auto[1]	56	1			T35	1		T63	1		T84	1
auto[2013265920:2147483647]	auto[0]	41	1			T64	1		T128	1		T96	1
auto[2013265920:2147483647]	auto[1]	55	1			T47	1		T79	1		T236	1
auto[2147483648:2281701375]	auto[0]	45	1			T35	1		T92	1		T93	1
auto[2147483648:2281701375]	auto[1]	54	1			T64	2		T7	1		T128	2
auto[2281701376:2415919103]	auto[0]	54	1			T63	1		T64	1		T66	1
auto[2281701376:2415919103]	auto[1]	48	1			T63	1		T64	1		T96	1
auto[2415919104:2550136831]	auto[0]	40	1			T25	1		T67	1		T146	1
auto[2415919104:2550136831]	auto[1]	44	1			T15	1		T92	1		T7	1
auto[2550136832:2684354559]	auto[0]	39	1			T25	1		T64	1		T66	1
auto[2550136832:2684354559]	auto[1]	52	1			T25	1		T28	1		T66	1
auto[2684354560:2818572287]	auto[0]	42	1			T25	1		T63	2		T67	1
auto[2684354560:2818572287]	auto[1]	50	1			T25	1		T63	1		T57	1
auto[2818572288:2952790015]	auto[0]	47	1			T7	1		T66	1		T227	1
auto[2818572288:2952790015]	auto[1]	50	1			T66	1		T128	1		T132	1
auto[2952790016:3087007743]	auto[0]	43	1			T4	1		T91	1		T7	1
auto[2952790016:3087007743]	auto[1]	50	1			T95	1		T28	1		T63	1
auto[3087007744:3221225471]	auto[0]	54	1			T128	2		T100	1		T85	1
auto[3087007744:3221225471]	auto[1]	56	1			T25	1		T94	1		T47	1
auto[3221225472:3355443199]	auto[0]	41	1			T25	1		T67	1		T66	1
auto[3221225472:3355443199]	auto[1]	63	1			T25	1		T47	1		T66	1
auto[3355443200:3489660927]	auto[0]	49	1			T68	1		T93	1		T128	1
auto[3355443200:3489660927]	auto[1]	57	1			T6	1		T65	1		T7	1
auto[3489660928:3623878655]	auto[0]	49	1			T5	1		T91	1		T93	1
auto[3489660928:3623878655]	auto[1]	66	1			T6	1		T33	1		T25	1
auto[3623878656:3758096383]	auto[0]	53	1			T63	1		T119	1		T85	1
auto[3623878656:3758096383]	auto[1]	61	1			T95	1		T66	1		T128	4
auto[3758096384:3892314111]	auto[0]	39	1			T66	2		T85	1		T86	1
auto[3758096384:3892314111]	auto[1]	45	1			T25	2		T47	1		T7	1
auto[3892314112:4026531839]	auto[0]	43	1			T15	1		T50	1		T59	1
auto[3892314112:4026531839]	auto[1]	35	1			T7	1		T97	1		T18	1
auto[4026531840:4160749567]	auto[0]	39	1			T64	1		T128	1		T59	2
auto[4026531840:4160749567]	auto[1]	66	1			T25	2		T64	1		T66	1
auto[4160749568:4294967295]	auto[0]	48	1			T94	1		T7	1		T128	1
auto[4160749568:4294967295]	auto[1]	55	1			T6	1		T25	1		T65	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1485

1

T4

1

T15

4

T5

2

auto[1]

1667

1

T4

4

T15

1

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T25	2		T79	1		T66	1
auto[134217728:268435455]	99	1			T5	1		T25	3		T35	1
auto[268435456:402653183]	98	1			T4	1		T68	2		T47	1
auto[402653184:536870911]	95	1			T95	1		T67	1		T92	1
auto[536870912:671088639]	114	1			T15	1		T25	1		T94	1
auto[671088640:805306367]	106	1			T68	1		T94	1		T63	1
auto[805306368:939524095]	98	1			T4	1		T15	1		T5	1
auto[939524096:1073741823]	92	1			T94	1		T64	1		T236	1
auto[1073741824:1207959551]	113	1			T95	1		T7	2		T50	1
auto[1207959552:1342177279]	111	1			T25	1		T63	1		T91	2
auto[1342177280:1476395007]	99	1			T25	1		T79	1		T92	1
auto[1476395008:1610612735]	87	1			T25	1		T65	1		T63	1
auto[1610612736:1744830463]	98	1			T15	1		T6	1		T65	2
auto[1744830464:1879048191]	87	1			T25	1		T66	1		T49	1
auto[1879048192:2013265919]	89	1			T25	1		T92	1		T66	2
auto[2013265920:2147483647]	97	1			T15	1		T63	2		T64	1
auto[2147483648:2281701375]	98	1			T25	1		T28	1		T7	1
auto[2281701376:2415919103]	83	1			T25	2		T64	1		T66	3
auto[2415919104:2550136831]	89	1			T79	1		T91	1		T128	1
auto[2550136832:2684354559]	95	1			T63	1		T91	1		T64	1
auto[2684354560:2818572287]	93	1			T5	1		T25	1		T35	1
auto[2818572288:2952790015]	98	1			T33	1		T25	1		T94	1
auto[2952790016:3087007743]	99	1			T95	1		T63	2		T64	3
auto[3087007744:3221225471]	103	1			T25	1		T35	1		T47	1
auto[3221225472:3355443199]	88	1			T6	1		T25	2		T64	1
auto[3355443200:3489660927]	93	1			T25	2		T28	1		T47	1
auto[3489660928:3623878655]	104	1			T4	1		T63	1		T64	1
auto[3623878656:3758096383]	104	1			T64	1		T7	1		T93	1
auto[3758096384:3892314111]	102	1			T6	1		T25	1		T95	1
auto[3892314112:4026531839]	111	1			T4	1		T25	1		T63	2
auto[4026531840:4160749567]	111	1			T15	1		T5	1		T6	1
auto[4160749568:4294967295]	102	1			T4	1		T25	2		T64	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T25	1		T66	1		T132	1
auto[0:134217727]	auto[1]	48	1			T25	1		T79	1		T236	1
auto[134217728:268435455]	auto[0]	48	1			T5	1		T25	1		T35	1
auto[134217728:268435455]	auto[1]	51	1			T25	2		T64	1		T85	1
auto[268435456:402653183]	auto[0]	46	1			T68	2		T47	1		T66	1
auto[268435456:402653183]	auto[1]	52	1			T4	1		T134	1		T135	1
auto[402653184:536870911]	auto[0]	54	1			T67	1		T93	1		T66	1
auto[402653184:536870911]	auto[1]	41	1			T95	1		T92	1		T66	1
auto[536870912:671088639]	auto[0]	50	1			T64	2		T146	1		T58	2
auto[536870912:671088639]	auto[1]	64	1			T15	1		T25	1		T94	1
auto[671088640:805306367]	auto[0]	54	1			T68	1		T7	1		T146	1
auto[671088640:805306367]	auto[1]	52	1			T94	1		T63	1		T66	1
auto[805306368:939524095]	auto[0]	48	1			T15	1		T64	2		T7	1
auto[805306368:939524095]	auto[1]	50	1			T4	1		T5	1		T25	1
auto[939524096:1073741823]	auto[0]	54	1			T94	1		T64	1		T236	1
auto[939524096:1073741823]	auto[1]	38	1			T96	1		T58	1		T224	1
auto[1073741824:1207959551]	auto[0]	48	1			T95	1		T7	1		T84	1
auto[1073741824:1207959551]	auto[1]	65	1			T7	1		T50	1		T99	1
auto[1207959552:1342177279]	auto[0]	54	1			T25	1		T91	1		T93	1
auto[1207959552:1342177279]	auto[1]	57	1			T63	1		T91	1		T7	2
auto[1342177280:1476395007]	auto[0]	41	1			T92	1		T50	1		T8	1
auto[1342177280:1476395007]	auto[1]	58	1			T25	1		T79	1		T7	1
auto[1476395008:1610612735]	auto[0]	38	1			T25	1		T65	1		T63	1
auto[1476395008:1610612735]	auto[1]	49	1			T50	1		T48	1		T113	1
auto[1610612736:1744830463]	auto[0]	47	1			T15	1		T128	1		T45	1
auto[1610612736:1744830463]	auto[1]	51	1			T6	1		T65	2		T64	2
auto[1744830464:1879048191]	auto[0]	47	1			T25	1		T59	1		T125	1
auto[1744830464:1879048191]	auto[1]	40	1			T66	1		T49	1		T84	1
auto[1879048192:2013265919]	auto[0]	45	1			T66	1		T119	1		T52	1
auto[1879048192:2013265919]	auto[1]	44	1			T25	1		T92	1		T66	1
auto[2013265920:2147483647]	auto[0]	49	1			T15	1		T63	2		T7	2
auto[2013265920:2147483647]	auto[1]	48	1			T64	1		T66	1		T124	1
auto[2147483648:2281701375]	auto[0]	43	1			T7	1		T236	1		T84	1
auto[2147483648:2281701375]	auto[1]	55	1			T25	1		T28	1		T128	1
auto[2281701376:2415919103]	auto[0]	47	1			T25	1		T64	1		T66	1
auto[2281701376:2415919103]	auto[1]	36	1			T25	1		T66	2		T370	1
auto[2415919104:2550136831]	auto[0]	43	1			T79	1		T91	1		T128	1
auto[2415919104:2550136831]	auto[1]	46	1			T132	1		T227	1		T330	1
auto[2550136832:2684354559]	auto[0]	42	1			T64	1		T128	1		T407	1
auto[2550136832:2684354559]	auto[1]	53	1			T63	1		T91	1		T66	2
auto[2684354560:2818572287]	auto[0]	35	1			T5	1		T25	1		T35	1
auto[2684354560:2818572287]	auto[1]	58	1			T47	1		T7	1		T128	1
auto[2818572288:2952790015]	auto[0]	39	1			T94	1		T95	1		T92	1
auto[2818572288:2952790015]	auto[1]	59	1			T33	1		T25	1		T85	2
auto[2952790016:3087007743]	auto[0]	44	1			T63	1		T64	1		T128	1
auto[2952790016:3087007743]	auto[1]	55	1			T95	1		T63	1		T64	2
auto[3087007744:3221225471]	auto[0]	48	1			T35	1		T64	1		T72	1
auto[3087007744:3221225471]	auto[1]	55	1			T25	1		T47	1		T7	1
auto[3221225472:3355443199]	auto[0]	35	1			T7	1		T93	1		T66	1
auto[3221225472:3355443199]	auto[1]	53	1			T6	1		T25	2		T64	1
auto[3355443200:3489660927]	auto[0]	45	1			T67	1		T66	2		T132	1
auto[3355443200:3489660927]	auto[1]	48	1			T25	2		T28	1		T47	1
auto[3489660928:3623878655]	auto[0]	49	1			T4	1		T93	1		T49	1
auto[3489660928:3623878655]	auto[1]	55	1			T63	1		T64	1		T67	1
auto[3623878656:3758096383]	auto[0]	48	1			T66	1		T128	1		T58	1
auto[3623878656:3758096383]	auto[1]	56	1			T64	1		T7	1		T93	1
auto[3758096384:3892314111]	auto[0]	41	1			T47	1		T67	1		T7	1
auto[3758096384:3892314111]	auto[1]	61	1			T6	1		T25	1		T95	1
auto[3892314112:4026531839]	auto[0]	51	1			T63	1		T7	1		T128	1
auto[3892314112:4026531839]	auto[1]	60	1			T4	1		T25	1		T63	1
auto[4026531840:4160749567]	auto[0]	61	1			T15	1		T6	1		T63	1
auto[4026531840:4160749567]	auto[1]	50	1			T5	1		T47	1		T72	1
auto[4160749568:4294967295]	auto[0]	43	1			T25	1		T64	1		T236	1
auto[4160749568:4294967295]	auto[1]	59	1			T4	1		T25	1		T128	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1465

1

T4

1

T15

4

T5

3

auto[1]

1686

1

T4

4

T15

1

T5

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T47	2		T113	1		T85	1
auto[134217728:268435455]	100	1			T4	1		T25	3		T64	1
auto[268435456:402653183]	111	1			T63	1		T64	1		T7	2
auto[402653184:536870911]	109	1			T95	2		T63	1		T64	1
auto[536870912:671088639]	93	1			T63	1		T128	1		T132	1
auto[671088640:805306367]	93	1			T15	1		T6	1		T25	1
auto[805306368:939524095]	107	1			T15	1		T64	1		T93	1
auto[939524096:1073741823]	102	1			T47	1		T91	1		T64	1
auto[1073741824:1207959551]	74	1			T15	1		T25	1		T35	1
auto[1207959552:1342177279]	73	1			T5	1		T94	1		T28	1
auto[1342177280:1476395007]	108	1			T67	1		T7	1		T66	1
auto[1476395008:1610612735]	95	1			T4	1		T25	2		T7	1
auto[1610612736:1744830463]	105	1			T25	2		T64	2		T66	1
auto[1744830464:1879048191]	103	1			T4	1		T6	1		T79	1
auto[1879048192:2013265919]	100	1			T4	1		T7	1		T93	1
auto[2013265920:2147483647]	95	1			T5	1		T25	2		T65	1
auto[2147483648:2281701375]	98	1			T25	2		T47	1		T63	1
auto[2281701376:2415919103]	98	1			T15	1		T68	1		T66	1
auto[2415919104:2550136831]	106	1			T25	2		T94	1		T63	1
auto[2550136832:2684354559]	111	1			T6	1		T65	1		T64	1
auto[2684354560:2818572287]	83	1			T25	1		T63	1		T91	1
auto[2818572288:2952790015]	93	1			T25	2		T92	1		T128	2
auto[2952790016:3087007743]	113	1			T15	1		T6	1		T94	1
auto[3087007744:3221225471]	93	1			T28	1		T91	1		T7	1
auto[3221225472:3355443199]	119	1			T5	1		T25	1		T68	1
auto[3355443200:3489660927]	94	1			T4	1		T25	1		T68	1
auto[3489660928:3623878655]	109	1			T25	2		T65	1		T63	1
auto[3623878656:3758096383]	93	1			T95	1		T79	1		T64	2
auto[3758096384:3892314111]	100	1			T33	1		T94	1		T63	2
auto[3892314112:4026531839]	86	1			T91	1		T64	1		T72	1
auto[4026531840:4160749567]	94	1			T25	1		T35	1		T95	2
auto[4160749568:4294967295]	99	1			T5	1		T25	3		T35	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T113	1		T123	1		T130	1
auto[0:134217727]	auto[1]	52	1			T47	2		T85	1		T86	1
auto[134217728:268435455]	auto[0]	42	1			T25	2		T64	1		T7	1
auto[134217728:268435455]	auto[1]	58	1			T4	1		T25	1		T52	1
auto[268435456:402653183]	auto[0]	44	1			T48	1		T130	1		T31	1
auto[268435456:402653183]	auto[1]	67	1			T63	1		T64	1		T7	2
auto[402653184:536870911]	auto[0]	53	1			T95	1		T67	1		T66	1
auto[402653184:536870911]	auto[1]	56	1			T95	1		T63	1		T64	1
auto[536870912:671088639]	auto[0]	50	1			T63	1		T128	1		T407	1
auto[536870912:671088639]	auto[1]	43	1			T132	1		T97	1		T99	1
auto[671088640:805306367]	auto[0]	34	1			T15	1		T58	1		T86	2
auto[671088640:805306367]	auto[1]	59	1			T6	1		T25	1		T370	1
auto[805306368:939524095]	auto[0]	52	1			T15	1		T64	1		T66	1
auto[805306368:939524095]	auto[1]	55	1			T93	1		T113	1		T85	2
auto[939524096:1073741823]	auto[0]	57	1			T47	1		T67	1		T92	1
auto[939524096:1073741823]	auto[1]	45	1			T91	1		T64	1		T128	1
auto[1073741824:1207959551]	auto[0]	36	1			T15	1		T35	1		T47	1
auto[1073741824:1207959551]	auto[1]	38	1			T25	1		T92	1		T7	1
auto[1207959552:1342177279]	auto[0]	28	1			T5	1		T28	1		T66	1
auto[1207959552:1342177279]	auto[1]	45	1			T94	1		T124	1		T146	1
auto[1342177280:1476395007]	auto[0]	53	1			T7	1		T236	1		T128	1
auto[1342177280:1476395007]	auto[1]	55	1			T67	1		T66	1		T236	1
auto[1476395008:1610612735]	auto[0]	37	1			T58	1		T120	1		T330	1
auto[1476395008:1610612735]	auto[1]	58	1			T4	1		T25	2		T7	1
auto[1610612736:1744830463]	auto[0]	53	1			T25	1		T64	1		T66	1
auto[1610612736:1744830463]	auto[1]	52	1			T25	1		T64	1		T128	1
auto[1744830464:1879048191]	auto[0]	43	1			T4	1		T79	1		T66	1
auto[1744830464:1879048191]	auto[1]	60	1			T6	1		T99	1		T100	1
auto[1879048192:2013265919]	auto[0]	47	1			T93	1		T66	1		T128	2
auto[1879048192:2013265919]	auto[1]	53	1			T4	1		T7	1		T66	1
auto[2013265920:2147483647]	auto[0]	49	1			T5	1		T25	1		T99	1
auto[2013265920:2147483647]	auto[1]	46	1			T25	1		T65	1		T95	1
auto[2147483648:2281701375]	auto[0]	41	1			T63	1		T7	1		T128	1
auto[2147483648:2281701375]	auto[1]	57	1			T25	2		T47	1		T7	2
auto[2281701376:2415919103]	auto[0]	38	1			T15	1		T68	1		T58	1
auto[2281701376:2415919103]	auto[1]	60	1			T66	1		T128	1		T97	1
auto[2415919104:2550136831]	auto[0]	48	1			T94	1		T63	1		T64	1
auto[2415919104:2550136831]	auto[1]	58	1			T25	2		T64	2		T66	1
auto[2550136832:2684354559]	auto[0]	57	1			T64	1		T7	1		T93	1
auto[2550136832:2684354559]	auto[1]	54	1			T6	1		T65	1		T128	1
auto[2684354560:2818572287]	auto[0]	39	1			T25	1		T7	1		T128	1
auto[2684354560:2818572287]	auto[1]	44	1			T63	1		T91	1		T7	1
auto[2818572288:2952790015]	auto[0]	45	1			T25	1		T92	1		T128	1
auto[2818572288:2952790015]	auto[1]	48	1			T25	1		T128	1		T49	1
auto[2952790016:3087007743]	auto[0]	49	1			T93	1		T119	1		T227	1
auto[2952790016:3087007743]	auto[1]	64	1			T15	1		T6	1		T94	1
auto[3087007744:3221225471]	auto[0]	41	1			T91	1		T7	1		T66	1
auto[3087007744:3221225471]	auto[1]	52	1			T28	1		T66	1		T128	1
auto[3221225472:3355443199]	auto[0]	54	1			T5	1		T68	1		T63	1
auto[3221225472:3355443199]	auto[1]	65	1			T25	1		T64	1		T92	1
auto[3355443200:3489660927]	auto[0]	37	1			T25	1		T84	1		T238	1
auto[3355443200:3489660927]	auto[1]	57	1			T4	1		T68	1		T47	1
auto[3489660928:3623878655]	auto[0]	55	1			T65	1		T63	1		T64	1
auto[3489660928:3623878655]	auto[1]	54	1			T25	2		T79	1		T7	1
auto[3623878656:3758096383]	auto[0]	46	1			T79	1		T64	2		T176	1
auto[3623878656:3758096383]	auto[1]	47	1			T95	1		T119	1		T49	1
auto[3758096384:3892314111]	auto[0]	58	1			T94	1		T63	1		T64	1
auto[3758096384:3892314111]	auto[1]	42	1			T33	1		T63	1		T7	1
auto[3892314112:4026531839]	auto[0]	47	1			T64	1		T7	1		T119	1
auto[3892314112:4026531839]	auto[1]	39	1			T91	1		T72	1		T128	1
auto[4026531840:4160749567]	auto[0]	42	1			T35	1		T95	1		T91	1
auto[4026531840:4160749567]	auto[1]	52	1			T25	1		T95	1		T47	1
auto[4160749568:4294967295]	auto[0]	48	1			T25	1		T64	1		T45	1
auto[4160749568:4294967295]	auto[1]	51	1			T5	1		T25	2		T35	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1480

1

T15

4

T5

1

T6

1

auto[1]

1672

1

T4

5

T15

1

T5

3