Unified Coverage Report :: Group Instance : max_owner_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4248

1

T15

8

T5

4

T6

8

auto[1]

2056

1

T4

10

T15

2

T5

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	214	1			T47	2		T79	2		T64	4
auto[134217728:268435455]	180	1			T6	2		T25	2		T72	2
auto[268435456:402653183]	184	1			T15	2		T25	2		T91	2
auto[402653184:536870911]	194	1			T25	2		T63	2		T7	6
auto[536870912:671088639]	220	1			T5	2		T25	2		T47	2
auto[671088640:805306367]	206	1			T63	2		T64	2		T7	2
auto[805306368:939524095]	196	1			T64	2		T7	2		T66	4
auto[939524096:1073741823]	192	1			T4	2		T25	2		T7	2
auto[1073741824:1207959551]	216	1			T25	2		T47	2		T64	4
auto[1207959552:1342177279]	158	1			T25	4		T95	2		T64	4
auto[1342177280:1476395007]	202	1			T7	2		T66	2		T146	2
auto[1476395008:1610612735]	180	1			T6	2		T25	2		T63	2
auto[1610612736:1744830463]	196	1			T4	2		T25	2		T94	2
auto[1744830464:1879048191]	178	1			T68	2		T65	2		T64	2
auto[1879048192:2013265919]	190	1			T25	4		T94	6		T63	2
auto[2013265920:2147483647]	188	1			T4	2		T15	2		T68	2
auto[2147483648:2281701375]	198	1			T25	2		T84	2		T58	2
auto[2281701376:2415919103]	174	1			T25	2		T65	2		T47	2
auto[2415919104:2550136831]	204	1			T25	2		T63	2		T64	2
auto[2550136832:2684354559]	214	1			T25	2		T95	2		T63	2
auto[2684354560:2818572287]	202	1			T15	2		T64	2		T7	2
auto[2818572288:2952790015]	184	1			T28	2		T64	2		T66	2
auto[2952790016:3087007743]	188	1			T5	2		T68	2		T35	2
auto[3087007744:3221225471]	184	1			T25	6		T65	2		T63	2
auto[3221225472:3355443199]	176	1			T95	4		T63	2		T91	2
auto[3355443200:3489660927]	234	1			T5	2		T25	6		T63	2
auto[3489660928:3623878655]	208	1			T64	2		T49	2		T84	2
auto[3623878656:3758096383]	190	1			T25	4		T47	2		T66	2
auto[3758096384:3892314111]	206	1			T4	2		T15	2		T33	2
auto[3892314112:4026531839]	212	1			T6	2		T25	2		T63	2
auto[4026531840:4160749567]	220	1			T15	2		T35	4		T66	2
auto[4160749568:4294967295]	216	1			T4	2		T5	2		T6	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	140	1			T47	2		T79	2		T64	4
auto[0:134217727]	auto[1]	74	1			T128	2		T113	2		T87	4
auto[134217728:268435455]	auto[0]	134	1			T6	2		T72	2		T128	2
auto[134217728:268435455]	auto[1]	46	1			T25	2		T128	2		T99	4
auto[268435456:402653183]	auto[0]	116	1			T15	2		T67	2		T92	2
auto[268435456:402653183]	auto[1]	68	1			T25	2		T91	2		T66	2
auto[402653184:536870911]	auto[0]	106	1			T7	4		T66	4		T128	4
auto[402653184:536870911]	auto[1]	88	1			T25	2		T63	2		T7	2
auto[536870912:671088639]	auto[0]	178	1			T5	2		T25	2		T47	2
auto[536870912:671088639]	auto[1]	42	1			T59	2		T85	2		T31	2
auto[671088640:805306367]	auto[0]	132	1			T63	2		T119	2		T96	2
auto[671088640:805306367]	auto[1]	74	1			T64	2		T7	2		T58	2
auto[805306368:939524095]	auto[0]	128	1			T7	2		T66	4		T227	2
auto[805306368:939524095]	auto[1]	68	1			T64	2		T27	2		T413	2
auto[939524096:1073741823]	auto[0]	134	1			T7	2		T66	2		T130	2
auto[939524096:1073741823]	auto[1]	58	1			T4	2		T25	2		T58	2
auto[1073741824:1207959551]	auto[0]	162	1			T25	2		T47	2		T64	4
auto[1073741824:1207959551]	auto[1]	54	1			T66	2		T49	2		T132	2
auto[1207959552:1342177279]	auto[0]	118	1			T25	2		T95	2		T64	4
auto[1207959552:1342177279]	auto[1]	40	1			T25	2		T84	2		T87	2
auto[1342177280:1476395007]	auto[0]	120	1			T7	2		T66	2		T146	2
auto[1342177280:1476395007]	auto[1]	82	1			T69	2		T19	2		T267	4
auto[1476395008:1610612735]	auto[0]	136	1			T6	2		T25	2		T63	2
auto[1476395008:1610612735]	auto[1]	44	1			T134	2		T39	2		T414	2
auto[1610612736:1744830463]	auto[0]	132	1			T25	2		T66	2		T128	2
auto[1610612736:1744830463]	auto[1]	64	1			T4	2		T94	2		T128	2
auto[1744830464:1879048191]	auto[0]	128	1			T64	2		T7	2		T66	4
auto[1744830464:1879048191]	auto[1]	50	1			T68	2		T65	2		T132	2
auto[1879048192:2013265919]	auto[0]	128	1			T25	2		T94	6		T64	2
auto[1879048192:2013265919]	auto[1]	62	1			T25	2		T63	2		T79	2
auto[2013265920:2147483647]	auto[0]	128	1			T68	2		T66	2		T128	2
auto[2013265920:2147483647]	auto[1]	60	1			T4	2		T15	2		T95	2
auto[2147483648:2281701375]	auto[0]	128	1			T25	2		T84	2		T58	2
auto[2147483648:2281701375]	auto[1]	70	1			T18	2		T370	2		T411	2
auto[2281701376:2415919103]	auto[0]	114	1			T47	2		T67	2		T7	2
auto[2281701376:2415919103]	auto[1]	60	1			T25	2		T65	2		T128	2
auto[2415919104:2550136831]	auto[0]	130	1			T63	2		T64	2		T128	2
auto[2415919104:2550136831]	auto[1]	74	1			T25	2		T128	2		T59	4
auto[2550136832:2684354559]	auto[0]	148	1			T25	2		T95	2		T93	2
auto[2550136832:2684354559]	auto[1]	66	1			T63	2		T64	2		T58	2
auto[2684354560:2818572287]	auto[0]	136	1			T15	2		T64	2		T7	2
auto[2684354560:2818572287]	auto[1]	66	1			T66	2		T132	2		T58	2
auto[2818572288:2952790015]	auto[0]	120	1			T28	2		T64	2		T66	2
auto[2818572288:2952790015]	auto[1]	64	1			T149	2		T134	2		T59	2
auto[2952790016:3087007743]	auto[0]	126	1			T5	2		T68	2		T7	2
auto[2952790016:3087007743]	auto[1]	62	1			T35	2		T64	4		T7	2
auto[3087007744:3221225471]	auto[0]	128	1			T25	4		T63	2		T67	2
auto[3087007744:3221225471]	auto[1]	56	1			T25	2		T65	2		T72	2
auto[3221225472:3355443199]	auto[0]	120	1			T95	4		T91	2		T66	2
auto[3221225472:3355443199]	auto[1]	56	1			T63	2		T48	2		T138	2
auto[3355443200:3489660927]	auto[0]	154	1			T25	2		T63	2		T7	2
auto[3355443200:3489660927]	auto[1]	80	1			T5	2		T25	4		T7	8
auto[3489660928:3623878655]	auto[0]	150	1			T64	2		T49	2		T58	2
auto[3489660928:3623878655]	auto[1]	58	1			T84	2		T113	2		T125	2
auto[3623878656:3758096383]	auto[0]	128	1			T25	2		T66	2		T50	2
auto[3623878656:3758096383]	auto[1]	62	1			T25	2		T47	2		T224	2
auto[3758096384:3892314111]	auto[0]	118	1			T15	2		T33	2		T95	2
auto[3758096384:3892314111]	auto[1]	88	1			T4	2		T47	2		T63	4
auto[3892314112:4026531839]	auto[0]	124	1			T6	2		T25	2		T93	2
auto[3892314112:4026531839]	auto[1]	88	1			T63	2		T64	2		T97	2
auto[4026531840:4160749567]	auto[0]	152	1			T15	2		T66	2		T128	2
auto[4026531840:4160749567]	auto[1]	68	1			T35	4		T85	2		T252	2
auto[4160749568:4294967295]	auto[0]	152	1			T6	2		T25	2		T63	2
auto[4160749568:4294967295]	auto[1]	64	1			T4	2		T5	2		T95	2