Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2779

1

T4

5

T15

5

T5

4

auto[1]

253

1

T79

1

T96

9

T97

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T25	1		T47	1		T7	1
auto[134217728:268435455]	92	1			T6	1		T64	1		T66	1
auto[268435456:402653183]	101	1			T28	1		T63	1		T7	1
auto[402653184:536870911]	79	1			T65	1		T95	1		T28	1
auto[536870912:671088639]	86	1			T95	1		T63	1		T92	1
auto[671088640:805306367]	101	1			T94	1		T47	1		T63	1
auto[805306368:939524095]	91	1			T15	1		T95	1		T7	2
auto[939524096:1073741823]	94	1			T25	2		T72	1		T7	1
auto[1073741824:1207959551]	85	1			T64	1		T66	1		T119	1
auto[1207959552:1342177279]	97	1			T25	1		T63	1		T64	1
auto[1342177280:1476395007]	106	1			T5	1		T25	1		T64	1
auto[1476395008:1610612735]	111	1			T6	1		T25	1		T35	1
auto[1610612736:1744830463]	120	1			T4	1		T15	1		T25	1
auto[1744830464:1879048191]	105	1			T25	1		T68	1		T95	1
auto[1879048192:2013265919]	95	1			T25	1		T47	1		T330	1
auto[2013265920:2147483647]	88	1			T5	1		T65	1		T91	1
auto[2147483648:2281701375]	101	1			T4	1		T15	1		T25	1
auto[2281701376:2415919103]	99	1			T25	2		T63	1		T91	1
auto[2415919104:2550136831]	89	1			T5	1		T33	1		T79	1
auto[2550136832:2684354559]	98	1			T25	2		T95	1		T47	1
auto[2684354560:2818572287]	88	1			T66	1		T128	1		T96	1
auto[2818572288:2952790015]	95	1			T4	1		T5	1		T25	1
auto[2952790016:3087007743]	82	1			T68	1		T7	2		T66	1
auto[3087007744:3221225471]	84	1			T4	1		T15	1		T66	1
auto[3221225472:3355443199]	99	1			T47	1		T63	1		T64	1
auto[3355443200:3489660927]	79	1			T15	1		T25	1		T64	1
auto[3489660928:3623878655]	84	1			T25	1		T94	1		T64	2
auto[3623878656:3758096383]	94	1			T35	1		T47	1		T79	1
auto[3758096384:3892314111]	89	1			T25	1		T35	1		T92	1
auto[3892314112:4026531839]	101	1			T4	1		T6	1		T94	1
auto[4026531840:4160749567]	97	1			T6	1		T25	1		T68	1
auto[4160749568:4294967295]	113	1			T25	1		T65	1		T64	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	87	1			T25	1		T47	1		T7	1
auto[0:134217727]	auto[1]	2	1			T401	1		T423	1		-	-
auto[134217728:268435455]	auto[0]	79	1			T6	1		T64	1		T66	1
auto[134217728:268435455]	auto[1]	13	1			T96	1		T100	2		T403	1
auto[268435456:402653183]	auto[0]	94	1			T28	1		T63	1		T7	1
auto[268435456:402653183]	auto[1]	7	1			T328	1		T295	1		T288	1
auto[402653184:536870911]	auto[0]	71	1			T65	1		T95	1		T28	1
auto[402653184:536870911]	auto[1]	8	1			T403	1		T402	1		T417	1
auto[536870912:671088639]	auto[0]	80	1			T95	1		T63	1		T92	1
auto[536870912:671088639]	auto[1]	6	1			T101	1		T288	1		T320	1
auto[671088640:805306367]	auto[0]	96	1			T94	1		T47	1		T63	1
auto[671088640:805306367]	auto[1]	5	1			T96	2		T100	1		T403	1
auto[805306368:939524095]	auto[0]	84	1			T15	1		T95	1		T7	2
auto[805306368:939524095]	auto[1]	7	1			T96	1		T97	1		T401	1
auto[939524096:1073741823]	auto[0]	88	1			T25	2		T72	1		T7	1
auto[939524096:1073741823]	auto[1]	6	1			T102	1		T264	1		T405	1
auto[1073741824:1207959551]	auto[0]	79	1			T64	1		T66	1		T119	1
auto[1073741824:1207959551]	auto[1]	6	1			T96	1		T288	1		T404	1
auto[1207959552:1342177279]	auto[0]	94	1			T25	1		T63	1		T64	1
auto[1207959552:1342177279]	auto[1]	3	1			T97	1		T99	1		T303	1
auto[1342177280:1476395007]	auto[0]	96	1			T5	1		T25	1		T64	1
auto[1342177280:1476395007]	auto[1]	10	1			T99	1		T295	1		T264	1
auto[1476395008:1610612735]	auto[0]	104	1			T6	1		T25	1		T35	1
auto[1476395008:1610612735]	auto[1]	7	1			T99	1		T102	1		T404	1
auto[1610612736:1744830463]	auto[0]	108	1			T4	1		T15	1		T25	1
auto[1610612736:1744830463]	auto[1]	12	1			T97	2		T247	1		T288	1
auto[1744830464:1879048191]	auto[0]	95	1			T25	1		T68	1		T95	1
auto[1744830464:1879048191]	auto[1]	10	1			T100	1		T295	1		T265	1
auto[1879048192:2013265919]	auto[0]	86	1			T25	1		T47	1		T330	1
auto[1879048192:2013265919]	auto[1]	9	1			T328	1		T102	1		T288	1
auto[2013265920:2147483647]	auto[0]	84	1			T5	1		T65	1		T91	1
auto[2013265920:2147483647]	auto[1]	4	1			T247	1		T288	1		T320	1
auto[2147483648:2281701375]	auto[0]	94	1			T4	1		T15	1		T25	1
auto[2147483648:2281701375]	auto[1]	7	1			T96	1		T247	2		T265	1
auto[2281701376:2415919103]	auto[0]	93	1			T25	2		T63	1		T91	1
auto[2281701376:2415919103]	auto[1]	6	1			T97	1		T101	1		T102	1
auto[2415919104:2550136831]	auto[0]	85	1			T5	1		T33	1		T79	1
auto[2415919104:2550136831]	auto[1]	4	1			T97	1		T405	1		T410	1
auto[2550136832:2684354559]	auto[0]	81	1			T25	2		T95	1		T47	1
auto[2550136832:2684354559]	auto[1]	17	1			T96	1		T99	2		T328	1
auto[2684354560:2818572287]	auto[0]	79	1			T66	1		T128	1		T132	1
auto[2684354560:2818572287]	auto[1]	9	1			T96	1		T101	1		T102	1
auto[2818572288:2952790015]	auto[0]	84	1			T4	1		T5	1		T25	1
auto[2818572288:2952790015]	auto[1]	11	1			T100	1		T102	3		T247	1
auto[2952790016:3087007743]	auto[0]	74	1			T68	1		T7	2		T66	1
auto[2952790016:3087007743]	auto[1]	8	1			T99	1		T383	1		T265	1
auto[3087007744:3221225471]	auto[0]	77	1			T4	1		T15	1		T66	1
auto[3087007744:3221225471]	auto[1]	7	1			T102	1		T383	1		T404	1
auto[3221225472:3355443199]	auto[0]	94	1			T47	1		T63	1		T64	1
auto[3221225472:3355443199]	auto[1]	5	1			T288	1		T418	1		T405	1
auto[3355443200:3489660927]	auto[0]	72	1			T15	1		T25	1		T64	1
auto[3355443200:3489660927]	auto[1]	7	1			T100	1		T383	1		T295	1
auto[3489660928:3623878655]	auto[0]	81	1			T25	1		T94	1		T64	2
auto[3489660928:3623878655]	auto[1]	3	1			T99	1		T384	1		T402	1
auto[3623878656:3758096383]	auto[0]	84	1			T35	1		T47	1		T67	2
auto[3623878656:3758096383]	auto[1]	10	1			T79	1		T99	1		T102	1
auto[3758096384:3892314111]	auto[0]	80	1			T25	1		T35	1		T92	1
auto[3758096384:3892314111]	auto[1]	9	1			T328	1		T265	1		T285	1
auto[3892314112:4026531839]	auto[0]	88	1			T4	1		T6	1		T94	1
auto[3892314112:4026531839]	auto[1]	13	1			T100	1		T403	1		T384	1
auto[4026531840:4160749567]	auto[0]	87	1			T6	1		T25	1		T68	1
auto[4026531840:4160749567]	auto[1]	10	1			T247	1		T384	1		T405	1
auto[4160749568:4294967295]	auto[0]	101	1			T25	1		T65	1		T64	3
auto[4160749568:4294967295]	auto[1]	12	1			T96	1		T97	1		T100	1