Unified Coverage Report :: Group Instance : sealing_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1465

1

T4

1

T15

5

T5

2

auto[1]

1688

1

T4

4

T5

2

T6

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T15	2		T72	1		T7	1
auto[134217728:268435455]	117	1			T25	1		T28	1		T7	2
auto[268435456:402653183]	108	1			T6	1		T25	1		T94	1
auto[402653184:536870911]	86	1			T4	1		T25	1		T47	1
auto[536870912:671088639]	96	1			T25	1		T63	1		T92	1
auto[671088640:805306367]	101	1			T25	2		T95	1		T79	1
auto[805306368:939524095]	86	1			T25	1		T65	1		T95	1
auto[939524096:1073741823]	103	1			T25	3		T66	2		T128	2
auto[1073741824:1207959551]	79	1			T63	1		T72	1		T66	2
auto[1207959552:1342177279]	106	1			T25	1		T47	1		T63	1
auto[1342177280:1476395007]	111	1			T33	1		T25	1		T95	1
auto[1476395008:1610612735]	113	1			T15	1		T65	1		T35	1
auto[1610612736:1744830463]	87	1			T6	1		T95	1		T47	1
auto[1744830464:1879048191]	94	1			T15	1		T25	1		T68	1
auto[1879048192:2013265919]	107	1			T25	1		T66	2		T132	1
auto[2013265920:2147483647]	105	1			T25	3		T68	1		T94	1
auto[2147483648:2281701375]	89	1			T25	1		T63	1		T7	1
auto[2281701376:2415919103]	108	1			T15	1		T6	1		T25	1
auto[2415919104:2550136831]	95	1			T25	1		T47	1		T63	1
auto[2550136832:2684354559]	100	1			T63	1		T91	1		T64	1
auto[2684354560:2818572287]	110	1			T25	1		T64	1		T67	2
auto[2818572288:2952790015]	89	1			T4	1		T65	1		T64	2
auto[2952790016:3087007743]	89	1			T68	1		T63	2		T58	1
auto[3087007744:3221225471]	97	1			T5	1		T25	2		T63	1
auto[3221225472:3355443199]	86	1			T5	1		T7	1		T128	1
auto[3355443200:3489660927]	98	1			T4	2		T25	1		T95	2
auto[3489660928:3623878655]	93	1			T6	1		T25	1		T94	2
auto[3623878656:3758096383]	106	1			T35	1		T28	1		T91	1
auto[3758096384:3892314111]	96	1			T4	1		T5	1		T64	1
auto[3892314112:4026531839]	98	1			T47	1		T64	1		T49	1
auto[4026531840:4160749567]	113	1			T95	1		T91	1		T64	1
auto[4160749568:4294967295]	81	1			T5	1		T25	1		T47	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T15	2		T72	1		T52	1
auto[0:134217727]	auto[1]	54	1			T7	1		T66	1		T97	1
auto[134217728:268435455]	auto[0]	57	1			T28	1		T66	1		T119	1
auto[134217728:268435455]	auto[1]	60	1			T25	1		T7	2		T128	1
auto[268435456:402653183]	auto[0]	49	1			T92	1		T58	2		T131	1
auto[268435456:402653183]	auto[1]	59	1			T6	1		T25	1		T94	1
auto[402653184:536870911]	auto[0]	42	1			T63	1		T120	1		T59	1
auto[402653184:536870911]	auto[1]	44	1			T4	1		T25	1		T47	1
auto[536870912:671088639]	auto[0]	44	1			T63	1		T93	1		T66	1
auto[536870912:671088639]	auto[1]	52	1			T25	1		T92	1		T7	2
auto[671088640:805306367]	auto[0]	46	1			T95	1		T91	1		T64	1
auto[671088640:805306367]	auto[1]	55	1			T25	2		T79	1		T64	1
auto[805306368:939524095]	auto[0]	43	1			T95	1		T93	1		T128	1
auto[805306368:939524095]	auto[1]	43	1			T25	1		T65	1		T79	1
auto[939524096:1073741823]	auto[0]	39	1			T66	2		T128	2		T45	1
auto[939524096:1073741823]	auto[1]	64	1			T25	3		T49	1		T58	1
auto[1073741824:1207959551]	auto[0]	33	1			T63	1		T72	1		T66	1
auto[1073741824:1207959551]	auto[1]	46	1			T66	1		T149	1		T49	1
auto[1207959552:1342177279]	auto[0]	48	1			T47	1		T63	1		T48	1
auto[1207959552:1342177279]	auto[1]	58	1			T25	1		T64	1		T93	1
auto[1342177280:1476395007]	auto[0]	51	1			T25	1		T95	1		T7	1
auto[1342177280:1476395007]	auto[1]	60	1			T33	1		T63	1		T7	1
auto[1476395008:1610612735]	auto[0]	56	1			T15	1		T35	1		T64	1
auto[1476395008:1610612735]	auto[1]	57	1			T65	1		T47	1		T91	1
auto[1610612736:1744830463]	auto[0]	39	1			T7	1		T128	1		T96	1
auto[1610612736:1744830463]	auto[1]	48	1			T6	1		T95	1		T47	1
auto[1744830464:1879048191]	auto[0]	52	1			T15	1		T25	1		T68	1
auto[1744830464:1879048191]	auto[1]	42	1			T92	1		T132	1		T227	1
auto[1879048192:2013265919]	auto[0]	51	1			T66	2		T132	1		T135	1
auto[1879048192:2013265919]	auto[1]	56	1			T25	1		T48	1		T135	1
auto[2013265920:2147483647]	auto[0]	46	1			T25	1		T7	1		T49	1
auto[2013265920:2147483647]	auto[1]	59	1			T25	2		T68	1		T94	1
auto[2147483648:2281701375]	auto[0]	44	1			T25	1		T63	1		T7	1
auto[2147483648:2281701375]	auto[1]	45	1			T132	1		T370	1		T180	1
auto[2281701376:2415919103]	auto[0]	55	1			T15	1		T64	2		T236	1
auto[2281701376:2415919103]	auto[1]	53	1			T6	1		T25	1		T146	1
auto[2415919104:2550136831]	auto[0]	46	1			T47	1		T128	1		T48	1
auto[2415919104:2550136831]	auto[1]	49	1			T25	1		T63	1		T99	2
auto[2550136832:2684354559]	auto[0]	46	1			T63	1		T7	1		T66	1
auto[2550136832:2684354559]	auto[1]	54	1			T91	1		T64	1		T66	1
auto[2684354560:2818572287]	auto[0]	55	1			T25	1		T67	2		T128	1
auto[2684354560:2818572287]	auto[1]	55	1			T64	1		T128	1		T58	1
auto[2818572288:2952790015]	auto[0]	45	1			T64	2		T66	2		T84	1
auto[2818572288:2952790015]	auto[1]	44	1			T4	1		T65	1		T84	1
auto[2952790016:3087007743]	auto[0]	48	1			T68	1		T227	1		T176	1
auto[2952790016:3087007743]	auto[1]	41	1			T63	2		T58	1		T388	1
auto[3087007744:3221225471]	auto[0]	46	1			T25	1		T63	1		T64	1
auto[3087007744:3221225471]	auto[1]	51	1			T5	1		T25	1		T7	1
auto[3221225472:3355443199]	auto[0]	40	1			T5	1		T7	1		T128	1
auto[3221225472:3355443199]	auto[1]	46	1			T146	1		T48	1		T58	2
auto[3355443200:3489660927]	auto[0]	38	1			T4	1		T66	1		T86	1
auto[3355443200:3489660927]	auto[1]	60	1			T4	1		T25	1		T95	2
auto[3489660928:3623878655]	auto[0]	42	1			T25	1		T94	2		T64	1
auto[3489660928:3623878655]	auto[1]	51	1			T6	1		T79	1		T64	1
auto[3623878656:3758096383]	auto[0]	45	1			T35	1		T64	1		T92	1
auto[3623878656:3758096383]	auto[1]	61	1			T28	1		T91	1		T64	2
auto[3758096384:3892314111]	auto[0]	44	1			T128	1		T50	1		T48	1
auto[3758096384:3892314111]	auto[1]	52	1			T4	1		T5	1		T64	1
auto[3892314112:4026531839]	auto[0]	43	1			T132	1		T407	1		T120	1
auto[3892314112:4026531839]	auto[1]	55	1			T47	1		T64	1		T49	1
auto[4026531840:4160749567]	auto[0]	44	1			T91	1		T130	1		T131	1
auto[4026531840:4160749567]	auto[1]	69	1			T95	1		T64	1		T7	1
auto[4160749568:4294967295]	auto[0]	36	1			T5	1		T7	1		T236	1
auto[4160749568:4294967295]	auto[1]	45	1			T25	1		T47	1		T67	1