dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1462 1 T4 1 T15 5 T5 2
auto[1] 1690 1 T4 4 T5 2 T6 3


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 90 1 T4 1 T25 1 T47 1
auto[134217728:268435455] 87 1 T15 1 T91 1 T64 2
auto[268435456:402653183] 98 1 T6 1 T25 1 T92 1
auto[402653184:536870911] 79 1 T49 1 T84 1 T134 1
auto[536870912:671088639] 95 1 T25 2 T95 1 T67 3
auto[671088640:805306367] 92 1 T25 3 T47 1 T91 1
auto[805306368:939524095] 95 1 T64 3 T66 1 T84 1
auto[939524096:1073741823] 101 1 T5 1 T25 1 T65 1
auto[1073741824:1207959551] 91 1 T6 1 T25 2 T64 1
auto[1207959552:1342177279] 104 1 T4 1 T25 1 T64 2
auto[1342177280:1476395007] 95 1 T25 1 T95 1 T28 1
auto[1476395008:1610612735] 110 1 T95 1 T47 1 T7 3
auto[1610612736:1744830463] 118 1 T25 3 T63 1 T64 1
auto[1744830464:1879048191] 105 1 T25 1 T47 1 T64 1
auto[1879048192:2013265919] 85 1 T5 1 T64 1 T66 2
auto[2013265920:2147483647] 108 1 T15 1 T5 1 T66 2
auto[2147483648:2281701375] 91 1 T35 1 T95 1 T63 1
auto[2281701376:2415919103] 113 1 T68 1 T35 1 T94 1
auto[2415919104:2550136831] 87 1 T95 1 T91 1 T128 1
auto[2550136832:2684354559] 102 1 T15 1 T6 1 T63 1
auto[2684354560:2818572287] 98 1 T94 1 T47 1 T64 1
auto[2818572288:2952790015] 92 1 T25 1 T94 1 T63 2
auto[2952790016:3087007743] 131 1 T25 2 T63 1 T79 1
auto[3087007744:3221225471] 91 1 T63 1 T64 1 T93 1
auto[3221225472:3355443199] 104 1 T25 2 T66 1 T128 3
auto[3355443200:3489660927] 98 1 T25 1 T65 1 T35 1
auto[3489660928:3623878655] 108 1 T25 1 T95 1 T47 1
auto[3623878656:3758096383] 83 1 T25 1 T68 1 T94 1
auto[3758096384:3892314111] 103 1 T4 1 T25 1 T95 1
auto[3892314112:4026531839] 96 1 T4 1 T5 1 T33 1
auto[4026531840:4160749567] 102 1 T4 1 T15 2 T6 1
auto[4160749568:4294967295] 100 1 T68 1 T65 1 T63 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 43 1 T25 1 T63 1 T128 2
auto[0:134217727] auto[1] 47 1 T4 1 T47 1 T64 1
auto[134217728:268435455] auto[0] 30 1 T15 1 T7 1 T84 2
auto[134217728:268435455] auto[1] 57 1 T91 1 T64 2 T7 1
auto[268435456:402653183] auto[0] 50 1 T66 1 T128 2 T120 1
auto[268435456:402653183] auto[1] 48 1 T6 1 T25 1 T92 1
auto[402653184:536870911] auto[0] 37 1 T49 1 T134 1 T48 1
auto[402653184:536870911] auto[1] 42 1 T84 1 T99 1 T426 1
auto[536870912:671088639] auto[0] 47 1 T25 2 T67 3 T92 1
auto[536870912:671088639] auto[1] 48 1 T95 1 T97 3 T135 1
auto[671088640:805306367] auto[0] 46 1 T25 1 T64 1 T93 1
auto[671088640:805306367] auto[1] 46 1 T25 2 T47 1 T91 1
auto[805306368:939524095] auto[0] 45 1 T64 1 T66 1 T227 1
auto[805306368:939524095] auto[1] 50 1 T64 2 T84 1 T58 1
auto[939524096:1073741823] auto[0] 48 1 T63 1 T85 1 T130 1
auto[939524096:1073741823] auto[1] 53 1 T5 1 T25 1 T65 1
auto[1073741824:1207959551] auto[0] 40 1 T7 1 T128 2 T49 1
auto[1073741824:1207959551] auto[1] 51 1 T6 1 T25 2 T64 1
auto[1207959552:1342177279] auto[0] 48 1 T4 1 T25 1 T64 1
auto[1207959552:1342177279] auto[1] 56 1 T64 1 T128 1 T134 1
auto[1342177280:1476395007] auto[0] 47 1 T28 1 T64 2 T7 3
auto[1342177280:1476395007] auto[1] 48 1 T25 1 T95 1 T52 1
auto[1476395008:1610612735] auto[0] 53 1 T95 1 T7 1 T119 1
auto[1476395008:1610612735] auto[1] 57 1 T47 1 T7 2 T58 1
auto[1610612736:1744830463] auto[0] 46 1 T52 1 T58 2 T227 2
auto[1610612736:1744830463] auto[1] 72 1 T25 3 T63 1 T64 1
auto[1744830464:1879048191] auto[0] 50 1 T64 1 T66 1 T135 1
auto[1744830464:1879048191] auto[1] 55 1 T25 1 T47 1 T7 1
auto[1879048192:2013265919] auto[0] 43 1 T66 1 T146 1 T45 1
auto[1879048192:2013265919] auto[1] 42 1 T5 1 T64 1 T66 1
auto[2013265920:2147483647] auto[0] 51 1 T15 1 T5 1 T66 2
auto[2013265920:2147483647] auto[1] 57 1 T370 1 T251 1 T101 1
auto[2147483648:2281701375] auto[0] 37 1 T35 1 T63 1 T7 1
auto[2147483648:2281701375] auto[1] 54 1 T95 1 T7 1 T128 1
auto[2281701376:2415919103] auto[0] 53 1 T68 1 T64 1 T236 1
auto[2281701376:2415919103] auto[1] 60 1 T35 1 T94 1 T63 1
auto[2415919104:2550136831] auto[0] 35 1 T128 1 T146 1 T49 1
auto[2415919104:2550136831] auto[1] 52 1 T95 1 T91 1 T58 2
auto[2550136832:2684354559] auto[0] 44 1 T15 1 T66 1 T236 1
auto[2550136832:2684354559] auto[1] 58 1 T6 1 T63 1 T7 1
auto[2684354560:2818572287] auto[0] 41 1 T94 1 T64 1 T7 2
auto[2684354560:2818572287] auto[1] 57 1 T47 1 T146 1 T49 1
auto[2818572288:2952790015] auto[0] 46 1 T63 2 T93 1 T128 1
auto[2818572288:2952790015] auto[1] 46 1 T25 1 T94 1 T227 1
auto[2952790016:3087007743] auto[0] 58 1 T25 1 T79 1 T64 1
auto[2952790016:3087007743] auto[1] 73 1 T25 1 T63 1 T92 1
auto[3087007744:3221225471] auto[0] 41 1 T63 1 T86 1 T251 1
auto[3087007744:3221225471] auto[1] 50 1 T64 1 T93 1 T124 1
auto[3221225472:3355443199] auto[0] 55 1 T25 1 T128 2 T52 1
auto[3221225472:3355443199] auto[1] 49 1 T25 1 T66 1 T128 1
auto[3355443200:3489660927] auto[0] 45 1 T35 1 T132 1 T48 1
auto[3355443200:3489660927] auto[1] 53 1 T25 1 T65 1 T64 1
auto[3489660928:3623878655] auto[0] 51 1 T64 1 T72 1 T7 1
auto[3489660928:3623878655] auto[1] 57 1 T25 1 T95 1 T47 1
auto[3623878656:3758096383] auto[0] 37 1 T94 1 T48 1 T407 1
auto[3623878656:3758096383] auto[1] 46 1 T25 1 T68 1 T7 1
auto[3758096384:3892314111] auto[0] 54 1 T95 1 T93 1 T128 1
auto[3758096384:3892314111] auto[1] 49 1 T4 1 T25 1 T28 1
auto[3892314112:4026531839] auto[0] 43 1 T5 1 T91 1 T49 2
auto[3892314112:4026531839] auto[1] 53 1 T4 1 T33 1 T25 1
auto[4026531840:4160749567] auto[0] 52 1 T15 2 T6 1 T47 1
auto[4026531840:4160749567] auto[1] 50 1 T4 1 T66 2 T227 1
auto[4160749568:4294967295] auto[0] 46 1 T68 1 T93 1 T66 1
auto[4160749568:4294967295] auto[1] 54 1 T65 1 T63 2 T66 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%