Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4228

1

T4

8

T15

4

T5

6

auto[1]

2076

1

T4

2

T15

6

T5

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	214	1			T95	2		T63	2		T66	4
auto[134217728:268435455]	202	1			T64	2		T67	2		T92	2
auto[268435456:402653183]	164	1			T64	2		T92	2		T7	2
auto[402653184:536870911]	226	1			T6	2		T94	2		T63	2
auto[536870912:671088639]	168	1			T64	2		T66	4		T128	2
auto[671088640:805306367]	198	1			T94	2		T91	2		T66	4
auto[805306368:939524095]	208	1			T15	2		T5	2		T63	2
auto[939524096:1073741823]	202	1			T25	2		T91	2		T7	2
auto[1073741824:1207959551]	204	1			T6	2		T25	2		T28	2
auto[1207959552:1342177279]	184	1			T65	4		T63	6		T7	2
auto[1342177280:1476395007]	162	1			T4	2		T25	2		T407	2
auto[1476395008:1610612735]	186	1			T25	4		T47	2		T64	2
auto[1610612736:1744830463]	206	1			T25	2		T95	2		T64	2
auto[1744830464:1879048191]	172	1			T4	2		T15	2		T33	2
auto[1879048192:2013265919]	194	1			T95	4		T79	2		T64	2
auto[2013265920:2147483647]	196	1			T6	2		T25	4		T68	2
auto[2147483648:2281701375]	200	1			T5	2		T6	2		T25	2
auto[2281701376:2415919103]	196	1			T15	2		T25	4		T128	2
auto[2415919104:2550136831]	222	1			T47	2		T64	6		T7	4
auto[2550136832:2684354559]	220	1			T5	2		T25	2		T47	2
auto[2684354560:2818572287]	188	1			T4	2		T28	2		T63	2
auto[2818572288:2952790015]	180	1			T25	6		T35	2		T91	2
auto[2952790016:3087007743]	182	1			T5	2		T25	4		T47	2
auto[3087007744:3221225471]	230	1			T4	2		T15	2		T72	2
auto[3221225472:3355443199]	194	1			T92	2		T7	2		T146	2
auto[3355443200:3489660927]	196	1			T4	2		T25	2		T63	2
auto[3489660928:3623878655]	220	1			T25	2		T65	2		T35	4
auto[3623878656:3758096383]	216	1			T68	2		T63	4		T64	2
auto[3758096384:3892314111]	182	1			T94	2		T95	2		T47	2
auto[3892314112:4026531839]	192	1			T15	2		T25	2		T66	4
auto[4026531840:4160749567]	194	1			T25	8		T95	2		T64	6
auto[4160749568:4294967295]	206	1			T25	4		T68	2		T95	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	142	1			T95	2		T66	4		T128	6
auto[0:134217727]	auto[1]	72	1			T63	2		T131	2		T87	4
auto[134217728:268435455]	auto[0]	132	1			T64	2		T67	2		T92	2
auto[134217728:268435455]	auto[1]	70	1			T66	2		T132	2		T45	2
auto[268435456:402653183]	auto[0]	92	1			T7	2		T236	2		T128	2
auto[268435456:402653183]	auto[1]	72	1			T64	2		T92	2		T66	2
auto[402653184:536870911]	auto[0]	146	1			T6	2		T94	2		T63	2
auto[402653184:536870911]	auto[1]	80	1			T7	2		T58	4		T85	4
auto[536870912:671088639]	auto[0]	122	1			T66	2		T49	4		T50	2
auto[536870912:671088639]	auto[1]	46	1			T64	2		T66	2		T128	2
auto[671088640:805306367]	auto[0]	126	1			T94	2		T91	2		T66	2
auto[671088640:805306367]	auto[1]	72	1			T66	2		T100	4		T129	2
auto[805306368:939524095]	auto[0]	152	1			T5	2		T63	2		T64	2
auto[805306368:939524095]	auto[1]	56	1			T15	2		T91	2		T128	2
auto[939524096:1073741823]	auto[0]	130	1			T25	2		T93	2		T128	2
auto[939524096:1073741823]	auto[1]	72	1			T91	2		T7	2		T124	2
auto[1073741824:1207959551]	auto[0]	142	1			T6	2		T25	2		T28	2
auto[1073741824:1207959551]	auto[1]	62	1			T128	4		T370	2		T175	2
auto[1207959552:1342177279]	auto[0]	126	1			T65	4		T63	4		T66	2
auto[1207959552:1342177279]	auto[1]	58	1			T63	2		T7	2		T66	2
auto[1342177280:1476395007]	auto[0]	110	1			T4	2		T25	2		T227	2
auto[1342177280:1476395007]	auto[1]	52	1			T407	2		T59	2		T286	2
auto[1476395008:1610612735]	auto[0]	126	1			T25	2		T47	2		T64	2
auto[1476395008:1610612735]	auto[1]	60	1			T25	2		T66	2		T137	4
auto[1610612736:1744830463]	auto[0]	130	1			T48	2		T227	4		T412	2
auto[1610612736:1744830463]	auto[1]	76	1			T25	2		T95	2		T64	2
auto[1744830464:1879048191]	auto[0]	114	1			T15	2		T7	2		T128	2
auto[1744830464:1879048191]	auto[1]	58	1			T4	2		T33	2		T93	2
auto[1879048192:2013265919]	auto[0]	114	1			T95	4		T79	2		T64	2
auto[1879048192:2013265919]	auto[1]	80	1			T149	2		T49	2		T50	2
auto[2013265920:2147483647]	auto[0]	136	1			T6	2		T25	4		T68	2
auto[2013265920:2147483647]	auto[1]	60	1			T64	2		T58	2		T125	2
auto[2147483648:2281701375]	auto[0]	136	1			T5	2		T6	2		T25	2
auto[2147483648:2281701375]	auto[1]	64	1			T91	2		T7	2		T128	2
auto[2281701376:2415919103]	auto[0]	132	1			T25	4		T128	2		T52	2
auto[2281701376:2415919103]	auto[1]	64	1			T15	2		T96	2		T227	2
auto[2415919104:2550136831]	auto[0]	160	1			T47	2		T64	2		T7	2
auto[2415919104:2550136831]	auto[1]	62	1			T64	4		T7	2		T93	2
auto[2550136832:2684354559]	auto[0]	146	1			T5	2		T25	2		T63	2
auto[2550136832:2684354559]	auto[1]	74	1			T47	2		T79	2		T64	2
auto[2684354560:2818572287]	auto[0]	130	1			T4	2		T28	2		T128	2
auto[2684354560:2818572287]	auto[1]	58	1			T63	2		T26	2		T88	2
auto[2818572288:2952790015]	auto[0]	116	1			T25	4		T35	2		T92	2
auto[2818572288:2952790015]	auto[1]	64	1			T25	2		T91	2		T64	2
auto[2952790016:3087007743]	auto[0]	130	1			T25	4		T64	2		T128	4
auto[2952790016:3087007743]	auto[1]	52	1			T5	2		T47	2		T97	2
auto[3087007744:3221225471]	auto[0]	156	1			T4	2		T7	2		T128	4
auto[3087007744:3221225471]	auto[1]	74	1			T15	2		T72	2		T132	2
auto[3221225472:3355443199]	auto[0]	142	1			T92	2		T7	2		T52	2
auto[3221225472:3355443199]	auto[1]	52	1			T146	2		T97	2		T227	2
auto[3355443200:3489660927]	auto[0]	124	1			T4	2		T63	2		T7	2
auto[3355443200:3489660927]	auto[1]	72	1			T25	2		T64	2		T7	2
auto[3489660928:3623878655]	auto[0]	156	1			T25	2		T65	2		T35	2
auto[3489660928:3623878655]	auto[1]	64	1			T35	2		T67	2		T58	2
auto[3623878656:3758096383]	auto[0]	146	1			T68	2		T63	2		T64	2
auto[3623878656:3758096383]	auto[1]	70	1			T63	2		T58	2		T387	2
auto[3758096384:3892314111]	auto[0]	118	1			T94	2		T95	2		T47	2
auto[3758096384:3892314111]	auto[1]	64	1			T63	2		T79	2		T58	2
auto[3892314112:4026531839]	auto[0]	132	1			T15	2		T25	2		T66	4
auto[3892314112:4026531839]	auto[1]	60	1			T84	2		T59	2		T131	2
auto[4026531840:4160749567]	auto[0]	122	1			T25	2		T64	2		T7	4
auto[4026531840:4160749567]	auto[1]	72	1			T25	6		T95	2		T64	4
auto[4160749568:4294967295]	auto[0]	142	1			T68	2		T64	2		T72	2
auto[4160749568:4294967295]	auto[1]	64	1			T25	4		T95	2		T93	2