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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.77 99.04 98.07 98.37 100.00 99.02 98.63 91.27


Total test records in report: 1079
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T1008 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.97681779 Aug 18 05:48:29 PM PDT 24 Aug 18 05:48:30 PM PDT 24 41712757 ps
T1009 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2021322237 Aug 18 05:48:06 PM PDT 24 Aug 18 05:48:11 PM PDT 24 845666669 ps
T1010 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3804128395 Aug 18 05:48:35 PM PDT 24 Aug 18 05:48:36 PM PDT 24 8237253 ps
T1011 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2979237775 Aug 18 05:48:12 PM PDT 24 Aug 18 05:48:13 PM PDT 24 26695079 ps
T1012 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3249317705 Aug 18 05:48:15 PM PDT 24 Aug 18 05:48:19 PM PDT 24 131172110 ps
T1013 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.72171183 Aug 18 05:48:24 PM PDT 24 Aug 18 05:48:26 PM PDT 24 122425227 ps
T1014 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3056713113 Aug 18 05:48:26 PM PDT 24 Aug 18 05:48:27 PM PDT 24 10429244 ps
T1015 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.410160658 Aug 18 05:48:31 PM PDT 24 Aug 18 05:48:32 PM PDT 24 14192592 ps
T1016 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2004732375 Aug 18 05:48:11 PM PDT 24 Aug 18 05:48:15 PM PDT 24 210627176 ps
T1017 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1227029753 Aug 18 05:48:13 PM PDT 24 Aug 18 05:48:14 PM PDT 24 90972090 ps
T1018 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.715733055 Aug 18 05:48:25 PM PDT 24 Aug 18 05:48:28 PM PDT 24 102937625 ps
T152 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2790189436 Aug 18 05:48:16 PM PDT 24 Aug 18 05:48:20 PM PDT 24 524854830 ps
T1019 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.4058716247 Aug 18 05:48:31 PM PDT 24 Aug 18 05:48:32 PM PDT 24 45279477 ps
T1020 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2550920777 Aug 18 05:48:08 PM PDT 24 Aug 18 05:48:18 PM PDT 24 1493968142 ps
T1021 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1145786782 Aug 18 05:48:23 PM PDT 24 Aug 18 05:48:24 PM PDT 24 34895791 ps
T1022 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.452288585 Aug 18 05:48:06 PM PDT 24 Aug 18 05:48:09 PM PDT 24 271966088 ps
T1023 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.360575615 Aug 18 05:48:27 PM PDT 24 Aug 18 05:48:28 PM PDT 24 8185832 ps
T1024 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3002784175 Aug 18 05:48:07 PM PDT 24 Aug 18 05:48:08 PM PDT 24 77266010 ps
T153 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.287153513 Aug 18 05:48:09 PM PDT 24 Aug 18 05:48:13 PM PDT 24 211632432 ps
T1025 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2427644067 Aug 18 05:48:16 PM PDT 24 Aug 18 05:48:19 PM PDT 24 232616710 ps
T1026 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.251146664 Aug 18 05:48:09 PM PDT 24 Aug 18 05:48:11 PM PDT 24 194414625 ps
T1027 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2158784906 Aug 18 05:48:09 PM PDT 24 Aug 18 05:48:24 PM PDT 24 809000877 ps
T1028 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2358281217 Aug 18 05:48:17 PM PDT 24 Aug 18 05:48:20 PM PDT 24 339987679 ps
T1029 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1692024151 Aug 18 05:48:06 PM PDT 24 Aug 18 05:48:09 PM PDT 24 92503487 ps
T1030 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1592757200 Aug 18 05:48:15 PM PDT 24 Aug 18 05:48:18 PM PDT 24 318350552 ps
T1031 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1571280314 Aug 18 05:48:08 PM PDT 24 Aug 18 05:48:17 PM PDT 24 1599536284 ps
T1032 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.759883331 Aug 18 05:48:22 PM PDT 24 Aug 18 05:48:26 PM PDT 24 308713226 ps
T161 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.4287522695 Aug 18 05:48:20 PM PDT 24 Aug 18 05:48:31 PM PDT 24 538571533 ps
T1033 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3093812049 Aug 18 05:48:11 PM PDT 24 Aug 18 05:48:14 PM PDT 24 140896338 ps
T1034 /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3238277317 Aug 18 05:48:07 PM PDT 24 Aug 18 05:48:22 PM PDT 24 431111410 ps
T1035 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1581503264 Aug 18 05:48:35 PM PDT 24 Aug 18 05:48:36 PM PDT 24 89452486 ps
T1036 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1744934515 Aug 18 05:48:21 PM PDT 24 Aug 18 05:48:22 PM PDT 24 48458874 ps
T1037 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3019812436 Aug 18 05:48:14 PM PDT 24 Aug 18 05:48:17 PM PDT 24 107511887 ps
T1038 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3524931082 Aug 18 05:48:09 PM PDT 24 Aug 18 05:48:10 PM PDT 24 40653059 ps
T1039 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1486480751 Aug 18 05:48:18 PM PDT 24 Aug 18 05:48:20 PM PDT 24 41903484 ps
T1040 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3950374125 Aug 18 05:48:22 PM PDT 24 Aug 18 05:48:24 PM PDT 24 35801119 ps
T1041 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.49296952 Aug 18 05:48:05 PM PDT 24 Aug 18 05:48:13 PM PDT 24 142753155 ps
T1042 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1636266403 Aug 18 05:48:14 PM PDT 24 Aug 18 05:48:15 PM PDT 24 11330220 ps
T1043 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1621933634 Aug 18 05:48:27 PM PDT 24 Aug 18 05:48:28 PM PDT 24 18429108 ps
T1044 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2146709483 Aug 18 05:48:19 PM PDT 24 Aug 18 05:48:21 PM PDT 24 12265009 ps
T162 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.4149426965 Aug 18 05:48:13 PM PDT 24 Aug 18 05:48:18 PM PDT 24 350163504 ps
T1045 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.423673371 Aug 18 05:48:05 PM PDT 24 Aug 18 05:48:16 PM PDT 24 1383419686 ps
T1046 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2482126719 Aug 18 05:48:09 PM PDT 24 Aug 18 05:48:11 PM PDT 24 285052551 ps
T1047 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1321785297 Aug 18 05:48:13 PM PDT 24 Aug 18 05:48:14 PM PDT 24 9070253 ps
T1048 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.566213088 Aug 18 05:48:19 PM PDT 24 Aug 18 05:48:21 PM PDT 24 163510708 ps
T1049 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1439854771 Aug 18 05:48:21 PM PDT 24 Aug 18 05:48:28 PM PDT 24 329890011 ps
T1050 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.742405830 Aug 18 05:48:09 PM PDT 24 Aug 18 05:48:11 PM PDT 24 32991097 ps
T1051 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2090958553 Aug 18 05:48:24 PM PDT 24 Aug 18 05:48:25 PM PDT 24 12964704 ps
T1052 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.910407792 Aug 18 05:48:23 PM PDT 24 Aug 18 05:48:25 PM PDT 24 99040810 ps
T1053 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.474558522 Aug 18 05:48:19 PM PDT 24 Aug 18 05:48:21 PM PDT 24 858828740 ps
T1054 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2377595114 Aug 18 05:48:30 PM PDT 24 Aug 18 05:48:31 PM PDT 24 15048615 ps
T1055 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2524711967 Aug 18 05:48:13 PM PDT 24 Aug 18 05:48:14 PM PDT 24 22915425 ps
T1056 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2249154769 Aug 18 05:48:14 PM PDT 24 Aug 18 05:48:16 PM PDT 24 49223438 ps
T1057 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2310706977 Aug 18 05:48:21 PM PDT 24 Aug 18 05:48:35 PM PDT 24 391794477 ps
T1058 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2267451756 Aug 18 05:48:30 PM PDT 24 Aug 18 05:48:31 PM PDT 24 27783829 ps
T1059 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.269681556 Aug 18 05:48:08 PM PDT 24 Aug 18 05:48:10 PM PDT 24 45422232 ps
T1060 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1021948489 Aug 18 05:48:19 PM PDT 24 Aug 18 05:48:23 PM PDT 24 767885665 ps
T1061 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3434554893 Aug 18 05:48:14 PM PDT 24 Aug 18 05:48:16 PM PDT 24 21872620 ps
T1062 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2966590819 Aug 18 05:48:05 PM PDT 24 Aug 18 05:48:05 PM PDT 24 10360011 ps
T1063 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3585711457 Aug 18 05:48:22 PM PDT 24 Aug 18 05:48:26 PM PDT 24 237374033 ps
T1064 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1809233492 Aug 18 05:48:21 PM PDT 24 Aug 18 05:48:27 PM PDT 24 228796361 ps
T1065 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.53256943 Aug 18 05:48:08 PM PDT 24 Aug 18 05:48:09 PM PDT 24 65033252 ps
T1066 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1178229361 Aug 18 05:48:16 PM PDT 24 Aug 18 05:48:17 PM PDT 24 22845080 ps
T1067 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2351090529 Aug 18 05:48:19 PM PDT 24 Aug 18 05:48:20 PM PDT 24 71663139 ps
T1068 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4266768753 Aug 18 05:48:29 PM PDT 24 Aug 18 05:48:30 PM PDT 24 68151842 ps
T1069 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.188629629 Aug 18 05:48:08 PM PDT 24 Aug 18 05:48:23 PM PDT 24 1703678279 ps
T1070 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2769750794 Aug 18 05:48:16 PM PDT 24 Aug 18 05:48:21 PM PDT 24 236051851 ps
T159 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2863937717 Aug 18 05:48:20 PM PDT 24 Aug 18 05:48:23 PM PDT 24 200864348 ps
T164 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2047130498 Aug 18 05:48:23 PM PDT 24 Aug 18 05:48:30 PM PDT 24 1068923631 ps
T1071 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2352192167 Aug 18 05:48:19 PM PDT 24 Aug 18 05:48:22 PM PDT 24 223833886 ps
T1072 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1810607727 Aug 18 05:47:53 PM PDT 24 Aug 18 05:47:57 PM PDT 24 286237440 ps
T1073 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.213080274 Aug 18 05:48:07 PM PDT 24 Aug 18 05:48:10 PM PDT 24 119868668 ps
T1074 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4154981864 Aug 18 05:48:37 PM PDT 24 Aug 18 05:48:38 PM PDT 24 17301301 ps
T1075 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2103983307 Aug 18 05:48:19 PM PDT 24 Aug 18 05:48:20 PM PDT 24 48987394 ps
T1076 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1986508369 Aug 18 05:48:30 PM PDT 24 Aug 18 05:48:31 PM PDT 24 34645110 ps
T169 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.68763044 Aug 18 05:48:22 PM PDT 24 Aug 18 05:48:25 PM PDT 24 222004695 ps
T1077 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.179712187 Aug 18 05:48:21 PM PDT 24 Aug 18 05:48:22 PM PDT 24 87172126 ps
T1078 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2567990829 Aug 18 05:48:07 PM PDT 24 Aug 18 05:48:08 PM PDT 24 12161916 ps
T1079 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2104281645 Aug 18 05:48:21 PM PDT 24 Aug 18 05:48:23 PM PDT 24 78038123 ps

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3638903233
Short name T6
Test name
Test status
Simulation time 464217586 ps
CPU time 6.84 seconds
Started Aug 18 06:15:56 PM PDT 24
Finished Aug 18 06:16:03 PM PDT 24
Peak memory 210352 kb
Host smart-fe6ed5c0-04ec-43aa-b4a2-ebe65c60140a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638903233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3638903233
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1966275980
Short name T25
Test name
Test status
Simulation time 1077237769 ps
CPU time 29.36 seconds
Started Aug 18 06:13:45 PM PDT 24
Finished Aug 18 06:14:14 PM PDT 24
Peak memory 221688 kb
Host smart-d4ce9cb8-8059-47f5-9296-cb9c9923ad2c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966275980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1966275980
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3249978178
Short name T7
Test name
Test status
Simulation time 1792400512 ps
CPU time 21.94 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:14:10 PM PDT 24
Peak memory 223068 kb
Host smart-af59f6ab-12ca-40e0-8958-5b11d0042dc0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249978178 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3249978178
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1513068801
Short name T128
Test name
Test status
Simulation time 4267793883 ps
CPU time 37.61 seconds
Started Aug 18 06:13:39 PM PDT 24
Finished Aug 18 06:14:17 PM PDT 24
Peak memory 216224 kb
Host smart-574e9dca-0bce-49c6-a497-09940c4c39e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513068801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1513068801
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1227910826
Short name T12
Test name
Test status
Simulation time 2534372991 ps
CPU time 12.83 seconds
Started Aug 18 06:13:35 PM PDT 24
Finished Aug 18 06:13:48 PM PDT 24
Peak memory 232132 kb
Host smart-a325beac-ba41-4373-8fc5-9acef8bdf98a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227910826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1227910826
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3437883626
Short name T86
Test name
Test status
Simulation time 2556089161 ps
CPU time 17.28 seconds
Started Aug 18 06:14:26 PM PDT 24
Finished Aug 18 06:14:43 PM PDT 24
Peak memory 223204 kb
Host smart-f4994828-8077-41fa-b7cc-2d364e1c2124
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437883626 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3437883626
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.303873112
Short name T66
Test name
Test status
Simulation time 3540180404 ps
CPU time 30.49 seconds
Started Aug 18 06:15:48 PM PDT 24
Finished Aug 18 06:16:19 PM PDT 24
Peak memory 216136 kb
Host smart-c3bbb004-fd81-42ca-84d1-5d3e52e0a4e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303873112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.303873112
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3209877194
Short name T47
Test name
Test status
Simulation time 252557472 ps
CPU time 3.51 seconds
Started Aug 18 06:15:15 PM PDT 24
Finished Aug 18 06:15:19 PM PDT 24
Peak memory 222552 kb
Host smart-c9677fa0-cfd1-4f22-9c96-7f6e80b42b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209877194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3209877194
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1070188219
Short name T10
Test name
Test status
Simulation time 54279379 ps
CPU time 2.5 seconds
Started Aug 18 06:14:26 PM PDT 24
Finished Aug 18 06:14:29 PM PDT 24
Peak memory 215100 kb
Host smart-aae926f5-79d6-4949-923c-6f59d983dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070188219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1070188219
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.3370347111
Short name T404
Test name
Test status
Simulation time 241256820 ps
CPU time 13.26 seconds
Started Aug 18 06:14:13 PM PDT 24
Finished Aug 18 06:14:26 PM PDT 24
Peak memory 216228 kb
Host smart-0b95aab9-8138-47ea-843e-a0ebd4c72ff7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3370347111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.3370347111
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1504438566
Short name T75
Test name
Test status
Simulation time 359393380 ps
CPU time 8.41 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:25 PM PDT 24
Peak memory 214832 kb
Host smart-39f5957d-b3c1-48cb-8f8a-f4f20139958e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504438566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1504438566
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3188553398
Short name T131
Test name
Test status
Simulation time 6021814448 ps
CPU time 79.75 seconds
Started Aug 18 06:15:32 PM PDT 24
Finished Aug 18 06:16:52 PM PDT 24
Peak memory 222980 kb
Host smart-86136470-1231-40f1-ab30-e0506ad31c6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188553398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3188553398
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2328899898
Short name T99
Test name
Test status
Simulation time 252454151 ps
CPU time 11.32 seconds
Started Aug 18 06:14:42 PM PDT 24
Finished Aug 18 06:14:53 PM PDT 24
Peak memory 216072 kb
Host smart-1f494746-b420-4e42-ac79-96a7a3c9b005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2328899898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2328899898
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.3262678606
Short name T64
Test name
Test status
Simulation time 1236599965 ps
CPU time 20.97 seconds
Started Aug 18 06:13:29 PM PDT 24
Finished Aug 18 06:13:55 PM PDT 24
Peak memory 223064 kb
Host smart-6d8f5f75-2b02-4c3d-862a-afec610ca7e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262678606 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.3262678606
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2710703906
Short name T401
Test name
Test status
Simulation time 4226413867 ps
CPU time 54.69 seconds
Started Aug 18 06:13:39 PM PDT 24
Finished Aug 18 06:14:34 PM PDT 24
Peak memory 215412 kb
Host smart-52ddd953-8ba6-4c69-b0fa-60c3d49f1e99
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2710703906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2710703906
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.902691715
Short name T55
Test name
Test status
Simulation time 337160951 ps
CPU time 5.04 seconds
Started Aug 18 06:13:55 PM PDT 24
Finished Aug 18 06:14:00 PM PDT 24
Peak memory 221136 kb
Host smart-7eddb344-9c6b-4e0e-89c1-72ae1aee4097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902691715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.902691715
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2466203270
Short name T122
Test name
Test status
Simulation time 1148249417 ps
CPU time 41.35 seconds
Started Aug 18 06:14:08 PM PDT 24
Finished Aug 18 06:14:49 PM PDT 24
Peak memory 216360 kb
Host smart-2e44a651-e755-452f-a8c8-39af18141e2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466203270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2466203270
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.930175382
Short name T385
Test name
Test status
Simulation time 301662185 ps
CPU time 9.81 seconds
Started Aug 18 06:13:56 PM PDT 24
Finished Aug 18 06:14:06 PM PDT 24
Peak memory 215096 kb
Host smart-323429b5-0c9b-40fd-9315-ed40f58a7d4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=930175382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.930175382
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.933411094
Short name T151
Test name
Test status
Simulation time 496397234 ps
CPU time 6.53 seconds
Started Aug 18 05:47:53 PM PDT 24
Finished Aug 18 05:48:00 PM PDT 24
Peak memory 214468 kb
Host smart-a04c47d3-19b6-4326-aba1-165ca06d7131
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933411094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
933411094
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3439002652
Short name T20
Test name
Test status
Simulation time 48761337 ps
CPU time 2.35 seconds
Started Aug 18 06:15:08 PM PDT 24
Finished Aug 18 06:15:11 PM PDT 24
Peak memory 223164 kb
Host smart-41c2dafe-f90d-4777-abea-9dcdeb1fe38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439002652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3439002652
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.159065512
Short name T87
Test name
Test status
Simulation time 553570259 ps
CPU time 17.16 seconds
Started Aug 18 06:13:50 PM PDT 24
Finished Aug 18 06:14:07 PM PDT 24
Peak memory 221228 kb
Host smart-70952a5d-5ecb-46af-b28e-227c0ae44fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159065512 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.159065512
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3586658283
Short name T59
Test name
Test status
Simulation time 104345047 ps
CPU time 5.23 seconds
Started Aug 18 06:15:15 PM PDT 24
Finished Aug 18 06:15:21 PM PDT 24
Peak memory 220420 kb
Host smart-c0f3099e-eafa-44f6-a0c1-dc075e4e080b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586658283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3586658283
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3332932529
Short name T409
Test name
Test status
Simulation time 377241526 ps
CPU time 5.92 seconds
Started Aug 18 06:14:16 PM PDT 24
Finished Aug 18 06:14:23 PM PDT 24
Peak memory 214748 kb
Host smart-0eeaba85-9014-4314-97dc-c81a9d55e39f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3332932529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3332932529
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.113962499
Short name T38
Test name
Test status
Simulation time 161240529 ps
CPU time 4.63 seconds
Started Aug 18 06:14:39 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 208896 kb
Host smart-bce5f927-f157-4e4b-9acb-e67961162f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113962499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.113962499
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.932883483
Short name T67
Test name
Test status
Simulation time 263530841 ps
CPU time 3.06 seconds
Started Aug 18 06:15:45 PM PDT 24
Finished Aug 18 06:15:48 PM PDT 24
Peak memory 223044 kb
Host smart-b75b70b2-6274-454f-bc4c-a2951fc1fdac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932883483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.932883483
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3801554434
Short name T227
Test name
Test status
Simulation time 994808382 ps
CPU time 13.59 seconds
Started Aug 18 06:14:54 PM PDT 24
Finished Aug 18 06:15:08 PM PDT 24
Peak memory 215348 kb
Host smart-344294d3-daa1-4700-82d2-88c0e45cf2ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801554434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3801554434
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.236736375
Short name T384
Test name
Test status
Simulation time 78654806 ps
CPU time 4.66 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:43 PM PDT 24
Peak memory 214776 kb
Host smart-e76e9fd4-8d76-41b9-8652-14a85e6f8a56
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=236736375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.236736375
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1634671649
Short name T28
Test name
Test status
Simulation time 105251943 ps
CPU time 3.64 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 208424 kb
Host smart-edb71a69-e2b5-4a15-813c-3a63995420a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634671649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1634671649
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.830176017
Short name T88
Test name
Test status
Simulation time 870032743 ps
CPU time 12.93 seconds
Started Aug 18 06:13:50 PM PDT 24
Finished Aug 18 06:14:03 PM PDT 24
Peak memory 223076 kb
Host smart-435b7fb5-1524-4ca9-ab93-b796d6f7fe24
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830176017 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.830176017
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1532588322
Short name T97
Test name
Test status
Simulation time 703966452 ps
CPU time 9.17 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:56 PM PDT 24
Peak memory 215956 kb
Host smart-f31f9739-6c4a-419e-89a3-7e7b99bb06eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1532588322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1532588322
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3419192272
Short name T297
Test name
Test status
Simulation time 1717670493 ps
CPU time 8.23 seconds
Started Aug 18 06:15:26 PM PDT 24
Finished Aug 18 06:15:34 PM PDT 24
Peak memory 216252 kb
Host smart-0ab51c30-c588-4b4c-8e5b-fe9f2d552feb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3419192272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3419192272
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3115694502
Short name T42
Test name
Test status
Simulation time 255473672 ps
CPU time 2.77 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 210280 kb
Host smart-e8a3910e-be12-4cf1-8bcb-2a71c7711d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3115694502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3115694502
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3162630218
Short name T69
Test name
Test status
Simulation time 830966511 ps
CPU time 18.76 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:14:10 PM PDT 24
Peak memory 221144 kb
Host smart-7f9c945c-123d-4358-9e90-2a434cff9ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162630218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3162630218
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2401680407
Short name T248
Test name
Test status
Simulation time 2971127599 ps
CPU time 42.84 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:15:23 PM PDT 24
Peak memory 223044 kb
Host smart-e2bf39b0-ac59-49db-8ae8-9876b75f2c40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401680407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2401680407
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.2197150985
Short name T432
Test name
Test status
Simulation time 43689761 ps
CPU time 0.75 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:47 PM PDT 24
Peak memory 206444 kb
Host smart-fb582875-6a61-4c2a-9fb1-141a76e7f531
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197150985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.2197150985
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.287153513
Short name T153
Test name
Test status
Simulation time 211632432 ps
CPU time 4.15 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:13 PM PDT 24
Peak memory 214400 kb
Host smart-a4dd1518-6b07-46b6-8321-d0f1c43a09b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287153513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
287153513
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2072421563
Short name T100
Test name
Test status
Simulation time 233234683 ps
CPU time 6.56 seconds
Started Aug 18 06:15:02 PM PDT 24
Finished Aug 18 06:15:09 PM PDT 24
Peak memory 216108 kb
Host smart-87a57c37-7dd4-4f86-be38-ce4e9f18ac0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2072421563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2072421563
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2951998551
Short name T184
Test name
Test status
Simulation time 4679560870 ps
CPU time 32.52 seconds
Started Aug 18 06:14:30 PM PDT 24
Finished Aug 18 06:15:03 PM PDT 24
Peak memory 216812 kb
Host smart-1089c6f4-0067-40b0-b2ce-8b84b17097f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951998551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2951998551
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3067410720
Short name T125
Test name
Test status
Simulation time 435940200 ps
CPU time 6.09 seconds
Started Aug 18 06:14:32 PM PDT 24
Finished Aug 18 06:14:38 PM PDT 24
Peak memory 221172 kb
Host smart-cbbd0efc-a928-4474-a537-90c6594ab281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067410720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3067410720
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2256475297
Short name T80
Test name
Test status
Simulation time 109771095 ps
CPU time 3.99 seconds
Started Aug 18 05:48:07 PM PDT 24
Finished Aug 18 05:48:11 PM PDT 24
Peak memory 214836 kb
Host smart-9569c934-f4c5-4238-a58d-848c8611b935
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256475297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2256475297
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.514974683
Short name T157
Test name
Test status
Simulation time 2124002834 ps
CPU time 6.26 seconds
Started Aug 18 05:48:29 PM PDT 24
Finished Aug 18 05:48:35 PM PDT 24
Peak memory 215732 kb
Host smart-b0e3897a-f208-4413-a10a-51c7c5cf914a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514974683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.514974683
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1334050658
Short name T288
Test name
Test status
Simulation time 8033741246 ps
CPU time 86.23 seconds
Started Aug 18 06:13:53 PM PDT 24
Finished Aug 18 06:15:19 PM PDT 24
Peak memory 216420 kb
Host smart-6b98bb0d-45bb-4ed7-9a28-c03ae98bebc0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1334050658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1334050658
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3892010026
Short name T24
Test name
Test status
Simulation time 95116212 ps
CPU time 4.5 seconds
Started Aug 18 06:15:04 PM PDT 24
Finished Aug 18 06:15:09 PM PDT 24
Peak memory 214804 kb
Host smart-79ad6f26-5f95-4cf1-bbc1-c5ea2079b7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892010026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3892010026
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2302341110
Short name T191
Test name
Test status
Simulation time 6686212968 ps
CPU time 51.17 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:15:41 PM PDT 24
Peak memory 216224 kb
Host smart-c64d8960-5bf2-4ad7-84d3-e25233795bec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302341110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2302341110
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.655232568
Short name T45
Test name
Test status
Simulation time 31651840 ps
CPU time 1.9 seconds
Started Aug 18 06:14:35 PM PDT 24
Finished Aug 18 06:14:37 PM PDT 24
Peak memory 214680 kb
Host smart-71524425-de1c-49c7-9a0b-636a825e5a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655232568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.655232568
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1973952316
Short name T1
Test name
Test status
Simulation time 1498559058 ps
CPU time 22.56 seconds
Started Aug 18 06:14:33 PM PDT 24
Finished Aug 18 06:14:56 PM PDT 24
Peak memory 209548 kb
Host smart-2e589a78-cf8f-4067-b604-b66812264c40
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973952316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1973952316
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2254777917
Short name T92
Test name
Test status
Simulation time 86710013 ps
CPU time 2.32 seconds
Started Aug 18 06:14:01 PM PDT 24
Finished Aug 18 06:14:04 PM PDT 24
Peak memory 214688 kb
Host smart-991be753-effd-467b-9f53-cc3cc13b6581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254777917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2254777917
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1312190296
Short name T116
Test name
Test status
Simulation time 165483837 ps
CPU time 4 seconds
Started Aug 18 06:15:18 PM PDT 24
Finished Aug 18 06:15:22 PM PDT 24
Peak memory 218104 kb
Host smart-27440ec1-782d-4c98-8bb0-38d9bb3c7fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312190296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1312190296
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.4059220815
Short name T117
Test name
Test status
Simulation time 593456182 ps
CPU time 3.96 seconds
Started Aug 18 06:13:35 PM PDT 24
Finished Aug 18 06:13:39 PM PDT 24
Peak memory 218584 kb
Host smart-677ad5e4-5f60-4474-a6ae-9e0bce8f838d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059220815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.4059220815
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.723083138
Short name T359
Test name
Test status
Simulation time 3389677616 ps
CPU time 109.9 seconds
Started Aug 18 06:13:45 PM PDT 24
Finished Aug 18 06:15:35 PM PDT 24
Peak memory 216192 kb
Host smart-8d7581a5-fbef-4fcb-a837-b52217f39e95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723083138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.723083138
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.92644906
Short name T221
Test name
Test status
Simulation time 1606349911 ps
CPU time 39.98 seconds
Started Aug 18 06:13:56 PM PDT 24
Finished Aug 18 06:14:36 PM PDT 24
Peak memory 220784 kb
Host smart-a0a53e5e-7ebb-497f-acbd-52bc0f270cbc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92644906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.92644906
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2209407185
Short name T235
Test name
Test status
Simulation time 86420411 ps
CPU time 2.45 seconds
Started Aug 18 06:14:58 PM PDT 24
Finished Aug 18 06:15:00 PM PDT 24
Peak memory 214724 kb
Host smart-844caf57-2df6-49e3-8075-343902cd9896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209407185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2209407185
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.4287522695
Short name T161
Test name
Test status
Simulation time 538571533 ps
CPU time 10.81 seconds
Started Aug 18 05:48:20 PM PDT 24
Finished Aug 18 05:48:31 PM PDT 24
Peak memory 206432 kb
Host smart-dcc1bf9e-61d2-4699-afd6-f074218129f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287522695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.4287522695
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.685199070
Short name T14
Test name
Test status
Simulation time 547145131 ps
CPU time 11.65 seconds
Started Aug 18 06:13:27 PM PDT 24
Finished Aug 18 06:13:39 PM PDT 24
Peak memory 232452 kb
Host smart-5f1fdff4-986b-42f2-85da-915bcfbd14bd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685199070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.685199070
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1483176103
Short name T21
Test name
Test status
Simulation time 165714016 ps
CPU time 1.72 seconds
Started Aug 18 06:15:28 PM PDT 24
Finished Aug 18 06:15:30 PM PDT 24
Peak memory 222304 kb
Host smart-9bdb0780-6c95-437c-9b30-3db7afb1323f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483176103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1483176103
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3843797316
Short name T264
Test name
Test status
Simulation time 5541169842 ps
CPU time 81.18 seconds
Started Aug 18 06:14:14 PM PDT 24
Finished Aug 18 06:15:35 PM PDT 24
Peak memory 218124 kb
Host smart-dded7d9e-a90f-4eb0-b121-8823c759c91f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3843797316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3843797316
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.4245437845
Short name T218
Test name
Test status
Simulation time 160948175 ps
CPU time 2.67 seconds
Started Aug 18 06:14:05 PM PDT 24
Finished Aug 18 06:14:08 PM PDT 24
Peak memory 220728 kb
Host smart-b917d3f4-93e2-45a0-a4d6-08dabbb9aaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245437845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4245437845
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2207942217
Short name T294
Test name
Test status
Simulation time 155344070 ps
CPU time 6.05 seconds
Started Aug 18 06:14:09 PM PDT 24
Finished Aug 18 06:14:15 PM PDT 24
Peak memory 214740 kb
Host smart-3ba98e83-589a-4681-ad2a-78d1a129fe6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207942217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2207942217
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.4018553485
Short name T256
Test name
Test status
Simulation time 284999745 ps
CPU time 3.18 seconds
Started Aug 18 06:14:12 PM PDT 24
Finished Aug 18 06:14:16 PM PDT 24
Peak memory 214768 kb
Host smart-d7690f6f-482f-4ad3-a344-56baddb28426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018553485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.4018553485
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.122594714
Short name T35
Test name
Test status
Simulation time 51742287 ps
CPU time 2.41 seconds
Started Aug 18 06:14:24 PM PDT 24
Finished Aug 18 06:14:26 PM PDT 24
Peak memory 222868 kb
Host smart-d57073e1-823e-40cb-8653-6bd1035ebdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122594714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.122594714
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2183034549
Short name T797
Test name
Test status
Simulation time 124321043 ps
CPU time 3.86 seconds
Started Aug 18 06:14:17 PM PDT 24
Finished Aug 18 06:14:21 PM PDT 24
Peak memory 222924 kb
Host smart-d9cc0706-01c6-425d-89de-1b0a0e3d0391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183034549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2183034549
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3244460759
Short name T415
Test name
Test status
Simulation time 1201106041 ps
CPU time 12.47 seconds
Started Aug 18 06:14:25 PM PDT 24
Finished Aug 18 06:14:37 PM PDT 24
Peak memory 214716 kb
Host smart-d9911553-3748-490b-81b4-a30ff373fe11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3244460759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3244460759
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3929796125
Short name T279
Test name
Test status
Simulation time 595372226 ps
CPU time 14.93 seconds
Started Aug 18 06:16:03 PM PDT 24
Finished Aug 18 06:16:18 PM PDT 24
Peak memory 216296 kb
Host smart-acaf8de3-19ab-4fc6-b3ed-a5033a9b2a1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929796125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3929796125
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2031911013
Short name T356
Test name
Test status
Simulation time 129155341 ps
CPU time 2.45 seconds
Started Aug 18 06:13:42 PM PDT 24
Finished Aug 18 06:13:45 PM PDT 24
Peak memory 214880 kb
Host smart-9f208794-55cd-40ac-b6ba-fc2a1c8fb758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031911013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2031911013
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.893968654
Short name T154
Test name
Test status
Simulation time 434014774 ps
CPU time 6.51 seconds
Started Aug 18 05:48:21 PM PDT 24
Finished Aug 18 05:48:27 PM PDT 24
Peak memory 206644 kb
Host smart-11e35ddb-b352-42bb-8f15-cee2d8dddead
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893968654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err
.893968654
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.172578662
Short name T166
Test name
Test status
Simulation time 154005801 ps
CPU time 1.57 seconds
Started Aug 18 06:14:37 PM PDT 24
Finished Aug 18 06:14:39 PM PDT 24
Peak memory 210600 kb
Host smart-aa2de366-403a-4a61-9fe3-e81da1d5b17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172578662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.172578662
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3378193949
Short name T114
Test name
Test status
Simulation time 140490068 ps
CPU time 3.9 seconds
Started Aug 18 06:14:46 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 223072 kb
Host smart-79387fac-09ba-4b5e-97dd-ef6b6b9dc024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378193949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3378193949
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.596973747
Short name T115
Test name
Test status
Simulation time 308600013 ps
CPU time 2.9 seconds
Started Aug 18 06:14:35 PM PDT 24
Finished Aug 18 06:14:38 PM PDT 24
Peak memory 219020 kb
Host smart-60c3fb8c-cc8e-48b5-83e1-8352ce06b19c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596973747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.596973747
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.209945038
Short name T17
Test name
Test status
Simulation time 204578832 ps
CPU time 2.76 seconds
Started Aug 18 06:13:49 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 209132 kb
Host smart-c4d69d36-f81f-473e-a0c8-67998ae98a65
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209945038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.209945038
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1874777071
Short name T567
Test name
Test status
Simulation time 101214231 ps
CPU time 2.46 seconds
Started Aug 18 06:13:50 PM PDT 24
Finished Aug 18 06:13:54 PM PDT 24
Peak memory 210576 kb
Host smart-b654e12d-5c55-4ecd-8da4-68aa362fea0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874777071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1874777071
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.365769092
Short name T233
Test name
Test status
Simulation time 1613778468 ps
CPU time 16.9 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:55 PM PDT 24
Peak memory 222864 kb
Host smart-192097b8-3b1e-40f7-9bfd-3675e8e2a9d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365769092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.365769092
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2300674506
Short name T216
Test name
Test status
Simulation time 2973456462 ps
CPU time 28.97 seconds
Started Aug 18 06:14:52 PM PDT 24
Finished Aug 18 06:15:21 PM PDT 24
Peak memory 222936 kb
Host smart-424d0b88-f767-4da4-aab0-3ab835aab8e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300674506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2300674506
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2195982577
Short name T402
Test name
Test status
Simulation time 59566180 ps
CPU time 4.08 seconds
Started Aug 18 06:14:54 PM PDT 24
Finished Aug 18 06:14:58 PM PDT 24
Peak memory 214768 kb
Host smart-767c2c83-8eeb-471a-98e7-b1b3801892a8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2195982577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2195982577
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.406198812
Short name T416
Test name
Test status
Simulation time 56115958 ps
CPU time 3.99 seconds
Started Aug 18 06:13:14 PM PDT 24
Finished Aug 18 06:13:18 PM PDT 24
Peak memory 214784 kb
Host smart-28222e8f-9926-4905-8d4e-16f43693a139
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=406198812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.406198812
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1839619222
Short name T200
Test name
Test status
Simulation time 111311507003 ps
CPU time 154.71 seconds
Started Aug 18 06:15:41 PM PDT 24
Finished Aug 18 06:18:16 PM PDT 24
Peak memory 222908 kb
Host smart-cff51174-3aea-4c05-92ef-606c8eb3bed6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839619222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1839619222
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.813961786
Short name T195
Test name
Test status
Simulation time 527328595 ps
CPU time 21.21 seconds
Started Aug 18 06:16:22 PM PDT 24
Finished Aug 18 06:16:44 PM PDT 24
Peak memory 223236 kb
Host smart-2d7cae10-058a-412f-a749-141c2f057d2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813961786 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.813961786
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.27026486
Short name T206
Test name
Test status
Simulation time 8205225557 ps
CPU time 55.78 seconds
Started Aug 18 06:13:49 PM PDT 24
Finished Aug 18 06:14:45 PM PDT 24
Peak memory 223164 kb
Host smart-86f03255-ac11-49e5-9b8f-ae4163b80d67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27026486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.27026486
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1190876508
Short name T156
Test name
Test status
Simulation time 533449836 ps
CPU time 5.26 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:13 PM PDT 24
Peak memory 214532 kb
Host smart-31b481f5-e0df-45cb-9f46-2de869a7a55d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190876508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1190876508
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.68763044
Short name T169
Test name
Test status
Simulation time 222004695 ps
CPU time 3.02 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:25 PM PDT 24
Peak memory 214548 kb
Host smart-d93ab319-af98-4945-8273-0ad2a50f1e9c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68763044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.68763044
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2047130498
Short name T164
Test name
Test status
Simulation time 1068923631 ps
CPU time 7.56 seconds
Started Aug 18 05:48:23 PM PDT 24
Finished Aug 18 05:48:30 PM PDT 24
Peak memory 206320 kb
Host smart-e53d922e-609b-4f25-8db8-fe3f137870a3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047130498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2047130498
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1001642557
Short name T53
Test name
Test status
Simulation time 472511073 ps
CPU time 3.9 seconds
Started Aug 18 06:13:55 PM PDT 24
Finished Aug 18 06:13:59 PM PDT 24
Peak memory 210032 kb
Host smart-2b33eb7d-73cb-47ec-bff0-d3b9a032152c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001642557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1001642557
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3042622277
Short name T118
Test name
Test status
Simulation time 655064528 ps
CPU time 3.22 seconds
Started Aug 18 06:14:44 PM PDT 24
Finished Aug 18 06:14:47 PM PDT 24
Peak memory 218936 kb
Host smart-fe1bc9c6-0980-4427-8bc4-83b345cf2c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042622277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3042622277
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2817896511
Short name T363
Test name
Test status
Simulation time 1841019922 ps
CPU time 4.37 seconds
Started Aug 18 06:13:40 PM PDT 24
Finished Aug 18 06:13:44 PM PDT 24
Peak memory 209780 kb
Host smart-8715960a-2479-45e1-8560-4c7c59885bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817896511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2817896511
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.448344520
Short name T375
Test name
Test status
Simulation time 2655032923 ps
CPU time 13.69 seconds
Started Aug 18 06:13:09 PM PDT 24
Finished Aug 18 06:13:23 PM PDT 24
Peak memory 221752 kb
Host smart-087f1513-b346-4310-8a2a-1877241c7ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448344520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.448344520
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3016301810
Short name T302
Test name
Test status
Simulation time 66580697 ps
CPU time 2.78 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:55 PM PDT 24
Peak memory 215760 kb
Host smart-58034bb5-c6b4-4638-a364-71e392835a62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3016301810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3016301810
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.4044404186
Short name T18
Test name
Test status
Simulation time 207367193 ps
CPU time 7.82 seconds
Started Aug 18 06:14:01 PM PDT 24
Finished Aug 18 06:14:09 PM PDT 24
Peak memory 223184 kb
Host smart-e0e165c2-a7cd-44e1-b95a-610946be1560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044404186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.4044404186
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1924953607
Short name T327
Test name
Test status
Simulation time 29667389 ps
CPU time 2.17 seconds
Started Aug 18 06:13:50 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 207552 kb
Host smart-92a81682-d60a-48e4-99f1-ca7cccfd0da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924953607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1924953607
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2480341100
Short name T465
Test name
Test status
Simulation time 92097592 ps
CPU time 2.98 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 209200 kb
Host smart-cf1fbd43-2677-4646-9d83-a71ec3415de2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2480341100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2480341100
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.284763555
Short name T367
Test name
Test status
Simulation time 757440447 ps
CPU time 8.17 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:55 PM PDT 24
Peak memory 209588 kb
Host smart-a0f1d7ca-e677-4f72-b912-4d6cfa512db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284763555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.284763555
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1896941236
Short name T276
Test name
Test status
Simulation time 323320876 ps
CPU time 3.15 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 214728 kb
Host smart-a5f3877c-d4b1-4c71-9705-7b75aff85b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1896941236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1896941236
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2858147551
Short name T374
Test name
Test status
Simulation time 90025106 ps
CPU time 2.91 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:54 PM PDT 24
Peak memory 221136 kb
Host smart-4516aaeb-af86-4a5c-bd87-97d7263e328a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858147551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2858147551
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_random.249491406
Short name T252
Test name
Test status
Simulation time 106146834 ps
CPU time 4.71 seconds
Started Aug 18 06:13:52 PM PDT 24
Finished Aug 18 06:13:57 PM PDT 24
Peak memory 207896 kb
Host smart-d5eb950c-7569-4d11-806e-52cc52187bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249491406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.249491406
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1122963230
Short name T101
Test name
Test status
Simulation time 54770025 ps
CPU time 2.34 seconds
Started Aug 18 06:14:09 PM PDT 24
Finished Aug 18 06:14:11 PM PDT 24
Peak memory 215688 kb
Host smart-b4bb9f77-289a-4563-8c11-37978588abe3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1122963230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1122963230
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2425034755
Short name T142
Test name
Test status
Simulation time 2512370831 ps
CPU time 19.26 seconds
Started Aug 18 06:14:01 PM PDT 24
Finished Aug 18 06:14:20 PM PDT 24
Peak memory 215612 kb
Host smart-80946592-cc83-45d9-a11b-153eb4c27ef1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425034755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2425034755
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2088414741
Short name T212
Test name
Test status
Simulation time 66330652 ps
CPU time 3.47 seconds
Started Aug 18 06:14:00 PM PDT 24
Finished Aug 18 06:14:03 PM PDT 24
Peak memory 211240 kb
Host smart-2e2408e3-0ecc-41d7-ba44-e9221944a2c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088414741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2088414741
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2694402623
Short name T403
Test name
Test status
Simulation time 201175452 ps
CPU time 5.82 seconds
Started Aug 18 06:14:08 PM PDT 24
Finished Aug 18 06:14:14 PM PDT 24
Peak memory 214808 kb
Host smart-b7370b9c-3a77-4a1a-b2d6-9c90f2892fae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2694402623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2694402623
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3497909028
Short name T204
Test name
Test status
Simulation time 298735775 ps
CPU time 4.76 seconds
Started Aug 18 06:14:00 PM PDT 24
Finished Aug 18 06:14:05 PM PDT 24
Peak memory 214792 kb
Host smart-7f08ea79-7e6a-4675-820d-9fe3c4c8064d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497909028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3497909028
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.4040616960
Short name T320
Test name
Test status
Simulation time 102712056 ps
CPU time 3.94 seconds
Started Aug 18 06:14:11 PM PDT 24
Finished Aug 18 06:14:16 PM PDT 24
Peak memory 215536 kb
Host smart-b6c7f63d-ae52-49ed-af35-668d36d59d33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4040616960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.4040616960
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.207704089
Short name T346
Test name
Test status
Simulation time 53925380 ps
CPU time 2.13 seconds
Started Aug 18 06:14:02 PM PDT 24
Finished Aug 18 06:14:04 PM PDT 24
Peak memory 218752 kb
Host smart-1637064b-21e4-4a31-be5f-edf3acc9de72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207704089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.207704089
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1287487206
Short name T311
Test name
Test status
Simulation time 51195584 ps
CPU time 2.23 seconds
Started Aug 18 06:14:18 PM PDT 24
Finished Aug 18 06:14:21 PM PDT 24
Peak memory 214776 kb
Host smart-b4de0cfd-d931-45b6-8aff-d8828f0f205e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1287487206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1287487206
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1391840087
Short name T141
Test name
Test status
Simulation time 1195424313 ps
CPU time 13 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:51 PM PDT 24
Peak memory 223088 kb
Host smart-ef894ce5-9ed5-4bcb-810d-c392793d6d13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391840087 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1391840087
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.981135696
Short name T371
Test name
Test status
Simulation time 123110724 ps
CPU time 4.77 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:45 PM PDT 24
Peak memory 214796 kb
Host smart-3ca896cb-fc0b-4eb5-b330-308e6e38082c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981135696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.981135696
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1179958585
Short name T350
Test name
Test status
Simulation time 2645389480 ps
CPU time 9.67 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:15:03 PM PDT 24
Peak memory 223156 kb
Host smart-951faef0-a026-4721-ada5-b5d1198e05be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179958585 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1179958585
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1999265584
Short name T357
Test name
Test status
Simulation time 2947206870 ps
CPU time 35.84 seconds
Started Aug 18 06:15:20 PM PDT 24
Finished Aug 18 06:15:56 PM PDT 24
Peak memory 215984 kb
Host smart-97434540-9e01-4a85-8734-cf5d77c42b92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999265584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1999265584
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2759053469
Short name T217
Test name
Test status
Simulation time 536320344 ps
CPU time 8.56 seconds
Started Aug 18 06:15:33 PM PDT 24
Finished Aug 18 06:15:41 PM PDT 24
Peak memory 214704 kb
Host smart-b731b80a-2937-404b-baf3-b0d11d7ca47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759053469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2759053469
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1421180719
Short name T419
Test name
Test status
Simulation time 12823000943 ps
CPU time 71.89 seconds
Started Aug 18 06:15:48 PM PDT 24
Finished Aug 18 06:17:00 PM PDT 24
Peak memory 222916 kb
Host smart-453d4de6-0535-4614-9928-8cfb63687b39
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421180719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1421180719
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2319161825
Short name T190
Test name
Test status
Simulation time 3476459913 ps
CPU time 14.46 seconds
Started Aug 18 06:13:45 PM PDT 24
Finished Aug 18 06:14:00 PM PDT 24
Peak memory 223156 kb
Host smart-2f55f2d5-b608-4db2-8b90-7f135f61cd79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319161825 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2319161825
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3276897063
Short name T220
Test name
Test status
Simulation time 1817545527 ps
CPU time 20.96 seconds
Started Aug 18 06:13:41 PM PDT 24
Finished Aug 18 06:14:02 PM PDT 24
Peak memory 222292 kb
Host smart-7a77488b-705d-4108-8c1d-c42cd940d4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276897063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3276897063
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.4165727650
Short name T926
Test name
Test status
Simulation time 224172454 ps
CPU time 8.06 seconds
Started Aug 18 05:48:11 PM PDT 24
Finished Aug 18 05:48:19 PM PDT 24
Peak memory 206240 kb
Host smart-e2476296-d8a0-4b6a-9e41-6aad9aa36f74
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165727650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.4
165727650
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3014470175
Short name T382
Test name
Test status
Simulation time 1086761918 ps
CPU time 14.53 seconds
Started Aug 18 05:47:54 PM PDT 24
Finished Aug 18 05:48:08 PM PDT 24
Peak memory 206268 kb
Host smart-b2b8ef4c-4af1-4666-b657-2e0c0bfc236d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014470175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
014470175
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2157991457
Short name T987
Test name
Test status
Simulation time 122609629 ps
CPU time 1.03 seconds
Started Aug 18 05:47:55 PM PDT 24
Finished Aug 18 05:47:56 PM PDT 24
Peak memory 206168 kb
Host smart-1ef8413e-1924-41af-b81f-b38e299ebcd6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157991457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
157991457
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2753700364
Short name T993
Test name
Test status
Simulation time 28698228 ps
CPU time 1.6 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 214520 kb
Host smart-8873f0bc-63e5-45d9-ba0d-477407299a67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753700364 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2753700364
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1192779707
Short name T983
Test name
Test status
Simulation time 19353311 ps
CPU time 1.06 seconds
Started Aug 18 05:48:01 PM PDT 24
Finished Aug 18 05:48:03 PM PDT 24
Peak memory 206296 kb
Host smart-40322ec6-5502-45d6-902c-406f9d886b74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192779707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1192779707
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.408740713
Short name T940
Test name
Test status
Simulation time 120416701 ps
CPU time 0.7 seconds
Started Aug 18 05:48:00 PM PDT 24
Finished Aug 18 05:48:00 PM PDT 24
Peak memory 206072 kb
Host smart-04f76444-85ba-4761-8d4a-d89ef4d809ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408740713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.408740713
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.213080274
Short name T1073
Test name
Test status
Simulation time 119868668 ps
CPU time 2.76 seconds
Started Aug 18 05:48:07 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 206304 kb
Host smart-ed584c62-4a32-4caf-a7ae-bf2fbbdbfb51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213080274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.213080274
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3841580629
Short name T78
Test name
Test status
Simulation time 99193240 ps
CPU time 1.97 seconds
Started Aug 18 05:47:56 PM PDT 24
Finished Aug 18 05:47:58 PM PDT 24
Peak memory 214820 kb
Host smart-15268781-77f6-429c-b644-e0b73fed1e9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841580629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3841580629
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2376766485
Short name T969
Test name
Test status
Simulation time 287575527 ps
CPU time 4.01 seconds
Started Aug 18 05:47:58 PM PDT 24
Finished Aug 18 05:48:02 PM PDT 24
Peak memory 214828 kb
Host smart-0b76d58f-a56b-4cb8-9fd5-322ef53dca7b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376766485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2376766485
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1810607727
Short name T1072
Test name
Test status
Simulation time 286237440 ps
CPU time 3.63 seconds
Started Aug 18 05:47:53 PM PDT 24
Finished Aug 18 05:47:57 PM PDT 24
Peak memory 214604 kb
Host smart-abb16ce9-9dec-426b-8002-43f3655ee017
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810607727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1810607727
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2550920777
Short name T1020
Test name
Test status
Simulation time 1493968142 ps
CPU time 9.56 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:18 PM PDT 24
Peak memory 206460 kb
Host smart-f65838b3-db10-4c0f-9f61-38de8e59c56e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550920777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
550920777
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.49296952
Short name T1041
Test name
Test status
Simulation time 142753155 ps
CPU time 7.45 seconds
Started Aug 18 05:48:05 PM PDT 24
Finished Aug 18 05:48:13 PM PDT 24
Peak memory 206408 kb
Host smart-eeec628c-7034-4b0f-b952-4e2adf21585a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49296952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.49296952
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1098823610
Short name T956
Test name
Test status
Simulation time 77976647 ps
CPU time 1.43 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:11 PM PDT 24
Peak memory 206304 kb
Host smart-765649e5-0fa6-4dea-98be-e0244852816f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098823610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
098823610
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2755391214
Short name T946
Test name
Test status
Simulation time 116507526 ps
CPU time 1.8 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 214708 kb
Host smart-9be0bff1-72fb-4438-876c-97cb1de8592a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755391214 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.2755391214
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.31210480
Short name T971
Test name
Test status
Simulation time 17570758 ps
CPU time 1.2 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 206280 kb
Host smart-d9376909-145c-48ce-8c44-4e5b3378ec17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31210480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.31210480
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1729612550
Short name T917
Test name
Test status
Simulation time 10823920 ps
CPU time 0.7 seconds
Started Aug 18 05:48:07 PM PDT 24
Finished Aug 18 05:48:08 PM PDT 24
Peak memory 206020 kb
Host smart-a220130a-a86f-4f1d-a7f8-31761e359899
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729612550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1729612550
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.4237972108
Short name T954
Test name
Test status
Simulation time 167700755 ps
CPU time 3.21 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:12 PM PDT 24
Peak memory 206392 kb
Host smart-93e9947b-80de-4f8f-a534-d4d20fadce82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237972108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.4237972108
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3758559609
Short name T970
Test name
Test status
Simulation time 327498286 ps
CPU time 7.5 seconds
Started Aug 18 05:48:21 PM PDT 24
Finished Aug 18 05:48:29 PM PDT 24
Peak memory 214832 kb
Host smart-91db63a7-a840-46d2-9052-3d9703846d5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758559609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3758559609
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.348783088
Short name T976
Test name
Test status
Simulation time 43655685 ps
CPU time 1.52 seconds
Started Aug 18 05:48:10 PM PDT 24
Finished Aug 18 05:48:11 PM PDT 24
Peak memory 214528 kb
Host smart-581cb83a-5295-4162-887d-fd23d18eed67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348783088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.348783088
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2358281217
Short name T1028
Test name
Test status
Simulation time 339987679 ps
CPU time 2.11 seconds
Started Aug 18 05:48:17 PM PDT 24
Finished Aug 18 05:48:20 PM PDT 24
Peak memory 214648 kb
Host smart-ec243fd2-7259-4f47-a9d4-75117e9fdfdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358281217 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2358281217
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2103983307
Short name T1075
Test name
Test status
Simulation time 48987394 ps
CPU time 1.09 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:20 PM PDT 24
Peak memory 206304 kb
Host smart-60829453-d869-49a2-9ce7-d0f81ff596b4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103983307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2103983307
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1636266403
Short name T1042
Test name
Test status
Simulation time 11330220 ps
CPU time 0.7 seconds
Started Aug 18 05:48:14 PM PDT 24
Finished Aug 18 05:48:15 PM PDT 24
Peak memory 206028 kb
Host smart-1a0b813c-0173-4c74-bbe9-c5012031ee4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636266403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1636266403
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1389756684
Short name T980
Test name
Test status
Simulation time 123232465 ps
CPU time 4.13 seconds
Started Aug 18 05:48:13 PM PDT 24
Finished Aug 18 05:48:18 PM PDT 24
Peak memory 206424 kb
Host smart-fc726722-fd87-47f9-845c-69961c820b4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389756684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1389756684
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.1592757200
Short name T1030
Test name
Test status
Simulation time 318350552 ps
CPU time 3.18 seconds
Started Aug 18 05:48:15 PM PDT 24
Finished Aug 18 05:48:18 PM PDT 24
Peak memory 214936 kb
Host smart-181a4280-099b-4326-ae65-1aeb37de50f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592757200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.1592757200
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.2263831478
Short name T955
Test name
Test status
Simulation time 359215120 ps
CPU time 4.55 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 214876 kb
Host smart-b12f514c-9299-418c-a7ed-e9d6cff97453
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263831478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.2263831478
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.447902268
Short name T938
Test name
Test status
Simulation time 77629255 ps
CPU time 3.06 seconds
Started Aug 18 05:48:11 PM PDT 24
Finished Aug 18 05:48:15 PM PDT 24
Peak memory 214616 kb
Host smart-77bc781b-2be7-4513-9fd6-99af22389474
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447902268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.447902268
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1478143144
Short name T935
Test name
Test status
Simulation time 329266157 ps
CPU time 1.48 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:18 PM PDT 24
Peak memory 214580 kb
Host smart-f1dac1e5-1a27-47f8-bc26-5d1f5fd8a9b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478143144 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1478143144
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3173180592
Short name T975
Test name
Test status
Simulation time 89435484 ps
CPU time 1.19 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:17 PM PDT 24
Peak memory 206324 kb
Host smart-a11739ec-5ebe-44dc-9cf8-a352a3cf2a2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173180592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3173180592
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1607458649
Short name T992
Test name
Test status
Simulation time 35359560 ps
CPU time 0.84 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:17 PM PDT 24
Peak memory 205992 kb
Host smart-623025bf-34d7-4b1a-b07f-4dc49cdccd02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607458649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1607458649
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2249154769
Short name T1056
Test name
Test status
Simulation time 49223438 ps
CPU time 1.49 seconds
Started Aug 18 05:48:14 PM PDT 24
Finished Aug 18 05:48:16 PM PDT 24
Peak memory 206348 kb
Host smart-31f4ca66-510a-4dbd-98c6-e0582d48a535
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249154769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2249154769
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3938779087
Short name T76
Test name
Test status
Simulation time 134145573 ps
CPU time 3.77 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:20 PM PDT 24
Peak memory 214728 kb
Host smart-03270ca4-3df2-426f-b91f-64c20c970742
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938779087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3938779087
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.4077765051
Short name T1006
Test name
Test status
Simulation time 209097463 ps
CPU time 6.99 seconds
Started Aug 18 05:48:10 PM PDT 24
Finished Aug 18 05:48:17 PM PDT 24
Peak memory 214864 kb
Host smart-6052f418-837c-4c10-bffc-7518a3687cde
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077765051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.4077765051
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3105001087
Short name T934
Test name
Test status
Simulation time 129357364 ps
CPU time 2.76 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:19 PM PDT 24
Peak memory 214552 kb
Host smart-9cb583a8-2dd1-409a-b668-7826adae945a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105001087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3105001087
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2194971088
Short name T1000
Test name
Test status
Simulation time 36163812 ps
CPU time 2.29 seconds
Started Aug 18 05:48:20 PM PDT 24
Finished Aug 18 05:48:23 PM PDT 24
Peak memory 214628 kb
Host smart-529d31a0-3f89-4f1a-a4f0-8a83defc31ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194971088 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2194971088
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2351090529
Short name T1067
Test name
Test status
Simulation time 71663139 ps
CPU time 1.16 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:20 PM PDT 24
Peak memory 206264 kb
Host smart-6049209c-4f6d-4f29-b2aa-0edfaca2efc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351090529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2351090529
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3420536557
Short name T959
Test name
Test status
Simulation time 11333082 ps
CPU time 0.73 seconds
Started Aug 18 05:48:15 PM PDT 24
Finished Aug 18 05:48:16 PM PDT 24
Peak memory 206040 kb
Host smart-f15e952a-8265-464d-84a7-658a2cdcb0da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420536557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3420536557
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3320958675
Short name T106
Test name
Test status
Simulation time 185454350 ps
CPU time 2.26 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 206432 kb
Host smart-17683d6b-287e-4472-95a9-16a221f1e1f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320958675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3320958675
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.179712187
Short name T1077
Test name
Test status
Simulation time 87172126 ps
CPU time 1.62 seconds
Started Aug 18 05:48:21 PM PDT 24
Finished Aug 18 05:48:22 PM PDT 24
Peak memory 214916 kb
Host smart-947dd447-7a36-4163-b741-8348c1453fd6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179712187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.179712187
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.620543482
Short name T978
Test name
Test status
Simulation time 741841418 ps
CPU time 6.99 seconds
Started Aug 18 05:48:15 PM PDT 24
Finished Aug 18 05:48:22 PM PDT 24
Peak memory 214888 kb
Host smart-ab213b53-60fe-4191-b5dc-dae6887915b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620543482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.620543482
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3249317705
Short name T1012
Test name
Test status
Simulation time 131172110 ps
CPU time 3.84 seconds
Started Aug 18 05:48:15 PM PDT 24
Finished Aug 18 05:48:19 PM PDT 24
Peak memory 214476 kb
Host smart-3f143945-462b-4e12-9ae9-2fcef2b0bd47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249317705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3249317705
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.173574750
Short name T165
Test name
Test status
Simulation time 75082669 ps
CPU time 2.68 seconds
Started Aug 18 05:48:15 PM PDT 24
Finished Aug 18 05:48:18 PM PDT 24
Peak memory 215720 kb
Host smart-e3254481-c58c-4993-b99f-f7a1c731717a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173574750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.173574750
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1145786782
Short name T1021
Test name
Test status
Simulation time 34895791 ps
CPU time 1.22 seconds
Started Aug 18 05:48:23 PM PDT 24
Finished Aug 18 05:48:24 PM PDT 24
Peak memory 206432 kb
Host smart-5e9aac33-4698-4af8-8377-22ce989a9629
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145786782 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1145786782
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3814490818
Short name T109
Test name
Test status
Simulation time 33417302 ps
CPU time 1.2 seconds
Started Aug 18 05:48:24 PM PDT 24
Finished Aug 18 05:48:25 PM PDT 24
Peak memory 206304 kb
Host smart-606d9ff3-ca5d-44ad-8cff-f7780bc739b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814490818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3814490818
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1178229361
Short name T1066
Test name
Test status
Simulation time 22845080 ps
CPU time 0.84 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:17 PM PDT 24
Peak memory 206124 kb
Host smart-5a642def-460b-4a0b-a33b-f6ef14a614b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178229361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1178229361
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4073629300
Short name T1007
Test name
Test status
Simulation time 426459131 ps
CPU time 2.5 seconds
Started Aug 18 05:48:23 PM PDT 24
Finished Aug 18 05:48:26 PM PDT 24
Peak memory 206404 kb
Host smart-fbdd2239-df50-4291-ae56-ba4b89a7fa29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073629300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4073629300
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.599795211
Short name T81
Test name
Test status
Simulation time 200486770 ps
CPU time 5.1 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 219536 kb
Host smart-a8b168ce-096e-4135-93ff-574e54a94260
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599795211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shado
w_reg_errors.599795211
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2310706977
Short name T1057
Test name
Test status
Simulation time 391794477 ps
CPU time 14.01 seconds
Started Aug 18 05:48:21 PM PDT 24
Finished Aug 18 05:48:35 PM PDT 24
Peak memory 220928 kb
Host smart-8fb7cdf0-3167-4e0b-a945-952385180a14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310706977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2310706977
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1655743043
Short name T957
Test name
Test status
Simulation time 212096055 ps
CPU time 3.95 seconds
Started Aug 18 05:48:12 PM PDT 24
Finished Aug 18 05:48:16 PM PDT 24
Peak memory 214780 kb
Host smart-e1a855eb-6a15-4eff-92c5-0027a7b0c0d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655743043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1655743043
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1906254256
Short name T960
Test name
Test status
Simulation time 197471428 ps
CPU time 2.99 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:22 PM PDT 24
Peak memory 206372 kb
Host smart-9f4fe0be-7f32-4ae0-84ff-4c3909993071
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906254256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1906254256
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.566213088
Short name T1048
Test name
Test status
Simulation time 163510708 ps
CPU time 1.84 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 206468 kb
Host smart-ef3a37c3-dad6-4396-acfe-06a850b2dd72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566213088 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.566213088
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3950374125
Short name T1040
Test name
Test status
Simulation time 35801119 ps
CPU time 1.25 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:24 PM PDT 24
Peak memory 206300 kb
Host smart-9869dc74-3447-4042-8228-4e7be7fa35c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950374125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3950374125
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3056713113
Short name T1014
Test name
Test status
Simulation time 10429244 ps
CPU time 0.68 seconds
Started Aug 18 05:48:26 PM PDT 24
Finished Aug 18 05:48:27 PM PDT 24
Peak memory 206052 kb
Host smart-c5092736-e954-4fe1-94d3-ef0580ec2f5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056713113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3056713113
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.590258354
Short name T972
Test name
Test status
Simulation time 40002734 ps
CPU time 2.23 seconds
Started Aug 18 05:48:24 PM PDT 24
Finished Aug 18 05:48:26 PM PDT 24
Peak memory 206360 kb
Host smart-5fb94ae8-121f-47c6-9b84-a46582ae7d67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590258354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.590258354
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1360536840
Short name T995
Test name
Test status
Simulation time 352829758 ps
CPU time 2.57 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:24 PM PDT 24
Peak memory 214852 kb
Host smart-b618715c-a865-48c2-8d86-742b735e5e0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360536840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1360536840
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1021948489
Short name T1060
Test name
Test status
Simulation time 767885665 ps
CPU time 4.55 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:23 PM PDT 24
Peak memory 221476 kb
Host smart-b1f3ace5-e7d2-4597-a232-c096be577e7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021948489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1021948489
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2352192167
Short name T1071
Test name
Test status
Simulation time 223833886 ps
CPU time 2.2 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:22 PM PDT 24
Peak memory 214708 kb
Host smart-72ea348d-88d7-4715-89b1-2017d6841e23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352192167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2352192167
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.12960135
Short name T961
Test name
Test status
Simulation time 350180685 ps
CPU time 1.64 seconds
Started Aug 18 05:48:21 PM PDT 24
Finished Aug 18 05:48:22 PM PDT 24
Peak memory 214664 kb
Host smart-fec3266e-9db5-4bae-af7a-278f8f5d0092
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12960135 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.12960135
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1001600850
Short name T958
Test name
Test status
Simulation time 24401538 ps
CPU time 0.99 seconds
Started Aug 18 05:48:27 PM PDT 24
Finished Aug 18 05:48:28 PM PDT 24
Peak memory 206276 kb
Host smart-1d092c47-ebe4-4c05-89f8-e77e645e0f32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001600850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1001600850
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3602146484
Short name T920
Test name
Test status
Simulation time 39677305 ps
CPU time 0.9 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:23 PM PDT 24
Peak memory 206112 kb
Host smart-a650db1e-119d-4fe9-a954-60b8fea3efa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602146484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3602146484
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2225972886
Short name T108
Test name
Test status
Simulation time 48864905 ps
CPU time 2.19 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:24 PM PDT 24
Peak memory 206348 kb
Host smart-6c132fc7-fdac-4aaf-827f-08522424a8ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225972886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2225972886
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.72171183
Short name T1013
Test name
Test status
Simulation time 122425227 ps
CPU time 2.23 seconds
Started Aug 18 05:48:24 PM PDT 24
Finished Aug 18 05:48:26 PM PDT 24
Peak memory 214780 kb
Host smart-77bcedaf-cb51-43a5-831a-f2e2cd9b86dc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72171183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow
_reg_errors.72171183
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1367301128
Short name T74
Test name
Test status
Simulation time 283019898 ps
CPU time 7.13 seconds
Started Aug 18 05:48:20 PM PDT 24
Finished Aug 18 05:48:27 PM PDT 24
Peak memory 214864 kb
Host smart-0c726887-c26e-4948-a2c3-39aea641b3e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367301128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1367301128
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3743123871
Short name T1004
Test name
Test status
Simulation time 272054207 ps
CPU time 2.02 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:24 PM PDT 24
Peak memory 216708 kb
Host smart-f461e8c8-c291-4094-b1fe-fd3b92856f4c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743123871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3743123871
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2863937717
Short name T159
Test name
Test status
Simulation time 200864348 ps
CPU time 3.31 seconds
Started Aug 18 05:48:20 PM PDT 24
Finished Aug 18 05:48:23 PM PDT 24
Peak memory 214484 kb
Host smart-d042c3d3-5077-4fb3-9644-e7db3c6984e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863937717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2863937717
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2528907973
Short name T977
Test name
Test status
Simulation time 136226994 ps
CPU time 1.69 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 214560 kb
Host smart-3cb847f6-f05b-4534-b274-1f68fe212e0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528907973 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2528907973
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3122054992
Short name T110
Test name
Test status
Simulation time 11108981 ps
CPU time 0.95 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:23 PM PDT 24
Peak memory 206348 kb
Host smart-35a870bc-39ff-4e40-a0c3-809b63ff56eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122054992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3122054992
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2090958553
Short name T1051
Test name
Test status
Simulation time 12964704 ps
CPU time 0.86 seconds
Started Aug 18 05:48:24 PM PDT 24
Finished Aug 18 05:48:25 PM PDT 24
Peak memory 206244 kb
Host smart-b0fabbaa-fc9b-4ff2-a070-360003a8fa57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090958553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2090958553
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.474558522
Short name T1053
Test name
Test status
Simulation time 858828740 ps
CPU time 2.46 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 206340 kb
Host smart-ceb59b83-eb30-4bef-b300-86a97c6cda6b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474558522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.474558522
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1809233492
Short name T1064
Test name
Test status
Simulation time 228796361 ps
CPU time 5.69 seconds
Started Aug 18 05:48:21 PM PDT 24
Finished Aug 18 05:48:27 PM PDT 24
Peak memory 219280 kb
Host smart-4533e18b-ec46-4f2e-90b9-3d3b85d659c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809233492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1809233492
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.4248848458
Short name T1002
Test name
Test status
Simulation time 294305120 ps
CPU time 3.83 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:26 PM PDT 24
Peak memory 214840 kb
Host smart-8007968c-2672-4292-b357-8fb8974f8f7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248848458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.4248848458
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1358006007
Short name T996
Test name
Test status
Simulation time 80844773 ps
CPU time 2.78 seconds
Started Aug 18 05:48:27 PM PDT 24
Finished Aug 18 05:48:30 PM PDT 24
Peak memory 214640 kb
Host smart-3f31fddd-5eb3-45ff-abb3-81980e04a21b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358006007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1358006007
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1486480751
Short name T1039
Test name
Test status
Simulation time 41903484 ps
CPU time 1.55 seconds
Started Aug 18 05:48:18 PM PDT 24
Finished Aug 18 05:48:20 PM PDT 24
Peak memory 206400 kb
Host smart-cc718c0c-a9e1-4d6e-9f0c-1b772a69fd80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486480751 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1486480751
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.407738648
Short name T930
Test name
Test status
Simulation time 22965095 ps
CPU time 0.87 seconds
Started Aug 18 05:48:20 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 206112 kb
Host smart-8f32c985-1beb-4676-b3ca-53254455a268
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407738648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.407738648
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.515164250
Short name T944
Test name
Test status
Simulation time 7559388 ps
CPU time 0.72 seconds
Started Aug 18 05:48:23 PM PDT 24
Finished Aug 18 05:48:24 PM PDT 24
Peak memory 206040 kb
Host smart-a2663be1-107a-4cee-b1d2-1346aa82bc4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515164250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.515164250
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1744934515
Short name T1036
Test name
Test status
Simulation time 48458874 ps
CPU time 1.47 seconds
Started Aug 18 05:48:21 PM PDT 24
Finished Aug 18 05:48:22 PM PDT 24
Peak memory 206356 kb
Host smart-ff15df40-4dee-4a3f-92b3-d11f24bfab45
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744934515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1744934515
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.759883331
Short name T1032
Test name
Test status
Simulation time 308713226 ps
CPU time 3.17 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:26 PM PDT 24
Peak memory 214904 kb
Host smart-c8b32e0d-ba13-455c-9b37-ab3701ed7e80
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759883331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.759883331
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.342135375
Short name T974
Test name
Test status
Simulation time 217682523 ps
CPU time 7.83 seconds
Started Aug 18 05:48:21 PM PDT 24
Finished Aug 18 05:48:29 PM PDT 24
Peak memory 214864 kb
Host smart-ea58cc8b-85e4-4db2-b71b-5a0bd7b7f1f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342135375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.342135375
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4111184652
Short name T914
Test name
Test status
Simulation time 418702178 ps
CPU time 1.73 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:24 PM PDT 24
Peak memory 214648 kb
Host smart-7a32779f-0c4c-4e9e-9615-b9a8294fd746
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111184652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4111184652
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1323241755
Short name T168
Test name
Test status
Simulation time 334140927 ps
CPU time 10.37 seconds
Started Aug 18 05:48:21 PM PDT 24
Finished Aug 18 05:48:32 PM PDT 24
Peak memory 214544 kb
Host smart-0625c9fe-6ccd-4abc-96f9-f1e04ee923c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323241755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1323241755
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4106228692
Short name T982
Test name
Test status
Simulation time 32620373 ps
CPU time 1.85 seconds
Started Aug 18 05:48:20 PM PDT 24
Finished Aug 18 05:48:22 PM PDT 24
Peak memory 214604 kb
Host smart-a09f27fe-4e68-4ecd-828b-79ba866590fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106228692 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.4106228692
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2146709483
Short name T1044
Test name
Test status
Simulation time 12265009 ps
CPU time 1.16 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 206388 kb
Host smart-a10ea366-afdd-4fd9-bcc5-48b737b8bb5c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146709483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2146709483
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.867266279
Short name T915
Test name
Test status
Simulation time 46836371 ps
CPU time 0.84 seconds
Started Aug 18 05:48:20 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 206044 kb
Host smart-fa69642d-9013-4567-b43e-0e73940285ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867266279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.867266279
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1176736547
Short name T947
Test name
Test status
Simulation time 184234138 ps
CPU time 3.38 seconds
Started Aug 18 05:48:23 PM PDT 24
Finished Aug 18 05:48:26 PM PDT 24
Peak memory 206260 kb
Host smart-615dc03e-dbb0-4b1d-b555-9da3b8011ae1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176736547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1176736547
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.715733055
Short name T1018
Test name
Test status
Simulation time 102937625 ps
CPU time 2.96 seconds
Started Aug 18 05:48:25 PM PDT 24
Finished Aug 18 05:48:28 PM PDT 24
Peak memory 214868 kb
Host smart-d3324c68-1d9f-401e-a11b-19ce3dc5114b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715733055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.715733055
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1439854771
Short name T1049
Test name
Test status
Simulation time 329890011 ps
CPU time 6.8 seconds
Started Aug 18 05:48:21 PM PDT 24
Finished Aug 18 05:48:28 PM PDT 24
Peak memory 214888 kb
Host smart-7b23cbae-4780-4f7b-8fa1-8a703a1a5e1f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439854771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1439854771
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3585711457
Short name T1063
Test name
Test status
Simulation time 237374033 ps
CPU time 4.49 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:26 PM PDT 24
Peak memory 217644 kb
Host smart-1c08d86f-3596-49eb-bd76-6ede573a560c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585711457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3585711457
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2104281645
Short name T1079
Test name
Test status
Simulation time 78038123 ps
CPU time 1.15 seconds
Started Aug 18 05:48:21 PM PDT 24
Finished Aug 18 05:48:23 PM PDT 24
Peak memory 206428 kb
Host smart-8075a5a3-8d5a-4b4d-ae13-0906d30dc028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104281645 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2104281645
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1677804485
Short name T111
Test name
Test status
Simulation time 24361575 ps
CPU time 1.17 seconds
Started Aug 18 05:48:23 PM PDT 24
Finished Aug 18 05:48:25 PM PDT 24
Peak memory 206260 kb
Host smart-a0e54dd1-fee2-463a-8a60-d6461cf953f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677804485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1677804485
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.4023476187
Short name T986
Test name
Test status
Simulation time 10420213 ps
CPU time 0.79 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:23 PM PDT 24
Peak memory 206108 kb
Host smart-a6cb5f4b-8724-47f1-9477-75c4dd812092
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023476187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.4023476187
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3696340946
Short name T1001
Test name
Test status
Simulation time 34290180 ps
CPU time 2.35 seconds
Started Aug 18 05:48:22 PM PDT 24
Finished Aug 18 05:48:24 PM PDT 24
Peak memory 206232 kb
Host smart-4a7aab28-3dcc-4e7a-8468-e7d5dd1c2ed2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696340946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3696340946
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.2297505203
Short name T965
Test name
Test status
Simulation time 568226444 ps
CPU time 4.66 seconds
Started Aug 18 05:48:26 PM PDT 24
Finished Aug 18 05:48:31 PM PDT 24
Peak memory 214852 kb
Host smart-1ab906ca-535f-4aaf-a9ad-4bb92384e398
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297505203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.2297505203
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3030193508
Short name T927
Test name
Test status
Simulation time 388702130 ps
CPU time 6.83 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:26 PM PDT 24
Peak memory 214884 kb
Host smart-72e86470-6c2d-4b50-a69d-5fe611527146
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030193508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3030193508
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.910407792
Short name T1052
Test name
Test status
Simulation time 99040810 ps
CPU time 1.81 seconds
Started Aug 18 05:48:23 PM PDT 24
Finished Aug 18 05:48:25 PM PDT 24
Peak memory 214592 kb
Host smart-550975cb-d5ba-4f1c-8e05-d227a1a99c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910407792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.910407792
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1856580231
Short name T163
Test name
Test status
Simulation time 419477668 ps
CPU time 5.21 seconds
Started Aug 18 05:48:18 PM PDT 24
Finished Aug 18 05:48:24 PM PDT 24
Peak memory 214544 kb
Host smart-045e1705-664b-4241-9487-7e5b0bb23310
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856580231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1856580231
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.423673371
Short name T1045
Test name
Test status
Simulation time 1383419686 ps
CPU time 10.53 seconds
Started Aug 18 05:48:05 PM PDT 24
Finished Aug 18 05:48:16 PM PDT 24
Peak memory 206356 kb
Host smart-1a12d9dc-d1c2-43ea-aa71-58a5c22185ff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423673371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.423673371
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.188629629
Short name T1069
Test name
Test status
Simulation time 1703678279 ps
CPU time 14.39 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:23 PM PDT 24
Peak memory 206256 kb
Host smart-860d466c-b6c6-4521-8c21-ab7162145b8d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188629629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.188629629
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1087171697
Short name T155
Test name
Test status
Simulation time 64131698 ps
CPU time 0.92 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 206172 kb
Host smart-48f5cff5-2e6f-4dd4-bf70-19ff5a11ba96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087171697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
087171697
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.308043771
Short name T929
Test name
Test status
Simulation time 44593965 ps
CPU time 1.96 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:11 PM PDT 24
Peak memory 214516 kb
Host smart-36d97e8c-8bf3-4adc-8075-4a0ffb9c3e90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308043771 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.308043771
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3524931082
Short name T1038
Test name
Test status
Simulation time 40653059 ps
CPU time 1.06 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 206348 kb
Host smart-7f017d04-aaf7-4da9-86ad-8fbcab6cf7c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524931082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3524931082
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2979237775
Short name T1011
Test name
Test status
Simulation time 26695079 ps
CPU time 0.86 seconds
Started Aug 18 05:48:12 PM PDT 24
Finished Aug 18 05:48:13 PM PDT 24
Peak memory 206132 kb
Host smart-61754de5-3581-4fb8-a0a9-0437e5654093
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979237775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2979237775
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3093812049
Short name T1033
Test name
Test status
Simulation time 140896338 ps
CPU time 2.81 seconds
Started Aug 18 05:48:11 PM PDT 24
Finished Aug 18 05:48:14 PM PDT 24
Peak memory 206340 kb
Host smart-179f5ad2-3aec-4e39-bffc-9fd4335e8c0c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093812049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3093812049
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1860379555
Short name T966
Test name
Test status
Simulation time 301060937 ps
CPU time 2.99 seconds
Started Aug 18 05:48:06 PM PDT 24
Finished Aug 18 05:48:09 PM PDT 24
Peak memory 214836 kb
Host smart-1d9f985d-d444-401e-9020-dbed565fe814
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860379555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1860379555
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2021322237
Short name T1009
Test name
Test status
Simulation time 845666669 ps
CPU time 4.45 seconds
Started Aug 18 05:48:06 PM PDT 24
Finished Aug 18 05:48:11 PM PDT 24
Peak memory 214868 kb
Host smart-53abbdf7-dabb-4b07-918f-55796ff6cd79
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2021322237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2021322237
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.701812619
Short name T952
Test name
Test status
Simulation time 133395447 ps
CPU time 2.74 seconds
Started Aug 18 05:48:12 PM PDT 24
Finished Aug 18 05:48:15 PM PDT 24
Peak memory 222820 kb
Host smart-14c732c5-0e1c-47b8-9a64-1e8d93c79ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701812619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.701812619
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2839887572
Short name T968
Test name
Test status
Simulation time 114871495 ps
CPU time 5.55 seconds
Started Aug 18 05:48:06 PM PDT 24
Finished Aug 18 05:48:12 PM PDT 24
Peak memory 214552 kb
Host smart-8a912922-8bcf-42c3-b97e-8c0bbda835a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839887572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2839887572
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3123722051
Short name T997
Test name
Test status
Simulation time 51708211 ps
CPU time 0.94 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:20 PM PDT 24
Peak memory 205972 kb
Host smart-1ca29283-ce5d-4144-975f-71235ec1f572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123722051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3123722051
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3195980224
Short name T950
Test name
Test status
Simulation time 37296250 ps
CPU time 0.84 seconds
Started Aug 18 05:48:19 PM PDT 24
Finished Aug 18 05:48:20 PM PDT 24
Peak memory 206096 kb
Host smart-3d994323-fe38-4f3e-a93a-08f3c7712192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3195980224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3195980224
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1232090391
Short name T923
Test name
Test status
Simulation time 62784517 ps
CPU time 0.8 seconds
Started Aug 18 05:48:20 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 206064 kb
Host smart-61fcaaab-b4c7-472e-af3c-2ba7b5272a8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232090391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1232090391
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.97681779
Short name T1008
Test name
Test status
Simulation time 41712757 ps
CPU time 0.82 seconds
Started Aug 18 05:48:29 PM PDT 24
Finished Aug 18 05:48:30 PM PDT 24
Peak memory 206072 kb
Host smart-adf9b773-5dd5-4690-a2fc-cb5e92f74f6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97681779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.97681779
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3454362641
Short name T979
Test name
Test status
Simulation time 20298122 ps
CPU time 0.72 seconds
Started Aug 18 05:48:30 PM PDT 24
Finished Aug 18 05:48:31 PM PDT 24
Peak memory 206096 kb
Host smart-78bf3a5e-fc83-4917-81f8-d2657e80e9aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454362641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3454362641
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1838641601
Short name T989
Test name
Test status
Simulation time 11091315 ps
CPU time 0.83 seconds
Started Aug 18 05:48:28 PM PDT 24
Finished Aug 18 05:48:29 PM PDT 24
Peak memory 206048 kb
Host smart-f15a53a0-71a6-4f63-be9a-9afa17d97d74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838641601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1838641601
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3120731644
Short name T994
Test name
Test status
Simulation time 8190192 ps
CPU time 0.68 seconds
Started Aug 18 05:48:32 PM PDT 24
Finished Aug 18 05:48:33 PM PDT 24
Peak memory 206088 kb
Host smart-c69f6317-8a33-4926-bb76-c826a8e579cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120731644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3120731644
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2961444683
Short name T999
Test name
Test status
Simulation time 25810478 ps
CPU time 0.73 seconds
Started Aug 18 05:48:29 PM PDT 24
Finished Aug 18 05:48:30 PM PDT 24
Peak memory 206032 kb
Host smart-ef8b7ccf-53b0-43e7-8892-613935605cc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961444683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2961444683
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1986508369
Short name T1076
Test name
Test status
Simulation time 34645110 ps
CPU time 0.73 seconds
Started Aug 18 05:48:30 PM PDT 24
Finished Aug 18 05:48:31 PM PDT 24
Peak memory 206108 kb
Host smart-9f5d110e-370e-4b60-9e0f-5ce15457842e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986508369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1986508369
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2236694175
Short name T985
Test name
Test status
Simulation time 36118114 ps
CPU time 0.71 seconds
Started Aug 18 05:48:28 PM PDT 24
Finished Aug 18 05:48:29 PM PDT 24
Peak memory 206128 kb
Host smart-4bcd9e80-8ae3-446c-bf5e-f4abdbc155a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236694175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2236694175
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2460026165
Short name T172
Test name
Test status
Simulation time 431306322 ps
CPU time 14.64 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:23 PM PDT 24
Peak memory 206356 kb
Host smart-5aba769b-436b-4060-bea5-3ce821f867f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460026165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
460026165
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.4144262411
Short name T381
Test name
Test status
Simulation time 1665889602 ps
CPU time 7.86 seconds
Started Aug 18 05:48:06 PM PDT 24
Finished Aug 18 05:48:14 PM PDT 24
Peak memory 206316 kb
Host smart-52d98062-ab40-4a54-b436-69c2cf8f3b03
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144262411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.4
144262411
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.53256943
Short name T1065
Test name
Test status
Simulation time 65033252 ps
CPU time 0.98 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:09 PM PDT 24
Peak memory 206168 kb
Host smart-abfff5b2-7b74-4bf1-8feb-814e283b1916
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53256943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.53256943
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4062161031
Short name T937
Test name
Test status
Simulation time 57350976 ps
CPU time 2.01 seconds
Started Aug 18 05:48:05 PM PDT 24
Finished Aug 18 05:48:08 PM PDT 24
Peak memory 214464 kb
Host smart-b21d584a-953e-4780-b1f4-b43bfa7d77e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062161031 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.4062161031
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.631068224
Short name T953
Test name
Test status
Simulation time 46538798 ps
CPU time 1.14 seconds
Started Aug 18 05:48:10 PM PDT 24
Finished Aug 18 05:48:11 PM PDT 24
Peak memory 206344 kb
Host smart-26a141d8-516e-4cdb-a5e4-75cfa8343dea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631068224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.631068224
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3623459660
Short name T963
Test name
Test status
Simulation time 12630694 ps
CPU time 0.71 seconds
Started Aug 18 05:48:07 PM PDT 24
Finished Aug 18 05:48:08 PM PDT 24
Peak memory 206052 kb
Host smart-56193c01-c618-4591-a588-3175f4131e1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623459660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3623459660
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.875899750
Short name T107
Test name
Test status
Simulation time 71769154 ps
CPU time 1.95 seconds
Started Aug 18 05:48:11 PM PDT 24
Finished Aug 18 05:48:13 PM PDT 24
Peak memory 206360 kb
Host smart-c0d1b032-7f82-476b-8cdd-f7e73dfda0db
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875899750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.875899750
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3231188651
Short name T73
Test name
Test status
Simulation time 160155258 ps
CPU time 1.54 seconds
Started Aug 18 05:48:07 PM PDT 24
Finished Aug 18 05:48:08 PM PDT 24
Peak memory 214848 kb
Host smart-4249fe0b-b56d-40ee-a359-f7b5a240e871
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231188651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3231188651
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.663159959
Short name T984
Test name
Test status
Simulation time 2557540479 ps
CPU time 7.75 seconds
Started Aug 18 05:48:10 PM PDT 24
Finished Aug 18 05:48:18 PM PDT 24
Peak memory 215036 kb
Host smart-7535a350-f8e1-45ab-9e44-70f027046bc1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663159959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.k
eymgr_shadow_reg_errors_with_csr_rw.663159959
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1692024151
Short name T1029
Test name
Test status
Simulation time 92503487 ps
CPU time 2.92 seconds
Started Aug 18 05:48:06 PM PDT 24
Finished Aug 18 05:48:09 PM PDT 24
Peak memory 214668 kb
Host smart-39b34362-43ba-4ba2-bca7-096269f30e1a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692024151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1692024151
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.575278509
Short name T919
Test name
Test status
Simulation time 32308539 ps
CPU time 0.85 seconds
Started Aug 18 05:48:37 PM PDT 24
Finished Aug 18 05:48:38 PM PDT 24
Peak memory 206112 kb
Host smart-7c61b137-e4a4-465c-a237-0828d25b68a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575278509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.575278509
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.410160658
Short name T1015
Test name
Test status
Simulation time 14192592 ps
CPU time 0.75 seconds
Started Aug 18 05:48:31 PM PDT 24
Finished Aug 18 05:48:32 PM PDT 24
Peak memory 206032 kb
Host smart-250aa964-a5c6-4ad9-a2a5-c45ce2716ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410160658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.410160658
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2603375599
Short name T936
Test name
Test status
Simulation time 15342431 ps
CPU time 0.86 seconds
Started Aug 18 05:48:28 PM PDT 24
Finished Aug 18 05:48:29 PM PDT 24
Peak memory 206260 kb
Host smart-f17f474b-86a8-4723-9d5c-b1a6794ccb47
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603375599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2603375599
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2377595114
Short name T1054
Test name
Test status
Simulation time 15048615 ps
CPU time 0.7 seconds
Started Aug 18 05:48:30 PM PDT 24
Finished Aug 18 05:48:31 PM PDT 24
Peak memory 206120 kb
Host smart-5142682a-09ea-4c84-9c33-e8c7f8c4decd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377595114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2377595114
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.4058716247
Short name T1019
Test name
Test status
Simulation time 45279477 ps
CPU time 0.88 seconds
Started Aug 18 05:48:31 PM PDT 24
Finished Aug 18 05:48:32 PM PDT 24
Peak memory 205988 kb
Host smart-42ddb773-df41-48f8-87ce-233343c0261c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058716247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.4058716247
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1581503264
Short name T1035
Test name
Test status
Simulation time 89452486 ps
CPU time 0.71 seconds
Started Aug 18 05:48:35 PM PDT 24
Finished Aug 18 05:48:36 PM PDT 24
Peak memory 206124 kb
Host smart-9bdfee0c-a20c-4e2b-a4b6-867faec3c09f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581503264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1581503264
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.74649113
Short name T932
Test name
Test status
Simulation time 12802277 ps
CPU time 0.7 seconds
Started Aug 18 05:48:28 PM PDT 24
Finished Aug 18 05:48:29 PM PDT 24
Peak memory 205964 kb
Host smart-95e2cf6d-5fe4-4f99-8676-e2b535dd0fb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74649113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.74649113
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.1791045711
Short name T991
Test name
Test status
Simulation time 9652536 ps
CPU time 0.81 seconds
Started Aug 18 05:48:35 PM PDT 24
Finished Aug 18 05:48:36 PM PDT 24
Peak memory 206012 kb
Host smart-029978ab-6220-4c19-abd2-cb8a5f236d56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791045711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1791045711
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.4124180671
Short name T918
Test name
Test status
Simulation time 18206835 ps
CPU time 0.81 seconds
Started Aug 18 05:48:36 PM PDT 24
Finished Aug 18 05:48:37 PM PDT 24
Peak memory 206112 kb
Host smart-b8e57235-89e4-44f9-9d60-f9799d068951
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124180671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.4124180671
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1621933634
Short name T1043
Test name
Test status
Simulation time 18429108 ps
CPU time 0.69 seconds
Started Aug 18 05:48:27 PM PDT 24
Finished Aug 18 05:48:28 PM PDT 24
Peak memory 206104 kb
Host smart-452a42c0-6f40-4dfe-9849-d7284fc089b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621933634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1621933634
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3238277317
Short name T1034
Test name
Test status
Simulation time 431111410 ps
CPU time 15.24 seconds
Started Aug 18 05:48:07 PM PDT 24
Finished Aug 18 05:48:22 PM PDT 24
Peak memory 206228 kb
Host smart-d5cbc9be-b413-47ea-9383-aacb19bfddb1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238277317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
238277317
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1571280314
Short name T1031
Test name
Test status
Simulation time 1599536284 ps
CPU time 8.65 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:17 PM PDT 24
Peak memory 206268 kb
Host smart-121a33e0-4436-45bc-8db9-78ea9e79e5b3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571280314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
571280314
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.347918003
Short name T973
Test name
Test status
Simulation time 28848376 ps
CPU time 1.17 seconds
Started Aug 18 05:48:10 PM PDT 24
Finished Aug 18 05:48:11 PM PDT 24
Peak memory 206272 kb
Host smart-da79f12d-4ba9-4fa8-9e91-a659be10235a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347918003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.347918003
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.251146664
Short name T1026
Test name
Test status
Simulation time 194414625 ps
CPU time 2.26 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:11 PM PDT 24
Peak memory 214768 kb
Host smart-7120c678-c9f3-4d1e-9963-0d794d6ed217
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251146664 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.251146664
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2371859919
Short name T998
Test name
Test status
Simulation time 19926662 ps
CPU time 0.96 seconds
Started Aug 18 05:48:07 PM PDT 24
Finished Aug 18 05:48:08 PM PDT 24
Peak memory 206156 kb
Host smart-56c56630-bcc2-4973-9397-6523ed616639
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371859919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2371859919
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2567990829
Short name T1078
Test name
Test status
Simulation time 12161916 ps
CPU time 0.86 seconds
Started Aug 18 05:48:07 PM PDT 24
Finished Aug 18 05:48:08 PM PDT 24
Peak memory 206128 kb
Host smart-1217a052-0036-406c-b601-32a3b91a8739
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567990829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2567990829
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1972376136
Short name T939
Test name
Test status
Simulation time 36999602 ps
CPU time 1.31 seconds
Started Aug 18 05:48:11 PM PDT 24
Finished Aug 18 05:48:12 PM PDT 24
Peak memory 206392 kb
Host smart-42124a03-2c0d-4a97-b66a-8c04398f7275
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972376136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1972376136
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2604743332
Short name T82
Test name
Test status
Simulation time 274069160 ps
CPU time 2.5 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 215056 kb
Host smart-83c9def3-db64-4a63-9d48-f66fb0042248
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604743332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2604743332
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1764237478
Short name T931
Test name
Test status
Simulation time 605484576 ps
CPU time 14.79 seconds
Started Aug 18 05:48:06 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 214864 kb
Host smart-0da1cb11-f52c-41a3-979a-b7e3c428f1e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764237478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1764237478
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2487510973
Short name T1005
Test name
Test status
Simulation time 148660308 ps
CPU time 1.94 seconds
Started Aug 18 05:48:07 PM PDT 24
Finished Aug 18 05:48:09 PM PDT 24
Peak memory 215744 kb
Host smart-f7c0b34d-b9ee-4f84-b49d-162bafa70ab9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487510973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2487510973
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.226710254
Short name T933
Test name
Test status
Simulation time 272091693 ps
CPU time 3.74 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:12 PM PDT 24
Peak memory 214508 kb
Host smart-71543f61-e823-4638-a074-4e938f6519da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226710254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
226710254
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.787737248
Short name T967
Test name
Test status
Simulation time 37842846 ps
CPU time 0.71 seconds
Started Aug 18 05:48:30 PM PDT 24
Finished Aug 18 05:48:31 PM PDT 24
Peak memory 206092 kb
Host smart-fe3aa9f0-b588-4cd8-a6d0-793d45aeae1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787737248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.787737248
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1816082964
Short name T942
Test name
Test status
Simulation time 12837343 ps
CPU time 0.82 seconds
Started Aug 18 05:48:35 PM PDT 24
Finished Aug 18 05:48:36 PM PDT 24
Peak memory 206036 kb
Host smart-fffef3f1-f9de-495e-9dc7-9b758500fc9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816082964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1816082964
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4154981864
Short name T1074
Test name
Test status
Simulation time 17301301 ps
CPU time 0.72 seconds
Started Aug 18 05:48:37 PM PDT 24
Finished Aug 18 05:48:38 PM PDT 24
Peak memory 206112 kb
Host smart-3b5b725f-4c58-49e0-a637-f7f7aef70db5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154981864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.4154981864
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4266768753
Short name T1068
Test name
Test status
Simulation time 68151842 ps
CPU time 0.71 seconds
Started Aug 18 05:48:29 PM PDT 24
Finished Aug 18 05:48:30 PM PDT 24
Peak memory 206124 kb
Host smart-629e6c1b-af69-4938-8971-dd51e2133c92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266768753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4266768753
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1865104472
Short name T921
Test name
Test status
Simulation time 42054295 ps
CPU time 0.8 seconds
Started Aug 18 05:48:29 PM PDT 24
Finished Aug 18 05:48:30 PM PDT 24
Peak memory 206124 kb
Host smart-4526be8b-01be-477f-87d9-47e08b29285a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865104472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1865104472
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.2267451756
Short name T1058
Test name
Test status
Simulation time 27783829 ps
CPU time 0.85 seconds
Started Aug 18 05:48:30 PM PDT 24
Finished Aug 18 05:48:31 PM PDT 24
Peak memory 206108 kb
Host smart-6447fb74-a827-4011-84b1-d980ce1dd9df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267451756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2267451756
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1528977500
Short name T916
Test name
Test status
Simulation time 35927951 ps
CPU time 0.77 seconds
Started Aug 18 05:48:28 PM PDT 24
Finished Aug 18 05:48:29 PM PDT 24
Peak memory 206044 kb
Host smart-9d4d1b8d-501b-4700-87fe-536c7cc8bbd1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528977500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1528977500
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3804128395
Short name T1010
Test name
Test status
Simulation time 8237253 ps
CPU time 0.77 seconds
Started Aug 18 05:48:35 PM PDT 24
Finished Aug 18 05:48:36 PM PDT 24
Peak memory 206036 kb
Host smart-1be5bc83-9126-4ffd-a433-bd725514f1e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804128395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3804128395
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2198980523
Short name T1003
Test name
Test status
Simulation time 42271801 ps
CPU time 0.81 seconds
Started Aug 18 05:48:33 PM PDT 24
Finished Aug 18 05:48:34 PM PDT 24
Peak memory 206196 kb
Host smart-6d5a12f1-dd01-4c18-b68a-fbf0c167455b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198980523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2198980523
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.360575615
Short name T1023
Test name
Test status
Simulation time 8185832 ps
CPU time 0.68 seconds
Started Aug 18 05:48:27 PM PDT 24
Finished Aug 18 05:48:28 PM PDT 24
Peak memory 206108 kb
Host smart-7c4b13c2-e7fa-42f3-89a2-f65849731c36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360575615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.360575615
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2482126719
Short name T1046
Test name
Test status
Simulation time 285052551 ps
CPU time 1.76 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:11 PM PDT 24
Peak memory 218644 kb
Host smart-6697be86-64e6-4fd1-b296-a742075d6c6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482126719 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2482126719
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3002784175
Short name T1024
Test name
Test status
Simulation time 77266010 ps
CPU time 1.2 seconds
Started Aug 18 05:48:07 PM PDT 24
Finished Aug 18 05:48:08 PM PDT 24
Peak memory 206352 kb
Host smart-d56f2216-0ba0-45b6-ab5d-8235e8e9654e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002784175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3002784175
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2966590819
Short name T1062
Test name
Test status
Simulation time 10360011 ps
CPU time 0.77 seconds
Started Aug 18 05:48:05 PM PDT 24
Finished Aug 18 05:48:05 PM PDT 24
Peak memory 206012 kb
Host smart-f3cdf098-80b7-4fd3-9d0f-76e067aadedc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966590819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2966590819
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3546827669
Short name T105
Test name
Test status
Simulation time 73543475 ps
CPU time 2.12 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 206272 kb
Host smart-4a0c19a6-9189-4b41-a6cb-08ea872811b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546827669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3546827669
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3966504787
Short name T83
Test name
Test status
Simulation time 93426235 ps
CPU time 2.37 seconds
Started Aug 18 05:48:07 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 214872 kb
Host smart-dd3627e6-a854-4033-b87c-cfa646c6f07f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966504787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3966504787
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.452288585
Short name T1022
Test name
Test status
Simulation time 271966088 ps
CPU time 3.47 seconds
Started Aug 18 05:48:06 PM PDT 24
Finished Aug 18 05:48:09 PM PDT 24
Peak memory 214820 kb
Host smart-afb1ccf3-91d5-4895-b687-724177963e67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452288585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.452288585
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.269681556
Short name T1059
Test name
Test status
Simulation time 45422232 ps
CPU time 1.95 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 214612 kb
Host smart-b2e01cd6-0c09-4fbe-aadf-5b3ce7700e76
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269681556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.269681556
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2004732375
Short name T1016
Test name
Test status
Simulation time 210627176 ps
CPU time 4.51 seconds
Started Aug 18 05:48:11 PM PDT 24
Finished Aug 18 05:48:15 PM PDT 24
Peak memory 214368 kb
Host smart-e9bcb0ed-709d-4346-9380-b1ea6b2e5896
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004732375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2004732375
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1110027823
Short name T964
Test name
Test status
Simulation time 54068148 ps
CPU time 2.25 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:12 PM PDT 24
Peak memory 214568 kb
Host smart-fa303d1a-bfd7-4568-a6d6-cf6acef7e7b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110027823 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1110027823
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3778947760
Short name T922
Test name
Test status
Simulation time 33044124 ps
CPU time 0.96 seconds
Started Aug 18 05:48:11 PM PDT 24
Finished Aug 18 05:48:12 PM PDT 24
Peak memory 206192 kb
Host smart-e5336e56-efc7-45a2-8db5-00ac96ddb8b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778947760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3778947760
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1321785297
Short name T1047
Test name
Test status
Simulation time 9070253 ps
CPU time 0.74 seconds
Started Aug 18 05:48:13 PM PDT 24
Finished Aug 18 05:48:14 PM PDT 24
Peak memory 206096 kb
Host smart-cc2b7043-cb05-4998-a56f-983f8b858b50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321785297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1321785297
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3434554893
Short name T1061
Test name
Test status
Simulation time 21872620 ps
CPU time 1.61 seconds
Started Aug 18 05:48:14 PM PDT 24
Finished Aug 18 05:48:16 PM PDT 24
Peak memory 206348 kb
Host smart-98e06c1a-7a40-4114-a95e-4d9fd606b267
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434554893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3434554893
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3800300705
Short name T77
Test name
Test status
Simulation time 133440393 ps
CPU time 2.65 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 214840 kb
Host smart-96c36e99-499b-47d9-a536-6f8171cb870e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800300705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3800300705
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2158784906
Short name T1027
Test name
Test status
Simulation time 809000877 ps
CPU time 14.24 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:24 PM PDT 24
Peak memory 214812 kb
Host smart-e28dbdb3-8da0-4a70-b695-f21d07f9cc5d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158784906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2158784906
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.742405830
Short name T1050
Test name
Test status
Simulation time 32991097 ps
CPU time 1.91 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:11 PM PDT 24
Peak memory 214532 kb
Host smart-a2005954-8a9a-4a5f-9495-2f7dc5af34f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742405830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.742405830
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.4149426965
Short name T162
Test name
Test status
Simulation time 350163504 ps
CPU time 5.39 seconds
Started Aug 18 05:48:13 PM PDT 24
Finished Aug 18 05:48:18 PM PDT 24
Peak memory 214520 kb
Host smart-9860ee19-5d87-4d3e-b5ad-84fb599bc6bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149426965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.4149426965
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.651417775
Short name T941
Test name
Test status
Simulation time 222593515 ps
CPU time 1.4 seconds
Started Aug 18 05:48:08 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 206432 kb
Host smart-9e0b5e2f-cb40-4142-be2f-6c948a542032
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651417775 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.651417775
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1227029753
Short name T1017
Test name
Test status
Simulation time 90972090 ps
CPU time 1.44 seconds
Started Aug 18 05:48:13 PM PDT 24
Finished Aug 18 05:48:14 PM PDT 24
Peak memory 206372 kb
Host smart-d348ee9b-4e90-4d4a-bfe6-80c51b21eeb2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227029753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1227029753
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3187045803
Short name T949
Test name
Test status
Simulation time 44493071 ps
CPU time 0.79 seconds
Started Aug 18 05:48:11 PM PDT 24
Finished Aug 18 05:48:12 PM PDT 24
Peak memory 205944 kb
Host smart-5fbe7817-b05f-4f67-9af9-5f305a04d1bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187045803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3187045803
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2132922658
Short name T104
Test name
Test status
Simulation time 156743368 ps
CPU time 1.44 seconds
Started Aug 18 05:48:09 PM PDT 24
Finished Aug 18 05:48:11 PM PDT 24
Peak memory 206276 kb
Host smart-620773ef-db39-43de-a6d1-28f527448751
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132922658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2132922658
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3365594582
Short name T945
Test name
Test status
Simulation time 197889746 ps
CPU time 2.77 seconds
Started Aug 18 05:48:11 PM PDT 24
Finished Aug 18 05:48:14 PM PDT 24
Peak memory 214988 kb
Host smart-a4fa6153-3931-41c3-8f71-1519ba9141f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365594582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3365594582
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2552437942
Short name T951
Test name
Test status
Simulation time 3239934723 ps
CPU time 8.01 seconds
Started Aug 18 05:48:11 PM PDT 24
Finished Aug 18 05:48:19 PM PDT 24
Peak memory 215068 kb
Host smart-54bce796-9040-4382-85a5-c68b34350848
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552437942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2552437942
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2769750794
Short name T1070
Test name
Test status
Simulation time 236051851 ps
CPU time 4.6 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:21 PM PDT 24
Peak memory 214636 kb
Host smart-17f29e4b-3005-4aff-af6b-0909d8fcf60d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769750794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2769750794
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2983063547
Short name T167
Test name
Test status
Simulation time 109751347 ps
CPU time 3.58 seconds
Started Aug 18 05:48:13 PM PDT 24
Finished Aug 18 05:48:17 PM PDT 24
Peak memory 214472 kb
Host smart-82712486-9c20-4676-8770-da4b37d0f3cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983063547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2983063547
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3019812436
Short name T1037
Test name
Test status
Simulation time 107511887 ps
CPU time 2.09 seconds
Started Aug 18 05:48:14 PM PDT 24
Finished Aug 18 05:48:17 PM PDT 24
Peak memory 214664 kb
Host smart-fc02900a-653e-4ace-9774-ebc83ea4d3d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019812436 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3019812436
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.4013051208
Short name T981
Test name
Test status
Simulation time 85267374 ps
CPU time 1.2 seconds
Started Aug 18 05:48:15 PM PDT 24
Finished Aug 18 05:48:16 PM PDT 24
Peak memory 206320 kb
Host smart-92e0e4ea-27c9-41b2-b9b9-e3c274e4a664
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013051208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.4013051208
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1261798875
Short name T990
Test name
Test status
Simulation time 12942842 ps
CPU time 0.72 seconds
Started Aug 18 05:48:10 PM PDT 24
Finished Aug 18 05:48:10 PM PDT 24
Peak memory 206024 kb
Host smart-24d07b05-af67-4e5e-a517-634cd0cc9554
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261798875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1261798875
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2524711967
Short name T1055
Test name
Test status
Simulation time 22915425 ps
CPU time 1.62 seconds
Started Aug 18 05:48:13 PM PDT 24
Finished Aug 18 05:48:14 PM PDT 24
Peak memory 206360 kb
Host smart-30aa6688-f5ce-449a-9f47-b58eaae4499f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524711967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2524711967
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2982154446
Short name T924
Test name
Test status
Simulation time 318602949 ps
CPU time 2.8 seconds
Started Aug 18 05:48:12 PM PDT 24
Finished Aug 18 05:48:15 PM PDT 24
Peak memory 214924 kb
Host smart-f49cb9e6-b2a5-41a7-bfd7-fb4350b6398d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982154446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2982154446
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2130036955
Short name T948
Test name
Test status
Simulation time 316559385 ps
CPU time 8.75 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:25 PM PDT 24
Peak memory 214916 kb
Host smart-170a8163-bc88-49ba-96c9-5add23695b1d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130036955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2130036955
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2886293547
Short name T925
Test name
Test status
Simulation time 336305598 ps
CPU time 3.48 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:20 PM PDT 24
Peak memory 214684 kb
Host smart-7bdf3ca0-7cad-4efb-aa4d-3efe31e170e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886293547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2886293547
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2790189436
Short name T152
Test name
Test status
Simulation time 524854830 ps
CPU time 4.03 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:20 PM PDT 24
Peak memory 214548 kb
Host smart-b86be471-d83c-4b58-b63a-a51a211e333a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790189436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2790189436
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3142168078
Short name T173
Test name
Test status
Simulation time 35714282 ps
CPU time 1.12 seconds
Started Aug 18 05:48:11 PM PDT 24
Finished Aug 18 05:48:12 PM PDT 24
Peak memory 206472 kb
Host smart-6c04b8c2-5bb9-45f9-ab39-4af8445b59a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142168078 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3142168078
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2836350208
Short name T928
Test name
Test status
Simulation time 14242932 ps
CPU time 1.07 seconds
Started Aug 18 05:48:11 PM PDT 24
Finished Aug 18 05:48:12 PM PDT 24
Peak memory 206348 kb
Host smart-6eaad41b-1d73-49fe-97bc-cada9c434659
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836350208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2836350208
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.305709750
Short name T988
Test name
Test status
Simulation time 153244854 ps
CPU time 0.88 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:17 PM PDT 24
Peak memory 206028 kb
Host smart-2d090ff7-97f8-4af6-b72b-2dd16391ab7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305709750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.305709750
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2183208831
Short name T962
Test name
Test status
Simulation time 87946599 ps
CPU time 1.6 seconds
Started Aug 18 05:48:14 PM PDT 24
Finished Aug 18 05:48:15 PM PDT 24
Peak memory 206316 kb
Host smart-fc001076-cdc4-4270-8607-0baf8b67644a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183208831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2183208831
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2427644067
Short name T1025
Test name
Test status
Simulation time 232616710 ps
CPU time 3.37 seconds
Started Aug 18 05:48:16 PM PDT 24
Finished Aug 18 05:48:19 PM PDT 24
Peak memory 214804 kb
Host smart-212da41e-bd12-4007-a625-4bb0d30dd23d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427644067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2427644067
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3176302899
Short name T943
Test name
Test status
Simulation time 617316345 ps
CPU time 3.8 seconds
Started Aug 18 05:48:13 PM PDT 24
Finished Aug 18 05:48:16 PM PDT 24
Peak memory 214588 kb
Host smart-e0b66b54-96f0-4547-93c9-acfbaff88ebd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176302899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3176302899
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1793979010
Short name T158
Test name
Test status
Simulation time 358459474 ps
CPU time 5.09 seconds
Started Aug 18 05:48:13 PM PDT 24
Finished Aug 18 05:48:18 PM PDT 24
Peak memory 214444 kb
Host smart-99771466-9128-48db-a14b-775b338424f4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793979010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1793979010
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3519677968
Short name T816
Test name
Test status
Simulation time 63550655 ps
CPU time 0.73 seconds
Started Aug 18 06:14:35 PM PDT 24
Finished Aug 18 06:14:35 PM PDT 24
Peak memory 206248 kb
Host smart-36cd545e-ae1c-4815-ba55-b2f3d23d9acd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519677968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3519677968
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.326455466
Short name T410
Test name
Test status
Simulation time 972386230 ps
CPU time 47.21 seconds
Started Aug 18 06:13:03 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 215180 kb
Host smart-040896f8-d608-4cd3-a445-161392efa72a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=326455466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.326455466
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3321306239
Short name T824
Test name
Test status
Simulation time 46908961 ps
CPU time 1.91 seconds
Started Aug 18 06:13:10 PM PDT 24
Finished Aug 18 06:13:12 PM PDT 24
Peak memory 217164 kb
Host smart-a88425b3-8275-429a-938a-d3e6a5f3c479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321306239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3321306239
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.996936569
Short name T904
Test name
Test status
Simulation time 255115273 ps
CPU time 3.36 seconds
Started Aug 18 06:13:04 PM PDT 24
Finished Aug 18 06:13:07 PM PDT 24
Peak memory 214860 kb
Host smart-001d5908-f10e-4a5f-9626-d151caf58d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996936569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.996936569
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.625251816
Short name T331
Test name
Test status
Simulation time 56983783 ps
CPU time 1.93 seconds
Started Aug 18 06:13:07 PM PDT 24
Finished Aug 18 06:13:09 PM PDT 24
Peak memory 215668 kb
Host smart-722fa285-01a4-4adb-b70a-58483223c71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625251816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.625251816
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3561240791
Short name T849
Test name
Test status
Simulation time 86550751 ps
CPU time 3.83 seconds
Started Aug 18 06:14:15 PM PDT 24
Finished Aug 18 06:14:19 PM PDT 24
Peak memory 213996 kb
Host smart-0545109a-5ff0-4ad5-970e-6d27b573831a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561240791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3561240791
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1910650020
Short name T211
Test name
Test status
Simulation time 168163441 ps
CPU time 2.85 seconds
Started Aug 18 06:13:28 PM PDT 24
Finished Aug 18 06:13:36 PM PDT 24
Peak memory 209588 kb
Host smart-5faa92ba-0133-48fc-9668-d001ab7d2a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910650020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1910650020
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.3318544166
Short name T228
Test name
Test status
Simulation time 106317730 ps
CPU time 4.5 seconds
Started Aug 18 06:13:09 PM PDT 24
Finished Aug 18 06:13:13 PM PDT 24
Peak memory 218928 kb
Host smart-fa1e1aee-4784-420e-a17e-70f14f4acea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318544166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.3318544166
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1298586291
Short name T13
Test name
Test status
Simulation time 426359977 ps
CPU time 9.68 seconds
Started Aug 18 06:14:15 PM PDT 24
Finished Aug 18 06:14:25 PM PDT 24
Peak memory 237412 kb
Host smart-6d50ac85-6bed-4e7e-947d-0575caaab826
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298586291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1298586291
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3363929917
Short name T776
Test name
Test status
Simulation time 204463831 ps
CPU time 5.76 seconds
Started Aug 18 06:14:34 PM PDT 24
Finished Aug 18 06:14:39 PM PDT 24
Peak memory 207104 kb
Host smart-6a83ae9d-d57e-42ae-b999-8bf41b131a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363929917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3363929917
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2634062704
Short name T646
Test name
Test status
Simulation time 80676755 ps
CPU time 3.43 seconds
Started Aug 18 06:13:35 PM PDT 24
Finished Aug 18 06:13:39 PM PDT 24
Peak memory 209048 kb
Host smart-8caf52dd-dcaf-4da0-b183-9d8b5e67619c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634062704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2634062704
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3067083265
Short name T808
Test name
Test status
Simulation time 34495005 ps
CPU time 2.27 seconds
Started Aug 18 06:13:04 PM PDT 24
Finished Aug 18 06:13:06 PM PDT 24
Peak memory 207572 kb
Host smart-9c3fd885-91ba-4b25-bb6a-96c4a18b4be8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067083265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3067083265
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3018268329
Short name T225
Test name
Test status
Simulation time 365205498 ps
CPU time 3.35 seconds
Started Aug 18 06:14:15 PM PDT 24
Finished Aug 18 06:14:19 PM PDT 24
Peak memory 205772 kb
Host smart-ec308d18-4c40-4577-b95e-993e10f5e863
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018268329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3018268329
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2720876441
Short name T407
Test name
Test status
Simulation time 1436285170 ps
CPU time 7.62 seconds
Started Aug 18 06:14:15 PM PDT 24
Finished Aug 18 06:14:28 PM PDT 24
Peak memory 208624 kb
Host smart-d907764f-5a12-40a9-b1dc-2bb6b772adc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720876441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2720876441
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.4263293678
Short name T473
Test name
Test status
Simulation time 73115878 ps
CPU time 3.08 seconds
Started Aug 18 06:13:04 PM PDT 24
Finished Aug 18 06:13:07 PM PDT 24
Peak memory 209052 kb
Host smart-01703879-87e0-44d9-a3b6-f43ef35e3698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263293678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.4263293678
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1819630027
Short name T469
Test name
Test status
Simulation time 1359108056 ps
CPU time 11.85 seconds
Started Aug 18 06:13:07 PM PDT 24
Finished Aug 18 06:13:19 PM PDT 24
Peak memory 215592 kb
Host smart-139cf4d1-cfee-4100-8b4b-ff270f579b66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819630027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1819630027
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2709710767
Short name T854
Test name
Test status
Simulation time 287499240 ps
CPU time 9.68 seconds
Started Aug 18 06:14:15 PM PDT 24
Finished Aug 18 06:14:26 PM PDT 24
Peak memory 222268 kb
Host smart-12d24e9b-d045-464f-93ff-05f55e7c9791
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709710767 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2709710767
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.326385615
Short name T377
Test name
Test status
Simulation time 97140437 ps
CPU time 1.6 seconds
Started Aug 18 06:14:35 PM PDT 24
Finished Aug 18 06:14:37 PM PDT 24
Peak memory 209084 kb
Host smart-eb7bdd2b-0102-4c06-af65-561568a36d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326385615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.326385615
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2645647597
Short name T614
Test name
Test status
Simulation time 11937644 ps
CPU time 0.82 seconds
Started Aug 18 06:13:06 PM PDT 24
Finished Aug 18 06:13:07 PM PDT 24
Peak memory 206416 kb
Host smart-a01ae8c7-e689-448e-9e83-86a785cb65f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645647597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2645647597
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2495860507
Short name T102
Test name
Test status
Simulation time 1118462162 ps
CPU time 15.47 seconds
Started Aug 18 06:13:06 PM PDT 24
Finished Aug 18 06:13:21 PM PDT 24
Peak memory 214796 kb
Host smart-a92062d3-504e-4a83-bd67-e58c7e5dac95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2495860507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2495860507
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.174436338
Short name T754
Test name
Test status
Simulation time 1466319849 ps
CPU time 6.57 seconds
Started Aug 18 06:13:06 PM PDT 24
Finished Aug 18 06:13:12 PM PDT 24
Peak memory 209496 kb
Host smart-7f187c73-cd7b-4dde-98e2-82ac3a3608ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174436338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.174436338
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3160384417
Short name T470
Test name
Test status
Simulation time 34084483 ps
CPU time 1.79 seconds
Started Aug 18 06:13:06 PM PDT 24
Finished Aug 18 06:13:08 PM PDT 24
Peak memory 208224 kb
Host smart-0bb013f5-e33e-432b-9d12-ed15ccbb0f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160384417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3160384417
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2865591921
Short name T237
Test name
Test status
Simulation time 168604969 ps
CPU time 1.71 seconds
Started Aug 18 06:13:08 PM PDT 24
Finished Aug 18 06:13:10 PM PDT 24
Peak memory 214724 kb
Host smart-ecb84d42-6c9f-48fe-aca6-ab9ee16cbca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865591921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2865591921
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.2298091667
Short name T299
Test name
Test status
Simulation time 104271340 ps
CPU time 4.95 seconds
Started Aug 18 06:13:08 PM PDT 24
Finished Aug 18 06:13:13 PM PDT 24
Peak memory 210660 kb
Host smart-e1f51ab2-f3b6-49a8-a538-60f0077f0ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298091667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.2298091667
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2390630196
Short name T447
Test name
Test status
Simulation time 54112910 ps
CPU time 2.91 seconds
Started Aug 18 06:13:14 PM PDT 24
Finished Aug 18 06:13:17 PM PDT 24
Peak memory 209536 kb
Host smart-8c21550c-653d-410d-893f-e88d13cd07ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390630196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2390630196
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2877231298
Short name T43
Test name
Test status
Simulation time 758881243 ps
CPU time 6.87 seconds
Started Aug 18 06:13:12 PM PDT 24
Finished Aug 18 06:13:19 PM PDT 24
Peak memory 238168 kb
Host smart-2d2fa74d-d06d-4f07-9b5b-ce95232e1b3b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877231298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2877231298
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4015397739
Short name T486
Test name
Test status
Simulation time 161067887 ps
CPU time 4.78 seconds
Started Aug 18 06:13:25 PM PDT 24
Finished Aug 18 06:13:30 PM PDT 24
Peak memory 207372 kb
Host smart-3f65a9e1-d3a8-4198-bf64-edfbffb122b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015397739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4015397739
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3888931353
Short name T691
Test name
Test status
Simulation time 83925760 ps
CPU time 1.86 seconds
Started Aug 18 06:13:12 PM PDT 24
Finished Aug 18 06:13:14 PM PDT 24
Peak memory 207728 kb
Host smart-fe5d7854-798d-4947-93c6-62ece9583f0a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888931353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3888931353
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2426328328
Short name T573
Test name
Test status
Simulation time 237692077 ps
CPU time 1.82 seconds
Started Aug 18 06:13:17 PM PDT 24
Finished Aug 18 06:13:19 PM PDT 24
Peak memory 207436 kb
Host smart-7ee4a775-5b2f-4746-8ce2-7bf268f28164
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426328328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2426328328
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.4290321742
Short name T779
Test name
Test status
Simulation time 923921718 ps
CPU time 7.52 seconds
Started Aug 18 06:13:05 PM PDT 24
Finished Aug 18 06:13:12 PM PDT 24
Peak memory 209336 kb
Host smart-e3463240-7b4d-4e6a-b70e-41010bad0d6b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290321742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.4290321742
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1524322676
Short name T93
Test name
Test status
Simulation time 113504278 ps
CPU time 3.6 seconds
Started Aug 18 06:13:13 PM PDT 24
Finished Aug 18 06:13:22 PM PDT 24
Peak memory 210788 kb
Host smart-d268b8d8-2f46-4dbc-9102-93bfe97bb4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524322676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1524322676
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1151128531
Short name T454
Test name
Test status
Simulation time 58148692 ps
CPU time 2.24 seconds
Started Aug 18 06:14:31 PM PDT 24
Finished Aug 18 06:14:34 PM PDT 24
Peak memory 207152 kb
Host smart-b2dc648f-30c3-45b8-a6cb-2af79aa8e3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151128531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1151128531
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3293627623
Short name T304
Test name
Test status
Simulation time 287708105 ps
CPU time 4.69 seconds
Started Aug 18 06:13:23 PM PDT 24
Finished Aug 18 06:13:28 PM PDT 24
Peak memory 220340 kb
Host smart-01237bf6-1bad-4d02-aa59-87ccd9f71716
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293627623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3293627623
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3413270770
Short name T563
Test name
Test status
Simulation time 71256388 ps
CPU time 3.82 seconds
Started Aug 18 06:13:26 PM PDT 24
Finished Aug 18 06:13:30 PM PDT 24
Peak memory 208656 kb
Host smart-2c44ae93-cd56-4eaa-b3dc-89331e4438b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413270770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3413270770
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.77120936
Short name T182
Test name
Test status
Simulation time 1107069154 ps
CPU time 11.45 seconds
Started Aug 18 06:13:06 PM PDT 24
Finished Aug 18 06:13:17 PM PDT 24
Peak memory 211488 kb
Host smart-6c0dabb5-0882-4a36-8a3b-9b9e75fe354e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77120936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.77120936
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3964543257
Short name T757
Test name
Test status
Simulation time 9006068 ps
CPU time 0.74 seconds
Started Aug 18 06:13:42 PM PDT 24
Finished Aug 18 06:13:43 PM PDT 24
Peak memory 206420 kb
Host smart-69e91825-2d5d-4f13-97f8-33f44b4ce752
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964543257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3964543257
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2529628374
Short name T421
Test name
Test status
Simulation time 46248521 ps
CPU time 3.21 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 215684 kb
Host smart-557b881b-49a7-4353-b829-d7168f3fb814
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2529628374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2529628374
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.4240732687
Short name T561
Test name
Test status
Simulation time 127975945 ps
CPU time 1.7 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:53 PM PDT 24
Peak memory 210092 kb
Host smart-f318692b-f02c-4b88-8dc2-d4309bf0be68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240732687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.4240732687
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2930344379
Short name T489
Test name
Test status
Simulation time 171989700 ps
CPU time 2.11 seconds
Started Aug 18 06:13:40 PM PDT 24
Finished Aug 18 06:13:42 PM PDT 24
Peak memory 207644 kb
Host smart-354c6b38-b17e-4225-a5e2-5f6226b148e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930344379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2930344379
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.2251187110
Short name T873
Test name
Test status
Simulation time 227225020 ps
CPU time 4.78 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 207540 kb
Host smart-67920df7-e0dc-45f0-95c5-7ca892ee07da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251187110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.2251187110
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1705051813
Short name T222
Test name
Test status
Simulation time 103561617 ps
CPU time 3.67 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 208380 kb
Host smart-c69aceb0-efbe-4515-a0c2-c7c1f453ae17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705051813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1705051813
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3370486486
Short name T412
Test name
Test status
Simulation time 439927724 ps
CPU time 5.07 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 208080 kb
Host smart-94048804-d109-4502-a87e-85c12f4b6bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370486486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3370486486
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.496279528
Short name T657
Test name
Test status
Simulation time 1096533271 ps
CPU time 28.68 seconds
Started Aug 18 06:13:43 PM PDT 24
Finished Aug 18 06:14:11 PM PDT 24
Peak memory 209072 kb
Host smart-f4c17899-fde6-47d9-b977-954de56ca250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496279528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.496279528
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.23990536
Short name T707
Test name
Test status
Simulation time 101241589 ps
CPU time 2.95 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 207484 kb
Host smart-fbb0047f-60da-4a47-a37d-29ff9001264f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23990536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.23990536
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1064986408
Short name T493
Test name
Test status
Simulation time 836430062 ps
CPU time 3.33 seconds
Started Aug 18 06:13:38 PM PDT 24
Finished Aug 18 06:13:42 PM PDT 24
Peak memory 207460 kb
Host smart-2b3b50c7-3f58-48bd-924a-6270431dd279
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064986408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1064986408
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3103188308
Short name T3
Test name
Test status
Simulation time 827345530 ps
CPU time 5.83 seconds
Started Aug 18 06:13:44 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 208460 kb
Host smart-34010a86-9826-45fe-907d-7f5bf908770d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103188308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3103188308
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.656976973
Short name T907
Test name
Test status
Simulation time 379609988 ps
CPU time 4.07 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:56 PM PDT 24
Peak memory 214776 kb
Host smart-67517f10-6843-4659-8db9-53e1c7466629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656976973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.656976973
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3394722331
Short name T448
Test name
Test status
Simulation time 404362374 ps
CPU time 2.28 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 207408 kb
Host smart-871a3233-5f46-4f84-9898-34b8747c0d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394722331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3394722331
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2744173725
Short name T821
Test name
Test status
Simulation time 227982661 ps
CPU time 3.38 seconds
Started Aug 18 06:13:45 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 207884 kb
Host smart-f25c5513-2782-44ce-a92e-75e978054257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744173725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2744173725
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2174912074
Short name T376
Test name
Test status
Simulation time 65502780 ps
CPU time 2.01 seconds
Started Aug 18 06:14:00 PM PDT 24
Finished Aug 18 06:14:03 PM PDT 24
Peak memory 210596 kb
Host smart-f1dd1536-6890-4d42-bacb-7248360a336e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174912074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2174912074
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.4132526898
Short name T137
Test name
Test status
Simulation time 305849926 ps
CPU time 7.73 seconds
Started Aug 18 06:13:38 PM PDT 24
Finished Aug 18 06:13:46 PM PDT 24
Peak memory 208760 kb
Host smart-4ccb76bd-adba-4b42-9c58-0b4ec890c8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132526898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.4132526898
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1686032053
Short name T876
Test name
Test status
Simulation time 1142490543 ps
CPU time 5.66 seconds
Started Aug 18 06:13:42 PM PDT 24
Finished Aug 18 06:13:47 PM PDT 24
Peak memory 214772 kb
Host smart-d5eeceb1-88f7-4118-976c-c2d6f1c84dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686032053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1686032053
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3248993054
Short name T368
Test name
Test status
Simulation time 155395135 ps
CPU time 6.31 seconds
Started Aug 18 06:14:05 PM PDT 24
Finished Aug 18 06:14:11 PM PDT 24
Peak memory 222900 kb
Host smart-4154dd97-3496-4f94-9a57-186f6efd89c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248993054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3248993054
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2389271854
Short name T739
Test name
Test status
Simulation time 46417289 ps
CPU time 3.24 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 209700 kb
Host smart-c28e1e30-8568-4627-9b3c-885f576f422a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389271854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2389271854
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.214173053
Short name T786
Test name
Test status
Simulation time 82877875 ps
CPU time 3.93 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 208000 kb
Host smart-c24418e8-38c2-4f92-bd1f-4bc01a2f5f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214173053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.214173053
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.1308831286
Short name T488
Test name
Test status
Simulation time 38825139 ps
CPU time 2.36 seconds
Started Aug 18 06:14:01 PM PDT 24
Finished Aug 18 06:14:04 PM PDT 24
Peak memory 207472 kb
Host smart-e46817e3-46b9-4f6d-ab9c-b22f950195a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308831286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.1308831286
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.434947117
Short name T344
Test name
Test status
Simulation time 242917223 ps
CPU time 6.13 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:58 PM PDT 24
Peak memory 209144 kb
Host smart-6b625837-8c77-42e0-8a30-78c09224e546
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434947117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.434947117
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1624144811
Short name T648
Test name
Test status
Simulation time 537794185 ps
CPU time 3.19 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 209924 kb
Host smart-af1f2a11-b4ce-4035-95a8-f5b1843965a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624144811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1624144811
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1671432172
Short name T571
Test name
Test status
Simulation time 84839589 ps
CPU time 2.64 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:48 PM PDT 24
Peak memory 207320 kb
Host smart-e418ce0c-a70e-4651-b5fe-5ba598984436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671432172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1671432172
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.4130083982
Short name T208
Test name
Test status
Simulation time 1691636916 ps
CPU time 12.64 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:14:04 PM PDT 24
Peak memory 215552 kb
Host smart-dc1880ac-975f-4f5a-9bc1-d126ecaae444
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130083982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.4130083982
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2103833425
Short name T699
Test name
Test status
Simulation time 171165385 ps
CPU time 7.22 seconds
Started Aug 18 06:13:44 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 208620 kb
Host smart-26c8fafe-5f73-4348-9ab8-5a2099f052fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103833425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2103833425
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.205239342
Short name T740
Test name
Test status
Simulation time 94042179 ps
CPU time 1.3 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 210080 kb
Host smart-f32a31da-6f25-4e88-acff-0c80388a32e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205239342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.205239342
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3952922144
Short name T542
Test name
Test status
Simulation time 42949898 ps
CPU time 0.86 seconds
Started Aug 18 06:13:52 PM PDT 24
Finished Aug 18 06:13:53 PM PDT 24
Peak memory 206300 kb
Host smart-a338af69-b764-494e-888b-2e355397a295
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952922144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3952922144
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1569879104
Short name T566
Test name
Test status
Simulation time 29179314 ps
CPU time 1.47 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:48 PM PDT 24
Peak memory 209492 kb
Host smart-76119828-da4c-439a-9947-0f17900ed794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569879104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1569879104
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1483193650
Short name T51
Test name
Test status
Simulation time 450841362 ps
CPU time 4.52 seconds
Started Aug 18 06:13:53 PM PDT 24
Finished Aug 18 06:13:58 PM PDT 24
Peak memory 221572 kb
Host smart-9cc14f23-7f72-417a-aac9-7ac54118ee71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483193650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1483193650
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2202207262
Short name T732
Test name
Test status
Simulation time 146402530 ps
CPU time 3.97 seconds
Started Aug 18 06:14:05 PM PDT 24
Finished Aug 18 06:14:09 PM PDT 24
Peak memory 209384 kb
Host smart-c57dde8a-80f0-4b0f-b940-41eb69d64c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202207262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2202207262
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3708261296
Short name T653
Test name
Test status
Simulation time 581046054 ps
CPU time 7.01 seconds
Started Aug 18 06:13:49 PM PDT 24
Finished Aug 18 06:13:57 PM PDT 24
Peak memory 210732 kb
Host smart-7b63a792-6d29-4da0-9751-1f29dbac46d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708261296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3708261296
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1349875486
Short name T462
Test name
Test status
Simulation time 830345637 ps
CPU time 5.77 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 209104 kb
Host smart-eb612c0a-ac0e-481d-aa29-4000b4f072a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349875486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1349875486
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3722503754
Short name T349
Test name
Test status
Simulation time 445862355 ps
CPU time 6.04 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:58 PM PDT 24
Peak memory 209024 kb
Host smart-d4f76622-285b-4ba4-ad4c-7497ed9ed52d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722503754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3722503754
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3726561912
Short name T305
Test name
Test status
Simulation time 5541874674 ps
CPU time 9.32 seconds
Started Aug 18 06:13:41 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 208752 kb
Host smart-7d9fb874-6cab-47f6-a3d1-b4d2ae91c41d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726561912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3726561912
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2075346010
Short name T16
Test name
Test status
Simulation time 1704182034 ps
CPU time 43.77 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:14:36 PM PDT 24
Peak memory 208300 kb
Host smart-ae743255-337f-42ab-950f-ba9b3375e4c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075346010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2075346010
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.307712778
Short name T284
Test name
Test status
Simulation time 51469458 ps
CPU time 2.81 seconds
Started Aug 18 06:13:44 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 209936 kb
Host smart-848ab123-6996-4b93-988f-29c767297f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307712778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.307712778
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3433507213
Short name T677
Test name
Test status
Simulation time 60983659 ps
CPU time 2.17 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 207304 kb
Host smart-58fbac66-f174-4e79-876f-0e267afeac8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433507213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3433507213
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.2364630621
Short name T289
Test name
Test status
Simulation time 144234247 ps
CPU time 5.52 seconds
Started Aug 18 06:13:43 PM PDT 24
Finished Aug 18 06:13:48 PM PDT 24
Peak memory 214796 kb
Host smart-92cafca2-420f-4460-8488-473ac69e68de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364630621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.2364630621
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.226496513
Short name T523
Test name
Test status
Simulation time 67704451 ps
CPU time 2.68 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:54 PM PDT 24
Peak memory 210792 kb
Host smart-ffb51011-e69c-481e-94d1-21e46be6a142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226496513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.226496513
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1888533675
Short name T637
Test name
Test status
Simulation time 25633906 ps
CPU time 0.76 seconds
Started Aug 18 06:13:50 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 206404 kb
Host smart-c37abab6-d006-4b04-bcb0-4f200aa0eaac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888533675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1888533675
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3054704867
Short name T301
Test name
Test status
Simulation time 39231366 ps
CPU time 2.68 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:55 PM PDT 24
Peak memory 215772 kb
Host smart-76364839-3862-4613-8c0f-614f68e73afd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3054704867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3054704867
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.945478926
Short name T760
Test name
Test status
Simulation time 169583326 ps
CPU time 3.48 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 217528 kb
Host smart-444072b5-d4d6-4b38-98f1-868f23d74e2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945478926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.945478926
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.141555113
Short name T679
Test name
Test status
Simulation time 28765401 ps
CPU time 1.95 seconds
Started Aug 18 06:13:52 PM PDT 24
Finished Aug 18 06:13:54 PM PDT 24
Peak memory 207688 kb
Host smart-5278d0b3-d2e9-46aa-9099-e8ae073714da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141555113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.141555113
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1922505110
Short name T897
Test name
Test status
Simulation time 146629831 ps
CPU time 6.11 seconds
Started Aug 18 06:13:54 PM PDT 24
Finished Aug 18 06:14:00 PM PDT 24
Peak memory 216000 kb
Host smart-eca3ec12-59a4-43f5-bdc6-a4300a32a033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922505110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1922505110
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1332663715
Short name T696
Test name
Test status
Simulation time 91619712 ps
CPU time 1.64 seconds
Started Aug 18 06:14:00 PM PDT 24
Finished Aug 18 06:14:02 PM PDT 24
Peak memory 206856 kb
Host smart-e18df48e-0bbe-4e47-bed1-ef28bdba260c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332663715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1332663715
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.3708077565
Short name T230
Test name
Test status
Simulation time 124538472 ps
CPU time 3.13 seconds
Started Aug 18 06:13:49 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 208024 kb
Host smart-f7d3ae0f-36f7-4a73-9ca7-17c30033439f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708077565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.3708077565
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1574131532
Short name T771
Test name
Test status
Simulation time 2022550153 ps
CPU time 39.95 seconds
Started Aug 18 06:14:21 PM PDT 24
Finished Aug 18 06:15:01 PM PDT 24
Peak memory 208528 kb
Host smart-93732014-c1e1-4a93-927d-6da05407f428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574131532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1574131532
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.329285175
Short name T659
Test name
Test status
Simulation time 19346520 ps
CPU time 1.72 seconds
Started Aug 18 06:13:49 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 207396 kb
Host smart-fdb90d9d-b907-48b5-b0ca-d9181143775f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329285175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.329285175
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2422782343
Short name T688
Test name
Test status
Simulation time 490657811 ps
CPU time 2.74 seconds
Started Aug 18 06:13:53 PM PDT 24
Finished Aug 18 06:14:01 PM PDT 24
Peak memory 207444 kb
Host smart-502ca97a-6746-463a-af2b-f0f4a88ece97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422782343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2422782343
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1597803150
Short name T719
Test name
Test status
Simulation time 907251401 ps
CPU time 7.63 seconds
Started Aug 18 06:14:01 PM PDT 24
Finished Aug 18 06:14:08 PM PDT 24
Peak memory 209108 kb
Host smart-b27843b4-af2d-47c4-b6b2-d807ef6b757f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597803150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1597803150
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2360338535
Short name T767
Test name
Test status
Simulation time 275766715 ps
CPU time 4.84 seconds
Started Aug 18 06:14:03 PM PDT 24
Finished Aug 18 06:14:08 PM PDT 24
Peak memory 214880 kb
Host smart-d09db515-ab4a-480a-96a9-de318c0f802a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360338535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2360338535
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2722719382
Short name T391
Test name
Test status
Simulation time 35809686 ps
CPU time 2.33 seconds
Started Aug 18 06:13:49 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 207324 kb
Host smart-ac4f42e0-f0aa-4ed1-8e05-f61abb775952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722719382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2722719382
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1424876182
Short name T183
Test name
Test status
Simulation time 57824660 ps
CPU time 0.81 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:48 PM PDT 24
Peak memory 206424 kb
Host smart-2ab9c994-0b5c-4f5d-bac1-6d22a00c1a8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424876182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1424876182
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3595205875
Short name T529
Test name
Test status
Simulation time 298933468 ps
CPU time 3.83 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:55 PM PDT 24
Peak memory 218924 kb
Host smart-9ba7553f-259b-48b9-a834-6c1770058e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595205875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3595205875
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.816436516
Short name T484
Test name
Test status
Simulation time 927470379 ps
CPU time 12.01 seconds
Started Aug 18 06:13:52 PM PDT 24
Finished Aug 18 06:14:04 PM PDT 24
Peak memory 211536 kb
Host smart-c1ed2c36-2932-4e21-b45a-83e74810ccb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816436516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.816436516
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.4091765498
Short name T912
Test name
Test status
Simulation time 60304830 ps
CPU time 0.77 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 206424 kb
Host smart-673c2e79-1970-48d6-9253-ec245c707c92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091765498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4091765498
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1944252844
Short name T632
Test name
Test status
Simulation time 463618173 ps
CPU time 2.88 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 222100 kb
Host smart-99e622b6-e2e8-4045-8afe-31ad61209539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944252844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1944252844
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2027895059
Short name T68
Test name
Test status
Simulation time 89319904 ps
CPU time 3.71 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:55 PM PDT 24
Peak memory 210208 kb
Host smart-9c4e4d83-0870-4b0b-878f-e040433d6aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027895059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2027895059
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1323633170
Short name T373
Test name
Test status
Simulation time 111372313 ps
CPU time 2.42 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 222632 kb
Host smart-04b62856-ce9a-4d22-a6b0-ec0dd404aae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323633170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1323633170
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2133384994
Short name T234
Test name
Test status
Simulation time 71632727 ps
CPU time 1.7 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:53 PM PDT 24
Peak memory 214708 kb
Host smart-6cacf3ec-ff18-4645-a5ee-d0ca165a10b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133384994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2133384994
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.4123645864
Short name T103
Test name
Test status
Simulation time 1681069176 ps
CPU time 25.46 seconds
Started Aug 18 06:14:00 PM PDT 24
Finished Aug 18 06:14:26 PM PDT 24
Peak memory 222900 kb
Host smart-a908afd0-d00c-465c-98b0-de761bc102cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123645864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.4123645864
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3799452034
Short name T826
Test name
Test status
Simulation time 435959152 ps
CPU time 3.63 seconds
Started Aug 18 06:13:55 PM PDT 24
Finished Aug 18 06:13:59 PM PDT 24
Peak memory 207364 kb
Host smart-f27f2ce3-a9bd-40e1-8ff4-e433d1fe1139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799452034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3799452034
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1158052260
Short name T801
Test name
Test status
Simulation time 131129345 ps
CPU time 2.4 seconds
Started Aug 18 06:13:49 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 208952 kb
Host smart-cd4f0690-06f6-4e1f-90e6-8575452f80ab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158052260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1158052260
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2302816375
Short name T147
Test name
Test status
Simulation time 399455288 ps
CPU time 3.07 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 209248 kb
Host smart-0f1550a0-73bd-4582-86b5-3e191d364ffc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302816375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2302816375
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3991267495
Short name T536
Test name
Test status
Simulation time 401218630 ps
CPU time 9.88 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:14:02 PM PDT 24
Peak memory 214836 kb
Host smart-5820aa44-7aec-4dc9-bd77-b6553132c979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991267495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3991267495
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2990145983
Short name T811
Test name
Test status
Simulation time 21143015 ps
CPU time 1.68 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:48 PM PDT 24
Peak memory 207444 kb
Host smart-60008550-61f0-4b34-83f7-0763b5b2ff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990145983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2990145983
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3222351653
Short name T226
Test name
Test status
Simulation time 293527226 ps
CPU time 3.56 seconds
Started Aug 18 06:14:02 PM PDT 24
Finished Aug 18 06:14:06 PM PDT 24
Peak memory 210240 kb
Host smart-83ae2755-901a-4c5e-b173-bbf31f02b618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222351653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3222351653
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2133571708
Short name T647
Test name
Test status
Simulation time 115509321 ps
CPU time 0.85 seconds
Started Aug 18 06:13:59 PM PDT 24
Finished Aug 18 06:14:00 PM PDT 24
Peak memory 206444 kb
Host smart-b96a9fb5-8e50-4467-9d18-e96488e6fe20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133571708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2133571708
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1397360549
Short name T244
Test name
Test status
Simulation time 102228899 ps
CPU time 2.25 seconds
Started Aug 18 06:13:54 PM PDT 24
Finished Aug 18 06:13:56 PM PDT 24
Peak memory 214776 kb
Host smart-994b346c-bb24-420e-a67c-d0946a3901f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397360549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1397360549
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2551182858
Short name T560
Test name
Test status
Simulation time 204800914 ps
CPU time 2.14 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 214728 kb
Host smart-6370810f-6122-4daa-9f8b-623df345d219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551182858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2551182858
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3172421488
Short name T651
Test name
Test status
Simulation time 164812078 ps
CPU time 2.13 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:54 PM PDT 24
Peak memory 214736 kb
Host smart-3f8f6f4b-50df-41fb-828a-0ad3d9d4f1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172421488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3172421488
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3688468635
Short name T877
Test name
Test status
Simulation time 430289336 ps
CPU time 5.47 seconds
Started Aug 18 06:13:50 PM PDT 24
Finished Aug 18 06:13:57 PM PDT 24
Peak memory 222904 kb
Host smart-e8c9169c-991d-4d68-a817-05242c2458ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688468635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3688468635
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.1527667424
Short name T783
Test name
Test status
Simulation time 4100334682 ps
CPU time 22.41 seconds
Started Aug 18 06:13:58 PM PDT 24
Finished Aug 18 06:14:20 PM PDT 24
Peak memory 209024 kb
Host smart-dd8f2328-4d35-480e-9dd4-9f48494f8d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527667424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1527667424
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2278966514
Short name T282
Test name
Test status
Simulation time 340320529 ps
CPU time 3.36 seconds
Started Aug 18 06:14:03 PM PDT 24
Finished Aug 18 06:14:06 PM PDT 24
Peak memory 209048 kb
Host smart-bcc35120-e8e7-468b-a752-ecb0f0acd115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278966514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2278966514
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.957908156
Short name T361
Test name
Test status
Simulation time 128871157 ps
CPU time 2.34 seconds
Started Aug 18 06:13:56 PM PDT 24
Finished Aug 18 06:13:59 PM PDT 24
Peak memory 207304 kb
Host smart-edf4e180-4330-4fa7-8b62-666614abb758
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957908156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.957908156
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1371645163
Short name T596
Test name
Test status
Simulation time 69411229 ps
CPU time 3.38 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:55 PM PDT 24
Peak memory 209440 kb
Host smart-25b3d409-01d9-40bb-9681-5cdc307eab39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371645163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1371645163
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.547466788
Short name T893
Test name
Test status
Simulation time 402263296 ps
CPU time 5.24 seconds
Started Aug 18 06:13:52 PM PDT 24
Finished Aug 18 06:13:57 PM PDT 24
Peak memory 209044 kb
Host smart-6177c121-077e-4184-9d33-532370e6c0ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547466788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.547466788
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.245973175
Short name T738
Test name
Test status
Simulation time 65266559 ps
CPU time 2.81 seconds
Started Aug 18 06:13:56 PM PDT 24
Finished Aug 18 06:13:59 PM PDT 24
Peak memory 209104 kb
Host smart-3970f169-1f2b-44c4-baf1-c55fdf213e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245973175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.245973175
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2934822951
Short name T532
Test name
Test status
Simulation time 38467511 ps
CPU time 2.12 seconds
Started Aug 18 06:13:57 PM PDT 24
Finished Aug 18 06:14:00 PM PDT 24
Peak memory 207420 kb
Host smart-1a3013e4-0679-4f7b-bf04-d2b27050b9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934822951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2934822951
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.349229559
Short name T667
Test name
Test status
Simulation time 610991546 ps
CPU time 19.39 seconds
Started Aug 18 06:14:12 PM PDT 24
Finished Aug 18 06:14:32 PM PDT 24
Peak memory 214816 kb
Host smart-1b65edc9-14ae-48c3-b1d5-0ed5d1fcc6eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349229559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.349229559
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.614665998
Short name T72
Test name
Test status
Simulation time 370780402 ps
CPU time 7.08 seconds
Started Aug 18 06:14:03 PM PDT 24
Finished Aug 18 06:14:10 PM PDT 24
Peak memory 219540 kb
Host smart-44be9e71-0bea-4bdb-b349-fcf3466d8b84
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614665998 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.614665998
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.1405079676
Short name T669
Test name
Test status
Simulation time 843043269 ps
CPU time 5.88 seconds
Started Aug 18 06:14:04 PM PDT 24
Finished Aug 18 06:14:10 PM PDT 24
Peak memory 210436 kb
Host smart-0a0069ba-5175-489e-9c71-b11f7e3e8b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405079676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.1405079676
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3609561751
Short name T789
Test name
Test status
Simulation time 50869718 ps
CPU time 1.64 seconds
Started Aug 18 06:13:52 PM PDT 24
Finished Aug 18 06:13:54 PM PDT 24
Peak memory 210044 kb
Host smart-98e5a105-9b48-432d-afc0-0e958b10faec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609561751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3609561751
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1063941110
Short name T174
Test name
Test status
Simulation time 26611049 ps
CPU time 0.77 seconds
Started Aug 18 06:13:50 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 206392 kb
Host smart-9115332f-d93b-4fd3-bf92-feaaa43c541a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063941110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1063941110
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1190990693
Short name T40
Test name
Test status
Simulation time 367625417 ps
CPU time 5.41 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:57 PM PDT 24
Peak memory 210236 kb
Host smart-388ed488-d97d-4f59-80de-142ad5f4b09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190990693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1190990693
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2421278866
Short name T594
Test name
Test status
Simulation time 167522286 ps
CPU time 2.39 seconds
Started Aug 18 06:14:09 PM PDT 24
Finished Aug 18 06:14:11 PM PDT 24
Peak memory 210336 kb
Host smart-18fc3c14-4235-45ce-992c-f4601701fd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421278866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2421278866
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2897194298
Short name T259
Test name
Test status
Simulation time 306961316 ps
CPU time 3.28 seconds
Started Aug 18 06:14:08 PM PDT 24
Finished Aug 18 06:14:12 PM PDT 24
Peak memory 222852 kb
Host smart-e1685bde-e616-492a-a2f4-31312ebe6f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897194298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2897194298
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.79488964
Short name T129
Test name
Test status
Simulation time 26635845 ps
CPU time 2.18 seconds
Started Aug 18 06:13:50 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 216100 kb
Host smart-50236f89-9b06-46d0-bb78-565b416808ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=79488964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.79488964
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.951646304
Short name T516
Test name
Test status
Simulation time 287483826 ps
CPU time 3.7 seconds
Started Aug 18 06:13:59 PM PDT 24
Finished Aug 18 06:14:08 PM PDT 24
Peak memory 208544 kb
Host smart-7878fb35-1d15-40a6-b355-e1f9e325b1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951646304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.951646304
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.138771645
Short name T805
Test name
Test status
Simulation time 148692455 ps
CPU time 4.65 seconds
Started Aug 18 06:14:00 PM PDT 24
Finished Aug 18 06:14:05 PM PDT 24
Peak memory 209108 kb
Host smart-9b493ed8-0ef4-4254-8b4a-7e7525bab060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138771645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.138771645
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2483142069
Short name T729
Test name
Test status
Simulation time 172857508 ps
CPU time 2.91 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 207424 kb
Host smart-2c9ba484-48b0-4e68-94bd-e9e325be03b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483142069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2483142069
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.4059500659
Short name T606
Test name
Test status
Simulation time 405121220 ps
CPU time 3.4 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 209348 kb
Host smart-8e5c8975-6b72-40b1-8add-32bfec797fad
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059500659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.4059500659
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.4127169111
Short name T685
Test name
Test status
Simulation time 58801892 ps
CPU time 2.24 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 207336 kb
Host smart-d3761925-26a9-45d2-8d13-850f6e1cf706
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4127169111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.4127169111
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.4019911395
Short name T840
Test name
Test status
Simulation time 114432164 ps
CPU time 2.03 seconds
Started Aug 18 06:14:11 PM PDT 24
Finished Aug 18 06:14:13 PM PDT 24
Peak memory 209220 kb
Host smart-4bc4968d-3be3-4188-9e9e-da41eb922b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019911395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.4019911395
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2057895682
Short name T394
Test name
Test status
Simulation time 475030306 ps
CPU time 5.38 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 208908 kb
Host smart-a07d6032-c3c8-484f-9482-c20d05def8a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057895682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2057895682
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.4172514043
Short name T296
Test name
Test status
Simulation time 2023300128 ps
CPU time 6.62 seconds
Started Aug 18 06:13:49 PM PDT 24
Finished Aug 18 06:13:56 PM PDT 24
Peak memory 214760 kb
Host smart-716108b6-ae66-4770-991e-8d40c234990f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172514043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.4172514043
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2543765406
Short name T852
Test name
Test status
Simulation time 26746147 ps
CPU time 0.85 seconds
Started Aug 18 06:13:56 PM PDT 24
Finished Aug 18 06:13:58 PM PDT 24
Peak memory 206424 kb
Host smart-fcf0dea2-ac33-4bd7-a6ae-012c52451a99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543765406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2543765406
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2852061284
Short name T422
Test name
Test status
Simulation time 234055592 ps
CPU time 2.83 seconds
Started Aug 18 06:14:03 PM PDT 24
Finished Aug 18 06:14:06 PM PDT 24
Peak memory 215456 kb
Host smart-78cb2026-932e-4a34-82d5-18f1b1598ed2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2852061284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2852061284
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.630423314
Short name T338
Test name
Test status
Simulation time 137224038 ps
CPU time 3.41 seconds
Started Aug 18 06:14:00 PM PDT 24
Finished Aug 18 06:14:03 PM PDT 24
Peak memory 221748 kb
Host smart-941b475b-363d-456e-8594-04a1d6fa6927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630423314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.630423314
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3560805534
Short name T390
Test name
Test status
Simulation time 1162848755 ps
CPU time 2.93 seconds
Started Aug 18 06:14:10 PM PDT 24
Finished Aug 18 06:14:13 PM PDT 24
Peak memory 218832 kb
Host smart-b8a2a835-c527-410b-8d96-4be31c80ed32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560805534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3560805534
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.1587941974
Short name T56
Test name
Test status
Simulation time 1415742104 ps
CPU time 5.07 seconds
Started Aug 18 06:14:03 PM PDT 24
Finished Aug 18 06:14:08 PM PDT 24
Peak memory 209720 kb
Host smart-230997d4-f405-4d01-ae52-916b07c84772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587941974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.1587941974
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.4134879249
Short name T177
Test name
Test status
Simulation time 77122185 ps
CPU time 1.66 seconds
Started Aug 18 06:14:00 PM PDT 24
Finished Aug 18 06:14:02 PM PDT 24
Peak memory 214756 kb
Host smart-e098587e-3472-45b3-a588-e6f90ad6c3bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134879249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.4134879249
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2710334810
Short name T360
Test name
Test status
Simulation time 1081532182 ps
CPU time 4.61 seconds
Started Aug 18 06:14:18 PM PDT 24
Finished Aug 18 06:14:23 PM PDT 24
Peak memory 220836 kb
Host smart-fc70a66f-50dd-43a9-b406-ac2938a1873e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710334810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2710334810
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2826957259
Short name T517
Test name
Test status
Simulation time 51047498 ps
CPU time 3.49 seconds
Started Aug 18 06:13:57 PM PDT 24
Finished Aug 18 06:14:00 PM PDT 24
Peak memory 208580 kb
Host smart-1708e14d-0407-45f6-9e55-95c0b0fed307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826957259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2826957259
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1326865137
Short name T780
Test name
Test status
Simulation time 1172858172 ps
CPU time 7.01 seconds
Started Aug 18 06:13:58 PM PDT 24
Finished Aug 18 06:14:05 PM PDT 24
Peak memory 209112 kb
Host smart-106a6411-fc51-438e-9c04-6efd9dc681bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326865137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1326865137
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.941952225
Short name T798
Test name
Test status
Simulation time 367223083 ps
CPU time 3.19 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 207228 kb
Host smart-82b7c841-2828-43f9-a01a-a6a72ae73685
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941952225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.941952225
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.62354667
Short name T439
Test name
Test status
Simulation time 35369529 ps
CPU time 2.15 seconds
Started Aug 18 06:14:00 PM PDT 24
Finished Aug 18 06:14:02 PM PDT 24
Peak memory 207388 kb
Host smart-b5435713-17a2-4b7f-9e15-e598953d987b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62354667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.62354667
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1660770795
Short name T728
Test name
Test status
Simulation time 194011874 ps
CPU time 2.98 seconds
Started Aug 18 06:14:13 PM PDT 24
Finished Aug 18 06:14:16 PM PDT 24
Peak memory 209204 kb
Host smart-ad45fd94-e075-4935-bd94-d90f57433574
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660770795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1660770795
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.4178774900
Short name T727
Test name
Test status
Simulation time 268574483 ps
CPU time 4.52 seconds
Started Aug 18 06:14:01 PM PDT 24
Finished Aug 18 06:14:05 PM PDT 24
Peak memory 209948 kb
Host smart-879d9a06-daee-4128-998e-081a5f122fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178774900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.4178774900
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3651105164
Short name T656
Test name
Test status
Simulation time 258572144 ps
CPU time 3.23 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 207580 kb
Host smart-29c35f54-0c7d-4109-ac5e-3b20078846c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651105164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3651105164
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2833342396
Short name T185
Test name
Test status
Simulation time 8985634754 ps
CPU time 58.02 seconds
Started Aug 18 06:14:02 PM PDT 24
Finished Aug 18 06:15:00 PM PDT 24
Peak memory 216300 kb
Host smart-9871f363-2bf5-4712-8a14-cc4d63ab54a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833342396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2833342396
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2235034826
Short name T312
Test name
Test status
Simulation time 1245727457 ps
CPU time 19.46 seconds
Started Aug 18 06:13:53 PM PDT 24
Finished Aug 18 06:14:13 PM PDT 24
Peak memory 223004 kb
Host smart-aabfd3d9-f823-4fd6-aeb1-eebf55c0a9ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235034826 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2235034826
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.551656451
Short name T539
Test name
Test status
Simulation time 246818564 ps
CPU time 4.52 seconds
Started Aug 18 06:13:55 PM PDT 24
Finished Aug 18 06:14:00 PM PDT 24
Peak memory 208700 kb
Host smart-fe2b0728-86e2-46b3-afeb-bd534f7b4a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551656451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.551656451
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3923113175
Short name T716
Test name
Test status
Simulation time 376071190 ps
CPU time 3.26 seconds
Started Aug 18 06:13:58 PM PDT 24
Finished Aug 18 06:14:02 PM PDT 24
Peak memory 211032 kb
Host smart-4cba5a37-071a-4dc6-b958-57923671bdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923113175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3923113175
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.363804275
Short name T590
Test name
Test status
Simulation time 13858388 ps
CPU time 0.74 seconds
Started Aug 18 06:13:57 PM PDT 24
Finished Aug 18 06:13:58 PM PDT 24
Peak memory 206388 kb
Host smart-4eba37ba-5f1a-4d90-8afa-e601b80da991
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363804275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.363804275
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1658174341
Short name T769
Test name
Test status
Simulation time 175452051 ps
CPU time 3.7 seconds
Started Aug 18 06:14:03 PM PDT 24
Finished Aug 18 06:14:07 PM PDT 24
Peak memory 210532 kb
Host smart-5e0dfe46-a1d8-408a-aa89-3d7426f71ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658174341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1658174341
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3288337181
Short name T888
Test name
Test status
Simulation time 21019982 ps
CPU time 1.58 seconds
Started Aug 18 06:13:55 PM PDT 24
Finished Aug 18 06:13:57 PM PDT 24
Peak memory 210380 kb
Host smart-08c41381-e811-494a-821c-1c060afa911f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288337181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3288337181
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2958451124
Short name T369
Test name
Test status
Simulation time 118959397 ps
CPU time 1.97 seconds
Started Aug 18 06:13:58 PM PDT 24
Finished Aug 18 06:14:00 PM PDT 24
Peak memory 214720 kb
Host smart-b03fa887-50cd-45bf-9c0c-72cf9744e373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958451124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2958451124
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_random.1617632574
Short name T698
Test name
Test status
Simulation time 40133165 ps
CPU time 2.96 seconds
Started Aug 18 06:13:54 PM PDT 24
Finished Aug 18 06:13:57 PM PDT 24
Peak memory 207980 kb
Host smart-079f5942-4d47-4a91-ae85-51a215528554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617632574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1617632574
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.607506647
Short name T313
Test name
Test status
Simulation time 174323332 ps
CPU time 5.23 seconds
Started Aug 18 06:14:30 PM PDT 24
Finished Aug 18 06:14:35 PM PDT 24
Peak memory 208816 kb
Host smart-f022bcbf-5daf-4ec7-acd1-c88f515bb749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607506647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.607506647
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1246602956
Short name T753
Test name
Test status
Simulation time 84223020 ps
CPU time 1.98 seconds
Started Aug 18 06:14:11 PM PDT 24
Finished Aug 18 06:14:18 PM PDT 24
Peak memory 207436 kb
Host smart-f635610f-728b-43cc-92e0-e6d5482db6a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246602956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1246602956
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1238231718
Short name T619
Test name
Test status
Simulation time 65791639 ps
CPU time 2.27 seconds
Started Aug 18 06:14:02 PM PDT 24
Finished Aug 18 06:14:04 PM PDT 24
Peak memory 207444 kb
Host smart-2d17fe2d-b2ab-4401-a868-0545ab725504
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238231718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1238231718
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.4070770366
Short name T457
Test name
Test status
Simulation time 44243291 ps
CPU time 1.89 seconds
Started Aug 18 06:14:08 PM PDT 24
Finished Aug 18 06:14:10 PM PDT 24
Peak memory 207796 kb
Host smart-6f103e2f-f5c2-4ba9-9e66-4bf605fe2f51
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070770366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.4070770366
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2167655345
Short name T527
Test name
Test status
Simulation time 1484942360 ps
CPU time 25.75 seconds
Started Aug 18 06:13:59 PM PDT 24
Finished Aug 18 06:14:25 PM PDT 24
Peak memory 210816 kb
Host smart-d5e60413-ae50-4931-92d3-d58e32d24801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167655345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2167655345
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2753624935
Short name T543
Test name
Test status
Simulation time 218698428 ps
CPU time 2.89 seconds
Started Aug 18 06:13:56 PM PDT 24
Finished Aug 18 06:14:00 PM PDT 24
Peak memory 208956 kb
Host smart-bbdd5b39-c14a-4c73-b870-459eb510e434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753624935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2753624935
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.1020964156
Short name T171
Test name
Test status
Simulation time 7609611012 ps
CPU time 20.57 seconds
Started Aug 18 06:13:56 PM PDT 24
Finished Aug 18 06:14:17 PM PDT 24
Peak memory 223048 kb
Host smart-341a85cc-1dea-43de-8bf8-995e8daecf4e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020964156 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.1020964156
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3538951595
Short name T495
Test name
Test status
Simulation time 1864664603 ps
CPU time 7.48 seconds
Started Aug 18 06:14:08 PM PDT 24
Finished Aug 18 06:14:16 PM PDT 24
Peak memory 208076 kb
Host smart-d587dee1-957c-49a7-979e-3ff515b348ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538951595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3538951595
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2138155042
Short name T871
Test name
Test status
Simulation time 4710777811 ps
CPU time 24.3 seconds
Started Aug 18 06:13:58 PM PDT 24
Finished Aug 18 06:14:22 PM PDT 24
Peak memory 212072 kb
Host smart-910fb2c2-c166-4276-b3d6-b8b299d86ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138155042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2138155042
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.4278817446
Short name T437
Test name
Test status
Simulation time 31023958 ps
CPU time 0.7 seconds
Started Aug 18 06:14:02 PM PDT 24
Finished Aug 18 06:14:03 PM PDT 24
Peak memory 206360 kb
Host smart-470faa55-3022-433f-82f5-157856d01736
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278817446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.4278817446
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1963985724
Short name T772
Test name
Test status
Simulation time 764657581 ps
CPU time 3.22 seconds
Started Aug 18 06:14:07 PM PDT 24
Finished Aug 18 06:14:10 PM PDT 24
Peak memory 218772 kb
Host smart-a4d28b6f-22ca-47e6-8a89-4495219789e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963985724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1963985724
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1918474226
Short name T599
Test name
Test status
Simulation time 494724471 ps
CPU time 16.7 seconds
Started Aug 18 06:13:56 PM PDT 24
Finished Aug 18 06:14:18 PM PDT 24
Peak memory 220080 kb
Host smart-79c4ec30-4317-4501-ac11-af5f20d70dc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918474226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1918474226
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_random.2375803031
Short name T631
Test name
Test status
Simulation time 136171802 ps
CPU time 5.53 seconds
Started Aug 18 06:14:07 PM PDT 24
Finished Aug 18 06:14:13 PM PDT 24
Peak memory 207988 kb
Host smart-97f0700d-09ff-4628-8150-559eb09e4a8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375803031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2375803031
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.4078250191
Short name T700
Test name
Test status
Simulation time 1122227758 ps
CPU time 27.78 seconds
Started Aug 18 06:14:01 PM PDT 24
Finished Aug 18 06:14:29 PM PDT 24
Peak memory 208924 kb
Host smart-18ecb83d-5c45-4c5f-8310-877a13d0e4ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078250191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4078250191
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.526295130
Short name T526
Test name
Test status
Simulation time 204296323 ps
CPU time 6.67 seconds
Started Aug 18 06:14:02 PM PDT 24
Finished Aug 18 06:14:09 PM PDT 24
Peak memory 209264 kb
Host smart-d230e04f-ea46-42c7-a17e-4f6077bf4b7a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526295130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.526295130
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1573901611
Short name T310
Test name
Test status
Simulation time 298882118 ps
CPU time 3.65 seconds
Started Aug 18 06:14:08 PM PDT 24
Finished Aug 18 06:14:12 PM PDT 24
Peak memory 209180 kb
Host smart-857c89ad-d273-4827-b7d3-834a1e9ee189
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573901611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1573901611
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.4217214461
Short name T875
Test name
Test status
Simulation time 379750677 ps
CPU time 4.77 seconds
Started Aug 18 06:14:05 PM PDT 24
Finished Aug 18 06:14:10 PM PDT 24
Peak memory 208700 kb
Host smart-cf6980a7-ab8e-49d9-9c38-ae1e1705c407
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217214461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.4217214461
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3397297289
Short name T396
Test name
Test status
Simulation time 51055932 ps
CPU time 1.97 seconds
Started Aug 18 06:13:57 PM PDT 24
Finished Aug 18 06:13:59 PM PDT 24
Peak memory 207792 kb
Host smart-7a3e5165-176d-457f-88b4-5985cf5f1de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397297289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3397297289
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.4205727332
Short name T451
Test name
Test status
Simulation time 528552300 ps
CPU time 5 seconds
Started Aug 18 06:14:02 PM PDT 24
Finished Aug 18 06:14:07 PM PDT 24
Peak memory 208920 kb
Host smart-33938948-170a-4c1b-95bc-605593bd7ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205727332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.4205727332
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1479111148
Short name T711
Test name
Test status
Simulation time 319676580 ps
CPU time 12.8 seconds
Started Aug 18 06:14:06 PM PDT 24
Finished Aug 18 06:14:19 PM PDT 24
Peak memory 219612 kb
Host smart-6792ed3d-c38c-4e38-9cb0-03364b3e147c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479111148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1479111148
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2688602778
Short name T89
Test name
Test status
Simulation time 355912387 ps
CPU time 10.05 seconds
Started Aug 18 06:14:20 PM PDT 24
Finished Aug 18 06:14:30 PM PDT 24
Peak memory 223100 kb
Host smart-910de9da-aa4a-4197-8a0e-4ea185f49b09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688602778 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2688602778
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2467320718
Short name T498
Test name
Test status
Simulation time 199690543 ps
CPU time 2.98 seconds
Started Aug 18 06:13:57 PM PDT 24
Finished Aug 18 06:14:00 PM PDT 24
Peak memory 208064 kb
Host smart-54365d14-9fbf-4d64-8049-a9c538c829b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467320718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2467320718
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2382195045
Short name T380
Test name
Test status
Simulation time 157769642 ps
CPU time 2.43 seconds
Started Aug 18 06:14:21 PM PDT 24
Finished Aug 18 06:14:24 PM PDT 24
Peak memory 210908 kb
Host smart-859ac4da-e9de-4380-8f40-78a8807b592a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382195045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2382195045
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1211455550
Short name T592
Test name
Test status
Simulation time 81290167 ps
CPU time 0.86 seconds
Started Aug 18 06:13:25 PM PDT 24
Finished Aug 18 06:13:26 PM PDT 24
Peak memory 206428 kb
Host smart-ec8f642d-a945-4159-ab07-f8a89a0497e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211455550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1211455550
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3983473223
Short name T79
Test name
Test status
Simulation time 112662341 ps
CPU time 2.52 seconds
Started Aug 18 06:13:13 PM PDT 24
Finished Aug 18 06:13:15 PM PDT 24
Peak memory 214788 kb
Host smart-999b9257-e945-4a82-9deb-964dd7c4fcd2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3983473223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3983473223
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3553456902
Short name T832
Test name
Test status
Simulation time 723205375 ps
CPU time 15.85 seconds
Started Aug 18 06:13:27 PM PDT 24
Finished Aug 18 06:13:43 PM PDT 24
Peak memory 209688 kb
Host smart-ba23dbcc-0efe-4187-8aaf-2cfe439aef87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553456902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3553456902
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2693286548
Short name T389
Test name
Test status
Simulation time 159549171 ps
CPU time 2.93 seconds
Started Aug 18 06:13:32 PM PDT 24
Finished Aug 18 06:13:35 PM PDT 24
Peak memory 208004 kb
Host smart-ba65d326-b56a-46d2-9366-df0508e2aad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693286548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2693286548
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.210398673
Short name T249
Test name
Test status
Simulation time 497824883 ps
CPU time 3.96 seconds
Started Aug 18 06:13:18 PM PDT 24
Finished Aug 18 06:13:22 PM PDT 24
Peak memory 209808 kb
Host smart-9828b93f-bdbd-4e63-89e4-af9ab7e59cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210398673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.210398673
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1391279397
Short name T908
Test name
Test status
Simulation time 217785838 ps
CPU time 3.69 seconds
Started Aug 18 06:13:19 PM PDT 24
Finished Aug 18 06:13:23 PM PDT 24
Peak memory 222792 kb
Host smart-c956e4a4-616d-40f1-ad99-9e34fd9b2e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391279397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1391279397
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1175859741
Short name T213
Test name
Test status
Simulation time 72763091 ps
CPU time 3.51 seconds
Started Aug 18 06:13:28 PM PDT 24
Finished Aug 18 06:13:32 PM PDT 24
Peak memory 222952 kb
Host smart-fb9f9aa9-06b8-4351-b7bc-3bf899088dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175859741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1175859741
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2155069637
Short name T519
Test name
Test status
Simulation time 786058481 ps
CPU time 25.16 seconds
Started Aug 18 06:13:12 PM PDT 24
Finished Aug 18 06:13:37 PM PDT 24
Peak memory 210220 kb
Host smart-37dc335d-d6e8-4d94-996d-cf1766e83533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155069637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2155069637
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.220171473
Short name T44
Test name
Test status
Simulation time 2354915923 ps
CPU time 5.41 seconds
Started Aug 18 06:13:28 PM PDT 24
Finished Aug 18 06:13:33 PM PDT 24
Peak memory 234276 kb
Host smart-ee87df06-b0a2-4e4c-8f9d-b5e029c50e88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220171473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.220171473
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.377974676
Short name T843
Test name
Test status
Simulation time 135596787 ps
CPU time 2.93 seconds
Started Aug 18 06:13:13 PM PDT 24
Finished Aug 18 06:13:16 PM PDT 24
Peak memory 208416 kb
Host smart-7535b2b3-536e-4d60-984c-3a5feb2d1153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377974676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.377974676
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.688845753
Short name T342
Test name
Test status
Simulation time 224141031 ps
CPU time 4.49 seconds
Started Aug 18 06:13:09 PM PDT 24
Finished Aug 18 06:13:14 PM PDT 24
Peak memory 209300 kb
Host smart-4e7f3843-f653-4f9f-a927-9409460da31f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688845753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.688845753
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2359240411
Short name T308
Test name
Test status
Simulation time 72246286 ps
CPU time 2.94 seconds
Started Aug 18 06:13:05 PM PDT 24
Finished Aug 18 06:13:08 PM PDT 24
Peak memory 208708 kb
Host smart-97814473-2110-4f3e-9216-7b6075bd8ef2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359240411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2359240411
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.340448153
Short name T300
Test name
Test status
Simulation time 50661619 ps
CPU time 2.81 seconds
Started Aug 18 06:13:10 PM PDT 24
Finished Aug 18 06:13:13 PM PDT 24
Peak memory 208920 kb
Host smart-cbc9a267-5ecc-4b59-862c-61975d90157e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340448153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.340448153
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.591343507
Short name T687
Test name
Test status
Simulation time 93470973 ps
CPU time 3.62 seconds
Started Aug 18 06:13:20 PM PDT 24
Finished Aug 18 06:13:24 PM PDT 24
Peak memory 214584 kb
Host smart-236f3549-6e65-4ede-94e5-83362de2027d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591343507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.591343507
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.697156467
Short name T675
Test name
Test status
Simulation time 228649867 ps
CPU time 2.72 seconds
Started Aug 18 06:13:20 PM PDT 24
Finished Aug 18 06:13:23 PM PDT 24
Peak memory 207224 kb
Host smart-74134018-f13f-44c6-a508-86f9fac4596a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697156467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.697156467
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.2504246770
Short name T796
Test name
Test status
Simulation time 296104134 ps
CPU time 3.43 seconds
Started Aug 18 06:13:19 PM PDT 24
Finished Aug 18 06:13:22 PM PDT 24
Peak memory 208672 kb
Host smart-aeb272c0-da6a-4c32-8e04-6fe3910a8f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504246770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.2504246770
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3181965659
Short name T36
Test name
Test status
Simulation time 168263537 ps
CPU time 3.75 seconds
Started Aug 18 06:13:23 PM PDT 24
Finished Aug 18 06:13:31 PM PDT 24
Peak memory 210880 kb
Host smart-5854f9d3-f110-4f36-81e7-8c52efd52a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181965659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3181965659
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2657989122
Short name T644
Test name
Test status
Simulation time 44211718 ps
CPU time 0.79 seconds
Started Aug 18 06:14:12 PM PDT 24
Finished Aug 18 06:14:13 PM PDT 24
Peak memory 206384 kb
Host smart-b6130b54-3d17-4cb5-937d-4af9b521eb72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657989122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2657989122
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1225579954
Short name T426
Test name
Test status
Simulation time 306694349 ps
CPU time 2.81 seconds
Started Aug 18 06:14:00 PM PDT 24
Finished Aug 18 06:14:03 PM PDT 24
Peak memory 214740 kb
Host smart-d319c2c6-49a8-45b3-9857-2db9336a8471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225579954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1225579954
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3776827651
Short name T882
Test name
Test status
Simulation time 152496269 ps
CPU time 4.21 seconds
Started Aug 18 06:14:07 PM PDT 24
Finished Aug 18 06:14:12 PM PDT 24
Peak memory 208788 kb
Host smart-d3795d3c-2bf9-4705-bf60-ecf2ae187899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776827651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3776827651
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2501738310
Short name T804
Test name
Test status
Simulation time 254910158 ps
CPU time 3.39 seconds
Started Aug 18 06:14:17 PM PDT 24
Finished Aug 18 06:14:20 PM PDT 24
Peak memory 210584 kb
Host smart-d7d1a5da-eba3-4737-8a36-33ffbf4f3426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501738310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2501738310
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3189230054
Short name T548
Test name
Test status
Simulation time 1097546956 ps
CPU time 10.71 seconds
Started Aug 18 06:14:31 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 208152 kb
Host smart-df1f591b-ca30-49ae-bace-5e2fd3a0678c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189230054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3189230054
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1773344727
Short name T554
Test name
Test status
Simulation time 79245356 ps
CPU time 1.75 seconds
Started Aug 18 06:14:08 PM PDT 24
Finished Aug 18 06:14:10 PM PDT 24
Peak memory 207456 kb
Host smart-bd3f0907-359e-410a-a8a1-73773c54d68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773344727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1773344727
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1614090314
Short name T799
Test name
Test status
Simulation time 2738461263 ps
CPU time 20.28 seconds
Started Aug 18 06:14:00 PM PDT 24
Finished Aug 18 06:14:21 PM PDT 24
Peak memory 209236 kb
Host smart-57ea3eee-a97b-4bc1-bec6-a436726c3792
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614090314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1614090314
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2213801146
Short name T746
Test name
Test status
Simulation time 68082975 ps
CPU time 3.37 seconds
Started Aug 18 06:14:10 PM PDT 24
Finished Aug 18 06:14:14 PM PDT 24
Peak memory 209204 kb
Host smart-61b9fbe0-36f9-4bc9-867c-7bb5ff0aadd5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213801146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2213801146
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1464696983
Short name T464
Test name
Test status
Simulation time 82220242 ps
CPU time 3.64 seconds
Started Aug 18 06:14:04 PM PDT 24
Finished Aug 18 06:14:07 PM PDT 24
Peak memory 209068 kb
Host smart-40b29f0e-26a0-4d8b-a71d-0fbe82c64de6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464696983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1464696983
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4017426859
Short name T388
Test name
Test status
Simulation time 88554793 ps
CPU time 2.3 seconds
Started Aug 18 06:14:12 PM PDT 24
Finished Aug 18 06:14:14 PM PDT 24
Peak memory 215872 kb
Host smart-fcaab060-df43-48c1-82ce-81a104c75556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017426859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4017426859
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1240611070
Short name T845
Test name
Test status
Simulation time 267723020 ps
CPU time 3.91 seconds
Started Aug 18 06:14:22 PM PDT 24
Finished Aug 18 06:14:26 PM PDT 24
Peak memory 208968 kb
Host smart-1bf6762d-be4b-4b21-a5d6-53a2467cc791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240611070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1240611070
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1484499202
Short name T874
Test name
Test status
Simulation time 491859577 ps
CPU time 9.51 seconds
Started Aug 18 06:14:17 PM PDT 24
Finished Aug 18 06:14:27 PM PDT 24
Peak memory 215580 kb
Host smart-789a2d39-0bf7-486b-a97f-e8c8bbea01d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484499202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1484499202
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1020479970
Short name T827
Test name
Test status
Simulation time 97825582 ps
CPU time 2.27 seconds
Started Aug 18 06:14:07 PM PDT 24
Finished Aug 18 06:14:10 PM PDT 24
Peak memory 207772 kb
Host smart-a63bac89-5f99-49b3-b0a5-317a9c3daec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020479970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1020479970
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3934617576
Short name T883
Test name
Test status
Simulation time 141946998 ps
CPU time 2.12 seconds
Started Aug 18 06:14:01 PM PDT 24
Finished Aug 18 06:14:04 PM PDT 24
Peak memory 210532 kb
Host smart-6f6c6d01-0748-4bd0-9a1f-12ae63e6603a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934617576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3934617576
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.239749546
Short name T509
Test name
Test status
Simulation time 59707586 ps
CPU time 0.79 seconds
Started Aug 18 06:14:24 PM PDT 24
Finished Aug 18 06:14:25 PM PDT 24
Peak memory 206376 kb
Host smart-1ee44033-0908-4293-8b1d-673e0176a0ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239749546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.239749546
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3471682564
Short name T255
Test name
Test status
Simulation time 192579190 ps
CPU time 2.47 seconds
Started Aug 18 06:14:04 PM PDT 24
Finished Aug 18 06:14:07 PM PDT 24
Peak memory 210116 kb
Host smart-a012bd9d-afa3-4904-98f3-73fd30dd9d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471682564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3471682564
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3671744857
Short name T22
Test name
Test status
Simulation time 595024575 ps
CPU time 8.65 seconds
Started Aug 18 06:14:10 PM PDT 24
Finished Aug 18 06:14:19 PM PDT 24
Peak memory 210172 kb
Host smart-76332ce7-0f3c-4bfd-8606-0439a33dc2de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671744857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3671744857
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1563061493
Short name T815
Test name
Test status
Simulation time 176178933 ps
CPU time 3.52 seconds
Started Aug 18 06:14:09 PM PDT 24
Finished Aug 18 06:14:13 PM PDT 24
Peak memory 215008 kb
Host smart-0a0c4659-475c-4d6f-8d63-c14acff1474f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563061493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1563061493
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2784123669
Short name T499
Test name
Test status
Simulation time 150268333 ps
CPU time 4.94 seconds
Started Aug 18 06:14:11 PM PDT 24
Finished Aug 18 06:14:16 PM PDT 24
Peak memory 208644 kb
Host smart-da5dfd11-c728-4377-82b7-1ce33909f14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784123669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2784123669
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.452223044
Short name T744
Test name
Test status
Simulation time 144496446 ps
CPU time 3.82 seconds
Started Aug 18 06:14:03 PM PDT 24
Finished Aug 18 06:14:07 PM PDT 24
Peak memory 209492 kb
Host smart-6f921d79-a476-4fff-9b16-920348b0e883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452223044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.452223044
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2972767163
Short name T570
Test name
Test status
Simulation time 408673072 ps
CPU time 4.04 seconds
Started Aug 18 06:14:19 PM PDT 24
Finished Aug 18 06:14:23 PM PDT 24
Peak memory 207496 kb
Host smart-589c8df7-521e-462f-80d1-9b8292e8ee5e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972767163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2972767163
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.87702388
Short name T501
Test name
Test status
Simulation time 22755870 ps
CPU time 1.83 seconds
Started Aug 18 06:14:17 PM PDT 24
Finished Aug 18 06:14:19 PM PDT 24
Peak memory 207680 kb
Host smart-594df52d-5d65-4319-bc04-7153b5f70b13
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87702388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.87702388
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3072930315
Short name T722
Test name
Test status
Simulation time 142708356 ps
CPU time 3.82 seconds
Started Aug 18 06:14:02 PM PDT 24
Finished Aug 18 06:14:06 PM PDT 24
Peak memory 209268 kb
Host smart-137c9e19-92a5-461a-a229-a13ae44c3726
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072930315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3072930315
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_smoke.649490399
Short name T630
Test name
Test status
Simulation time 5069083715 ps
CPU time 12.89 seconds
Started Aug 18 06:14:21 PM PDT 24
Finished Aug 18 06:14:34 PM PDT 24
Peak memory 209280 kb
Host smart-cfd629bd-4dc2-45ba-8947-4caa6bfc7e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649490399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.649490399
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3018780070
Short name T283
Test name
Test status
Simulation time 104084149 ps
CPU time 5.03 seconds
Started Aug 18 06:14:07 PM PDT 24
Finished Aug 18 06:14:12 PM PDT 24
Peak memory 218872 kb
Host smart-bbb7d4b4-28d2-4b90-b2e3-b244094ff15e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018780070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3018780070
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.712690218
Short name T680
Test name
Test status
Simulation time 1587411195 ps
CPU time 14.66 seconds
Started Aug 18 06:14:15 PM PDT 24
Finished Aug 18 06:14:30 PM PDT 24
Peak memory 223092 kb
Host smart-3b4f8793-fda5-476f-9b04-edfbb33b3354
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712690218 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.712690218
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1152076240
Short name T365
Test name
Test status
Simulation time 147933484 ps
CPU time 4.1 seconds
Started Aug 18 06:14:13 PM PDT 24
Finished Aug 18 06:14:18 PM PDT 24
Peak memory 208764 kb
Host smart-7480529c-436d-4704-b72c-8de3da67e67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152076240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1152076240
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.3410663092
Short name T709
Test name
Test status
Simulation time 566640762 ps
CPU time 2.06 seconds
Started Aug 18 06:14:23 PM PDT 24
Finished Aug 18 06:14:25 PM PDT 24
Peak memory 210484 kb
Host smart-5f8e9e50-6831-41a3-9b2b-ab11d8fde7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410663092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.3410663092
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.301907396
Short name T511
Test name
Test status
Simulation time 8941907 ps
CPU time 0.84 seconds
Started Aug 18 06:14:08 PM PDT 24
Finished Aug 18 06:14:10 PM PDT 24
Peak memory 206380 kb
Host smart-e6e85c2f-d482-4d66-b92b-a7bff77812dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301907396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.301907396
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.315263486
Short name T663
Test name
Test status
Simulation time 148694071 ps
CPU time 3.1 seconds
Started Aug 18 06:14:18 PM PDT 24
Finished Aug 18 06:14:21 PM PDT 24
Peak memory 211256 kb
Host smart-aab17eb1-5bcd-4862-8419-14491040e4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315263486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.315263486
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2389482421
Short name T292
Test name
Test status
Simulation time 160110079 ps
CPU time 5.67 seconds
Started Aug 18 06:14:23 PM PDT 24
Finished Aug 18 06:14:29 PM PDT 24
Peak memory 209956 kb
Host smart-1b20c246-088b-49eb-96aa-0b3d14dd0c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389482421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2389482421
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1181390415
Short name T4
Test name
Test status
Simulation time 98971038 ps
CPU time 4.22 seconds
Started Aug 18 06:14:15 PM PDT 24
Finished Aug 18 06:14:20 PM PDT 24
Peak memory 209884 kb
Host smart-8d14c9c8-f465-4740-99a6-084e7fb5e6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181390415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1181390415
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.26873050
Short name T541
Test name
Test status
Simulation time 428492166 ps
CPU time 3.84 seconds
Started Aug 18 06:14:01 PM PDT 24
Finished Aug 18 06:14:05 PM PDT 24
Peak memory 222940 kb
Host smart-7014ec4d-bac7-4d26-afc1-6aa73bab1815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26873050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.26873050
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1183811836
Short name T649
Test name
Test status
Simulation time 175010663 ps
CPU time 3.98 seconds
Started Aug 18 06:14:21 PM PDT 24
Finished Aug 18 06:14:25 PM PDT 24
Peak memory 218696 kb
Host smart-37f6444a-2e38-41ca-a519-023db5b1c83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183811836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1183811836
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.4181077882
Short name T435
Test name
Test status
Simulation time 703145809 ps
CPU time 18.14 seconds
Started Aug 18 06:14:08 PM PDT 24
Finished Aug 18 06:14:26 PM PDT 24
Peak memory 208576 kb
Host smart-9519adac-3102-49f8-8a97-9b980bdd08a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181077882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.4181077882
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2257800139
Short name T399
Test name
Test status
Simulation time 460556094 ps
CPU time 3.54 seconds
Started Aug 18 06:14:09 PM PDT 24
Finished Aug 18 06:14:12 PM PDT 24
Peak memory 207404 kb
Host smart-599d4d29-c2b5-483f-a8e3-4c14a86b23c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257800139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2257800139
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3145099150
Short name T483
Test name
Test status
Simulation time 20886744 ps
CPU time 1.78 seconds
Started Aug 18 06:14:11 PM PDT 24
Finished Aug 18 06:14:13 PM PDT 24
Peak memory 207356 kb
Host smart-26d49c40-d5d7-480b-bba9-e489f8a43559
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145099150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3145099150
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1598952433
Short name T718
Test name
Test status
Simulation time 335824331 ps
CPU time 9.18 seconds
Started Aug 18 06:14:07 PM PDT 24
Finished Aug 18 06:14:16 PM PDT 24
Peak memory 209020 kb
Host smart-acbaf177-d40e-4cc1-ba77-356683308ea1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598952433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1598952433
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.498611831
Short name T323
Test name
Test status
Simulation time 1037098111 ps
CPU time 6.52 seconds
Started Aug 18 06:14:22 PM PDT 24
Finished Aug 18 06:14:28 PM PDT 24
Peak memory 214760 kb
Host smart-63e6a7f5-56e4-44f9-b7a3-fa3f4ed5ea33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498611831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.498611831
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2499141183
Short name T492
Test name
Test status
Simulation time 41692554 ps
CPU time 2.37 seconds
Started Aug 18 06:14:11 PM PDT 24
Finished Aug 18 06:14:14 PM PDT 24
Peak memory 207416 kb
Host smart-ac62c055-fa3c-46ef-8017-504785872d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499141183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2499141183
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3086322874
Short name T678
Test name
Test status
Simulation time 1972194876 ps
CPU time 20.48 seconds
Started Aug 18 06:14:03 PM PDT 24
Finished Aug 18 06:14:23 PM PDT 24
Peak memory 220540 kb
Host smart-db406e69-2ce5-4914-88de-0b2ecc88c5b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086322874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3086322874
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1779360642
Short name T834
Test name
Test status
Simulation time 186333751 ps
CPU time 3.44 seconds
Started Aug 18 06:14:26 PM PDT 24
Finished Aug 18 06:14:29 PM PDT 24
Peak memory 208516 kb
Host smart-b2c5dbd0-8894-4496-987e-7a2dc95856d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779360642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1779360642
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2998606008
Short name T133
Test name
Test status
Simulation time 667000720 ps
CPU time 2.6 seconds
Started Aug 18 06:14:21 PM PDT 24
Finished Aug 18 06:14:23 PM PDT 24
Peak memory 210604 kb
Host smart-c331e0be-6805-411b-8bd0-9c7140f2e83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998606008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2998606008
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2398194739
Short name T788
Test name
Test status
Simulation time 29915296 ps
CPU time 0.72 seconds
Started Aug 18 06:14:20 PM PDT 24
Finished Aug 18 06:14:20 PM PDT 24
Peak memory 206404 kb
Host smart-3bdac045-6779-4f24-9644-21eccdd781ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398194739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2398194739
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3052484610
Short name T724
Test name
Test status
Simulation time 121610817 ps
CPU time 4.47 seconds
Started Aug 18 06:14:28 PM PDT 24
Finished Aug 18 06:14:33 PM PDT 24
Peak memory 209496 kb
Host smart-4f646f4e-03af-475c-b172-e45aeecb9e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052484610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3052484610
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1409032993
Short name T553
Test name
Test status
Simulation time 235981102 ps
CPU time 1.93 seconds
Started Aug 18 06:14:08 PM PDT 24
Finished Aug 18 06:14:10 PM PDT 24
Peak memory 208228 kb
Host smart-a6fe503a-2819-4309-8957-2b901653bf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409032993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1409032993
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1280500244
Short name T317
Test name
Test status
Simulation time 59528355 ps
CPU time 2.24 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:41 PM PDT 24
Peak memory 214772 kb
Host smart-a9b98665-712a-4f3e-922a-a8917fc85026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280500244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1280500244
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.114475944
Short name T752
Test name
Test status
Simulation time 78818870 ps
CPU time 2.35 seconds
Started Aug 18 06:14:17 PM PDT 24
Finished Aug 18 06:14:20 PM PDT 24
Peak memory 221952 kb
Host smart-d473de73-790e-4aa4-b571-efaa5aee5c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114475944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.114475944
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_random.1154287760
Short name T884
Test name
Test status
Simulation time 55478883 ps
CPU time 3.56 seconds
Started Aug 18 06:14:09 PM PDT 24
Finished Aug 18 06:14:13 PM PDT 24
Peak memory 208884 kb
Host smart-e0f06858-f2be-43ef-9298-f63c351f4e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154287760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1154287760
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1570613173
Short name T838
Test name
Test status
Simulation time 901831892 ps
CPU time 4.81 seconds
Started Aug 18 06:14:18 PM PDT 24
Finished Aug 18 06:14:22 PM PDT 24
Peak memory 208932 kb
Host smart-f0f7d95b-b8c3-409a-ba81-87755f52efb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570613173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1570613173
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1291590706
Short name T482
Test name
Test status
Simulation time 211496508 ps
CPU time 7.05 seconds
Started Aug 18 06:14:20 PM PDT 24
Finished Aug 18 06:14:27 PM PDT 24
Peak memory 208760 kb
Host smart-b7562336-0a96-491f-bd05-37c4d27a4985
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291590706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1291590706
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1741274229
Short name T890
Test name
Test status
Simulation time 103587693 ps
CPU time 4.26 seconds
Started Aug 18 06:14:07 PM PDT 24
Finished Aug 18 06:14:11 PM PDT 24
Peak memory 208648 kb
Host smart-0be5397a-2151-4985-8948-a570454c07dc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741274229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1741274229
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3457682498
Short name T853
Test name
Test status
Simulation time 280299865 ps
CPU time 3.4 seconds
Started Aug 18 06:14:11 PM PDT 24
Finished Aug 18 06:14:15 PM PDT 24
Peak memory 208960 kb
Host smart-c94a09c0-669d-4bc2-af12-28d742edcaeb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457682498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3457682498
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.447462947
Short name T461
Test name
Test status
Simulation time 81137287 ps
CPU time 1.96 seconds
Started Aug 18 06:14:25 PM PDT 24
Finished Aug 18 06:14:27 PM PDT 24
Peak memory 209916 kb
Host smart-e5158a32-22c2-4beb-b61a-8d9628f144e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447462947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.447462947
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.160102741
Short name T848
Test name
Test status
Simulation time 5440078320 ps
CPU time 49.48 seconds
Started Aug 18 06:14:19 PM PDT 24
Finished Aug 18 06:15:08 PM PDT 24
Peak memory 209396 kb
Host smart-5ddc7d66-7ca1-4192-82a9-08b1e2afbf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160102741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.160102741
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.298680704
Short name T286
Test name
Test status
Simulation time 589272543 ps
CPU time 4.32 seconds
Started Aug 18 06:14:20 PM PDT 24
Finished Aug 18 06:14:24 PM PDT 24
Peak memory 214804 kb
Host smart-f7a0b1d7-9d58-41ef-b024-047d9f42c3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298680704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.298680704
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1304777484
Short name T186
Test name
Test status
Simulation time 436256707 ps
CPU time 2.69 seconds
Started Aug 18 06:14:22 PM PDT 24
Finished Aug 18 06:14:25 PM PDT 24
Peak memory 211268 kb
Host smart-bf8c9620-c49b-4206-9eb1-c3ac769aeeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304777484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1304777484
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3048308415
Short name T504
Test name
Test status
Simulation time 13949504 ps
CPU time 0.9 seconds
Started Aug 18 06:14:22 PM PDT 24
Finished Aug 18 06:14:23 PM PDT 24
Peak memory 206468 kb
Host smart-4c8b8f40-7cc7-49e3-b66a-cb57a5de7ac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048308415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3048308415
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.3044673572
Short name T136
Test name
Test status
Simulation time 245054442 ps
CPU time 3.71 seconds
Started Aug 18 06:14:22 PM PDT 24
Finished Aug 18 06:14:26 PM PDT 24
Peak memory 209088 kb
Host smart-54bc72d2-ba5e-4df8-b650-45015929ce41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044673572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.3044673572
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.915711138
Short name T5
Test name
Test status
Simulation time 365606670 ps
CPU time 11.82 seconds
Started Aug 18 06:14:34 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 214776 kb
Host smart-f2717056-23f8-4820-a619-89d06e841076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915711138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.915711138
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2540511405
Short name T258
Test name
Test status
Simulation time 34501857 ps
CPU time 2.81 seconds
Started Aug 18 06:14:14 PM PDT 24
Finished Aug 18 06:14:17 PM PDT 24
Peak memory 222852 kb
Host smart-efa83f29-c330-4854-aa9a-9f154b1d333f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540511405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2540511405
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.479959851
Short name T896
Test name
Test status
Simulation time 36833161 ps
CPU time 2.47 seconds
Started Aug 18 06:14:27 PM PDT 24
Finished Aug 18 06:14:30 PM PDT 24
Peak memory 220580 kb
Host smart-58362862-c6f2-4d4e-8a35-a6397d3f14cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479959851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.479959851
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2721719630
Short name T370
Test name
Test status
Simulation time 89289398 ps
CPU time 3.15 seconds
Started Aug 18 06:14:25 PM PDT 24
Finished Aug 18 06:14:29 PM PDT 24
Peak memory 208688 kb
Host smart-ad93fa48-72ab-4e1d-b6f1-d70541e92fa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721719630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2721719630
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.634997646
Short name T694
Test name
Test status
Simulation time 104548553 ps
CPU time 4.69 seconds
Started Aug 18 06:14:23 PM PDT 24
Finished Aug 18 06:14:28 PM PDT 24
Peak memory 214788 kb
Host smart-290632ca-a844-4a15-ac30-d21f757e3392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634997646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.634997646
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.936521906
Short name T764
Test name
Test status
Simulation time 6192410388 ps
CPU time 26.17 seconds
Started Aug 18 06:14:33 PM PDT 24
Finished Aug 18 06:14:59 PM PDT 24
Peak memory 209412 kb
Host smart-43290c34-a616-4ed2-b410-a3fdd6784f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936521906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.936521906
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.427479337
Short name T513
Test name
Test status
Simulation time 104276304 ps
CPU time 3.23 seconds
Started Aug 18 06:14:19 PM PDT 24
Finished Aug 18 06:14:22 PM PDT 24
Peak memory 208368 kb
Host smart-b574e7d4-6707-443e-98eb-42d0995e38da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427479337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.427479337
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4076950556
Short name T278
Test name
Test status
Simulation time 533050765 ps
CPU time 4.63 seconds
Started Aug 18 06:14:30 PM PDT 24
Finished Aug 18 06:14:34 PM PDT 24
Peak memory 209396 kb
Host smart-41778322-8a77-48b8-bdf0-12addb8e41be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076950556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4076950556
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1407819165
Short name T250
Test name
Test status
Simulation time 97735706 ps
CPU time 2.1 seconds
Started Aug 18 06:14:14 PM PDT 24
Finished Aug 18 06:14:16 PM PDT 24
Peak memory 209256 kb
Host smart-82adde73-1c47-4cd6-8fde-c4e758fee7e2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407819165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1407819165
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1650036256
Short name T269
Test name
Test status
Simulation time 172470156 ps
CPU time 2.42 seconds
Started Aug 18 06:14:18 PM PDT 24
Finished Aug 18 06:14:21 PM PDT 24
Peak memory 207840 kb
Host smart-738a4341-6ae3-42a9-a581-ae1f3418981f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650036256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1650036256
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2484603969
Short name T189
Test name
Test status
Simulation time 135983859 ps
CPU time 2.28 seconds
Started Aug 18 06:14:18 PM PDT 24
Finished Aug 18 06:14:21 PM PDT 24
Peak memory 207172 kb
Host smart-3075a104-dbe9-4914-8318-a2c472161b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484603969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2484603969
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1595267728
Short name T598
Test name
Test status
Simulation time 3939810212 ps
CPU time 80.94 seconds
Started Aug 18 06:14:35 PM PDT 24
Finished Aug 18 06:15:56 PM PDT 24
Peak memory 216928 kb
Host smart-7d8a209c-424b-4af9-bdb3-4d8660aaa151
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595267728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1595267728
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2960848733
Short name T689
Test name
Test status
Simulation time 289918004 ps
CPU time 11.56 seconds
Started Aug 18 06:14:28 PM PDT 24
Finished Aug 18 06:14:39 PM PDT 24
Peak memory 219108 kb
Host smart-9cc3430f-a897-4890-bba4-1ceca8aa0e47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960848733 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2960848733
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.318379390
Short name T298
Test name
Test status
Simulation time 233452773 ps
CPU time 6.52 seconds
Started Aug 18 06:14:26 PM PDT 24
Finished Aug 18 06:14:32 PM PDT 24
Peak memory 214784 kb
Host smart-391c7f88-aad6-4664-b53d-db1445477a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318379390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.318379390
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1611322189
Short name T378
Test name
Test status
Simulation time 226591355 ps
CPU time 2.17 seconds
Started Aug 18 06:14:22 PM PDT 24
Finished Aug 18 06:14:24 PM PDT 24
Peak memory 211032 kb
Host smart-f0b1bd96-3860-4945-b964-776ac926f1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1611322189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1611322189
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1554014223
Short name T895
Test name
Test status
Simulation time 15523505 ps
CPU time 0.92 seconds
Started Aug 18 06:14:19 PM PDT 24
Finished Aug 18 06:14:20 PM PDT 24
Peak memory 206496 kb
Host smart-1fda7d7f-f560-4af7-ac67-3a86966e8d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554014223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1554014223
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.997797296
Short name T31
Test name
Test status
Simulation time 199448201 ps
CPU time 4.21 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 210776 kb
Host smart-61683014-1326-4dce-90f5-746f4ec9c894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997797296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.997797296
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2732820304
Short name T341
Test name
Test status
Simulation time 229992297 ps
CPU time 2.28 seconds
Started Aug 18 06:14:19 PM PDT 24
Finished Aug 18 06:14:21 PM PDT 24
Peak memory 210312 kb
Host smart-5ee10a0e-1ef7-4a9d-aa26-b57e1f4a5d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732820304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2732820304
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2890305477
Short name T23
Test name
Test status
Simulation time 1428601862 ps
CPU time 26.63 seconds
Started Aug 18 06:14:24 PM PDT 24
Finished Aug 18 06:14:51 PM PDT 24
Peak memory 222912 kb
Host smart-07e40129-79c4-4867-9379-2243502e7847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890305477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2890305477
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.995219055
Short name T236
Test name
Test status
Simulation time 254978994 ps
CPU time 3.27 seconds
Started Aug 18 06:14:24 PM PDT 24
Finished Aug 18 06:14:28 PM PDT 24
Peak memory 214724 kb
Host smart-aec76c57-2e18-4e8f-962c-139712451c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995219055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.995219055
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1356882050
Short name T207
Test name
Test status
Simulation time 641349541 ps
CPU time 3.52 seconds
Started Aug 18 06:14:19 PM PDT 24
Finished Aug 18 06:14:23 PM PDT 24
Peak memory 214772 kb
Host smart-8e4e773d-836a-490b-91aa-8770cda8fabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356882050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1356882050
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3543460068
Short name T810
Test name
Test status
Simulation time 46681820 ps
CPU time 3.24 seconds
Started Aug 18 06:14:30 PM PDT 24
Finished Aug 18 06:14:33 PM PDT 24
Peak memory 210316 kb
Host smart-e052b244-64a0-4de0-9f50-6721a1ced2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543460068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3543460068
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1241713944
Short name T268
Test name
Test status
Simulation time 424455408 ps
CPU time 3.13 seconds
Started Aug 18 06:14:18 PM PDT 24
Finished Aug 18 06:14:26 PM PDT 24
Peak memory 208916 kb
Host smart-19370137-d378-4c9e-aef0-7adda56d9095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241713944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1241713944
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3212113540
Short name T481
Test name
Test status
Simulation time 2725318702 ps
CPU time 31.38 seconds
Started Aug 18 06:14:26 PM PDT 24
Finished Aug 18 06:14:57 PM PDT 24
Peak memory 209208 kb
Host smart-a76f6038-104f-44d6-8297-bbed4fe6a168
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212113540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3212113540
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3555891678
Short name T625
Test name
Test status
Simulation time 130709987 ps
CPU time 3.16 seconds
Started Aug 18 06:14:35 PM PDT 24
Finished Aug 18 06:14:38 PM PDT 24
Peak memory 209296 kb
Host smart-408c2fab-d5fa-469a-978b-da6e22d50a65
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555891678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3555891678
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2674270058
Short name T475
Test name
Test status
Simulation time 901682085 ps
CPU time 26.92 seconds
Started Aug 18 06:14:23 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 209092 kb
Host smart-51d3988a-1eac-47a7-8a39-fcb6c7c1488c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674270058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2674270058
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3197567203
Short name T497
Test name
Test status
Simulation time 58459364 ps
CPU time 1.97 seconds
Started Aug 18 06:14:27 PM PDT 24
Finished Aug 18 06:14:29 PM PDT 24
Peak memory 208628 kb
Host smart-ab4390ee-14a2-47ab-a28e-bc03664f3819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197567203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3197567203
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3918324400
Short name T673
Test name
Test status
Simulation time 341829433 ps
CPU time 5.38 seconds
Started Aug 18 06:14:25 PM PDT 24
Finished Aug 18 06:14:31 PM PDT 24
Peak memory 207220 kb
Host smart-1cb02aea-a7d7-4f10-a4c0-832dc623c68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918324400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3918324400
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2286084760
Short name T460
Test name
Test status
Simulation time 36442166 ps
CPU time 2.43 seconds
Started Aug 18 06:14:23 PM PDT 24
Finished Aug 18 06:14:26 PM PDT 24
Peak memory 208440 kb
Host smart-9c2a6ba7-8300-4539-9010-bd1046265db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286084760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2286084760
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.236613250
Short name T750
Test name
Test status
Simulation time 100424908 ps
CPU time 2.21 seconds
Started Aug 18 06:14:39 PM PDT 24
Finished Aug 18 06:14:41 PM PDT 24
Peak memory 211004 kb
Host smart-02a05c95-acde-4bb0-b0af-5ddab76913fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236613250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.236613250
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1998876332
Short name T701
Test name
Test status
Simulation time 20093627 ps
CPU time 0.79 seconds
Started Aug 18 06:14:31 PM PDT 24
Finished Aug 18 06:14:32 PM PDT 24
Peak memory 206388 kb
Host smart-7b72a896-56c5-49f5-8fee-43fe3f4c3341
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998876332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1998876332
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2785720382
Short name T265
Test name
Test status
Simulation time 49677856 ps
CPU time 3.78 seconds
Started Aug 18 06:14:23 PM PDT 24
Finished Aug 18 06:14:27 PM PDT 24
Peak memory 214908 kb
Host smart-e00a15e3-a968-4860-b780-6dedb828e6c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2785720382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2785720382
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3433499958
Short name T209
Test name
Test status
Simulation time 88345466 ps
CPU time 3.9 seconds
Started Aug 18 06:14:36 PM PDT 24
Finished Aug 18 06:14:40 PM PDT 24
Peak memory 222176 kb
Host smart-98445983-0b3e-4f04-bb5c-d4e6609e4ea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433499958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3433499958
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1122847887
Short name T138
Test name
Test status
Simulation time 159504438 ps
CPU time 6.27 seconds
Started Aug 18 06:14:33 PM PDT 24
Finished Aug 18 06:14:39 PM PDT 24
Peak memory 214752 kb
Host smart-e64db919-2041-4af7-ba06-c829c87995d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122847887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1122847887
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.300324594
Short name T120
Test name
Test status
Simulation time 130762577 ps
CPU time 5.27 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:45 PM PDT 24
Peak memory 207256 kb
Host smart-8c436970-1a9f-4136-8711-25dda50726cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300324594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.300324594
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.935531914
Short name T889
Test name
Test status
Simulation time 517507109 ps
CPU time 3.82 seconds
Started Aug 18 06:14:37 PM PDT 24
Finished Aug 18 06:14:41 PM PDT 24
Peak memory 208180 kb
Host smart-d567603c-0864-4a90-b5f5-b07b522f3467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935531914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.935531914
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3929359991
Short name T846
Test name
Test status
Simulation time 404753244 ps
CPU time 2.78 seconds
Started Aug 18 06:14:32 PM PDT 24
Finished Aug 18 06:14:35 PM PDT 24
Peak memory 208900 kb
Host smart-230475cf-6cb2-4695-a21e-d57093476da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929359991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3929359991
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2985504737
Short name T70
Test name
Test status
Simulation time 62619786 ps
CPU time 3.14 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 208992 kb
Host smart-1a5e8efe-5a35-4942-9c35-97b0e1d46ff5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985504737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2985504737
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1384974313
Short name T745
Test name
Test status
Simulation time 90131060 ps
CPU time 2.82 seconds
Started Aug 18 06:14:30 PM PDT 24
Finished Aug 18 06:14:33 PM PDT 24
Peak memory 207372 kb
Host smart-c06e0619-bac2-4c2e-bef0-7ca4ed5561e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384974313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1384974313
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1864497337
Short name T830
Test name
Test status
Simulation time 156969856 ps
CPU time 3.62 seconds
Started Aug 18 06:14:30 PM PDT 24
Finished Aug 18 06:14:34 PM PDT 24
Peak memory 210576 kb
Host smart-a6a08e7d-7f83-478f-a074-8b33c89c6d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864497337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1864497337
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.3815976282
Short name T562
Test name
Test status
Simulation time 311383887 ps
CPU time 3.2 seconds
Started Aug 18 06:14:23 PM PDT 24
Finished Aug 18 06:14:26 PM PDT 24
Peak memory 208892 kb
Host smart-e8fbfb17-0567-4bd2-8b08-bc57c1bb1905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815976282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3815976282
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2732869915
Short name T144
Test name
Test status
Simulation time 566455212 ps
CPU time 4.53 seconds
Started Aug 18 06:14:37 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 210140 kb
Host smart-57c9bfbe-9245-4dbd-8dc1-b37cf9bdbb17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732869915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2732869915
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2828271115
Short name T628
Test name
Test status
Simulation time 334496580 ps
CPU time 8.56 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:49 PM PDT 24
Peak memory 210580 kb
Host smart-fa920a8a-d85a-49ae-a3db-a9e265f50f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828271115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2828271115
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3104687021
Short name T809
Test name
Test status
Simulation time 25952089 ps
CPU time 0.71 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 206368 kb
Host smart-5ff6cc09-da67-402a-ab22-1b748fc76e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104687021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3104687021
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.15696267
Short name T303
Test name
Test status
Simulation time 118108426 ps
CPU time 5.8 seconds
Started Aug 18 06:14:39 PM PDT 24
Finished Aug 18 06:14:45 PM PDT 24
Peak memory 223100 kb
Host smart-de047c41-0855-4f74-973d-127a0223c67c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=15696267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.15696267
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.493296433
Short name T205
Test name
Test status
Simulation time 513483010 ps
CPU time 4.3 seconds
Started Aug 18 06:14:46 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 209360 kb
Host smart-6ec6ef4d-9621-4614-ab57-49482e43cfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493296433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.493296433
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.458684424
Short name T781
Test name
Test status
Simulation time 197515869 ps
CPU time 2.64 seconds
Started Aug 18 06:14:22 PM PDT 24
Finished Aug 18 06:14:25 PM PDT 24
Peak memory 210504 kb
Host smart-9ccafce0-dfd3-4b90-bbe4-b23f870d475c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458684424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.458684424
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3879616000
Short name T46
Test name
Test status
Simulation time 287027103 ps
CPU time 3.17 seconds
Started Aug 18 06:14:35 PM PDT 24
Finished Aug 18 06:14:38 PM PDT 24
Peak memory 214788 kb
Host smart-b83b58d3-51d0-4127-b17a-1538bccaafe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879616000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3879616000
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3093673810
Short name T334
Test name
Test status
Simulation time 1452861893 ps
CPU time 20.86 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:15:02 PM PDT 24
Peak memory 221972 kb
Host smart-9bdcf070-24d7-4049-8205-241c4cbaf8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093673810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3093673810
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.4123009955
Short name T253
Test name
Test status
Simulation time 333164798 ps
CPU time 3.37 seconds
Started Aug 18 06:14:39 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 209188 kb
Host smart-623e43f3-105b-4f2d-a55d-1a75eecd4420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123009955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.4123009955
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1759765656
Short name T251
Test name
Test status
Simulation time 2823078562 ps
CPU time 34.77 seconds
Started Aug 18 06:14:37 PM PDT 24
Finished Aug 18 06:15:12 PM PDT 24
Peak memory 209516 kb
Host smart-0d423829-5f70-477f-8af7-35d0ed2cd340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759765656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1759765656
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3110980154
Short name T575
Test name
Test status
Simulation time 701060371 ps
CPU time 15.58 seconds
Started Aug 18 06:14:36 PM PDT 24
Finished Aug 18 06:14:52 PM PDT 24
Peak memory 208812 kb
Host smart-08111f76-3ba6-469b-b152-fec069b1a527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110980154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3110980154
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.201949418
Short name T855
Test name
Test status
Simulation time 400357257 ps
CPU time 3.56 seconds
Started Aug 18 06:14:37 PM PDT 24
Finished Aug 18 06:14:41 PM PDT 24
Peak memory 207008 kb
Host smart-0e3d8979-df32-46a6-be5d-2ca4d970026f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201949418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.201949418
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1439742244
Short name T178
Test name
Test status
Simulation time 99465382 ps
CPU time 2.51 seconds
Started Aug 18 06:14:39 PM PDT 24
Finished Aug 18 06:14:47 PM PDT 24
Peak memory 207244 kb
Host smart-458818d2-b001-4419-a5e4-4bda918ac294
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439742244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1439742244
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1180221315
Short name T588
Test name
Test status
Simulation time 536963532 ps
CPU time 16.35 seconds
Started Aug 18 06:14:27 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 208948 kb
Host smart-dce49294-dc1d-486b-b573-7c199d9fccc3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180221315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1180221315
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3583948067
Short name T452
Test name
Test status
Simulation time 52246392 ps
CPU time 2.12 seconds
Started Aug 18 06:14:36 PM PDT 24
Finished Aug 18 06:14:38 PM PDT 24
Peak memory 208688 kb
Host smart-044e38d8-422a-4693-a80e-f7b1554f3f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583948067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3583948067
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.541007923
Short name T393
Test name
Test status
Simulation time 155648415 ps
CPU time 4.5 seconds
Started Aug 18 06:14:37 PM PDT 24
Finished Aug 18 06:14:41 PM PDT 24
Peak memory 209032 kb
Host smart-1d91b350-6698-43d6-9bcb-7e0f9040f20d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541007923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.541007923
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2264107962
Short name T610
Test name
Test status
Simulation time 662147461 ps
CPU time 5.75 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 214824 kb
Host smart-1a4479d7-ff8e-41a1-9c56-137011976e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264107962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2264107962
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2053637468
Short name T639
Test name
Test status
Simulation time 1776018331 ps
CPU time 10.11 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 210700 kb
Host smart-831e3b0e-c284-48c2-a210-73111793502f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053637468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2053637468
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2971128400
Short name T442
Test name
Test status
Simulation time 9182247 ps
CPU time 0.74 seconds
Started Aug 18 06:14:56 PM PDT 24
Finished Aug 18 06:14:57 PM PDT 24
Peak memory 206420 kb
Host smart-28e1dee3-c6f9-4aef-ba9c-39c96b8e0b3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971128400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2971128400
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3421947088
Short name T847
Test name
Test status
Simulation time 254170268 ps
CPU time 14.49 seconds
Started Aug 18 06:14:53 PM PDT 24
Finished Aug 18 06:15:08 PM PDT 24
Peak memory 215240 kb
Host smart-45442d88-135f-4604-bcea-d1dab3126341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3421947088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3421947088
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2756136923
Short name T872
Test name
Test status
Simulation time 24842760 ps
CPU time 1.83 seconds
Started Aug 18 06:14:35 PM PDT 24
Finished Aug 18 06:14:37 PM PDT 24
Peak memory 207980 kb
Host smart-921410b4-df42-4a08-a783-f8eba3898544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756136923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2756136923
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3100675243
Short name T395
Test name
Test status
Simulation time 247504781 ps
CPU time 4.07 seconds
Started Aug 18 06:14:39 PM PDT 24
Finished Aug 18 06:14:43 PM PDT 24
Peak memory 214768 kb
Host smart-bc1e89d8-53e7-4ed0-ad93-88e63cc872b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100675243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3100675243
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2957941168
Short name T741
Test name
Test status
Simulation time 95811894 ps
CPU time 2.06 seconds
Started Aug 18 06:14:45 PM PDT 24
Finished Aug 18 06:14:52 PM PDT 24
Peak memory 214720 kb
Host smart-2eca661b-dbea-4599-8667-8388abd5e5b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957941168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2957941168
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.108948622
Short name T658
Test name
Test status
Simulation time 35569300 ps
CPU time 2.79 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 210664 kb
Host smart-820cc3cf-e17f-4f3c-8021-73fbe53274ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108948622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.108948622
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3962670638
Short name T684
Test name
Test status
Simulation time 74690896 ps
CPU time 4.05 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 210624 kb
Host smart-c9200396-2bdb-4e61-8a47-c334c5932321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962670638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3962670638
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2025468898
Short name T71
Test name
Test status
Simulation time 300118795 ps
CPU time 3.17 seconds
Started Aug 18 06:14:44 PM PDT 24
Finished Aug 18 06:14:48 PM PDT 24
Peak memory 207952 kb
Host smart-fdbd8b94-99fa-452d-a196-1114120e7eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025468898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2025468898
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3121120280
Short name T245
Test name
Test status
Simulation time 83822241 ps
CPU time 3.92 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 209284 kb
Host smart-3d520093-8a6e-40e7-a75e-f5e475324681
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121120280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3121120280
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.708128613
Short name T392
Test name
Test status
Simulation time 570214409 ps
CPU time 14.63 seconds
Started Aug 18 06:14:47 PM PDT 24
Finished Aug 18 06:15:02 PM PDT 24
Peak memory 208468 kb
Host smart-67ff12f4-f137-417a-a54c-8d725bb50fa0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708128613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.708128613
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2108723551
Short name T544
Test name
Test status
Simulation time 1399513225 ps
CPU time 14.09 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:55 PM PDT 24
Peak memory 208904 kb
Host smart-2b1e6258-5150-4450-898e-775fbfcc28f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108723551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2108723551
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.886283127
Short name T581
Test name
Test status
Simulation time 73505330 ps
CPU time 1.61 seconds
Started Aug 18 06:14:51 PM PDT 24
Finished Aug 18 06:14:53 PM PDT 24
Peak memory 208884 kb
Host smart-adb7c45c-f26d-44f3-80b4-005d242abf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886283127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.886283127
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1323916090
Short name T748
Test name
Test status
Simulation time 119564180 ps
CPU time 2.69 seconds
Started Aug 18 06:14:45 PM PDT 24
Finished Aug 18 06:14:47 PM PDT 24
Peak memory 207452 kb
Host smart-45d12ad1-9e4b-40eb-ab7b-a5b3d17d7e0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323916090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1323916090
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.578951254
Short name T354
Test name
Test status
Simulation time 3875441907 ps
CPU time 92.74 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:16:11 PM PDT 24
Peak memory 216252 kb
Host smart-0cee9eaf-1309-463f-b337-1c378902b9ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578951254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.578951254
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3644591622
Short name T387
Test name
Test status
Simulation time 896026646 ps
CPU time 5.68 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:47 PM PDT 24
Peak memory 214652 kb
Host smart-2792ad95-0c79-4307-b2e9-19e4575db548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644591622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3644591622
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2559010764
Short name T37
Test name
Test status
Simulation time 99913080 ps
CPU time 1.61 seconds
Started Aug 18 06:14:42 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 210296 kb
Host smart-f8bec20c-ad30-43c4-af03-a80ecd16e397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559010764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2559010764
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3086755020
Short name T761
Test name
Test status
Simulation time 22778979 ps
CPU time 0.73 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:14:43 PM PDT 24
Peak memory 206404 kb
Host smart-7a9f1a94-9e8d-4bb8-a406-ace5217bf6d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086755020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3086755020
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.731937380
Short name T362
Test name
Test status
Simulation time 131240302 ps
CPU time 2.77 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:41 PM PDT 24
Peak memory 216008 kb
Host smart-80b9d71e-8856-45b1-b39b-2227ee842515
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=731937380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.731937380
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.3500011630
Short name T636
Test name
Test status
Simulation time 491472611 ps
CPU time 10.04 seconds
Started Aug 18 06:14:51 PM PDT 24
Finished Aug 18 06:15:01 PM PDT 24
Peak memory 210024 kb
Host smart-6351b1b6-70d3-4787-b59d-0545f7f1accf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500011630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.3500011630
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2465002942
Short name T909
Test name
Test status
Simulation time 61041160 ps
CPU time 2.21 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:40 PM PDT 24
Peak memory 220940 kb
Host smart-75fc6864-fdf1-4b06-9d89-452078229aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465002942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2465002942
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.545465759
Short name T193
Test name
Test status
Simulation time 150249368 ps
CPU time 4.09 seconds
Started Aug 18 06:14:50 PM PDT 24
Finished Aug 18 06:14:54 PM PDT 24
Peak memory 215840 kb
Host smart-d9410237-7b0b-49b1-b79f-65b5409d9bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545465759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.545465759
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.937616921
Short name T550
Test name
Test status
Simulation time 1074120335 ps
CPU time 5.8 seconds
Started Aug 18 06:14:36 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 214784 kb
Host smart-bf5219ab-1e7b-4282-8d1c-72afde8e3f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937616921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.937616921
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2658463224
Short name T867
Test name
Test status
Simulation time 739348706 ps
CPU time 13.14 seconds
Started Aug 18 06:14:39 PM PDT 24
Finished Aug 18 06:14:52 PM PDT 24
Peak memory 209036 kb
Host smart-24fb1011-9a31-47e6-8786-86fdcd402b6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658463224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2658463224
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.486728795
Short name T817
Test name
Test status
Simulation time 319151775 ps
CPU time 3.83 seconds
Started Aug 18 06:14:36 PM PDT 24
Finished Aug 18 06:14:39 PM PDT 24
Peak memory 208976 kb
Host smart-6ca3c23a-0d87-45b2-b2fd-ec647396b3a7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486728795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.486728795
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3244780205
Short name T315
Test name
Test status
Simulation time 390654121 ps
CPU time 10.47 seconds
Started Aug 18 06:14:31 PM PDT 24
Finished Aug 18 06:14:41 PM PDT 24
Peak memory 209592 kb
Host smart-4f26d936-9e9a-47d4-ab4d-297dacdc5198
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244780205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3244780205
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.4111368466
Short name T358
Test name
Test status
Simulation time 93807660 ps
CPU time 2.11 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:40 PM PDT 24
Peak memory 209432 kb
Host smart-91f09e23-f56a-4cca-9743-578e9fa42a95
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111368466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.4111368466
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.460046320
Short name T243
Test name
Test status
Simulation time 2707873673 ps
CPU time 23.43 seconds
Started Aug 18 06:14:37 PM PDT 24
Finished Aug 18 06:15:00 PM PDT 24
Peak memory 209968 kb
Host smart-2be5f2d8-e27a-4510-8186-a6c08bed5887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460046320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.460046320
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3571073910
Short name T456
Test name
Test status
Simulation time 743957576 ps
CPU time 4.4 seconds
Started Aug 18 06:14:37 PM PDT 24
Finished Aug 18 06:14:41 PM PDT 24
Peak memory 208616 kb
Host smart-df2867b6-f89f-4f0f-acd8-0e6666f1f9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571073910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3571073910
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.4289733481
Short name T224
Test name
Test status
Simulation time 271883567 ps
CPU time 5.7 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 215740 kb
Host smart-6a62a106-4792-42fd-8f18-0b082efb9ec8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289733481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.4289733481
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2916538322
Short name T455
Test name
Test status
Simulation time 199754260 ps
CPU time 5.26 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 208052 kb
Host smart-ed7dc0d5-f1e8-4dbb-a0f1-8076c28352f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916538322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2916538322
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1083822466
Short name T188
Test name
Test status
Simulation time 99825580 ps
CPU time 2.35 seconds
Started Aug 18 06:14:37 PM PDT 24
Finished Aug 18 06:14:40 PM PDT 24
Peak memory 210712 kb
Host smart-397f3d64-e957-4ca0-b719-8482f7512ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083822466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1083822466
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2649127192
Short name T734
Test name
Test status
Simulation time 8173558 ps
CPU time 0.72 seconds
Started Aug 18 06:13:32 PM PDT 24
Finished Aug 18 06:13:33 PM PDT 24
Peak memory 206420 kb
Host smart-80d8162f-3d1f-4173-aa29-e74ecb950bcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649127192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2649127192
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.4003706666
Short name T424
Test name
Test status
Simulation time 30507816 ps
CPU time 2.38 seconds
Started Aug 18 06:13:24 PM PDT 24
Finished Aug 18 06:13:26 PM PDT 24
Peak memory 214792 kb
Host smart-89915828-d374-4220-b653-60d064a84bfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4003706666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.4003706666
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.4002686607
Short name T26
Test name
Test status
Simulation time 108774215 ps
CPU time 4.21 seconds
Started Aug 18 06:13:29 PM PDT 24
Finished Aug 18 06:13:33 PM PDT 24
Peak memory 210232 kb
Host smart-ed181065-cac0-487a-8714-4371b0cd8962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002686607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.4002686607
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.977051523
Short name T626
Test name
Test status
Simulation time 23065770 ps
CPU time 1.47 seconds
Started Aug 18 06:13:44 PM PDT 24
Finished Aug 18 06:13:47 PM PDT 24
Peak memory 207672 kb
Host smart-30606793-8808-4f66-a3bf-da782fcc3534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977051523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.977051523
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2430878437
Short name T901
Test name
Test status
Simulation time 178662895 ps
CPU time 4.54 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 221680 kb
Host smart-bb70f54b-b236-4e6c-ba61-94285465af29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430878437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2430878437
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3883404341
Short name T595
Test name
Test status
Simulation time 621077948 ps
CPU time 2.95 seconds
Started Aug 18 06:13:24 PM PDT 24
Finished Aug 18 06:13:27 PM PDT 24
Peak memory 217688 kb
Host smart-8eb0d269-19d5-4065-88d4-6b2665970017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883404341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3883404341
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.131936262
Short name T197
Test name
Test status
Simulation time 74810261 ps
CPU time 2.35 seconds
Started Aug 18 06:13:23 PM PDT 24
Finished Aug 18 06:13:26 PM PDT 24
Peak memory 222780 kb
Host smart-4a312d2e-4169-4ecd-8fcf-ff5ee5442900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=131936262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.131936262
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1556876375
Short name T839
Test name
Test status
Simulation time 851665854 ps
CPU time 12.22 seconds
Started Aug 18 06:13:28 PM PDT 24
Finished Aug 18 06:13:41 PM PDT 24
Peak memory 210236 kb
Host smart-823f62e1-6e7b-47fc-a2e1-2d228b94ce08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556876375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1556876375
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4275447969
Short name T813
Test name
Test status
Simulation time 274267617 ps
CPU time 2.76 seconds
Started Aug 18 06:13:28 PM PDT 24
Finished Aug 18 06:13:31 PM PDT 24
Peak memory 209124 kb
Host smart-52e3ab1c-8ac0-4ad2-bd43-1c1a81d92304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275447969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4275447969
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1416690209
Short name T713
Test name
Test status
Simulation time 4162728415 ps
CPU time 8.07 seconds
Started Aug 18 06:13:32 PM PDT 24
Finished Aug 18 06:13:41 PM PDT 24
Peak memory 208908 kb
Host smart-21e4cec5-104d-4419-bb1e-2ed85d4f47d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416690209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1416690209
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3037474580
Short name T857
Test name
Test status
Simulation time 197422256 ps
CPU time 5.8 seconds
Started Aug 18 06:13:31 PM PDT 24
Finished Aug 18 06:13:37 PM PDT 24
Peak memory 208776 kb
Host smart-623136f1-99a1-4521-bc66-3eff1c8f00f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037474580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3037474580
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.165046734
Short name T500
Test name
Test status
Simulation time 408292452 ps
CPU time 8.55 seconds
Started Aug 18 06:13:26 PM PDT 24
Finished Aug 18 06:13:34 PM PDT 24
Peak memory 207384 kb
Host smart-d29b7fb5-3bce-4574-b515-7791b35aab66
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165046734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.165046734
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.439052875
Short name T556
Test name
Test status
Simulation time 72604856 ps
CPU time 1.68 seconds
Started Aug 18 06:13:40 PM PDT 24
Finished Aug 18 06:13:42 PM PDT 24
Peak memory 216480 kb
Host smart-5dc4e3d7-5885-4a09-a6ac-d8018e8db687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439052875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.439052875
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3432613727
Short name T429
Test name
Test status
Simulation time 362870988 ps
CPU time 3.84 seconds
Started Aug 18 06:13:25 PM PDT 24
Finished Aug 18 06:13:29 PM PDT 24
Peak memory 209004 kb
Host smart-4e9512fa-456a-4228-8ec4-d8cf06b186f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432613727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3432613727
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2043311790
Short name T324
Test name
Test status
Simulation time 237725175 ps
CPU time 6.8 seconds
Started Aug 18 06:13:28 PM PDT 24
Finished Aug 18 06:13:35 PM PDT 24
Peak memory 209468 kb
Host smart-9c066048-77c3-4ad7-9133-f14c85af29a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043311790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2043311790
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1112092985
Short name T351
Test name
Test status
Simulation time 690767276 ps
CPU time 5.78 seconds
Started Aug 18 06:13:18 PM PDT 24
Finished Aug 18 06:13:24 PM PDT 24
Peak memory 214732 kb
Host smart-119e4736-172d-49d9-83a7-c70fa42f406e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112092985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1112092985
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3207052468
Short name T844
Test name
Test status
Simulation time 405346269 ps
CPU time 12.98 seconds
Started Aug 18 06:13:28 PM PDT 24
Finished Aug 18 06:13:41 PM PDT 24
Peak memory 211092 kb
Host smart-b649179a-36be-4cc0-88c0-d3fa1cd5d593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207052468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3207052468
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1705532146
Short name T743
Test name
Test status
Simulation time 10827208 ps
CPU time 0.73 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:14:43 PM PDT 24
Peak memory 206416 kb
Host smart-a3324524-1db5-4344-b0d7-43b2ca7f8dea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705532146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1705532146
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1254569570
Short name T27
Test name
Test status
Simulation time 67263672 ps
CPU time 2.81 seconds
Started Aug 18 06:14:51 PM PDT 24
Finished Aug 18 06:14:54 PM PDT 24
Peak memory 209484 kb
Host smart-aa2a8672-0e3c-4684-9be4-b0d92f5302e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254569570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1254569570
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1602085271
Short name T254
Test name
Test status
Simulation time 99973943 ps
CPU time 2.04 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:41 PM PDT 24
Peak memory 208232 kb
Host smart-85a47e72-01b7-471a-901c-8a8a3f346537
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602085271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1602085271
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1023323215
Short name T49
Test name
Test status
Simulation time 469530986 ps
CPU time 5.86 seconds
Started Aug 18 06:14:39 PM PDT 24
Finished Aug 18 06:14:45 PM PDT 24
Peak memory 214768 kb
Host smart-6d5cb49c-4a89-43d0-a850-9b4706e4e6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023323215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1023323215
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1378212690
Short name T702
Test name
Test status
Simulation time 345079432 ps
CPU time 3.09 seconds
Started Aug 18 06:14:59 PM PDT 24
Finished Aug 18 06:15:02 PM PDT 24
Peak memory 221924 kb
Host smart-a67cfb03-845f-4f29-bdf5-36089873aa85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378212690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1378212690
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1510988859
Short name T201
Test name
Test status
Simulation time 194329468 ps
CPU time 2.49 seconds
Started Aug 18 06:14:39 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 215176 kb
Host smart-148920fb-d038-4db4-bd15-85cf5086f1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510988859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1510988859
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.4059854688
Short name T267
Test name
Test status
Simulation time 116300847 ps
CPU time 5.34 seconds
Started Aug 18 06:14:44 PM PDT 24
Finished Aug 18 06:14:49 PM PDT 24
Peak memory 214820 kb
Host smart-b7dd2dce-2c3b-43fb-aade-dfc520df95d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059854688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.4059854688
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.997145534
Short name T579
Test name
Test status
Simulation time 73917659 ps
CPU time 3.69 seconds
Started Aug 18 06:14:36 PM PDT 24
Finished Aug 18 06:14:40 PM PDT 24
Peak memory 209068 kb
Host smart-f1552288-9fed-4eda-be52-9bc5d0d5497c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997145534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.997145534
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2966366022
Short name T337
Test name
Test status
Simulation time 33504339 ps
CPU time 2.39 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 207840 kb
Host smart-ccf9e90b-ab1a-4213-b455-74c5524b7eec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966366022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2966366022
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2354121326
Short name T443
Test name
Test status
Simulation time 74610924 ps
CPU time 3.67 seconds
Started Aug 18 06:14:39 PM PDT 24
Finished Aug 18 06:14:43 PM PDT 24
Peak memory 209420 kb
Host smart-2fdc47da-b1e0-48bb-97d2-5cc5baa50cc3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354121326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2354121326
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2825287095
Short name T476
Test name
Test status
Simulation time 541242464 ps
CPU time 6.21 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:52 PM PDT 24
Peak memory 208692 kb
Host smart-db1d61fb-e7e6-4e27-834e-e67371870662
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825287095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2825287095
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3427335778
Short name T149
Test name
Test status
Simulation time 2189129444 ps
CPU time 21.96 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:15:06 PM PDT 24
Peak memory 210080 kb
Host smart-11c69128-d3bd-45c0-8ed3-0770d458cf17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427335778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3427335778
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2075868069
Short name T878
Test name
Test status
Simulation time 173689162 ps
CPU time 3.43 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 209096 kb
Host smart-66ff7640-1d11-41e2-8678-056e16290b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075868069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2075868069
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3132033348
Short name T858
Test name
Test status
Simulation time 44393364 ps
CPU time 2.89 seconds
Started Aug 18 06:14:44 PM PDT 24
Finished Aug 18 06:14:47 PM PDT 24
Peak memory 208880 kb
Host smart-e4a5e47c-bbfe-4a78-ad03-935f46a28f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3132033348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3132033348
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.4089036625
Short name T569
Test name
Test status
Simulation time 120494855 ps
CPU time 2.06 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:40 PM PDT 24
Peak memory 210408 kb
Host smart-ed03d334-f2c9-4391-aebf-ab3f16381cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089036625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.4089036625
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3983518639
Short name T641
Test name
Test status
Simulation time 19964274 ps
CPU time 0.78 seconds
Started Aug 18 06:14:45 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 206420 kb
Host smart-38e0e23c-be75-44f1-bf98-71b3b08b5e8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983518639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3983518639
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.521075407
Short name T790
Test name
Test status
Simulation time 64942068 ps
CPU time 2.84 seconds
Started Aug 18 06:14:53 PM PDT 24
Finished Aug 18 06:14:56 PM PDT 24
Peak memory 214828 kb
Host smart-d1078d90-7a0d-4ccc-a050-b513cac68efe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=521075407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.521075407
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1924979615
Short name T436
Test name
Test status
Simulation time 2739325585 ps
CPU time 5.43 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:47 PM PDT 24
Peak memory 209412 kb
Host smart-e70e2286-95e0-4ead-81ef-b430e0688688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924979615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1924979615
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2322623177
Short name T318
Test name
Test status
Simulation time 84459620 ps
CPU time 3.96 seconds
Started Aug 18 06:14:46 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 214780 kb
Host smart-7469e034-74f7-4b10-9c8e-5140320dfff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322623177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2322623177
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3261294310
Short name T15
Test name
Test status
Simulation time 228044527 ps
CPU time 2.25 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 214736 kb
Host smart-322eae8c-58e1-41ae-bfd2-9183abb93c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261294310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3261294310
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3098991052
Short name T196
Test name
Test status
Simulation time 189592710 ps
CPU time 3.2 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:43 PM PDT 24
Peak memory 210496 kb
Host smart-978b85ee-da3a-4af4-a2e2-4c854c43e510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098991052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3098991052
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.511494120
Short name T778
Test name
Test status
Simulation time 707536845 ps
CPU time 5.63 seconds
Started Aug 18 06:15:01 PM PDT 24
Finished Aug 18 06:15:06 PM PDT 24
Peak memory 214868 kb
Host smart-11bd1b92-56ce-4cb4-a2e8-7c607095efed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511494120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.511494120
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1383783646
Short name T441
Test name
Test status
Simulation time 173140485 ps
CPU time 3.45 seconds
Started Aug 18 06:14:50 PM PDT 24
Finished Aug 18 06:14:53 PM PDT 24
Peak memory 207376 kb
Host smart-4f77d8fc-7b94-4647-be3f-15892b1b442c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383783646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1383783646
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.494393710
Short name T329
Test name
Test status
Simulation time 140622165 ps
CPU time 2.46 seconds
Started Aug 18 06:14:48 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 207432 kb
Host smart-229aded3-3f26-4de3-821d-c8ef06387395
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494393710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.494393710
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1535587928
Short name T287
Test name
Test status
Simulation time 69206962 ps
CPU time 3.2 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 208568 kb
Host smart-da3f13a7-0ce6-4dfd-94cc-976123b50033
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535587928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1535587928
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3214405992
Short name T582
Test name
Test status
Simulation time 159236810 ps
CPU time 4.38 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:43 PM PDT 24
Peak memory 208840 kb
Host smart-b8db7ebd-8dfa-446a-90c3-c9aeb014cf84
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214405992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3214405992
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1764513981
Short name T600
Test name
Test status
Simulation time 21173801 ps
CPU time 1.83 seconds
Started Aug 18 06:14:35 PM PDT 24
Finished Aug 18 06:14:37 PM PDT 24
Peak memory 209664 kb
Host smart-f8945347-7a59-4fdb-85ae-488ead914805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764513981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1764513981
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1607270006
Short name T535
Test name
Test status
Simulation time 125901309 ps
CPU time 2.76 seconds
Started Aug 18 06:14:45 PM PDT 24
Finished Aug 18 06:14:48 PM PDT 24
Peak memory 208944 kb
Host smart-614e9c25-0d40-4705-acb3-53bae65f1562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607270006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1607270006
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1993792534
Short name T841
Test name
Test status
Simulation time 198861886 ps
CPU time 4.37 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 209900 kb
Host smart-86718629-627f-440c-8548-01d6ec146e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993792534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1993792534
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1952845353
Short name T643
Test name
Test status
Simulation time 161044294 ps
CPU time 2.07 seconds
Started Aug 18 06:14:42 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 210740 kb
Host smart-0b94ed2e-bc62-40ac-8c7f-5760d0e2bf61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952845353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1952845353
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.349760200
Short name T450
Test name
Test status
Simulation time 9540382 ps
CPU time 0.82 seconds
Started Aug 18 06:14:46 PM PDT 24
Finished Aug 18 06:14:47 PM PDT 24
Peak memory 206432 kb
Host smart-43a3487c-36e3-4cf8-a3c0-4e62fcc7f1cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=349760200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.349760200
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2275613637
Short name T899
Test name
Test status
Simulation time 221262451 ps
CPU time 4.92 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 211172 kb
Host smart-b9fbecb3-3552-45ce-917f-4a136d158087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275613637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2275613637
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.4135106984
Short name T640
Test name
Test status
Simulation time 4021637037 ps
CPU time 16.21 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:15:00 PM PDT 24
Peak memory 218748 kb
Host smart-d9632b41-8de7-46f4-80c2-2288c24fd0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135106984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.4135106984
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2898139085
Short name T57
Test name
Test status
Simulation time 140992794 ps
CPU time 4.25 seconds
Started Aug 18 06:14:46 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 214712 kb
Host smart-5206fe5d-b8bc-40eb-8208-c681f036980d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898139085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2898139085
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1506093647
Short name T355
Test name
Test status
Simulation time 261882743 ps
CPU time 3.66 seconds
Started Aug 18 06:14:56 PM PDT 24
Finished Aug 18 06:15:00 PM PDT 24
Peak memory 207008 kb
Host smart-700f40a0-14af-4aee-89e1-0a91033bf8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506093647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1506093647
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2255793661
Short name T91
Test name
Test status
Simulation time 42924809 ps
CPU time 2.57 seconds
Started Aug 18 06:14:42 PM PDT 24
Finished Aug 18 06:14:45 PM PDT 24
Peak memory 208532 kb
Host smart-ec737e7f-44cd-4037-a8c2-9ad305821bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255793661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2255793661
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1241370726
Short name T583
Test name
Test status
Simulation time 93659239 ps
CPU time 3.91 seconds
Started Aug 18 06:14:58 PM PDT 24
Finished Aug 18 06:15:02 PM PDT 24
Peak memory 210096 kb
Host smart-22217d3d-e8f0-4f93-9676-8f400a20eead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241370726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1241370726
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.4089563724
Short name T34
Test name
Test status
Simulation time 37296388 ps
CPU time 2.38 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:43 PM PDT 24
Peak memory 207312 kb
Host smart-4b560152-6ed9-4214-90bb-f173117de408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089563724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4089563724
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2262645303
Short name T775
Test name
Test status
Simulation time 383049778 ps
CPU time 5.51 seconds
Started Aug 18 06:14:46 PM PDT 24
Finished Aug 18 06:14:51 PM PDT 24
Peak memory 208400 kb
Host smart-9842a23e-b47f-4649-acd7-d017d2138aba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262645303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2262645303
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2949234943
Short name T568
Test name
Test status
Simulation time 46409590 ps
CPU time 2.01 seconds
Started Aug 18 06:14:52 PM PDT 24
Finished Aug 18 06:14:54 PM PDT 24
Peak memory 209092 kb
Host smart-08e38744-fa84-4dc4-9160-6c9ebea188f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949234943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2949234943
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1569778104
Short name T880
Test name
Test status
Simulation time 169701407 ps
CPU time 2.66 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 207700 kb
Host smart-0436d80a-994c-43ae-911d-efb547e6a92d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569778104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1569778104
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.954116461
Short name T438
Test name
Test status
Simulation time 129356228 ps
CPU time 3.07 seconds
Started Aug 18 06:14:39 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 219088 kb
Host smart-c51329ac-2f77-46d2-aece-4c76dc377a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954116461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.954116461
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1532567654
Short name T670
Test name
Test status
Simulation time 82646797 ps
CPU time 2.22 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 208404 kb
Host smart-2ba33a04-ff6a-458c-a777-740e93fedc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532567654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1532567654
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3186641671
Short name T339
Test name
Test status
Simulation time 140173277 ps
CPU time 4.47 seconds
Started Aug 18 06:14:46 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 214688 kb
Host smart-1bfcb569-6fb0-4e95-84d8-2b6bf5c4cce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186641671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3186641671
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.924588935
Short name T607
Test name
Test status
Simulation time 521313539 ps
CPU time 1.87 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:43 PM PDT 24
Peak memory 210328 kb
Host smart-ca15a102-5520-4b10-9295-836e198d2a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924588935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.924588935
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2302584361
Short name T449
Test name
Test status
Simulation time 71661451 ps
CPU time 0.8 seconds
Started Aug 18 06:14:55 PM PDT 24
Finished Aug 18 06:14:56 PM PDT 24
Peak memory 206444 kb
Host smart-32f68efe-394a-4724-a671-44fce1024e6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302584361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2302584361
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2511721221
Short name T405
Test name
Test status
Simulation time 1980556265 ps
CPU time 44.5 seconds
Started Aug 18 06:14:37 PM PDT 24
Finished Aug 18 06:15:22 PM PDT 24
Peak memory 215036 kb
Host smart-1fe583f9-2796-498b-a710-f8e918ff2532
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2511721221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2511721221
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.270592226
Short name T655
Test name
Test status
Simulation time 72435709 ps
CPU time 1.93 seconds
Started Aug 18 06:14:53 PM PDT 24
Finished Aug 18 06:14:55 PM PDT 24
Peak memory 208236 kb
Host smart-d44e2dcf-ca45-4f3c-ba3b-776083566591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270592226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.270592226
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.43112788
Short name T819
Test name
Test status
Simulation time 100957961 ps
CPU time 2.41 seconds
Started Aug 18 06:14:45 PM PDT 24
Finished Aug 18 06:14:47 PM PDT 24
Peak memory 214784 kb
Host smart-eb7708d6-8303-4bc5-8af7-1caea0789fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43112788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.43112788
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.789442812
Short name T333
Test name
Test status
Simulation time 68464606 ps
CPU time 1.6 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:14:45 PM PDT 24
Peak memory 214720 kb
Host smart-8e91faf8-356c-469f-81c6-dd894cf66220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=789442812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.789442812
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1961509886
Short name T340
Test name
Test status
Simulation time 102451450 ps
CPU time 3.47 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 214840 kb
Host smart-5d3e7356-dccb-46df-8932-c145f174d8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961509886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1961509886
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3195011994
Short name T564
Test name
Test status
Simulation time 261647957 ps
CPU time 4.4 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 208316 kb
Host smart-67120ac2-4155-49cf-878d-446ff7c19bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195011994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3195011994
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.4150058724
Short name T229
Test name
Test status
Simulation time 175442772 ps
CPU time 3.83 seconds
Started Aug 18 06:14:44 PM PDT 24
Finished Aug 18 06:14:48 PM PDT 24
Peak memory 209160 kb
Host smart-a3f93efe-2156-4312-986f-52d686e7ffc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150058724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4150058724
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4057254039
Short name T664
Test name
Test status
Simulation time 64085358 ps
CPU time 3.23 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 208772 kb
Host smart-c1cce881-4725-4045-8708-a03e1b69e6ac
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057254039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4057254039
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2682287920
Short name T559
Test name
Test status
Simulation time 1526114004 ps
CPU time 40.97 seconds
Started Aug 18 06:14:44 PM PDT 24
Finished Aug 18 06:15:25 PM PDT 24
Peak memory 209732 kb
Host smart-ee92ab75-d01f-4b35-b7e8-2e045cc82e18
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682287920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2682287920
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3868414010
Short name T634
Test name
Test status
Simulation time 143710049 ps
CPU time 4.16 seconds
Started Aug 18 06:14:57 PM PDT 24
Finished Aug 18 06:15:01 PM PDT 24
Peak memory 208380 kb
Host smart-990702fe-eb3c-4b71-bfc0-49ad3f29d4ce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868414010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3868414010
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1284018584
Short name T682
Test name
Test status
Simulation time 301022640 ps
CPU time 2.34 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 214768 kb
Host smart-5c33a829-90b1-476c-85d1-f63da1cae8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284018584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1284018584
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1128971046
Short name T785
Test name
Test status
Simulation time 33509737 ps
CPU time 2.14 seconds
Started Aug 18 06:14:46 PM PDT 24
Finished Aug 18 06:14:49 PM PDT 24
Peak memory 207288 kb
Host smart-1eec1a13-b573-4b17-8a9a-a9a12f5a0516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128971046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1128971046
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.4126241017
Short name T58
Test name
Test status
Simulation time 288330009 ps
CPU time 13.95 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:54 PM PDT 24
Peak memory 222880 kb
Host smart-6d3303ce-5266-44cb-af96-4b5a2b66c6cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126241017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.4126241017
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2842116621
Short name T755
Test name
Test status
Simulation time 184632019 ps
CPU time 11.4 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:53 PM PDT 24
Peak memory 220856 kb
Host smart-e56f8a63-927b-4eb6-8ca2-20f94a250c2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842116621 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2842116621
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3844229111
Short name T364
Test name
Test status
Simulation time 301546790 ps
CPU time 3.75 seconds
Started Aug 18 06:14:48 PM PDT 24
Finished Aug 18 06:14:52 PM PDT 24
Peak memory 208128 kb
Host smart-1c23a845-65f8-42cb-a760-c2f75907a08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844229111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3844229111
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.957221464
Short name T400
Test name
Test status
Simulation time 214389734 ps
CPU time 2.53 seconds
Started Aug 18 06:14:51 PM PDT 24
Finished Aug 18 06:14:53 PM PDT 24
Peak memory 210360 kb
Host smart-f2e8837e-3ddc-479a-87e7-b164bdeac36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957221464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.957221464
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1227917156
Short name T558
Test name
Test status
Simulation time 63487708 ps
CPU time 0.75 seconds
Started Aug 18 06:14:48 PM PDT 24
Finished Aug 18 06:14:49 PM PDT 24
Peak memory 206412 kb
Host smart-82de8680-a924-4711-b2fd-cceaddfb366e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227917156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1227917156
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.329022081
Short name T113
Test name
Test status
Simulation time 43866691 ps
CPU time 2.56 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:41 PM PDT 24
Peak memory 214800 kb
Host smart-812c039c-6202-485f-8b68-5f7bc4285a15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=329022081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.329022081
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3360945749
Short name T198
Test name
Test status
Simulation time 117907035 ps
CPU time 1.95 seconds
Started Aug 18 06:14:44 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 209248 kb
Host smart-4755ee64-a8d8-4b04-a938-3ec737c36700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3360945749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3360945749
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1204972300
Short name T612
Test name
Test status
Simulation time 652725115 ps
CPU time 5.24 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:14:48 PM PDT 24
Peak memory 222920 kb
Host smart-c0229c76-a144-4059-a3b4-d16537a71b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204972300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1204972300
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1573891963
Short name T759
Test name
Test status
Simulation time 328292432 ps
CPU time 4.06 seconds
Started Aug 18 06:14:42 PM PDT 24
Finished Aug 18 06:14:47 PM PDT 24
Peak memory 222368 kb
Host smart-000bdf32-289b-4bac-9a5b-c5b49f4c1fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573891963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1573891963
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.3095627119
Short name T277
Test name
Test status
Simulation time 59931296 ps
CPU time 2.75 seconds
Started Aug 18 06:14:38 PM PDT 24
Finished Aug 18 06:14:40 PM PDT 24
Peak memory 215232 kb
Host smart-032972db-001a-49c4-a500-91b16b6bacfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095627119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.3095627119
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3159776202
Short name T593
Test name
Test status
Simulation time 228486618 ps
CPU time 6.81 seconds
Started Aug 18 06:14:53 PM PDT 24
Finished Aug 18 06:15:00 PM PDT 24
Peak memory 220776 kb
Host smart-aa3caa86-152a-4cc2-a056-258506aa8501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159776202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3159776202
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.985535290
Short name T306
Test name
Test status
Simulation time 736485010 ps
CPU time 8.33 seconds
Started Aug 18 06:14:47 PM PDT 24
Finished Aug 18 06:14:55 PM PDT 24
Peak memory 209672 kb
Host smart-8afcec20-f02e-4452-b437-9c9f72719572
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985535290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.985535290
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.4164338964
Short name T577
Test name
Test status
Simulation time 275632207 ps
CPU time 4.21 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:45 PM PDT 24
Peak memory 209248 kb
Host smart-2fba3f6e-10fa-4cec-ba5a-04704fdcb166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164338964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4164338964
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.783520612
Short name T240
Test name
Test status
Simulation time 899127874 ps
CPU time 20.79 seconds
Started Aug 18 06:14:55 PM PDT 24
Finished Aug 18 06:15:16 PM PDT 24
Peak memory 208944 kb
Host smart-e14998fb-202e-483a-82da-518614d5fadf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783520612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.783520612
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2530387603
Short name T879
Test name
Test status
Simulation time 816941370 ps
CPU time 6.23 seconds
Started Aug 18 06:14:51 PM PDT 24
Finished Aug 18 06:14:57 PM PDT 24
Peak memory 209192 kb
Host smart-597dcfcf-4c9e-4c8c-ad3b-c7aacface835
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530387603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2530387603
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3503265502
Short name T911
Test name
Test status
Simulation time 179918815 ps
CPU time 3.11 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 207412 kb
Host smart-f96c7f16-ab30-4716-9921-d8d4989a3a28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503265502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3503265502
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.149497636
Short name T690
Test name
Test status
Simulation time 525553950 ps
CPU time 2.85 seconds
Started Aug 18 06:14:52 PM PDT 24
Finished Aug 18 06:14:55 PM PDT 24
Peak memory 210300 kb
Host smart-b2f0bfc4-1acd-4591-8cce-0e9176375e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149497636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.149497636
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3909219907
Short name T674
Test name
Test status
Simulation time 33983453 ps
CPU time 2.21 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 208768 kb
Host smart-e59143d7-1012-4569-9718-ad45bd2bed3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909219907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3909219907
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.533334788
Short name T835
Test name
Test status
Simulation time 75001216 ps
CPU time 4.15 seconds
Started Aug 18 06:14:49 PM PDT 24
Finished Aug 18 06:14:53 PM PDT 24
Peak memory 215580 kb
Host smart-3fb41071-7b00-41db-bf87-e40c8f86b14a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533334788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.533334788
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3935202365
Short name T63
Test name
Test status
Simulation time 255306574 ps
CPU time 8.42 seconds
Started Aug 18 06:14:55 PM PDT 24
Finished Aug 18 06:15:03 PM PDT 24
Peak memory 223048 kb
Host smart-25edef50-e833-4ba4-89f5-0aa002f88323
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935202365 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3935202365
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2293664089
Short name T330
Test name
Test status
Simulation time 121599945 ps
CPU time 4.74 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:47 PM PDT 24
Peak memory 210428 kb
Host smart-838846f1-e690-477b-8d09-a01dbd373ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293664089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2293664089
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.4241640359
Short name T41
Test name
Test status
Simulation time 2268087174 ps
CPU time 19.84 seconds
Started Aug 18 06:14:46 PM PDT 24
Finished Aug 18 06:15:06 PM PDT 24
Peak memory 211372 kb
Host smart-9aa93b41-f953-415d-871f-5fdd0a5f6a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241640359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.4241640359
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3420522252
Short name T62
Test name
Test status
Simulation time 17646507 ps
CPU time 0.82 seconds
Started Aug 18 06:14:50 PM PDT 24
Finished Aug 18 06:14:51 PM PDT 24
Peak memory 206376 kb
Host smart-fbc00a06-4de9-45d2-b3bf-cd2d412b50c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420522252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3420522252
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.3949797967
Short name T589
Test name
Test status
Simulation time 136275408 ps
CPU time 3.05 seconds
Started Aug 18 06:14:45 PM PDT 24
Finished Aug 18 06:14:48 PM PDT 24
Peak memory 218652 kb
Host smart-1af413b5-0de6-48d2-808d-8bad984cffa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949797967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.3949797967
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3465435520
Short name T132
Test name
Test status
Simulation time 258304112 ps
CPU time 4.08 seconds
Started Aug 18 06:14:45 PM PDT 24
Finished Aug 18 06:14:49 PM PDT 24
Peak memory 218900 kb
Host smart-aa1d4cb9-ee33-4f39-ae28-165f52fcc1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465435520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3465435520
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.705888339
Short name T52
Test name
Test status
Simulation time 724905402 ps
CPU time 5.54 seconds
Started Aug 18 06:14:53 PM PDT 24
Finished Aug 18 06:14:59 PM PDT 24
Peak memory 210112 kb
Host smart-f5d3c8a3-9d03-4f02-97e9-d9fb3a9fea34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705888339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.705888339
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.420940335
Short name T686
Test name
Test status
Simulation time 589071244 ps
CPU time 15.65 seconds
Started Aug 18 06:14:47 PM PDT 24
Finished Aug 18 06:15:02 PM PDT 24
Peak memory 214736 kb
Host smart-3c2af341-536c-48a3-8683-b667bdc9db52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=420940335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.420940335
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3780562047
Short name T8
Test name
Test status
Simulation time 333257621 ps
CPU time 3.05 seconds
Started Aug 18 06:15:05 PM PDT 24
Finished Aug 18 06:15:08 PM PDT 24
Peak memory 215768 kb
Host smart-e9b4c08c-e089-4e1b-bc74-0571738d47f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780562047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3780562047
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1328686969
Short name T270
Test name
Test status
Simulation time 409160728 ps
CPU time 8.09 seconds
Started Aug 18 06:14:39 PM PDT 24
Finished Aug 18 06:14:52 PM PDT 24
Peak memory 209604 kb
Host smart-9a226bee-143b-4a87-beca-0c5edc733fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328686969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1328686969
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1142394958
Short name T604
Test name
Test status
Simulation time 210987833 ps
CPU time 6 seconds
Started Aug 18 06:14:45 PM PDT 24
Finished Aug 18 06:14:51 PM PDT 24
Peak memory 208560 kb
Host smart-6e7086fa-f99a-432c-82d5-c132e0824bd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142394958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1142394958
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2704926188
Short name T458
Test name
Test status
Simulation time 23333053 ps
CPU time 1.74 seconds
Started Aug 18 06:14:40 PM PDT 24
Finished Aug 18 06:14:42 PM PDT 24
Peak memory 207448 kb
Host smart-6ab75172-2edc-4903-bdab-6f9a460a4f95
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704926188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2704926188
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.988267282
Short name T703
Test name
Test status
Simulation time 2985059799 ps
CPU time 37.8 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:15:21 PM PDT 24
Peak memory 209016 kb
Host smart-026fdb87-b7b9-4f73-99c0-7cb1fd4ad1b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988267282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.988267282
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1227394492
Short name T314
Test name
Test status
Simulation time 65695426 ps
CPU time 2.24 seconds
Started Aug 18 06:14:45 PM PDT 24
Finished Aug 18 06:14:47 PM PDT 24
Peak memory 207436 kb
Host smart-60e3807a-2064-44cc-8f8f-fc0f5254ffcd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227394492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1227394492
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3541337968
Short name T261
Test name
Test status
Simulation time 311637801 ps
CPU time 4.12 seconds
Started Aug 18 06:14:44 PM PDT 24
Finished Aug 18 06:14:48 PM PDT 24
Peak memory 214716 kb
Host smart-134d8a47-e6c9-470e-a572-78009bd86a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541337968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3541337968
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1964619693
Short name T782
Test name
Test status
Simulation time 48741121 ps
CPU time 2.37 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:43 PM PDT 24
Peak memory 208460 kb
Host smart-e12f34eb-e4b1-45aa-935b-56178364e1ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964619693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1964619693
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3654094401
Short name T121
Test name
Test status
Simulation time 1106203814 ps
CPU time 9.87 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:14:53 PM PDT 24
Peak memory 222388 kb
Host smart-bf53e63c-f06a-4a4d-8e2b-b14637830dd9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654094401 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3654094401
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.298049302
Short name T514
Test name
Test status
Simulation time 105305090 ps
CPU time 3.34 seconds
Started Aug 18 06:14:45 PM PDT 24
Finished Aug 18 06:14:48 PM PDT 24
Peak memory 214824 kb
Host smart-698b1dc1-c831-4d23-a826-5ec9a9e2ce5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298049302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.298049302
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1103440793
Short name T597
Test name
Test status
Simulation time 284330336 ps
CPU time 2.97 seconds
Started Aug 18 06:14:43 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 210720 kb
Host smart-d276cb63-b7a2-414c-bd08-4d15e3a1bc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103440793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1103440793
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.726615503
Short name T615
Test name
Test status
Simulation time 40710111 ps
CPU time 0.83 seconds
Started Aug 18 06:15:05 PM PDT 24
Finished Aug 18 06:15:06 PM PDT 24
Peak memory 206412 kb
Host smart-6ed08254-bb23-4c21-b1af-c9cbc195bf66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726615503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.726615503
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2231834789
Short name T30
Test name
Test status
Simulation time 221066388 ps
CPU time 4.7 seconds
Started Aug 18 06:14:54 PM PDT 24
Finished Aug 18 06:14:59 PM PDT 24
Peak memory 214724 kb
Host smart-afbd0775-3fea-4fcd-8d42-1be775f78c61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231834789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2231834789
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3805320813
Short name T576
Test name
Test status
Simulation time 71755920 ps
CPU time 1.72 seconds
Started Aug 18 06:15:07 PM PDT 24
Finished Aug 18 06:15:08 PM PDT 24
Peak memory 208316 kb
Host smart-00af0daa-3034-4486-8530-d34575ebc7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805320813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3805320813
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1041210998
Short name T372
Test name
Test status
Simulation time 71096075 ps
CPU time 3.56 seconds
Started Aug 18 06:14:47 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 209336 kb
Host smart-703a281e-9ff0-4225-9817-dc73fc470ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041210998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1041210998
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.753399055
Short name T721
Test name
Test status
Simulation time 189650570 ps
CPU time 3.31 seconds
Started Aug 18 06:14:45 PM PDT 24
Finished Aug 18 06:14:49 PM PDT 24
Peak memory 214704 kb
Host smart-0a7a0701-5ec5-4b2d-b3a6-8d25ebeb4e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753399055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.753399055
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1879827407
Short name T505
Test name
Test status
Simulation time 151379677 ps
CPU time 5.11 seconds
Started Aug 18 06:14:45 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 220852 kb
Host smart-b8ec6ada-47c8-4ab4-ab12-9cfbaf022b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879827407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1879827407
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.1550084551
Short name T180
Test name
Test status
Simulation time 541766132 ps
CPU time 6.41 seconds
Started Aug 18 06:14:46 PM PDT 24
Finished Aug 18 06:14:52 PM PDT 24
Peak memory 208636 kb
Host smart-50bc4955-cfbf-436c-8897-74fa13fbd67e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550084551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.1550084551
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3991473579
Short name T478
Test name
Test status
Simulation time 852643371 ps
CPU time 18.32 seconds
Started Aug 18 06:14:44 PM PDT 24
Finished Aug 18 06:15:02 PM PDT 24
Peak memory 208948 kb
Host smart-37273665-557d-42c1-8888-896fcf652aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991473579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3991473579
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3052810277
Short name T665
Test name
Test status
Simulation time 108262913 ps
CPU time 2.84 seconds
Started Aug 18 06:14:52 PM PDT 24
Finished Aug 18 06:14:54 PM PDT 24
Peak memory 209116 kb
Host smart-a02d350a-1ed4-49cf-9aec-3ad7a5820b94
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052810277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3052810277
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2803213377
Short name T629
Test name
Test status
Simulation time 58487330 ps
CPU time 2.77 seconds
Started Aug 18 06:15:01 PM PDT 24
Finished Aug 18 06:15:03 PM PDT 24
Peak memory 208652 kb
Host smart-7bc4088f-ef5c-40f1-98b6-5203bed2ba1a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803213377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2803213377
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.562117874
Short name T309
Test name
Test status
Simulation time 388727269 ps
CPU time 5.16 seconds
Started Aug 18 06:15:07 PM PDT 24
Finished Aug 18 06:15:12 PM PDT 24
Peak memory 209180 kb
Host smart-d9002712-c196-4c07-81b9-4263fb06b217
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562117874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.562117874
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2429974539
Short name T472
Test name
Test status
Simulation time 41507601 ps
CPU time 2.24 seconds
Started Aug 18 06:14:44 PM PDT 24
Finished Aug 18 06:14:47 PM PDT 24
Peak memory 209864 kb
Host smart-6b258a31-4980-458f-b3d9-19ff58e82f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429974539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2429974539
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2612483157
Short name T814
Test name
Test status
Simulation time 81864483 ps
CPU time 3.46 seconds
Started Aug 18 06:15:08 PM PDT 24
Finished Aug 18 06:15:11 PM PDT 24
Peak memory 208820 kb
Host smart-a00222a4-0b52-4160-9127-1913116bc512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612483157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2612483157
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3819420581
Short name T408
Test name
Test status
Simulation time 5287798926 ps
CPU time 48.11 seconds
Started Aug 18 06:14:48 PM PDT 24
Finished Aug 18 06:15:37 PM PDT 24
Peak memory 220468 kb
Host smart-d6bd9f1b-2dd3-4970-bae5-4ebca13287ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819420581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3819420581
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3323648267
Short name T706
Test name
Test status
Simulation time 500215932 ps
CPU time 9.79 seconds
Started Aug 18 06:15:03 PM PDT 24
Finished Aug 18 06:15:13 PM PDT 24
Peak memory 222944 kb
Host smart-243782f8-0b7d-48b7-9919-c7b159b3909f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323648267 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3323648267
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.556975903
Short name T307
Test name
Test status
Simulation time 227886039 ps
CPU time 6.3 seconds
Started Aug 18 06:15:06 PM PDT 24
Finished Aug 18 06:15:12 PM PDT 24
Peak memory 208012 kb
Host smart-278d12ab-9fa0-4e85-9af8-2d13f41fa9b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556975903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.556975903
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.576920610
Short name T506
Test name
Test status
Simulation time 127305458 ps
CPU time 2.75 seconds
Started Aug 18 06:14:41 PM PDT 24
Finished Aug 18 06:14:44 PM PDT 24
Peak memory 210828 kb
Host smart-d6a01ac6-37b9-414b-9f4f-0d2392781007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576920610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.576920610
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1168023503
Short name T609
Test name
Test status
Simulation time 12455022 ps
CPU time 0.79 seconds
Started Aug 18 06:15:12 PM PDT 24
Finished Aug 18 06:15:13 PM PDT 24
Peak memory 206396 kb
Host smart-7e910c5a-d8a4-417d-a4ec-a3ccfe8a712e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168023503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1168023503
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2469590800
Short name T214
Test name
Test status
Simulation time 1325290905 ps
CPU time 12.37 seconds
Started Aug 18 06:15:20 PM PDT 24
Finished Aug 18 06:15:32 PM PDT 24
Peak memory 210336 kb
Host smart-ba9f6148-915c-41a4-bc98-f491e9cb2718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469590800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2469590800
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.821647576
Short name T232
Test name
Test status
Simulation time 258178347 ps
CPU time 2.4 seconds
Started Aug 18 06:15:00 PM PDT 24
Finished Aug 18 06:15:03 PM PDT 24
Peak memory 209644 kb
Host smart-a76b29ed-6568-41e0-8c25-c633ff5311ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821647576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.821647576
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2391027772
Short name T763
Test name
Test status
Simulation time 311174841 ps
CPU time 2.76 seconds
Started Aug 18 06:14:56 PM PDT 24
Finished Aug 18 06:14:59 PM PDT 24
Peak memory 214728 kb
Host smart-87706fc1-8510-4e5b-8955-e4f05279d4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391027772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2391027772
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3141397137
Short name T130
Test name
Test status
Simulation time 63263997 ps
CPU time 3.15 seconds
Started Aug 18 06:15:09 PM PDT 24
Finished Aug 18 06:15:13 PM PDT 24
Peak memory 220704 kb
Host smart-65f9d2ce-eb84-435c-a5be-39befcefa191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141397137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3141397137
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1235857282
Short name T466
Test name
Test status
Simulation time 291081349 ps
CPU time 4.44 seconds
Started Aug 18 06:14:42 PM PDT 24
Finished Aug 18 06:14:46 PM PDT 24
Peak memory 208588 kb
Host smart-a6a89d5b-dd39-4e75-b008-e713ee62c868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235857282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1235857282
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1705461876
Short name T440
Test name
Test status
Simulation time 226930124 ps
CPU time 5.62 seconds
Started Aug 18 06:15:09 PM PDT 24
Finished Aug 18 06:15:14 PM PDT 24
Peak memory 207360 kb
Host smart-1db27c96-ba02-4c07-b378-6ebfd4cdbcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705461876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1705461876
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2279590995
Short name T578
Test name
Test status
Simulation time 447369436 ps
CPU time 2.9 seconds
Started Aug 18 06:15:03 PM PDT 24
Finished Aug 18 06:15:06 PM PDT 24
Peak memory 208960 kb
Host smart-7eeb1f4a-652b-44f4-91e3-6eaaf9ece2d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279590995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2279590995
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2349907068
Short name T833
Test name
Test status
Simulation time 106704641 ps
CPU time 2.88 seconds
Started Aug 18 06:14:46 PM PDT 24
Finished Aug 18 06:14:49 PM PDT 24
Peak memory 207440 kb
Host smart-5e490bc1-1760-4d50-ad1b-60e98ab7eb87
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349907068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2349907068
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2312513144
Short name T555
Test name
Test status
Simulation time 37558712 ps
CPU time 2.35 seconds
Started Aug 18 06:15:12 PM PDT 24
Finished Aug 18 06:15:15 PM PDT 24
Peak memory 207552 kb
Host smart-53731179-8584-4fb6-9840-c5166646a875
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312513144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2312513144
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2196771585
Short name T272
Test name
Test status
Simulation time 4422227599 ps
CPU time 25.47 seconds
Started Aug 18 06:14:58 PM PDT 24
Finished Aug 18 06:15:24 PM PDT 24
Peak memory 218004 kb
Host smart-b10e7352-af42-41ab-bade-331c9a148853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196771585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2196771585
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.3480640672
Short name T574
Test name
Test status
Simulation time 73084294 ps
CPU time 2.24 seconds
Started Aug 18 06:15:07 PM PDT 24
Finished Aug 18 06:15:10 PM PDT 24
Peak memory 208868 kb
Host smart-5d918929-d055-433f-b989-953f0b0d67ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480640672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.3480640672
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.587206964
Short name T271
Test name
Test status
Simulation time 385201057 ps
CPU time 14.33 seconds
Started Aug 18 06:15:07 PM PDT 24
Finished Aug 18 06:15:21 PM PDT 24
Peak memory 217088 kb
Host smart-e1e7ad0b-52bc-4bb8-8190-daf4ae30ab1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587206964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.587206964
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.2355287331
Short name T537
Test name
Test status
Simulation time 1221052196 ps
CPU time 26.58 seconds
Started Aug 18 06:15:10 PM PDT 24
Finished Aug 18 06:15:37 PM PDT 24
Peak memory 223040 kb
Host smart-10ff6721-2f0a-4e65-8579-eb28195f52a0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355287331 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.2355287331
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1103076609
Short name T413
Test name
Test status
Simulation time 331401236 ps
CPU time 4.5 seconds
Started Aug 18 06:15:11 PM PDT 24
Finished Aug 18 06:15:16 PM PDT 24
Peak memory 208736 kb
Host smart-8459f8d9-4e1f-4e09-af2c-c44f4ad96405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103076609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1103076609
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1410736998
Short name T126
Test name
Test status
Simulation time 57785546 ps
CPU time 2.51 seconds
Started Aug 18 06:15:14 PM PDT 24
Finished Aug 18 06:15:17 PM PDT 24
Peak memory 210564 kb
Host smart-49ba79a1-8d49-4ce3-837d-6ffc4929930c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410736998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1410736998
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3538099280
Short name T468
Test name
Test status
Simulation time 18012971 ps
CPU time 0.83 seconds
Started Aug 18 06:15:14 PM PDT 24
Finished Aug 18 06:15:15 PM PDT 24
Peak memory 206388 kb
Host smart-6dbdac6e-9639-4cf1-bcfe-6adbbc4610bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538099280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3538099280
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.712732561
Short name T386
Test name
Test status
Simulation time 61523157 ps
CPU time 2.59 seconds
Started Aug 18 06:14:54 PM PDT 24
Finished Aug 18 06:14:57 PM PDT 24
Peak memory 214916 kb
Host smart-ceb0b55b-d03b-4cbd-b6b9-126a1e6f7224
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=712732561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.712732561
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.4179489746
Short name T823
Test name
Test status
Simulation time 52411885 ps
CPU time 2.48 seconds
Started Aug 18 06:15:08 PM PDT 24
Finished Aug 18 06:15:11 PM PDT 24
Peak memory 223280 kb
Host smart-3082a7ad-854b-4fcf-b69e-89e8c512fc78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179489746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.4179489746
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3874884196
Short name T735
Test name
Test status
Simulation time 769899679 ps
CPU time 4.28 seconds
Started Aug 18 06:14:53 PM PDT 24
Finished Aug 18 06:14:57 PM PDT 24
Peak memory 208580 kb
Host smart-3d303f3b-051c-4e50-9442-dcd7b186a898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874884196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3874884196
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.333862857
Short name T398
Test name
Test status
Simulation time 320867877 ps
CPU time 3.77 seconds
Started Aug 18 06:15:07 PM PDT 24
Finished Aug 18 06:15:11 PM PDT 24
Peak memory 219032 kb
Host smart-e0ff5370-695d-4d7c-a2a4-bdba656d95fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333862857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.333862857
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.588811992
Short name T602
Test name
Test status
Simulation time 245748149 ps
CPU time 4.23 seconds
Started Aug 18 06:15:10 PM PDT 24
Finished Aug 18 06:15:14 PM PDT 24
Peak memory 214784 kb
Host smart-1c0d5586-a427-4e85-a117-09979d5cf742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588811992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.588811992
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2868298173
Short name T668
Test name
Test status
Simulation time 197856141 ps
CPU time 2.75 seconds
Started Aug 18 06:15:15 PM PDT 24
Finished Aug 18 06:15:18 PM PDT 24
Peak memory 208164 kb
Host smart-df48ee62-03e7-449d-8abb-49591372d6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868298173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2868298173
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.945765425
Short name T445
Test name
Test status
Simulation time 84532193 ps
CPU time 3.6 seconds
Started Aug 18 06:14:57 PM PDT 24
Finished Aug 18 06:15:00 PM PDT 24
Peak memory 207392 kb
Host smart-2b96510c-35c6-4047-841f-571586cdbf71
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945765425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.945765425
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2858007014
Short name T148
Test name
Test status
Simulation time 394132066 ps
CPU time 3.05 seconds
Started Aug 18 06:14:47 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 209484 kb
Host smart-164e66be-e3c0-4139-b315-cc3ae6c45b60
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858007014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2858007014
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1545758939
Short name T223
Test name
Test status
Simulation time 153043549 ps
CPU time 1.76 seconds
Started Aug 18 06:14:48 PM PDT 24
Finished Aug 18 06:14:50 PM PDT 24
Peak memory 207416 kb
Host smart-ad1af1cd-3072-48d1-b07d-967b6c7ca1f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545758939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1545758939
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.471306796
Short name T572
Test name
Test status
Simulation time 55371875 ps
CPU time 2.6 seconds
Started Aug 18 06:15:04 PM PDT 24
Finished Aug 18 06:15:06 PM PDT 24
Peak memory 208772 kb
Host smart-130a7346-9ffe-4481-9c9b-d91b1f84249b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471306796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.471306796
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.2386596540
Short name T150
Test name
Test status
Simulation time 72148456 ps
CPU time 2.63 seconds
Started Aug 18 06:15:11 PM PDT 24
Finished Aug 18 06:15:14 PM PDT 24
Peak memory 207540 kb
Host smart-d62846e7-1376-4bc7-8ffd-b199fb68b9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386596540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.2386596540
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2636538074
Short name T770
Test name
Test status
Simulation time 756884360 ps
CPU time 3.83 seconds
Started Aug 18 06:15:03 PM PDT 24
Finished Aug 18 06:15:06 PM PDT 24
Peak memory 209580 kb
Host smart-09b26f6b-3bb1-4d0f-a6df-efb314d18b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636538074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2636538074
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1008010257
Short name T479
Test name
Test status
Simulation time 43417802 ps
CPU time 1.83 seconds
Started Aug 18 06:15:15 PM PDT 24
Finished Aug 18 06:15:17 PM PDT 24
Peak memory 208840 kb
Host smart-7866eac0-868e-4532-aadb-2a3941ac7add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008010257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1008010257
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.640627295
Short name T818
Test name
Test status
Simulation time 31641794 ps
CPU time 0.74 seconds
Started Aug 18 06:15:14 PM PDT 24
Finished Aug 18 06:15:15 PM PDT 24
Peak memory 206400 kb
Host smart-ab52c85d-b282-4b05-92d7-6eff1940aa01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640627295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.640627295
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.632986123
Short name T295
Test name
Test status
Simulation time 169517300 ps
CPU time 3.25 seconds
Started Aug 18 06:15:03 PM PDT 24
Finished Aug 18 06:15:07 PM PDT 24
Peak memory 215928 kb
Host smart-ae0b1be9-867c-48a6-a08e-caaa1733935d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=632986123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.632986123
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2995827552
Short name T336
Test name
Test status
Simulation time 369633731 ps
CPU time 4.54 seconds
Started Aug 18 06:15:08 PM PDT 24
Finished Aug 18 06:15:13 PM PDT 24
Peak memory 211040 kb
Host smart-0c60e9eb-c473-41a3-b42d-714d1b3351dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995827552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2995827552
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1935138257
Short name T54
Test name
Test status
Simulation time 62193689 ps
CPU time 3.63 seconds
Started Aug 18 06:15:15 PM PDT 24
Finished Aug 18 06:15:19 PM PDT 24
Peak memory 214752 kb
Host smart-d97b21e7-86aa-46ee-8552-c562da54eb81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935138257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1935138257
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3469362935
Short name T274
Test name
Test status
Simulation time 370283865 ps
CPU time 4.16 seconds
Started Aug 18 06:15:15 PM PDT 24
Finished Aug 18 06:15:20 PM PDT 24
Peak memory 222388 kb
Host smart-99065c18-d0a2-4bb0-931b-bd843feac7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469362935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3469362935
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.894167521
Short name T618
Test name
Test status
Simulation time 106588405 ps
CPU time 3.21 seconds
Started Aug 18 06:15:13 PM PDT 24
Finished Aug 18 06:15:16 PM PDT 24
Peak memory 217232 kb
Host smart-0c2c5f5b-0df9-4b10-b57b-152887eaadd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894167521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.894167521
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1961098252
Short name T905
Test name
Test status
Simulation time 32813852 ps
CPU time 2.59 seconds
Started Aug 18 06:15:15 PM PDT 24
Finished Aug 18 06:15:17 PM PDT 24
Peak memory 207948 kb
Host smart-4e914331-2df0-409d-a950-e6575be13bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961098252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1961098252
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1162023810
Short name T525
Test name
Test status
Simulation time 595400757 ps
CPU time 10.87 seconds
Started Aug 18 06:15:08 PM PDT 24
Finished Aug 18 06:15:18 PM PDT 24
Peak memory 208568 kb
Host smart-4e6b2e3f-c66e-44a7-8bff-93f96ce3b988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162023810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1162023810
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1523447854
Short name T660
Test name
Test status
Simulation time 38660149 ps
CPU time 1.75 seconds
Started Aug 18 06:15:08 PM PDT 24
Finished Aug 18 06:15:10 PM PDT 24
Peak memory 207404 kb
Host smart-2b7edc27-ff88-4087-b514-31d3dd347b78
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523447854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1523447854
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.25614416
Short name T794
Test name
Test status
Simulation time 319291751 ps
CPU time 4.25 seconds
Started Aug 18 06:15:15 PM PDT 24
Finished Aug 18 06:15:19 PM PDT 24
Peak memory 207432 kb
Host smart-259db764-0640-451e-98df-f13617fac22a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25614416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.25614416
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2737129384
Short name T836
Test name
Test status
Simulation time 119864094 ps
CPU time 2.42 seconds
Started Aug 18 06:15:15 PM PDT 24
Finished Aug 18 06:15:17 PM PDT 24
Peak memory 207452 kb
Host smart-3baae6a2-40ec-4711-92e2-88b086c586a2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737129384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2737129384
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2167197613
Short name T242
Test name
Test status
Simulation time 257494247 ps
CPU time 3.49 seconds
Started Aug 18 06:15:22 PM PDT 24
Finished Aug 18 06:15:26 PM PDT 24
Peak memory 214736 kb
Host smart-cc87359d-695e-4bc4-bf64-fc13709473f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167197613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2167197613
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3219833254
Short name T433
Test name
Test status
Simulation time 760432068 ps
CPU time 4.77 seconds
Started Aug 18 06:15:02 PM PDT 24
Finished Aug 18 06:15:07 PM PDT 24
Peak memory 209132 kb
Host smart-52398558-b8fe-47e9-ae9c-93dfd222345d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219833254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3219833254
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.615311886
Short name T203
Test name
Test status
Simulation time 5290753555 ps
CPU time 33.19 seconds
Started Aug 18 06:15:18 PM PDT 24
Finished Aug 18 06:15:52 PM PDT 24
Peak memory 215160 kb
Host smart-e4bca5b7-9e16-4320-ab97-f1b5f61e1232
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615311886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.615311886
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.4112188805
Short name T624
Test name
Test status
Simulation time 177522449 ps
CPU time 5.32 seconds
Started Aug 18 06:15:12 PM PDT 24
Finished Aug 18 06:15:18 PM PDT 24
Peak memory 210720 kb
Host smart-b609f740-5b0b-48f5-a8f4-6696dfe9acc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112188805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.4112188805
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2014712669
Short name T652
Test name
Test status
Simulation time 121806078 ps
CPU time 3.46 seconds
Started Aug 18 06:15:14 PM PDT 24
Finished Aug 18 06:15:18 PM PDT 24
Peak memory 211336 kb
Host smart-564745a0-053d-496c-acb6-548ebf126d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014712669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2014712669
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.367925420
Short name T428
Test name
Test status
Simulation time 44901867 ps
CPU time 0.92 seconds
Started Aug 18 06:13:31 PM PDT 24
Finished Aug 18 06:13:32 PM PDT 24
Peak memory 206400 kb
Host smart-c98cd6a2-8182-4a11-850c-0f79cdef4e1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367925420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.367925420
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3993881110
Short name T39
Test name
Test status
Simulation time 88673092 ps
CPU time 3.26 seconds
Started Aug 18 06:13:34 PM PDT 24
Finished Aug 18 06:13:38 PM PDT 24
Peak memory 210356 kb
Host smart-7f4e25f9-79fb-4e3a-9dc6-24e58513bdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993881110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3993881110
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4292758623
Short name T900
Test name
Test status
Simulation time 47105254 ps
CPU time 2.58 seconds
Started Aug 18 06:13:24 PM PDT 24
Finished Aug 18 06:13:27 PM PDT 24
Peak memory 214784 kb
Host smart-b8bfc065-dd26-458a-8fda-bb33d88d80a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292758623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4292758623
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1376923622
Short name T50
Test name
Test status
Simulation time 553239901 ps
CPU time 11.21 seconds
Started Aug 18 06:13:31 PM PDT 24
Finished Aug 18 06:13:42 PM PDT 24
Peak memory 221336 kb
Host smart-d105d9a9-bbae-409f-abe5-f05e5bb56709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376923622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1376923622
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.651398794
Short name T829
Test name
Test status
Simulation time 186991387 ps
CPU time 3.28 seconds
Started Aug 18 06:13:34 PM PDT 24
Finished Aug 18 06:13:38 PM PDT 24
Peak memory 214592 kb
Host smart-a9eeca07-acca-43db-9a3c-8efdf7cf61bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651398794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.651398794
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2039000158
Short name T586
Test name
Test status
Simulation time 33970501 ps
CPU time 1.57 seconds
Started Aug 18 06:13:15 PM PDT 24
Finished Aug 18 06:13:16 PM PDT 24
Peak memory 215356 kb
Host smart-02237a78-95f8-4915-8609-40d7de51d180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039000158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2039000158
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2813959811
Short name T638
Test name
Test status
Simulation time 980471319 ps
CPU time 4.25 seconds
Started Aug 18 06:13:26 PM PDT 24
Finished Aug 18 06:13:31 PM PDT 24
Peak memory 208164 kb
Host smart-39c876de-ef3d-44f8-ab1e-1759b2a6b012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813959811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2813959811
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1616485422
Short name T756
Test name
Test status
Simulation time 146405787 ps
CPU time 4.69 seconds
Started Aug 18 06:13:30 PM PDT 24
Finished Aug 18 06:13:35 PM PDT 24
Peak memory 207420 kb
Host smart-5651a3bd-12b5-4cb9-9cb0-1892072c3742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616485422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1616485422
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1816073131
Short name T551
Test name
Test status
Simulation time 138882771 ps
CPU time 3.55 seconds
Started Aug 18 06:13:20 PM PDT 24
Finished Aug 18 06:13:24 PM PDT 24
Peak memory 207180 kb
Host smart-dd8d1ab5-64b4-49b4-a734-8a78953fce1a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816073131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1816073131
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.322945942
Short name T534
Test name
Test status
Simulation time 24374376 ps
CPU time 2.01 seconds
Started Aug 18 06:13:34 PM PDT 24
Finished Aug 18 06:13:36 PM PDT 24
Peak memory 209116 kb
Host smart-5617712e-c3fe-47cd-a6b8-b97b7563a110
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322945942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.322945942
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.301844327
Short name T723
Test name
Test status
Simulation time 711252422 ps
CPU time 23.14 seconds
Started Aug 18 06:13:43 PM PDT 24
Finished Aug 18 06:14:06 PM PDT 24
Peak memory 209188 kb
Host smart-4a870c4c-7841-49b2-ac70-841273be96c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=301844327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.301844327
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.2821222080
Short name T246
Test name
Test status
Simulation time 1230050171 ps
CPU time 4.51 seconds
Started Aug 18 06:13:31 PM PDT 24
Finished Aug 18 06:13:36 PM PDT 24
Peak memory 210080 kb
Host smart-e1a3be9f-4847-4979-b05c-4f09cd7d5143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821222080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.2821222080
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4206747015
Short name T503
Test name
Test status
Simulation time 323069413 ps
CPU time 5.3 seconds
Started Aug 18 06:13:19 PM PDT 24
Finished Aug 18 06:13:24 PM PDT 24
Peak memory 208860 kb
Host smart-d898d667-8f49-404b-9de2-c9551b205948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4206747015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4206747015
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3344917544
Short name T828
Test name
Test status
Simulation time 436520887 ps
CPU time 17.11 seconds
Started Aug 18 06:13:29 PM PDT 24
Finished Aug 18 06:13:46 PM PDT 24
Peak memory 216284 kb
Host smart-b157f4bd-731a-4f26-8c86-f51d5af07f22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3344917544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3344917544
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2964623430
Short name T528
Test name
Test status
Simulation time 422937507 ps
CPU time 3.44 seconds
Started Aug 18 06:13:21 PM PDT 24
Finished Aug 18 06:13:25 PM PDT 24
Peak memory 208040 kb
Host smart-343392e5-ca4c-46fa-921c-bd9196a323d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964623430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2964623430
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3898694836
Short name T127
Test name
Test status
Simulation time 34257619 ps
CPU time 2.17 seconds
Started Aug 18 06:13:39 PM PDT 24
Finished Aug 18 06:13:41 PM PDT 24
Peak memory 210420 kb
Host smart-538121b7-432e-467b-8f08-a6f0e41f1a00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898694836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3898694836
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3873631710
Short name T434
Test name
Test status
Simulation time 41791183 ps
CPU time 0.77 seconds
Started Aug 18 06:15:20 PM PDT 24
Finished Aug 18 06:15:21 PM PDT 24
Peak memory 206372 kb
Host smart-24e0578e-854b-4739-b08b-731b5b1662cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873631710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3873631710
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3212401094
Short name T143
Test name
Test status
Simulation time 309922505 ps
CPU time 2.25 seconds
Started Aug 18 06:15:32 PM PDT 24
Finished Aug 18 06:15:35 PM PDT 24
Peak memory 208368 kb
Host smart-1bae3a85-4732-4839-a829-cf7f00ab1abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212401094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3212401094
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.460828899
Short name T650
Test name
Test status
Simulation time 99121916 ps
CPU time 1.75 seconds
Started Aug 18 06:15:18 PM PDT 24
Finished Aug 18 06:15:20 PM PDT 24
Peak memory 214836 kb
Host smart-ed76cc06-db10-4668-8c25-c89ce248c492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460828899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.460828899
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1835057647
Short name T765
Test name
Test status
Simulation time 57198177 ps
CPU time 2.86 seconds
Started Aug 18 06:15:19 PM PDT 24
Finished Aug 18 06:15:22 PM PDT 24
Peak memory 222860 kb
Host smart-b9093b3d-0a9d-4006-9283-a22461c2e8d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835057647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1835057647
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1580761797
Short name T850
Test name
Test status
Simulation time 43611371 ps
CPU time 2.77 seconds
Started Aug 18 06:15:28 PM PDT 24
Finished Aug 18 06:15:31 PM PDT 24
Peak memory 208892 kb
Host smart-1b8365b3-d26b-4a48-a353-b21416e96867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580761797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1580761797
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2679507574
Short name T335
Test name
Test status
Simulation time 202353361 ps
CPU time 3.51 seconds
Started Aug 18 06:15:17 PM PDT 24
Finished Aug 18 06:15:21 PM PDT 24
Peak memory 218964 kb
Host smart-93841db5-6d78-4728-93a6-941a183baf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2679507574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2679507574
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.241162722
Short name T290
Test name
Test status
Simulation time 99602079 ps
CPU time 2.57 seconds
Started Aug 18 06:15:12 PM PDT 24
Finished Aug 18 06:15:15 PM PDT 24
Peak memory 207440 kb
Host smart-c4457301-21e1-4e34-af20-6cf4d8cd2564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241162722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.241162722
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2106470683
Short name T792
Test name
Test status
Simulation time 466879972 ps
CPU time 6.34 seconds
Started Aug 18 06:15:18 PM PDT 24
Finished Aug 18 06:15:25 PM PDT 24
Peak memory 208672 kb
Host smart-ecad4d80-74bb-4296-a7ac-3194b23c9fc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106470683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2106470683
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2067382464
Short name T730
Test name
Test status
Simulation time 150488358 ps
CPU time 4.9 seconds
Started Aug 18 06:15:11 PM PDT 24
Finished Aug 18 06:15:16 PM PDT 24
Peak memory 209020 kb
Host smart-34417cf5-1586-4ad3-ba89-82654cc4700c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067382464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2067382464
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2643098258
Short name T736
Test name
Test status
Simulation time 1391514263 ps
CPU time 8.37 seconds
Started Aug 18 06:15:21 PM PDT 24
Finished Aug 18 06:15:29 PM PDT 24
Peak memory 209420 kb
Host smart-60b297e9-db78-4ae4-a414-e2ee5bf3e898
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643098258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2643098258
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3884468650
Short name T704
Test name
Test status
Simulation time 86438024 ps
CPU time 3.65 seconds
Started Aug 18 06:15:18 PM PDT 24
Finished Aug 18 06:15:22 PM PDT 24
Peak memory 214752 kb
Host smart-9837e05b-9a66-4674-90a6-1ea51c8a158c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884468650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3884468650
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1579980836
Short name T477
Test name
Test status
Simulation time 78263212 ps
CPU time 2.86 seconds
Started Aug 18 06:15:07 PM PDT 24
Finished Aug 18 06:15:10 PM PDT 24
Peak memory 209012 kb
Host smart-490814bc-37e8-4784-a2ec-95d704f765c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579980836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1579980836
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1800541511
Short name T348
Test name
Test status
Simulation time 51690035 ps
CPU time 2.29 seconds
Started Aug 18 06:15:15 PM PDT 24
Finished Aug 18 06:15:17 PM PDT 24
Peak memory 207672 kb
Host smart-2f9ceb4f-23fa-4e0f-93a2-9a4a0526743e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800541511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1800541511
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2987386070
Short name T187
Test name
Test status
Simulation time 53806922 ps
CPU time 1.59 seconds
Started Aug 18 06:15:15 PM PDT 24
Finished Aug 18 06:15:17 PM PDT 24
Peak memory 210216 kb
Host smart-5b7815fd-d085-44fa-8b4b-202e9017cd53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987386070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2987386070
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1885969252
Short name T611
Test name
Test status
Simulation time 31310878 ps
CPU time 1 seconds
Started Aug 18 06:15:22 PM PDT 24
Finished Aug 18 06:15:23 PM PDT 24
Peak memory 206532 kb
Host smart-fc4c4b7f-d7de-4fd7-84b7-b32d9275485e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885969252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1885969252
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3955733941
Short name T11
Test name
Test status
Simulation time 395915409 ps
CPU time 3.04 seconds
Started Aug 18 06:15:17 PM PDT 24
Finished Aug 18 06:15:20 PM PDT 24
Peak memory 218012 kb
Host smart-c24003a5-1bf4-4b12-8ea4-eeab517ba04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955733941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3955733941
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2029321779
Short name T139
Test name
Test status
Simulation time 75008863 ps
CPU time 3.46 seconds
Started Aug 18 06:15:27 PM PDT 24
Finished Aug 18 06:15:31 PM PDT 24
Peak memory 210824 kb
Host smart-6a3d2fda-327c-4f1f-8c13-423c69b3865c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029321779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2029321779
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.562311084
Short name T316
Test name
Test status
Simulation time 97360072 ps
CPU time 2.47 seconds
Started Aug 18 06:15:35 PM PDT 24
Finished Aug 18 06:15:37 PM PDT 24
Peak memory 222992 kb
Host smart-3adb5b1e-31ef-47c3-adbc-e333f13083f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562311084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.562311084
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.799384186
Short name T119
Test name
Test status
Simulation time 397094936 ps
CPU time 3.58 seconds
Started Aug 18 06:15:11 PM PDT 24
Finished Aug 18 06:15:15 PM PDT 24
Peak memory 214740 kb
Host smart-87b5a8bd-5890-402d-a59c-fdb35f3f8904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799384186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.799384186
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3894200988
Short name T319
Test name
Test status
Simulation time 182811225 ps
CPU time 5.52 seconds
Started Aug 18 06:15:17 PM PDT 24
Finished Aug 18 06:15:22 PM PDT 24
Peak memory 214884 kb
Host smart-c5e92dce-1c4d-4539-81f0-5960eb028b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894200988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3894200988
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3622870716
Short name T633
Test name
Test status
Simulation time 77480823 ps
CPU time 2.44 seconds
Started Aug 18 06:15:13 PM PDT 24
Finished Aug 18 06:15:15 PM PDT 24
Peak memory 207324 kb
Host smart-38aed634-c95d-4721-96b2-ccd73967cb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622870716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3622870716
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3159603063
Short name T518
Test name
Test status
Simulation time 139686285 ps
CPU time 2.95 seconds
Started Aug 18 06:15:27 PM PDT 24
Finished Aug 18 06:15:30 PM PDT 24
Peak memory 207460 kb
Host smart-e9f0faa9-ebd6-4a3f-9720-4bd3dee33b9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159603063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3159603063
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.807459654
Short name T806
Test name
Test status
Simulation time 1990820734 ps
CPU time 15.42 seconds
Started Aug 18 06:15:17 PM PDT 24
Finished Aug 18 06:15:33 PM PDT 24
Peak memory 209136 kb
Host smart-5dec50a9-c289-4b8e-ae56-eb0bdbe9ba04
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807459654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.807459654
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.661702557
Short name T731
Test name
Test status
Simulation time 10354853860 ps
CPU time 36.67 seconds
Started Aug 18 06:15:14 PM PDT 24
Finished Aug 18 06:15:51 PM PDT 24
Peak memory 209284 kb
Host smart-418737ec-640c-4599-957e-21c5b47f06b0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661702557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.661702557
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1930055174
Short name T654
Test name
Test status
Simulation time 221522420 ps
CPU time 1.96 seconds
Started Aug 18 06:15:18 PM PDT 24
Finished Aug 18 06:15:20 PM PDT 24
Peak memory 208056 kb
Host smart-2b39ee13-4050-44b0-a8d6-a643f0c12573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930055174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1930055174
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.187084542
Short name T444
Test name
Test status
Simulation time 38186966 ps
CPU time 2.21 seconds
Started Aug 18 06:15:24 PM PDT 24
Finished Aug 18 06:15:26 PM PDT 24
Peak memory 208832 kb
Host smart-b3c50b06-8a3a-44f9-a556-be4cafcbe08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187084542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.187084542
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1988568938
Short name T345
Test name
Test status
Simulation time 477429365 ps
CPU time 5.9 seconds
Started Aug 18 06:15:16 PM PDT 24
Finished Aug 18 06:15:22 PM PDT 24
Peak memory 222880 kb
Host smart-689126e8-7b30-474a-8572-b277990289ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988568938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1988568938
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1746934597
Short name T616
Test name
Test status
Simulation time 66380334 ps
CPU time 2.59 seconds
Started Aug 18 06:15:36 PM PDT 24
Finished Aug 18 06:15:39 PM PDT 24
Peak memory 210504 kb
Host smart-55e6243a-67cc-4e13-aecd-9d0bc140acfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746934597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1746934597
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.2348621255
Short name T681
Test name
Test status
Simulation time 47441123 ps
CPU time 0.76 seconds
Started Aug 18 06:15:30 PM PDT 24
Finished Aug 18 06:15:31 PM PDT 24
Peak memory 206548 kb
Host smart-b74d9eac-fe3e-458c-81dc-13d626d4edfc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348621255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.2348621255
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2401094699
Short name T383
Test name
Test status
Simulation time 33386860 ps
CPU time 2.66 seconds
Started Aug 18 06:15:31 PM PDT 24
Finished Aug 18 06:15:33 PM PDT 24
Peak memory 214680 kb
Host smart-557019d3-a249-4aee-a54f-01eb37e41727
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2401094699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2401094699
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.500477762
Short name T135
Test name
Test status
Simulation time 247902096 ps
CPU time 2.51 seconds
Started Aug 18 06:15:28 PM PDT 24
Finished Aug 18 06:15:31 PM PDT 24
Peak memory 207904 kb
Host smart-53210663-5ef0-41c3-80f6-e3e5739dcae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500477762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.500477762
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1944849055
Short name T530
Test name
Test status
Simulation time 85920492 ps
CPU time 2.98 seconds
Started Aug 18 06:15:34 PM PDT 24
Finished Aug 18 06:15:38 PM PDT 24
Peak memory 214708 kb
Host smart-dda5d54a-249d-4315-9045-cf2467c459fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944849055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1944849055
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1580371702
Short name T293
Test name
Test status
Simulation time 493452258 ps
CPU time 5.55 seconds
Started Aug 18 06:15:28 PM PDT 24
Finished Aug 18 06:15:34 PM PDT 24
Peak memory 222972 kb
Host smart-eae5be9b-8491-4fcb-b673-f41e5c424983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580371702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1580371702
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3236719176
Short name T773
Test name
Test status
Simulation time 422888639 ps
CPU time 7.45 seconds
Started Aug 18 06:15:35 PM PDT 24
Finished Aug 18 06:15:42 PM PDT 24
Peak memory 220832 kb
Host smart-65fb274d-2e05-4592-9bf1-8be543bcebc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236719176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3236719176
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1966428263
Short name T510
Test name
Test status
Simulation time 296743761 ps
CPU time 9.34 seconds
Started Aug 18 06:15:20 PM PDT 24
Finished Aug 18 06:15:29 PM PDT 24
Peak memory 218784 kb
Host smart-44bcd16e-bc66-4447-bf84-5c9a2a2eb89a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966428263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1966428263
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1594814377
Short name T822
Test name
Test status
Simulation time 39904606 ps
CPU time 2.17 seconds
Started Aug 18 06:15:31 PM PDT 24
Finished Aug 18 06:15:33 PM PDT 24
Peak memory 207116 kb
Host smart-7c59569a-26cb-4830-b35d-060c4c47c621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594814377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1594814377
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3820547933
Short name T902
Test name
Test status
Simulation time 330811337 ps
CPU time 2.92 seconds
Started Aug 18 06:15:30 PM PDT 24
Finished Aug 18 06:15:33 PM PDT 24
Peak memory 208900 kb
Host smart-f44e9698-b637-453f-bf86-447c039567b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820547933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3820547933
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2705774979
Short name T864
Test name
Test status
Simulation time 44504966 ps
CPU time 2.57 seconds
Started Aug 18 06:15:24 PM PDT 24
Finished Aug 18 06:15:27 PM PDT 24
Peak memory 208940 kb
Host smart-8ac58519-ca37-4071-8d4a-2197a5850539
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705774979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2705774979
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.481734818
Short name T580
Test name
Test status
Simulation time 278371314 ps
CPU time 3.1 seconds
Started Aug 18 06:15:24 PM PDT 24
Finished Aug 18 06:15:27 PM PDT 24
Peak memory 207472 kb
Host smart-c7b5b80a-b19d-482d-9afa-78d0908a0581
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481734818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.481734818
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.317125556
Short name T642
Test name
Test status
Simulation time 463213560 ps
CPU time 3.85 seconds
Started Aug 18 06:15:35 PM PDT 24
Finished Aug 18 06:15:39 PM PDT 24
Peak memory 214648 kb
Host smart-65980320-86a3-439d-9fce-0860e4371f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317125556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.317125556
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4180780976
Short name T446
Test name
Test status
Simulation time 30551171 ps
CPU time 1.99 seconds
Started Aug 18 06:15:21 PM PDT 24
Finished Aug 18 06:15:23 PM PDT 24
Peak memory 207448 kb
Host smart-371b473f-1458-44da-b9c7-4ed020d9a1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180780976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4180780976
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.4058116655
Short name T202
Test name
Test status
Simulation time 843692884 ps
CPU time 21.6 seconds
Started Aug 18 06:15:36 PM PDT 24
Finished Aug 18 06:15:58 PM PDT 24
Peak memory 222804 kb
Host smart-7979dd0c-ed6f-49fe-bb1a-662bc639cc4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058116655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.4058116655
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1885718448
Short name T241
Test name
Test status
Simulation time 125263439 ps
CPU time 2.64 seconds
Started Aug 18 06:15:34 PM PDT 24
Finished Aug 18 06:15:38 PM PDT 24
Peak memory 210148 kb
Host smart-908609b7-0a58-42e2-aba5-3dc6d8db804a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885718448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1885718448
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1565220038
Short name T887
Test name
Test status
Simulation time 60192163 ps
CPU time 2.59 seconds
Started Aug 18 06:15:37 PM PDT 24
Finished Aug 18 06:15:40 PM PDT 24
Peak memory 210692 kb
Host smart-891f81bf-93ad-41f2-9e2c-74b3ed26c4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565220038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1565220038
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2353362255
Short name T683
Test name
Test status
Simulation time 26461603 ps
CPU time 0.97 seconds
Started Aug 18 06:16:06 PM PDT 24
Finished Aug 18 06:16:07 PM PDT 24
Peak memory 206320 kb
Host smart-92911035-3d31-469b-b49e-e8931b8c6315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353362255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2353362255
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.849553172
Short name T247
Test name
Test status
Simulation time 91404095 ps
CPU time 3.64 seconds
Started Aug 18 06:15:21 PM PDT 24
Finished Aug 18 06:15:25 PM PDT 24
Peak memory 214728 kb
Host smart-2c4553a0-499b-4fe4-b130-dc87da937e8e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=849553172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.849553172
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.88199314
Short name T29
Test name
Test status
Simulation time 118522901 ps
CPU time 1.26 seconds
Started Aug 18 06:15:38 PM PDT 24
Finished Aug 18 06:15:39 PM PDT 24
Peak memory 215416 kb
Host smart-34524303-7aaf-4c8b-a76e-724be45d52e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88199314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.88199314
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.4084829230
Short name T124
Test name
Test status
Simulation time 112416450 ps
CPU time 2.08 seconds
Started Aug 18 06:15:34 PM PDT 24
Finished Aug 18 06:15:36 PM PDT 24
Peak memory 207960 kb
Host smart-cf72f9ab-eb6e-4d06-8e44-a84ee89c46a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084829230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.4084829230
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.325850230
Short name T762
Test name
Test status
Simulation time 5282632367 ps
CPU time 32.03 seconds
Started Aug 18 06:15:34 PM PDT 24
Finished Aug 18 06:16:06 PM PDT 24
Peak memory 214860 kb
Host smart-bfe1682a-20f7-41cc-93f9-f443b886e3ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325850230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.325850230
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.4159342699
Short name T540
Test name
Test status
Simulation time 663329307 ps
CPU time 3.24 seconds
Started Aug 18 06:15:45 PM PDT 24
Finished Aug 18 06:15:49 PM PDT 24
Peak memory 214764 kb
Host smart-3894fd36-7c41-4d22-bb56-4b90f491a89e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159342699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.4159342699
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_random.3881733132
Short name T325
Test name
Test status
Simulation time 60455241 ps
CPU time 3.71 seconds
Started Aug 18 06:15:34 PM PDT 24
Finished Aug 18 06:15:38 PM PDT 24
Peak memory 208264 kb
Host smart-8024ae97-f3f5-42b7-8688-664742a4387e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881733132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3881733132
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2605051116
Short name T587
Test name
Test status
Simulation time 93201161 ps
CPU time 2.09 seconds
Started Aug 18 06:15:41 PM PDT 24
Finished Aug 18 06:15:43 PM PDT 24
Peak memory 209204 kb
Host smart-b81f2da6-3bf6-40b2-8763-332b0ea4be66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605051116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2605051116
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2748778252
Short name T868
Test name
Test status
Simulation time 605133065 ps
CPU time 6.82 seconds
Started Aug 18 06:15:33 PM PDT 24
Finished Aug 18 06:15:39 PM PDT 24
Peak memory 208632 kb
Host smart-de596107-730b-4a6f-9bf1-7f1ff8494b3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748778252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2748778252
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.535712818
Short name T262
Test name
Test status
Simulation time 1295755395 ps
CPU time 19.67 seconds
Started Aug 18 06:15:34 PM PDT 24
Finished Aug 18 06:15:54 PM PDT 24
Peak memory 208744 kb
Host smart-c2a1c10c-80d7-4d7e-9fa5-24818bf34660
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535712818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.535712818
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.88666652
Short name T533
Test name
Test status
Simulation time 331811365 ps
CPU time 4.93 seconds
Started Aug 18 06:15:33 PM PDT 24
Finished Aug 18 06:15:38 PM PDT 24
Peak memory 208716 kb
Host smart-7bf5f63d-6539-4a1e-b5fc-bb953de23f8e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88666652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.88666652
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3859729615
Short name T820
Test name
Test status
Simulation time 634944682 ps
CPU time 4 seconds
Started Aug 18 06:15:48 PM PDT 24
Finished Aug 18 06:15:53 PM PDT 24
Peak memory 210364 kb
Host smart-a77e4ead-550d-4130-b20b-9695dfb31485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859729615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3859729615
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3578630536
Short name T491
Test name
Test status
Simulation time 21606366 ps
CPU time 1.79 seconds
Started Aug 18 06:15:34 PM PDT 24
Finished Aug 18 06:15:36 PM PDT 24
Peak memory 208932 kb
Host smart-ecdcca8b-c34e-44a0-ba64-f98b77232d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578630536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3578630536
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3669963242
Short name T733
Test name
Test status
Simulation time 354085710 ps
CPU time 2.76 seconds
Started Aug 18 06:15:38 PM PDT 24
Finished Aug 18 06:15:41 PM PDT 24
Peak memory 214800 kb
Host smart-3adffb4e-630a-4f9d-8d14-a4ace3743d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669963242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3669963242
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.205169177
Short name T490
Test name
Test status
Simulation time 213993731 ps
CPU time 2.46 seconds
Started Aug 18 06:15:32 PM PDT 24
Finished Aug 18 06:15:35 PM PDT 24
Peak memory 210696 kb
Host smart-d3cbaf8f-81ef-4c39-a2c0-46923d9395fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205169177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.205169177
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.3459988912
Short name T859
Test name
Test status
Simulation time 45325975 ps
CPU time 0.86 seconds
Started Aug 18 06:15:36 PM PDT 24
Finished Aug 18 06:15:37 PM PDT 24
Peak memory 206380 kb
Host smart-8b75f720-d458-490f-9546-a8fef3b64b08
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459988912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3459988912
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.602003714
Short name T860
Test name
Test status
Simulation time 272505330 ps
CPU time 3.69 seconds
Started Aug 18 06:15:35 PM PDT 24
Finished Aug 18 06:15:39 PM PDT 24
Peak memory 211004 kb
Host smart-fcb08e5a-f4fd-489c-8b7f-6143a860c0de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602003714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.602003714
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2812863479
Short name T179
Test name
Test status
Simulation time 315638405 ps
CPU time 3.63 seconds
Started Aug 18 06:15:29 PM PDT 24
Finished Aug 18 06:15:32 PM PDT 24
Peak memory 207400 kb
Host smart-b69ea635-bc79-42ae-af5f-beda6ef6d7b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812863479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2812863479
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.4201838761
Short name T742
Test name
Test status
Simulation time 350876507 ps
CPU time 4.35 seconds
Started Aug 18 06:15:49 PM PDT 24
Finished Aug 18 06:15:53 PM PDT 24
Peak memory 214940 kb
Host smart-addf5ece-58d4-462b-853d-a66831c7b4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201838761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4201838761
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1911168086
Short name T275
Test name
Test status
Simulation time 641135548 ps
CPU time 4.45 seconds
Started Aug 18 06:15:34 PM PDT 24
Finished Aug 18 06:15:38 PM PDT 24
Peak memory 222916 kb
Host smart-2c3bda06-39fe-48eb-bc3e-5a866a57af3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911168086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1911168086
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.607576090
Short name T913
Test name
Test status
Simulation time 106673309 ps
CPU time 3.29 seconds
Started Aug 18 06:15:41 PM PDT 24
Finished Aug 18 06:15:45 PM PDT 24
Peak memory 214736 kb
Host smart-00d5b611-f1fd-4819-bbb2-6bb9f7763f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607576090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.607576090
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3856996967
Short name T322
Test name
Test status
Simulation time 89233895 ps
CPU time 3.79 seconds
Started Aug 18 06:15:36 PM PDT 24
Finished Aug 18 06:15:40 PM PDT 24
Peak memory 214776 kb
Host smart-7cb5a155-d9ee-4b08-ae04-8d0eb20a410e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856996967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3856996967
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3993854331
Short name T856
Test name
Test status
Simulation time 189156412 ps
CPU time 5.09 seconds
Started Aug 18 06:15:38 PM PDT 24
Finished Aug 18 06:15:43 PM PDT 24
Peak memory 209008 kb
Host smart-9fd01922-b33e-4c7d-bdea-74850accf0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993854331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3993854331
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3320944609
Short name T726
Test name
Test status
Simulation time 193223640 ps
CPU time 3.51 seconds
Started Aug 18 06:15:41 PM PDT 24
Finished Aug 18 06:15:44 PM PDT 24
Peak memory 208748 kb
Host smart-69d2f1ae-0534-4316-a3a8-42f6e062e3a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320944609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3320944609
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2229761671
Short name T487
Test name
Test status
Simulation time 1714222303 ps
CPU time 21.09 seconds
Started Aug 18 06:15:40 PM PDT 24
Finished Aug 18 06:16:01 PM PDT 24
Peak memory 208276 kb
Host smart-4fb4300d-21dd-4ef2-8cf0-12ba3a8a48b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229761671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2229761671
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3027945122
Short name T715
Test name
Test status
Simulation time 277285586 ps
CPU time 4.21 seconds
Started Aug 18 06:15:36 PM PDT 24
Finished Aug 18 06:15:40 PM PDT 24
Peak memory 207372 kb
Host smart-45349f4b-dc76-44b1-94d4-fe88a4095a8a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027945122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3027945122
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.4227307755
Short name T94
Test name
Test status
Simulation time 191729428 ps
CPU time 3.82 seconds
Started Aug 18 06:15:37 PM PDT 24
Finished Aug 18 06:15:41 PM PDT 24
Peak memory 214756 kb
Host smart-3b1bce59-44c4-43af-ad2d-3a1c266b3137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227307755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.4227307755
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3493140991
Short name T547
Test name
Test status
Simulation time 3933873347 ps
CPU time 30.95 seconds
Started Aug 18 06:15:43 PM PDT 24
Finished Aug 18 06:16:14 PM PDT 24
Peak memory 208620 kb
Host smart-a7c5ea31-7e2f-4e1d-b935-21af4aaac1d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493140991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3493140991
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1919435728
Short name T692
Test name
Test status
Simulation time 906042954 ps
CPU time 21.95 seconds
Started Aug 18 06:15:35 PM PDT 24
Finished Aug 18 06:15:57 PM PDT 24
Peak memory 223016 kb
Host smart-045e8884-73d0-42f9-b6ca-bed0351500bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919435728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1919435728
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.1626155743
Short name T352
Test name
Test status
Simulation time 276300108 ps
CPU time 5.65 seconds
Started Aug 18 06:15:34 PM PDT 24
Finished Aug 18 06:15:40 PM PDT 24
Peak memory 208312 kb
Host smart-d7168714-2299-4729-a063-b9513ed95406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1626155743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1626155743
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1013265275
Short name T160
Test name
Test status
Simulation time 62736176 ps
CPU time 2.13 seconds
Started Aug 18 06:15:52 PM PDT 24
Finished Aug 18 06:15:54 PM PDT 24
Peak memory 210304 kb
Host smart-5d111426-8387-406c-b1c6-b6ef3e782c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013265275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1013265275
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2621309525
Short name T565
Test name
Test status
Simulation time 15537887 ps
CPU time 0.78 seconds
Started Aug 18 06:15:54 PM PDT 24
Finished Aug 18 06:15:55 PM PDT 24
Peak memory 206456 kb
Host smart-a8d0f2e0-6332-491b-8a0c-0d8ba3b09e0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621309525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2621309525
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1463044596
Short name T417
Test name
Test status
Simulation time 73913167 ps
CPU time 2.88 seconds
Started Aug 18 06:15:34 PM PDT 24
Finished Aug 18 06:15:38 PM PDT 24
Peak memory 215448 kb
Host smart-ac4c74a2-2c72-4e79-ab24-05c616bedd9b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1463044596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1463044596
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.776129002
Short name T894
Test name
Test status
Simulation time 94657920 ps
CPU time 1.89 seconds
Started Aug 18 06:15:37 PM PDT 24
Finished Aug 18 06:15:39 PM PDT 24
Peak memory 214824 kb
Host smart-c303012e-436a-4193-9177-56ee7834598e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776129002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.776129002
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2165311739
Short name T851
Test name
Test status
Simulation time 103649337 ps
CPU time 2.91 seconds
Started Aug 18 06:15:38 PM PDT 24
Finished Aug 18 06:15:41 PM PDT 24
Peak memory 208012 kb
Host smart-6f0a80a0-bdb2-4887-821a-204561ae2b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165311739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2165311739
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4222447806
Short name T48
Test name
Test status
Simulation time 186834002 ps
CPU time 2.4 seconds
Started Aug 18 06:15:41 PM PDT 24
Finished Aug 18 06:15:43 PM PDT 24
Peak memory 214804 kb
Host smart-1711a89a-8fed-451b-8634-2fd3d3ee9948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222447806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4222447806
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.175137612
Short name T842
Test name
Test status
Simulation time 91526924 ps
CPU time 3.45 seconds
Started Aug 18 06:15:34 PM PDT 24
Finished Aug 18 06:15:38 PM PDT 24
Peak memory 222836 kb
Host smart-855a6d70-a0b0-4e85-8ae6-8f9ae4abedac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175137612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.175137612
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.316906916
Short name T549
Test name
Test status
Simulation time 387954508 ps
CPU time 2.6 seconds
Started Aug 18 06:15:35 PM PDT 24
Finished Aug 18 06:15:38 PM PDT 24
Peak memory 214716 kb
Host smart-12bf0e68-b96f-4eb9-bb91-e1f13d020442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316906916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.316906916
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2315179138
Short name T862
Test name
Test status
Simulation time 319871095 ps
CPU time 2.45 seconds
Started Aug 18 06:15:38 PM PDT 24
Finished Aug 18 06:15:41 PM PDT 24
Peak memory 218752 kb
Host smart-831b9dab-68c1-4fda-9ec4-206836e588cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315179138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2315179138
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.4291477125
Short name T546
Test name
Test status
Simulation time 227434772 ps
CPU time 4.56 seconds
Started Aug 18 06:15:39 PM PDT 24
Finished Aug 18 06:15:44 PM PDT 24
Peak memory 208428 kb
Host smart-f3dc31c4-e5e4-4523-ac37-b6d687064053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291477125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.4291477125
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2421089398
Short name T515
Test name
Test status
Simulation time 367170995 ps
CPU time 5.83 seconds
Started Aug 18 06:15:45 PM PDT 24
Finished Aug 18 06:15:50 PM PDT 24
Peak memory 208712 kb
Host smart-3f359469-4fbc-4515-9263-012bcb0d1439
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2421089398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2421089398
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.133787927
Short name T712
Test name
Test status
Simulation time 102868052 ps
CPU time 2.62 seconds
Started Aug 18 06:15:34 PM PDT 24
Finished Aug 18 06:15:37 PM PDT 24
Peak memory 207820 kb
Host smart-41248fb4-3e7b-4a44-94ca-665766a72801
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133787927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.133787927
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.242063548
Short name T620
Test name
Test status
Simulation time 190353598 ps
CPU time 2.71 seconds
Started Aug 18 06:15:40 PM PDT 24
Finished Aug 18 06:15:42 PM PDT 24
Peak memory 207388 kb
Host smart-db9da428-909d-4d62-8c53-010eb5518cbb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242063548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.242063548
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.969909165
Short name T411
Test name
Test status
Simulation time 129127992 ps
CPU time 2.02 seconds
Started Aug 18 06:16:10 PM PDT 24
Finished Aug 18 06:16:12 PM PDT 24
Peak memory 218772 kb
Host smart-4ac03ce5-f8ca-4a17-88e6-4bd692fc267a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969909165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.969909165
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1650909640
Short name T747
Test name
Test status
Simulation time 37172597 ps
CPU time 2.35 seconds
Started Aug 18 06:15:46 PM PDT 24
Finished Aug 18 06:15:48 PM PDT 24
Peak memory 208848 kb
Host smart-9ab8a37f-f425-4d97-95e2-c0908b631efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650909640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1650909640
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.2452002223
Short name T9
Test name
Test status
Simulation time 431095637 ps
CPU time 16.41 seconds
Started Aug 18 06:15:35 PM PDT 24
Finished Aug 18 06:15:52 PM PDT 24
Peak memory 221220 kb
Host smart-7efc4110-59da-424b-91b3-14af1e5a4634
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452002223 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.2452002223
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3335783924
Short name T608
Test name
Test status
Simulation time 190373593 ps
CPU time 1.54 seconds
Started Aug 18 06:15:40 PM PDT 24
Finished Aug 18 06:15:41 PM PDT 24
Peak memory 210380 kb
Host smart-3ff6caa8-b77a-47f6-af6d-25fb0c17e94c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335783924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3335783924
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2135279978
Short name T507
Test name
Test status
Simulation time 12395398 ps
CPU time 0.8 seconds
Started Aug 18 06:15:49 PM PDT 24
Finished Aug 18 06:15:50 PM PDT 24
Peak memory 206328 kb
Host smart-e92a6c61-9000-4163-bc57-9d7d5760de0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135279978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2135279978
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3431718302
Short name T420
Test name
Test status
Simulation time 58687785 ps
CPU time 3.68 seconds
Started Aug 18 06:15:38 PM PDT 24
Finished Aug 18 06:15:41 PM PDT 24
Peak memory 214840 kb
Host smart-56bac416-28e4-4f3f-a983-80aaded84fa5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3431718302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3431718302
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.144642489
Short name T671
Test name
Test status
Simulation time 997630020 ps
CPU time 9.84 seconds
Started Aug 18 06:15:39 PM PDT 24
Finished Aug 18 06:15:48 PM PDT 24
Peak memory 220104 kb
Host smart-35871f21-f123-4018-9554-a6009115e8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144642489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.144642489
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.97272914
Short name T885
Test name
Test status
Simulation time 51454543 ps
CPU time 1.62 seconds
Started Aug 18 06:15:37 PM PDT 24
Finished Aug 18 06:15:39 PM PDT 24
Peak memory 214812 kb
Host smart-7ba7c51c-8a13-4497-b307-70a62403a881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97272914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.97272914
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3441211884
Short name T737
Test name
Test status
Simulation time 94067766 ps
CPU time 4.54 seconds
Started Aug 18 06:16:04 PM PDT 24
Finished Aug 18 06:16:09 PM PDT 24
Peak memory 222820 kb
Host smart-73eb02e6-8349-470a-8723-9cf478d03325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441211884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3441211884
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1172210136
Short name T192
Test name
Test status
Simulation time 54297495 ps
CPU time 3.55 seconds
Started Aug 18 06:15:39 PM PDT 24
Finished Aug 18 06:15:42 PM PDT 24
Peak memory 210680 kb
Host smart-d346f87f-eede-489f-913a-17940665626c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172210136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1172210136
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2337818281
Short name T793
Test name
Test status
Simulation time 169570078 ps
CPU time 5.14 seconds
Started Aug 18 06:15:36 PM PDT 24
Finished Aug 18 06:15:41 PM PDT 24
Peak memory 218884 kb
Host smart-e90054f8-25e2-455a-8bef-91695dcbfc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337818281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2337818281
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2803897263
Short name T603
Test name
Test status
Simulation time 255441027 ps
CPU time 6.27 seconds
Started Aug 18 06:16:09 PM PDT 24
Finished Aug 18 06:16:16 PM PDT 24
Peak memory 208496 kb
Host smart-0f519648-6057-4e1d-99a6-5b613661c0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803897263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2803897263
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2244623198
Short name T263
Test name
Test status
Simulation time 305841373 ps
CPU time 3.23 seconds
Started Aug 18 06:15:52 PM PDT 24
Finished Aug 18 06:15:55 PM PDT 24
Peak memory 209492 kb
Host smart-27980ef4-4d8e-4564-b8fa-77868cae6387
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244623198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2244623198
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2560190834
Short name T774
Test name
Test status
Simulation time 37940241 ps
CPU time 2.61 seconds
Started Aug 18 06:15:58 PM PDT 24
Finished Aug 18 06:16:01 PM PDT 24
Peak memory 209076 kb
Host smart-a1bd258b-c1bd-4c98-a828-e4cedfdebd47
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560190834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2560190834
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1674400624
Short name T471
Test name
Test status
Simulation time 168575075 ps
CPU time 5.04 seconds
Started Aug 18 06:15:44 PM PDT 24
Finished Aug 18 06:15:49 PM PDT 24
Peak memory 208440 kb
Host smart-0ef1e16a-1510-4dfc-986e-5d47553422e6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674400624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1674400624
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.980605541
Short name T496
Test name
Test status
Simulation time 121309948 ps
CPU time 4.5 seconds
Started Aug 18 06:15:55 PM PDT 24
Finished Aug 18 06:15:59 PM PDT 24
Peak memory 209340 kb
Host smart-de6321b8-e4e5-461c-a71b-7c8af920f39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980605541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.980605541
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.2638035624
Short name T886
Test name
Test status
Simulation time 221597947 ps
CPU time 3.82 seconds
Started Aug 18 06:15:39 PM PDT 24
Finished Aug 18 06:15:43 PM PDT 24
Peak memory 208904 kb
Host smart-d9a73d47-5264-4dbc-b9be-1e73deca6831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638035624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.2638035624
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1152740762
Short name T181
Test name
Test status
Simulation time 685608693 ps
CPU time 24.21 seconds
Started Aug 18 06:15:55 PM PDT 24
Finished Aug 18 06:16:20 PM PDT 24
Peak memory 222812 kb
Host smart-5efc1cc9-61c3-4e95-86fc-0ed37b8343f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152740762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1152740762
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.4247449510
Short name T321
Test name
Test status
Simulation time 1010735806 ps
CPU time 7.59 seconds
Started Aug 18 06:15:37 PM PDT 24
Finished Aug 18 06:15:45 PM PDT 24
Peak memory 209856 kb
Host smart-833c2d03-ba2d-4a1a-b85d-3300b8b3c9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247449510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.4247449510
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1493867948
Short name T708
Test name
Test status
Simulation time 47879800 ps
CPU time 2.73 seconds
Started Aug 18 06:16:07 PM PDT 24
Finished Aug 18 06:16:10 PM PDT 24
Peak memory 210636 kb
Host smart-f222d4b8-5379-4a44-9605-2606c264d06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493867948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1493867948
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.958972260
Short name T90
Test name
Test status
Simulation time 46722764 ps
CPU time 0.77 seconds
Started Aug 18 06:15:53 PM PDT 24
Finished Aug 18 06:15:54 PM PDT 24
Peak memory 206392 kb
Host smart-4d57df21-9136-487e-9eb1-2d823befa4f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958972260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.958972260
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1950395206
Short name T285
Test name
Test status
Simulation time 103260435 ps
CPU time 3.12 seconds
Started Aug 18 06:15:40 PM PDT 24
Finished Aug 18 06:15:43 PM PDT 24
Peak memory 215144 kb
Host smart-11d5f072-3eef-46f3-91c0-b3919feec091
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1950395206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1950395206
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2896096167
Short name T676
Test name
Test status
Simulation time 149438078 ps
CPU time 5.58 seconds
Started Aug 18 06:15:48 PM PDT 24
Finished Aug 18 06:15:54 PM PDT 24
Peak memory 223280 kb
Host smart-8a07b976-39b0-4428-95eb-a33e50aa2e70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896096167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2896096167
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.472065906
Short name T140
Test name
Test status
Simulation time 215047829 ps
CPU time 3.6 seconds
Started Aug 18 06:16:07 PM PDT 24
Finished Aug 18 06:16:10 PM PDT 24
Peak memory 214748 kb
Host smart-a35275b4-72d8-4f87-aa93-046a94fecf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472065906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.472065906
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.4116964708
Short name T332
Test name
Test status
Simulation time 77575659 ps
CPU time 2.66 seconds
Started Aug 18 06:15:54 PM PDT 24
Finished Aug 18 06:15:57 PM PDT 24
Peak memory 214780 kb
Host smart-f6fd6d1b-eae3-4603-ad75-587afcb30b65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116964708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.4116964708
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.956255610
Short name T238
Test name
Test status
Simulation time 79894050 ps
CPU time 1.57 seconds
Started Aug 18 06:15:46 PM PDT 24
Finished Aug 18 06:15:48 PM PDT 24
Peak memory 214656 kb
Host smart-2b5e2241-d296-4110-ab6c-0dba1c30d5ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956255610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.956255610
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2417121027
Short name T194
Test name
Test status
Simulation time 126541740 ps
CPU time 2.43 seconds
Started Aug 18 06:15:58 PM PDT 24
Finished Aug 18 06:16:01 PM PDT 24
Peak memory 210048 kb
Host smart-a9b7c3a0-8caf-4ee5-ab44-603b7308d648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417121027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2417121027
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3309555953
Short name T494
Test name
Test status
Simulation time 239102262 ps
CPU time 6.74 seconds
Started Aug 18 06:16:00 PM PDT 24
Finished Aug 18 06:16:07 PM PDT 24
Peak memory 207816 kb
Host smart-836e8426-d649-4d12-a286-5115e01c2c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309555953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3309555953
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3446364659
Short name T837
Test name
Test status
Simulation time 224465434 ps
CPU time 4.89 seconds
Started Aug 18 06:15:43 PM PDT 24
Finished Aug 18 06:15:48 PM PDT 24
Peak memory 208472 kb
Host smart-1a042fc7-0037-4b02-b079-99fc7558d37b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446364659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3446364659
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3434154670
Short name T672
Test name
Test status
Simulation time 336002574 ps
CPU time 3.28 seconds
Started Aug 18 06:15:38 PM PDT 24
Finished Aug 18 06:15:46 PM PDT 24
Peak memory 209400 kb
Host smart-eb2574ea-197e-4843-a13e-af0fc6fa2e95
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434154670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3434154670
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2381456620
Short name T366
Test name
Test status
Simulation time 2493381479 ps
CPU time 40.09 seconds
Started Aug 18 06:15:37 PM PDT 24
Finished Aug 18 06:16:18 PM PDT 24
Peak memory 209080 kb
Host smart-33538b10-66f6-4329-81df-80ac87d1170e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381456620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2381456620
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1848884984
Short name T524
Test name
Test status
Simulation time 63670286 ps
CPU time 3.22 seconds
Started Aug 18 06:16:02 PM PDT 24
Finished Aug 18 06:16:06 PM PDT 24
Peak memory 208880 kb
Host smart-9e9b3e91-fa5d-4d10-8fea-08cc567f093c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848884984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1848884984
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.423619967
Short name T33
Test name
Test status
Simulation time 128237219 ps
CPU time 1.83 seconds
Started Aug 18 06:15:49 PM PDT 24
Finished Aug 18 06:15:51 PM PDT 24
Peak memory 208448 kb
Host smart-75d42774-ac75-4cef-b1c5-bd96180be92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423619967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.423619967
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2537127167
Short name T613
Test name
Test status
Simulation time 73273590 ps
CPU time 1.69 seconds
Started Aug 18 06:15:40 PM PDT 24
Finished Aug 18 06:15:42 PM PDT 24
Peak memory 207292 kb
Host smart-d5f97550-0263-4971-b2b4-b28c9c9ae244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537127167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2537127167
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3036386888
Short name T459
Test name
Test status
Simulation time 6187983937 ps
CPU time 56.26 seconds
Started Aug 18 06:16:08 PM PDT 24
Finished Aug 18 06:17:04 PM PDT 24
Peak memory 214840 kb
Host smart-4b998087-9fd3-4217-b91f-49afd59cee9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036386888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3036386888
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2659315640
Short name T508
Test name
Test status
Simulation time 504097305 ps
CPU time 3.4 seconds
Started Aug 18 06:15:50 PM PDT 24
Finished Aug 18 06:15:53 PM PDT 24
Peak memory 211080 kb
Host smart-305ae1da-4fd1-4306-97f1-fdf98a969935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659315640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2659315640
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1351460839
Short name T605
Test name
Test status
Simulation time 31900995 ps
CPU time 0.92 seconds
Started Aug 18 06:16:02 PM PDT 24
Finished Aug 18 06:16:03 PM PDT 24
Peak memory 206564 kb
Host smart-976d53a8-2266-4a6c-8158-1cba71f5c7dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351460839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1351460839
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2721433686
Short name T406
Test name
Test status
Simulation time 204085917 ps
CPU time 4.02 seconds
Started Aug 18 06:15:55 PM PDT 24
Finished Aug 18 06:15:59 PM PDT 24
Peak memory 216112 kb
Host smart-6aa0e71f-7ea6-40af-831a-ee8f577fa18c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2721433686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2721433686
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3315118717
Short name T32
Test name
Test status
Simulation time 82329146 ps
CPU time 2.83 seconds
Started Aug 18 06:15:54 PM PDT 24
Finished Aug 18 06:15:57 PM PDT 24
Peak memory 218020 kb
Host smart-3906392c-e842-439a-8a5a-fafd503b40bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315118717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3315118717
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3517745238
Short name T802
Test name
Test status
Simulation time 88440747 ps
CPU time 1.84 seconds
Started Aug 18 06:15:59 PM PDT 24
Finished Aug 18 06:16:01 PM PDT 24
Peak memory 207776 kb
Host smart-44624467-bc0e-47b1-befb-75b922bd6d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517745238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3517745238
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.2102309160
Short name T831
Test name
Test status
Simulation time 83864993 ps
CPU time 2.99 seconds
Started Aug 18 06:15:53 PM PDT 24
Finished Aug 18 06:15:56 PM PDT 24
Peak memory 214756 kb
Host smart-3696d7d5-4604-4218-ac16-5d2f82e6c569
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102309160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2102309160
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3193652106
Short name T397
Test name
Test status
Simulation time 52830108 ps
CPU time 2.42 seconds
Started Aug 18 06:15:54 PM PDT 24
Finished Aug 18 06:15:57 PM PDT 24
Peak memory 220928 kb
Host smart-099dc902-b9ee-4168-a6b4-28d53e3513a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193652106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3193652106
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.842636650
Short name T65
Test name
Test status
Simulation time 47684869 ps
CPU time 3.42 seconds
Started Aug 18 06:15:59 PM PDT 24
Finished Aug 18 06:16:02 PM PDT 24
Peak memory 210108 kb
Host smart-dfef0f7d-cd6b-408c-b768-51b0a50c3593
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842636650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.842636650
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1396276747
Short name T861
Test name
Test status
Simulation time 600802499 ps
CPU time 14.93 seconds
Started Aug 18 06:15:42 PM PDT 24
Finished Aug 18 06:16:12 PM PDT 24
Peak memory 210968 kb
Host smart-9de71365-8693-4949-9da6-c0006b519515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396276747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1396276747
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3755497348
Short name T906
Test name
Test status
Simulation time 109433131 ps
CPU time 3.49 seconds
Started Aug 18 06:15:57 PM PDT 24
Finished Aug 18 06:16:00 PM PDT 24
Peak memory 207372 kb
Host smart-dddd3731-3832-436f-9219-8adb9348cb25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755497348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3755497348
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3105958637
Short name T891
Test name
Test status
Simulation time 5301169651 ps
CPU time 33.08 seconds
Started Aug 18 06:15:54 PM PDT 24
Finished Aug 18 06:16:27 PM PDT 24
Peak memory 209312 kb
Host smart-ecdba208-b053-40cb-b9d8-a5e02025c237
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3105958637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3105958637
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3575832119
Short name T865
Test name
Test status
Simulation time 439420184 ps
CPU time 6.34 seconds
Started Aug 18 06:15:50 PM PDT 24
Finished Aug 18 06:15:57 PM PDT 24
Peak memory 208964 kb
Host smart-67986f1a-ccd3-42ac-b94c-8ae7c8633483
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575832119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3575832119
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3276108618
Short name T557
Test name
Test status
Simulation time 87934185 ps
CPU time 2.01 seconds
Started Aug 18 06:15:52 PM PDT 24
Finished Aug 18 06:15:54 PM PDT 24
Peak memory 209272 kb
Host smart-b84d64ce-1558-4ad6-982b-9f6ca76842b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276108618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3276108618
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.772720054
Short name T751
Test name
Test status
Simulation time 476893829 ps
CPU time 3.65 seconds
Started Aug 18 06:15:54 PM PDT 24
Finished Aug 18 06:15:57 PM PDT 24
Peak memory 214792 kb
Host smart-fbb182bf-4be6-460f-92f9-b22b73eadb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772720054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.772720054
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.1918678987
Short name T474
Test name
Test status
Simulation time 175240082 ps
CPU time 3.91 seconds
Started Aug 18 06:15:58 PM PDT 24
Finished Aug 18 06:16:02 PM PDT 24
Peak memory 209080 kb
Host smart-97f5a0ac-ecbf-41ed-8352-e00fa1eaf34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918678987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1918678987
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1823865860
Short name T512
Test name
Test status
Simulation time 1261002691 ps
CPU time 6.38 seconds
Started Aug 18 06:16:02 PM PDT 24
Finished Aug 18 06:16:08 PM PDT 24
Peak memory 207548 kb
Host smart-47828289-bdf7-4a32-9e90-5b1d30433f00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823865860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1823865860
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3466662343
Short name T869
Test name
Test status
Simulation time 92929625 ps
CPU time 2.93 seconds
Started Aug 18 06:16:01 PM PDT 24
Finished Aug 18 06:16:04 PM PDT 24
Peak memory 211040 kb
Host smart-4d4e4a5b-8bf2-4a10-9de7-c7c4d23747d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466662343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3466662343
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1464314777
Short name T430
Test name
Test status
Simulation time 17639221 ps
CPU time 0.79 seconds
Started Aug 18 06:16:04 PM PDT 24
Finished Aug 18 06:16:05 PM PDT 24
Peak memory 206392 kb
Host smart-4a8401bd-49b5-45fa-9a22-d696e3ac798a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464314777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1464314777
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.277238468
Short name T96
Test name
Test status
Simulation time 132644843 ps
CPU time 7.63 seconds
Started Aug 18 06:16:03 PM PDT 24
Finished Aug 18 06:16:11 PM PDT 24
Peak memory 214784 kb
Host smart-a8eb1bff-a5ef-484c-85c8-39e06cc44ee9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=277238468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.277238468
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2448885230
Short name T170
Test name
Test status
Simulation time 80480712 ps
CPU time 3.9 seconds
Started Aug 18 06:16:15 PM PDT 24
Finished Aug 18 06:16:19 PM PDT 24
Peak memory 209804 kb
Host smart-aa8fa159-4643-427c-b894-d77e22fe9cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448885230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2448885230
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2039676346
Short name T175
Test name
Test status
Simulation time 476011722 ps
CPU time 3.47 seconds
Started Aug 18 06:16:10 PM PDT 24
Finished Aug 18 06:16:14 PM PDT 24
Peak memory 218656 kb
Host smart-c2633fa0-eaa9-4bfc-a697-62f027081cbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039676346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2039676346
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3129912798
Short name T714
Test name
Test status
Simulation time 130860019 ps
CPU time 2.26 seconds
Started Aug 18 06:16:08 PM PDT 24
Finished Aug 18 06:16:10 PM PDT 24
Peak memory 214784 kb
Host smart-bc6a6719-dd8b-4d93-8de2-3a8fd4e9815e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129912798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3129912798
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.3000760715
Short name T591
Test name
Test status
Simulation time 810418373 ps
CPU time 3.04 seconds
Started Aug 18 06:16:16 PM PDT 24
Finished Aug 18 06:16:19 PM PDT 24
Peak memory 214696 kb
Host smart-d5a0a2fb-8fc1-4649-aede-0318d8ba7128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000760715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.3000760715
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2037232335
Short name T521
Test name
Test status
Simulation time 183747432 ps
CPU time 2.86 seconds
Started Aug 18 06:16:04 PM PDT 24
Finished Aug 18 06:16:06 PM PDT 24
Peak memory 214824 kb
Host smart-b3a98718-cdc9-482b-b733-0e3cd8ed8076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037232335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2037232335
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1836172385
Short name T777
Test name
Test status
Simulation time 404928419 ps
CPU time 5.15 seconds
Started Aug 18 06:16:19 PM PDT 24
Finished Aug 18 06:16:24 PM PDT 24
Peak memory 214784 kb
Host smart-34693632-3183-4a7b-926b-d319b301aa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1836172385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1836172385
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1463973832
Short name T231
Test name
Test status
Simulation time 51802547 ps
CPU time 2.27 seconds
Started Aug 18 06:15:56 PM PDT 24
Finished Aug 18 06:15:59 PM PDT 24
Peak memory 208464 kb
Host smart-7f632a05-ae84-4abb-90d3-c630260a4576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463973832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1463973832
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3373818884
Short name T552
Test name
Test status
Simulation time 141024521 ps
CPU time 2.75 seconds
Started Aug 18 06:15:45 PM PDT 24
Finished Aug 18 06:15:48 PM PDT 24
Peak memory 207404 kb
Host smart-8b5ecffb-cc6a-4927-9934-ce86d5f2d0d3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373818884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3373818884
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1545996780
Short name T2
Test name
Test status
Simulation time 193399951 ps
CPU time 6.35 seconds
Started Aug 18 06:16:04 PM PDT 24
Finished Aug 18 06:16:20 PM PDT 24
Peak memory 208912 kb
Host smart-bbfb26c3-f05b-42c2-922a-677fcd241cda
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545996780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1545996780
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.888507507
Short name T291
Test name
Test status
Simulation time 40126170 ps
CPU time 1.75 seconds
Started Aug 18 06:16:06 PM PDT 24
Finished Aug 18 06:16:08 PM PDT 24
Peak memory 207436 kb
Host smart-c6c86473-a19f-437a-b089-6d29911eaaeb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888507507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.888507507
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1428556993
Short name T791
Test name
Test status
Simulation time 157912262 ps
CPU time 1.96 seconds
Started Aug 18 06:16:08 PM PDT 24
Finished Aug 18 06:16:10 PM PDT 24
Peak memory 207640 kb
Host smart-8b0f0089-7d7e-4557-8b49-67c504321f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428556993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1428556993
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1140823083
Short name T768
Test name
Test status
Simulation time 174023355 ps
CPU time 2.24 seconds
Started Aug 18 06:15:57 PM PDT 24
Finished Aug 18 06:15:59 PM PDT 24
Peak memory 207152 kb
Host smart-45e482ed-f517-433e-a7f4-fe122fbb6ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140823083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1140823083
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1316790063
Short name T210
Test name
Test status
Simulation time 3717555814 ps
CPU time 62.86 seconds
Started Aug 18 06:16:06 PM PDT 24
Finished Aug 18 06:17:09 PM PDT 24
Peak memory 214864 kb
Host smart-dfdc0964-b595-4856-8075-51447ac9c2dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316790063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1316790063
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.2099081097
Short name T219
Test name
Test status
Simulation time 292904660 ps
CPU time 13.09 seconds
Started Aug 18 06:16:12 PM PDT 24
Finished Aug 18 06:16:25 PM PDT 24
Peak memory 223020 kb
Host smart-22a6f2ba-6b85-423d-8442-cb66b3436134
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099081097 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.2099081097
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3844521562
Short name T784
Test name
Test status
Simulation time 1925227438 ps
CPU time 8.52 seconds
Started Aug 18 06:16:12 PM PDT 24
Finished Aug 18 06:16:20 PM PDT 24
Peak memory 218800 kb
Host smart-8c7809cd-3965-464e-b441-56cf0bbbe4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3844521562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3844521562
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.938007594
Short name T480
Test name
Test status
Simulation time 858443967 ps
CPU time 3.59 seconds
Started Aug 18 06:16:02 PM PDT 24
Finished Aug 18 06:16:06 PM PDT 24
Peak memory 210924 kb
Host smart-b2b1e1a9-f861-4e1d-830b-7d91751d76fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938007594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.938007594
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.4026178727
Short name T61
Test name
Test status
Simulation time 22177518 ps
CPU time 0.9 seconds
Started Aug 18 06:13:31 PM PDT 24
Finished Aug 18 06:13:32 PM PDT 24
Peak memory 206432 kb
Host smart-ed7a8677-eb1c-4e62-afc4-480d6b71f3d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026178727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.4026178727
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2229296374
Short name T425
Test name
Test status
Simulation time 104878867 ps
CPU time 3.74 seconds
Started Aug 18 06:13:42 PM PDT 24
Finished Aug 18 06:13:46 PM PDT 24
Peak memory 216152 kb
Host smart-e6a3c1c3-54ca-4370-bb15-2dc6f39713ee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2229296374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2229296374
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1966840391
Short name T19
Test name
Test status
Simulation time 97850398 ps
CPU time 1.92 seconds
Started Aug 18 06:13:33 PM PDT 24
Finished Aug 18 06:13:35 PM PDT 24
Peak memory 209548 kb
Host smart-3cf33299-e69f-4169-a626-260bb2718335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966840391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1966840391
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.1433568145
Short name T695
Test name
Test status
Simulation time 111030560 ps
CPU time 1.58 seconds
Started Aug 18 06:13:33 PM PDT 24
Finished Aug 18 06:13:34 PM PDT 24
Peak memory 208532 kb
Host smart-e1a88792-47b4-4432-811a-f37e812f5658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433568145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.1433568145
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3041283753
Short name T795
Test name
Test status
Simulation time 131912744 ps
CPU time 2.68 seconds
Started Aug 18 06:13:37 PM PDT 24
Finished Aug 18 06:13:40 PM PDT 24
Peak memory 214908 kb
Host smart-80a39a3f-c503-48db-92a0-a6866f3b06b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041283753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3041283753
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2198218784
Short name T239
Test name
Test status
Simulation time 107408480 ps
CPU time 2.98 seconds
Started Aug 18 06:13:40 PM PDT 24
Finished Aug 18 06:13:43 PM PDT 24
Peak memory 214692 kb
Host smart-b6567731-ae46-4daf-9fc0-2927739a0561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198218784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2198218784
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3883744516
Short name T870
Test name
Test status
Simulation time 134084909 ps
CPU time 2.31 seconds
Started Aug 18 06:13:42 PM PDT 24
Finished Aug 18 06:13:44 PM PDT 24
Peak memory 220324 kb
Host smart-c3d99708-a4ad-439f-90f0-961a0eb0d7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883744516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3883744516
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.639406379
Short name T766
Test name
Test status
Simulation time 193318985 ps
CPU time 4.62 seconds
Started Aug 18 06:13:40 PM PDT 24
Finished Aug 18 06:13:45 PM PDT 24
Peak memory 208428 kb
Host smart-27daf107-429c-41a3-9fa2-bf6a5531c543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639406379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.639406379
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1613014894
Short name T725
Test name
Test status
Simulation time 38468306 ps
CPU time 2.15 seconds
Started Aug 18 06:13:33 PM PDT 24
Finished Aug 18 06:13:36 PM PDT 24
Peak memory 207300 kb
Host smart-11c35f5f-d74f-452f-a915-d95d0d14f6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613014894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1613014894
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1659223709
Short name T343
Test name
Test status
Simulation time 319663295 ps
CPU time 3.9 seconds
Started Aug 18 06:13:27 PM PDT 24
Finished Aug 18 06:13:31 PM PDT 24
Peak memory 209320 kb
Host smart-bb4053ec-e6a9-4707-971a-75a44cda38a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659223709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1659223709
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.658454144
Short name T520
Test name
Test status
Simulation time 54124588 ps
CPU time 1.83 seconds
Started Aug 18 06:13:27 PM PDT 24
Finished Aug 18 06:13:29 PM PDT 24
Peak memory 207856 kb
Host smart-a72fb384-dff5-4ddf-ad08-bf7b4cbdc48b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658454144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.658454144
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.893810562
Short name T903
Test name
Test status
Simulation time 126975450 ps
CPU time 3.08 seconds
Started Aug 18 06:13:31 PM PDT 24
Finished Aug 18 06:13:34 PM PDT 24
Peak memory 207484 kb
Host smart-ec8c973e-e97f-47a4-a0a6-98d108818346
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893810562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.893810562
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2347615076
Short name T705
Test name
Test status
Simulation time 366802047 ps
CPU time 3.89 seconds
Started Aug 18 06:13:39 PM PDT 24
Finished Aug 18 06:13:48 PM PDT 24
Peak memory 218760 kb
Host smart-a1db1b3e-755f-4533-b636-2c863be08d9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347615076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2347615076
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1157871467
Short name T145
Test name
Test status
Simulation time 18629935 ps
CPU time 1.56 seconds
Started Aug 18 06:13:27 PM PDT 24
Finished Aug 18 06:13:28 PM PDT 24
Peak memory 207268 kb
Host smart-ecbdea43-af38-4406-bdf3-3b01ccb85756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157871467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1157871467
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.81498226
Short name T280
Test name
Test status
Simulation time 1770790796 ps
CPU time 25.41 seconds
Started Aug 18 06:13:38 PM PDT 24
Finished Aug 18 06:14:03 PM PDT 24
Peak memory 221596 kb
Host smart-f626fb0f-9a55-4696-b2e9-0eaa110d531b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81498226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.81498226
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2530100907
Short name T84
Test name
Test status
Simulation time 159282803 ps
CPU time 9.88 seconds
Started Aug 18 06:13:33 PM PDT 24
Finished Aug 18 06:13:43 PM PDT 24
Peak memory 223016 kb
Host smart-a9b057fc-0421-4811-8d90-906b55671447
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530100907 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2530100907
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.837296911
Short name T787
Test name
Test status
Simulation time 133998102 ps
CPU time 2.85 seconds
Started Aug 18 06:13:39 PM PDT 24
Finished Aug 18 06:13:42 PM PDT 24
Peak memory 214752 kb
Host smart-6b07f953-d894-4000-b4c2-a99c191f1194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837296911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.837296911
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3912549381
Short name T803
Test name
Test status
Simulation time 90345034 ps
CPU time 1.49 seconds
Started Aug 18 06:13:39 PM PDT 24
Finished Aug 18 06:13:41 PM PDT 24
Peak memory 210384 kb
Host smart-862d216d-5466-489b-b819-3959cca2b30e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912549381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3912549381
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3089112934
Short name T427
Test name
Test status
Simulation time 89682492 ps
CPU time 0.84 seconds
Started Aug 18 06:13:39 PM PDT 24
Finished Aug 18 06:13:40 PM PDT 24
Peak memory 206448 kb
Host smart-04af105d-c4df-4fa3-94a2-569072bcc682
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089112934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3089112934
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.972615091
Short name T418
Test name
Test status
Simulation time 229734341 ps
CPU time 3.26 seconds
Started Aug 18 06:13:39 PM PDT 24
Finished Aug 18 06:13:43 PM PDT 24
Peak memory 215804 kb
Host smart-8f223106-e47a-4153-9a88-58d125dfa64f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=972615091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.972615091
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3092112368
Short name T134
Test name
Test status
Simulation time 62547172 ps
CPU time 2.26 seconds
Started Aug 18 06:13:29 PM PDT 24
Finished Aug 18 06:13:32 PM PDT 24
Peak memory 214864 kb
Host smart-6fdeeda8-0dc3-40c9-bcd9-6f1b801decef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092112368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3092112368
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2726556358
Short name T635
Test name
Test status
Simulation time 48649797 ps
CPU time 2.71 seconds
Started Aug 18 06:13:45 PM PDT 24
Finished Aug 18 06:13:47 PM PDT 24
Peak memory 214892 kb
Host smart-9d6e3a4e-adc1-4a5a-afb4-201b2417f7cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726556358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2726556358
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.1850750520
Short name T260
Test name
Test status
Simulation time 102812116 ps
CPU time 4.8 seconds
Started Aug 18 06:13:44 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 222896 kb
Host smart-0a61266a-b947-4339-a7a9-50a030db0b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850750520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.1850750520
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1671787544
Short name T112
Test name
Test status
Simulation time 24432281 ps
CPU time 2 seconds
Started Aug 18 06:13:35 PM PDT 24
Finished Aug 18 06:13:38 PM PDT 24
Peak memory 208224 kb
Host smart-46507a4b-6e61-4219-91f8-174ceedcef5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671787544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1671787544
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2915175901
Short name T146
Test name
Test status
Simulation time 294731869 ps
CPU time 6.39 seconds
Started Aug 18 06:13:26 PM PDT 24
Finished Aug 18 06:13:33 PM PDT 24
Peak memory 209644 kb
Host smart-1eebb5f7-b061-4142-a2f1-9ff70a5ae13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915175901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2915175901
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1893757548
Short name T749
Test name
Test status
Simulation time 2133350779 ps
CPU time 7.52 seconds
Started Aug 18 06:13:28 PM PDT 24
Finished Aug 18 06:13:36 PM PDT 24
Peak memory 208424 kb
Host smart-9b55b349-eb66-492f-8273-188204884029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893757548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1893757548
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3654313727
Short name T623
Test name
Test status
Simulation time 126137433 ps
CPU time 3.51 seconds
Started Aug 18 06:13:41 PM PDT 24
Finished Aug 18 06:13:44 PM PDT 24
Peak memory 209376 kb
Host smart-efbcae14-da64-4d0e-a4fc-a33cb78f5406
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654313727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3654313727
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3208147754
Short name T485
Test name
Test status
Simulation time 735829254 ps
CPU time 8.09 seconds
Started Aug 18 06:13:45 PM PDT 24
Finished Aug 18 06:13:53 PM PDT 24
Peak memory 208532 kb
Host smart-f8947aaa-5308-43c4-b357-733a2da1f58b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208147754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3208147754
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.607162942
Short name T758
Test name
Test status
Simulation time 98608421 ps
CPU time 3.64 seconds
Started Aug 18 06:13:43 PM PDT 24
Finished Aug 18 06:13:47 PM PDT 24
Peak memory 208680 kb
Host smart-33220611-2426-4379-8747-17795d195f9a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607162942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.607162942
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2290819641
Short name T720
Test name
Test status
Simulation time 73579602 ps
CPU time 2.18 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 209240 kb
Host smart-621d7393-aaa8-4ae1-a5f0-1aa4e0812124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290819641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2290819641
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.837375464
Short name T622
Test name
Test status
Simulation time 369636794 ps
CPU time 3.24 seconds
Started Aug 18 06:13:37 PM PDT 24
Finished Aug 18 06:13:40 PM PDT 24
Peak memory 207200 kb
Host smart-86ecec90-861b-4b70-a401-7fc2be106c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837375464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.837375464
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.260070732
Short name T215
Test name
Test status
Simulation time 4798228929 ps
CPU time 43.56 seconds
Started Aug 18 06:13:45 PM PDT 24
Finished Aug 18 06:14:29 PM PDT 24
Peak memory 222984 kb
Host smart-21f5a102-84d0-48b0-83bf-1c7b07198e50
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260070732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.260070732
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.140931136
Short name T697
Test name
Test status
Simulation time 451331894 ps
CPU time 12.92 seconds
Started Aug 18 06:13:38 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 220036 kb
Host smart-13e3a7d4-0ef4-45b0-9783-db40c599cb37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140931136 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.140931136
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2447284283
Short name T176
Test name
Test status
Simulation time 252677335 ps
CPU time 4.66 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:53 PM PDT 24
Peak memory 207868 kb
Host smart-468dafd7-7c5e-401e-9bcc-7929dbb0a7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447284283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2447284283
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3798069853
Short name T379
Test name
Test status
Simulation time 2691361904 ps
CPU time 13.71 seconds
Started Aug 18 06:13:36 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 211816 kb
Host smart-b8885a31-15ef-4d99-acf1-4b27dde90424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798069853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3798069853
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1275100867
Short name T60
Test name
Test status
Simulation time 21028114 ps
CPU time 0.87 seconds
Started Aug 18 06:13:41 PM PDT 24
Finished Aug 18 06:13:42 PM PDT 24
Peak memory 206400 kb
Host smart-aed469ea-7777-4841-b400-5cac141c01c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275100867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1275100867
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.440287662
Short name T423
Test name
Test status
Simulation time 70873967 ps
CPU time 3.6 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 214792 kb
Host smart-b6e8fb95-a1cc-4d19-b3e7-0a0bd02f4183
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=440287662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.440287662
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.436696330
Short name T800
Test name
Test status
Simulation time 57338121 ps
CPU time 3.23 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 210652 kb
Host smart-b42258b3-2edb-4543-aff1-63719c6bec42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436696330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.436696330
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1572640095
Short name T538
Test name
Test status
Simulation time 97648369 ps
CPU time 4.04 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 214884 kb
Host smart-d0d92ddb-aa49-4fe8-b8bc-4328ef1ffe55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572640095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1572640095
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.963591652
Short name T281
Test name
Test status
Simulation time 89360347 ps
CPU time 3.96 seconds
Started Aug 18 06:13:51 PM PDT 24
Finished Aug 18 06:13:56 PM PDT 24
Peak memory 222888 kb
Host smart-f56b2376-4b73-4b32-9c9d-6b5bbf73790f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963591652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.963591652
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.171770149
Short name T666
Test name
Test status
Simulation time 45935427 ps
CPU time 2.4 seconds
Started Aug 18 06:13:43 PM PDT 24
Finished Aug 18 06:13:46 PM PDT 24
Peak memory 222760 kb
Host smart-dd6fabf6-4dd6-40cb-a598-09052922ee29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171770149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.171770149
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1139445808
Short name T123
Test name
Test status
Simulation time 60263445 ps
CPU time 2.44 seconds
Started Aug 18 06:13:45 PM PDT 24
Finished Aug 18 06:13:47 PM PDT 24
Peak memory 214820 kb
Host smart-be6b0d60-96e7-4387-ac33-2b6a04c71202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139445808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1139445808
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1122067184
Short name T326
Test name
Test status
Simulation time 4376578145 ps
CPU time 34.2 seconds
Started Aug 18 06:13:45 PM PDT 24
Finished Aug 18 06:14:19 PM PDT 24
Peak memory 218904 kb
Host smart-f8abd673-ca60-4e18-9f55-a3d083534181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122067184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1122067184
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.572903646
Short name T717
Test name
Test status
Simulation time 262674179 ps
CPU time 2.53 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 209204 kb
Host smart-87edf895-0a52-4a2d-94fd-1e02a67f519c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572903646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.572903646
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3600757048
Short name T502
Test name
Test status
Simulation time 61025620 ps
CPU time 2.88 seconds
Started Aug 18 06:13:44 PM PDT 24
Finished Aug 18 06:13:47 PM PDT 24
Peak memory 208872 kb
Host smart-e60c0404-747c-46f6-b496-5f22bc64e932
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600757048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3600757048
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.508079688
Short name T825
Test name
Test status
Simulation time 516920728 ps
CPU time 2.56 seconds
Started Aug 18 06:13:27 PM PDT 24
Finished Aug 18 06:13:30 PM PDT 24
Peak memory 207932 kb
Host smart-b252cec0-99c9-45c4-8385-ccb6846362d3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508079688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.508079688
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1767334785
Short name T807
Test name
Test status
Simulation time 161904648 ps
CPU time 4.87 seconds
Started Aug 18 06:13:39 PM PDT 24
Finished Aug 18 06:13:44 PM PDT 24
Peak memory 208924 kb
Host smart-6f28502c-b950-4a9b-820e-c420299e3d2c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767334785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1767334785
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.4044487239
Short name T898
Test name
Test status
Simulation time 19878907 ps
CPU time 1.64 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:48 PM PDT 24
Peak memory 216104 kb
Host smart-1a34f9ef-051b-46c2-88ea-b7305fba669f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044487239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.4044487239
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3477975395
Short name T645
Test name
Test status
Simulation time 138303811 ps
CPU time 2.49 seconds
Started Aug 18 06:13:26 PM PDT 24
Finished Aug 18 06:13:29 PM PDT 24
Peak memory 209160 kb
Host smart-b5e5198e-5124-419b-b9ad-c6f4c63bc09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477975395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3477975395
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.361540032
Short name T199
Test name
Test status
Simulation time 9038385530 ps
CPU time 50.34 seconds
Started Aug 18 06:13:38 PM PDT 24
Finished Aug 18 06:14:28 PM PDT 24
Peak memory 223028 kb
Host smart-96a03ff4-affb-4258-9a76-65d2fd636ff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361540032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.361540032
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2686811618
Short name T710
Test name
Test status
Simulation time 3319512144 ps
CPU time 35.84 seconds
Started Aug 18 06:13:50 PM PDT 24
Finished Aug 18 06:14:27 PM PDT 24
Peak memory 209008 kb
Host smart-ad02f41e-b542-4d0d-aa63-5f8ffefc2a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686811618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2686811618
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3944245274
Short name T531
Test name
Test status
Simulation time 46527595 ps
CPU time 1.91 seconds
Started Aug 18 06:13:43 PM PDT 24
Finished Aug 18 06:13:45 PM PDT 24
Peak memory 210208 kb
Host smart-d4bbd5f3-4771-40e4-88bc-174fba315611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944245274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3944245274
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1836123672
Short name T467
Test name
Test status
Simulation time 33505664 ps
CPU time 0.81 seconds
Started Aug 18 06:13:44 PM PDT 24
Finished Aug 18 06:13:45 PM PDT 24
Peak memory 206416 kb
Host smart-ff74be5f-2729-4c8f-a4b0-e971a8843db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836123672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1836123672
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3065755469
Short name T866
Test name
Test status
Simulation time 170526400 ps
CPU time 3.47 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 222944 kb
Host smart-4c418be0-3906-4f96-adc9-12fcb7e490d7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3065755469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3065755469
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.4241155241
Short name T661
Test name
Test status
Simulation time 88774394 ps
CPU time 2.95 seconds
Started Aug 18 06:13:49 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 221900 kb
Host smart-468fbac5-316f-44cc-af98-364558c664c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241155241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.4241155241
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.890385517
Short name T522
Test name
Test status
Simulation time 42958006 ps
CPU time 1.62 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 208852 kb
Host smart-bcdcd652-f10d-477d-b404-148ffafdfa3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890385517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.890385517
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3048367777
Short name T273
Test name
Test status
Simulation time 674851652 ps
CPU time 2.92 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 214852 kb
Host smart-5bacc18d-907d-4d74-b907-2018009eb3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048367777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3048367777
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2549438413
Short name T662
Test name
Test status
Simulation time 99847023 ps
CPU time 3.71 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 220788 kb
Host smart-8f606cd3-b44d-474c-b81e-f0de32fd8cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549438413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2549438413
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2775889140
Short name T95
Test name
Test status
Simulation time 102245781 ps
CPU time 3.56 seconds
Started Aug 18 06:13:42 PM PDT 24
Finished Aug 18 06:13:46 PM PDT 24
Peak memory 214812 kb
Host smart-4fccaee6-16c7-4343-875a-2aec48839746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775889140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2775889140
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.336422435
Short name T881
Test name
Test status
Simulation time 520392032 ps
CPU time 3.01 seconds
Started Aug 18 06:13:39 PM PDT 24
Finished Aug 18 06:13:43 PM PDT 24
Peak memory 207400 kb
Host smart-6c14e769-485e-4a91-aecb-5f67052fb124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336422435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.336422435
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.94318066
Short name T463
Test name
Test status
Simulation time 66422540 ps
CPU time 3.5 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 209368 kb
Host smart-0f274954-e431-43e1-9ab6-1352941ccdc3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94318066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.94318066
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3179443938
Short name T693
Test name
Test status
Simulation time 200222954 ps
CPU time 2.76 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 207288 kb
Host smart-2bed245f-f5ce-4a53-948e-4866b52f2e35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179443938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3179443938
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.4233595952
Short name T601
Test name
Test status
Simulation time 549703954 ps
CPU time 6.55 seconds
Started Aug 18 06:13:42 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 208484 kb
Host smart-d9f72f82-2d4a-4e75-81cd-afcc18753045
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233595952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.4233595952
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2416750847
Short name T347
Test name
Test status
Simulation time 101716108 ps
CPU time 2.47 seconds
Started Aug 18 06:13:37 PM PDT 24
Finished Aug 18 06:13:40 PM PDT 24
Peak memory 210920 kb
Host smart-00a0f6b4-e99a-4a7f-9f03-e1bc5d90d518
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416750847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2416750847
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2048049144
Short name T812
Test name
Test status
Simulation time 39255793 ps
CPU time 1.65 seconds
Started Aug 18 06:13:48 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 207312 kb
Host smart-b5fcd011-b0e8-49b5-b1b0-db95125a95d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048049144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2048049144
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2376454198
Short name T414
Test name
Test status
Simulation time 3306972163 ps
CPU time 32.66 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:14:20 PM PDT 24
Peak memory 209120 kb
Host smart-4f4d0b9c-ff96-4715-89a7-8054bac2bf31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376454198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2376454198
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3800749746
Short name T892
Test name
Test status
Simulation time 122272141 ps
CPU time 3.61 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 211276 kb
Host smart-e0671030-8220-4f5f-ad17-78d5879f5c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800749746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3800749746
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.268250742
Short name T617
Test name
Test status
Simulation time 35416621 ps
CPU time 0.77 seconds
Started Aug 18 06:13:45 PM PDT 24
Finished Aug 18 06:13:46 PM PDT 24
Peak memory 206396 kb
Host smart-7cde1ed3-f340-4ce8-8864-8002dd9dda38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268250742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.268250742
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2159792580
Short name T328
Test name
Test status
Simulation time 193013516 ps
CPU time 10.03 seconds
Started Aug 18 06:13:49 PM PDT 24
Finished Aug 18 06:13:59 PM PDT 24
Peak memory 214760 kb
Host smart-8fb4f5a8-7229-4ff0-a9c9-a38a67e686e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2159792580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2159792580
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1955794505
Short name T431
Test name
Test status
Simulation time 34461924 ps
CPU time 2.1 seconds
Started Aug 18 06:13:41 PM PDT 24
Finished Aug 18 06:13:43 PM PDT 24
Peak memory 209632 kb
Host smart-b3c8be69-06a0-4a40-870e-d7d0c8508b03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955794505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1955794505
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.31432998
Short name T585
Test name
Test status
Simulation time 399762375 ps
CPU time 8.46 seconds
Started Aug 18 06:13:50 PM PDT 24
Finished Aug 18 06:14:00 PM PDT 24
Peak memory 214716 kb
Host smart-5b029156-000c-49d9-9a24-f03c84a05d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31432998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.31432998
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.88024689
Short name T257
Test name
Test status
Simulation time 124111941 ps
CPU time 2.53 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:50 PM PDT 24
Peak memory 206548 kb
Host smart-241b2e3a-cee4-41b1-94dd-33c5a7521e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88024689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.88024689
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1531380113
Short name T98
Test name
Test status
Simulation time 346121399 ps
CPU time 3.88 seconds
Started Aug 18 06:13:41 PM PDT 24
Finished Aug 18 06:13:45 PM PDT 24
Peak memory 210136 kb
Host smart-19852dc4-e457-4ac3-bc8e-78ccf8cb4a31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531380113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1531380113
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.800086392
Short name T627
Test name
Test status
Simulation time 382154329 ps
CPU time 3.46 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 218836 kb
Host smart-c8d48a32-5793-4d34-87cf-8d81e0e3a9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800086392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.800086392
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.100091923
Short name T353
Test name
Test status
Simulation time 27436062 ps
CPU time 2.02 seconds
Started Aug 18 06:13:40 PM PDT 24
Finished Aug 18 06:13:42 PM PDT 24
Peak memory 209136 kb
Host smart-6f38e568-fc40-4664-b4ec-71869352b066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100091923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.100091923
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.4199210756
Short name T621
Test name
Test status
Simulation time 1909573834 ps
CPU time 5.3 seconds
Started Aug 18 06:13:43 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 209320 kb
Host smart-9d63d864-bbf8-4787-bf2a-b368f9521f00
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199210756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.4199210756
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.4076089825
Short name T584
Test name
Test status
Simulation time 294983674 ps
CPU time 4.04 seconds
Started Aug 18 06:13:47 PM PDT 24
Finished Aug 18 06:13:51 PM PDT 24
Peak memory 208492 kb
Host smart-dce4ad99-f26e-445c-858d-ebd5d661b3e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076089825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.4076089825
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3886163281
Short name T910
Test name
Test status
Simulation time 303147079 ps
CPU time 3.21 seconds
Started Aug 18 06:13:37 PM PDT 24
Finished Aug 18 06:13:40 PM PDT 24
Peak memory 207392 kb
Host smart-bbc815eb-da84-4acd-aaf6-9ae0b21800d2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886163281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3886163281
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1580166077
Short name T453
Test name
Test status
Simulation time 7267609220 ps
CPU time 10.68 seconds
Started Aug 18 06:13:44 PM PDT 24
Finished Aug 18 06:13:55 PM PDT 24
Peak memory 210008 kb
Host smart-326b76f2-c02c-4f26-a80e-ff41b524ff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580166077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1580166077
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1510330658
Short name T545
Test name
Test status
Simulation time 433300383 ps
CPU time 10.76 seconds
Started Aug 18 06:13:34 PM PDT 24
Finished Aug 18 06:13:45 PM PDT 24
Peak memory 208868 kb
Host smart-6467ae3b-62b7-4e89-a300-28f4f655a4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510330658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1510330658
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.263247435
Short name T85
Test name
Test status
Simulation time 218219244 ps
CPU time 14.12 seconds
Started Aug 18 06:13:44 PM PDT 24
Finished Aug 18 06:13:58 PM PDT 24
Peak memory 223048 kb
Host smart-751c87b1-fefb-4376-a17b-da77b632374d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263247435 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.263247435
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1895190961
Short name T266
Test name
Test status
Simulation time 46173358 ps
CPU time 3.16 seconds
Started Aug 18 06:13:46 PM PDT 24
Finished Aug 18 06:13:49 PM PDT 24
Peak memory 211124 kb
Host smart-2d32ea50-8b71-4ddb-80a1-14424cb0cb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895190961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1895190961
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.82001949
Short name T863
Test name
Test status
Simulation time 1048263492 ps
CPU time 2.64 seconds
Started Aug 18 06:13:49 PM PDT 24
Finished Aug 18 06:13:52 PM PDT 24
Peak memory 210476 kb
Host smart-817530c9-0a82-4c0b-8128-353422d5c095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82001949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.82001949
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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