Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	42	1			T5	1		T56	1		T97	1
auto[OpGenId]	8	1			T124	1		T27	1		T189	1
auto[OpGenSwOut]	19	1			T30	1		T6	1		T122	1
auto[OpGenHwOut]	20	1			T4	1		T5	1		T6	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1711	1			T4	4		T11	2		T5	1
auto[StInit]	80	1			T11	1		T13	1		T5	2
auto[StCreatorRootKey]	44	1			T56	2		T23	1		T114	1
auto[StOwnerIntKey]	53	1			T4	1		T5	1		T30	1
auto[StOwnerKey]	39	1			T17	1		T97	1		T101	1
auto[StDisabled]	428	1			T4	11		T11	2		T5	16
auto[StInvalid]	50	1			T20	1		T109	1		T43	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3400

1

T1

1

T2

1

T3

1

auto[1]

89

1

T4

1

T5

2

T30

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1707	1			T4	4		T11	2		T5	1
auto[StReset]	auto[1]	4	1			T36	1		T110	1		T190	1
auto[StInit]	auto[0]	51	1			T11	1		T13	1		T5	1
auto[StInit]	auto[1]	29	1			T5	1		T6	1		T112	1
auto[StCreatorRootKey]	auto[0]	24	1			T56	1		T23	1		T114	1
auto[StCreatorRootKey]	auto[1]	20	1			T56	1		T116	1		T178	1
auto[StOwnerIntKey]	auto[0]	35	1			T32	1		T117	1		T191	1
auto[StOwnerIntKey]	auto[1]	18	1			T4	1		T5	1		T30	1
auto[StOwnerKey]	auto[0]	31	1			T17	1		T101	1		T74	2
auto[StOwnerKey]	auto[1]	8	1			T97	1		T192	1		T193	1
auto[StDisabled]	auto[0]	418	1			T4	11		T11	2		T5	16
auto[StDisabled]	auto[1]	10	1			T124	2		T122	1		T178	1
auto[StInvalid]	auto[0]	50	1			T20	1		T109	1		T43	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut]]	--	--	2
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	2	1			T110	1		T190	1		-	-
auto[StReset]	auto[OpGenHwOut]	2	1			T36	1		T105	1		-	-
auto[StInit]	auto[OpAdvance]	14	1			T5	1		T112	1		T194	1
auto[StInit]	auto[OpGenId]	1	1			T106	1		-	-		-	-
auto[StInit]	auto[OpGenSwOut]	7	1			T195	1		T196	1		T197	1
auto[StInit]	auto[OpGenHwOut]	7	1			T6	1		T198	1		T199	1
auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T56	1		T116	1		T178	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T189	1		T200	1		T201	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T202	1		T203	1		T204	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	2	1			T205	1		T206	1		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T33	1		T29	1		T207	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T27	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T30	1		T6	1		T208	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	4	1			T4	1		T5	1		T75	1
auto[StOwnerKey]	auto[OpAdvance]	5	1			T97	1		T193	1		T25	1
auto[StOwnerKey]	auto[OpGenId]	2	1			T192	1		T203	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T209	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	2	1			T210	1		T211	1		-	-
auto[StDisabled]	auto[OpGenId]	1	1			T124	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	3	1			T122	1		T212	1		T213	1
auto[StDisabled]	auto[OpGenHwOut]	4	1			T124	1		T178	1		T214	1