Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.84	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	73	257	77.88

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	54	226	80.71	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4618

1

T1

3

T2

5

T3

14

auto[1]

530

1

T4

5

T22

2

T5

9

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4618

1

T1

3

T2

5

T3

14

auto[1]

530

1

T4

5

T22

2

T5

9

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4627

1

T1

3

T2

5

T3

14

auto[1]

521

1

T4

5

T12

1

T14

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4627

1

T1

3

T2

5

T3

14

auto[1]

521

1

T4

5

T12

1

T14

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	392	1			T3	2		T4	2		T11	1
auto[OpGenId]	1085	1			T1	1		T3	4		T4	14
auto[OpGenSwOut]	1128	1			T2	2		T3	7		T4	7
auto[OpGenHwOut]	2485	1			T1	2		T2	3		T3	1
auto[OpDisable]	58	1			T5	3		T111	1		T63	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	392	1			T3	2		T4	2		T11	1
auto[OpGenId]	1085	1			T1	1		T3	4		T4	14
auto[OpGenSwOut]	1128	1			T2	2		T3	7		T4	7
auto[OpGenHwOut]	2485	1			T1	2		T2	3		T3	1
auto[OpDisable]	58	1			T5	3		T111	1		T63	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4615

1

T1

3

T2

5

T3

14

auto[1]

533

1

T4

6

T14

1

T5

9

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4615

1

T1

3

T2

5

T3

14

auto[1]

533

1

T4

6

T14

1

T5

9

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4875

1

T1

3

T2

5

T3

3

auto[1]

273

1

T3

11

T14

12

T62

4

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1739	1			T1	1		T2	2		T3	10
auto[1]	672	1			T4	7		T11	2		T12	1
auto[2]	653	1			T4	8		T12	1		T13	1
auto[3]	698	1			T1	1		T2	1		T4	1
auto[4]	329	1			T2	1		T4	1		T15	1
auto[5]	364	1			T1	1		T3	3		T4	3
auto[6]	324	1			T2	1		T3	1		T4	3
auto[7]	369	1			T4	2		T11	1		T12	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1386	1			T1	1		T2	2		T3	4
clear_one[1]	672	1			T4	7		T11	2		T12	1
clear_one[2]	653	1			T4	8		T12	1		T13	1
clear_one[3]	698	1			T1	1		T2	1		T4	1
clear_none	1739	1			T1	1		T2	2		T3	10

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	957	1			T2	2		T3	1		T4	10
auto[StInit]	601	1			T2	1		T3	1		T4	3
auto[StCreatorRootKey]	553	1			T2	1		T3	3		T4	4
auto[StOwnerIntKey]	489	1			T2	1		T3	4		T4	3
auto[StOwnerKey]	478	1			T3	1		T4	5		T11	2
auto[StDisabled]	1775	1			T3	4		T4	14		T11	3
auto[StInvalid]	295	1			T1	3		T20	3		T42	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	957	1			T2	2		T3	1		T4	10
auto[StInit]	601	1			T2	1		T3	1		T4	3
auto[StCreatorRootKey]	553	1			T2	1		T3	3		T4	4
auto[StOwnerIntKey]	489	1			T2	1		T3	4		T4	3
auto[StOwnerKey]	478	1			T3	1		T4	5		T11	2
auto[StDisabled]	1775	1			T3	4		T4	14		T11	3
auto[StInvalid]	295	1			T1	3		T20	3		T42	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	54	226	80.71	54

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[1]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[1]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[3] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[3] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[3] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T3	1		T216	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	166	1			T4	1		T11	1		T13	2
auto[0]	auto[StReset]	auto[OpGenSwOut]	143	1			T2	1		T4	2		T11	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	240	1			T4	3		T15	2		T5	1
auto[0]	auto[StInit]	auto[OpAdvance]	44	1			T5	1		T19	1		T17	1
auto[0]	auto[StInit]	auto[OpGenId]	93	1			T3	1		T5	2		T56	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	75	1			T11	1		T5	1		T19	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	186	1			T4	2		T12	1		T15	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	15	1			T101	1		T74	1		T86	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	62	1			T3	2		T4	1		T5	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	45	1			T3	1		T56	1		T60	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	77	1			T4	1		T56	1		T140	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T4	1		T14	1		T119	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	23	1			T3	1		T101	1		T217	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	41	1			T2	1		T3	3		T5	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T218	1		T44	1		T219	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T3	1		T14	1		T22	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	14	1			T4	1		T14	1		T121	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	28	1			T14	2		T5	2		T62	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T136	1		T187	1		T220	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	23	1			T221	1		T179	2		T222	1
auto[0]	auto[StDisabled]	auto[OpGenId]	50	1			T62	2		T75	2		T223	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	82	1			T11	1		T14	2		T5	2
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	132	1			T4	2		T5	1		T137	1
auto[0]	auto[StDisabled]	auto[OpDisable]	10	1			T224	1		T124	2		T225	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	7	1			T42	1		T39	1		T226	1
auto[0]	auto[StInvalid]	auto[OpGenId]	25	1			T53	1		T39	1		T115	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	21	1			T109	1		T53	2		T227	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	21	1			T1	1		T20	1		T42	1
auto[1]	auto[StReset]	auto[OpGenId]	24	1			T4	1		T5	2		T74	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	22	1			T57	1		T228	1		T229	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	43	1			T111	1		T57	1		T185	2
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T22	1		T78	1		T230	1
auto[1]	auto[StInit]	auto[OpGenId]	5	1			T100	1		T231	1		T232	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	9	1			T124	1		T233	1		T234	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	18	1			T185	1		T218	1		T235	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T236	1		T180	1		T237	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T238	1		T239	1		T240	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T241	1		T242	1		T81	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T57	1		T243	1		T244	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T245	1		T246	1		-	-
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T5	2		T247	1		T179	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T5	1		T137	1		T140	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T4	1		T188	1		T174	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T11	1		T124	2		T78	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	18	1			T171	1		T248	1		T249	2
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T250	1		T124	1		T119	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T15	1		T251	1		T252	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	25	1			T124	1		T253	1		T84	2
auto[1]	auto[StDisabled]	auto[OpGenId]	51	1			T4	5		T5	1		T19	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	54	1			T11	1		T5	1		T136	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	157	1			T12	1		T187	1		T220	1
auto[1]	auto[StDisabled]	auto[OpDisable]	9	1			T5	1		T254	1		T130	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	5	1			T172	1		T255	1		T256	1
auto[1]	auto[StInvalid]	auto[OpGenId]	11	1			T42	1		T257	1		T229	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T258	1		T259	1		T260	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T258	1		T261	1		T226	1
auto[2]	auto[StReset]	auto[OpAdvance]	1	1			T246	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	25	1			T4	1		T5	1		T99	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	20	1			T5	1		T43	1		T253	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	27	1			T4	1		T220	1		T218	1
auto[2]	auto[StInit]	auto[OpAdvance]	2	1			T41	1		T262	1		-	-
auto[2]	auto[StInit]	auto[OpGenId]	10	1			T13	1		T5	1		T124	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	10	1			T23	1		T45	1		T119	2
auto[2]	auto[StInit]	auto[OpGenHwOut]	16	1			T223	1		T263	1		T264	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T265	1		T221	1		T210	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T4	1		T5	1		T98	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T5	1		T98	1		T74	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T12	1		T235	1		T263	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T120	1		T266	2		T267	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T4	1		T5	1		T250	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T97	1		T98	1		T76	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T139	1		T186	1		T268	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T98	1		T184	1		T81	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	10	1			T269	1		T270	1		T271	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T4	1		T175	1		T120	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	32	1			T272	1		T235	1		T268	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	26	1			T228	1		T82	1		T124	1
auto[2]	auto[StDisabled]	auto[OpGenId]	59	1			T14	1		T5	2		T127	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	50	1			T4	1		T5	1		T57	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T4	2		T139	1		T140	1
auto[2]	auto[StDisabled]	auto[OpDisable]	11	1			T5	2		T273	1		T248	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T43	1		T226	1		T274	1
auto[2]	auto[StInvalid]	auto[OpGenId]	10	1			T172	1		T275	1		T226	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T276	1		T277	1		T278	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T279	1		T276	1		T280	1
auto[3]	auto[StReset]	auto[OpGenId]	25	1			T5	1		T56	1		T21	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	24	1			T281	1		T124	1		T27	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	42	1			T185	1		T218	1		T43	1
auto[3]	auto[StInit]	auto[OpAdvance]	7	1			T56	1		T175	1		T112	1
auto[3]	auto[StInit]	auto[OpGenId]	5	1			T41	1		T233	1		T282	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	12	1			T14	2		T283	1		T284	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	19	1			T14	2		T56	1		T57	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	15	1			T14	1		T5	1		T82	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T5	1		T175	1		T124	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T78	1		T119	1		T285	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T2	1		T139	1		T218	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T249	1		T286	1		T287	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T14	1		T288	1		T289	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T14	1		T273	1		T124	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	46	1			T15	1		T187	1		T272	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T290	1		T291	1		T120	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	14	1			T11	1		T57	1		T75	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T74	1		T284	2		T119	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T139	1		T188	1		T186	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	20	1			T4	1		T98	2		T245	1
auto[3]	auto[StDisabled]	auto[OpGenId]	31	1			T22	1		T57	1		T121	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	42	1			T5	2		T171	1		T292	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	166	1			T15	1		T5	2		T64	1
auto[3]	auto[StDisabled]	auto[OpDisable]	6	1			T121	1		T113	1		T293	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	5	1			T109	1		T258	1		T261	1
auto[3]	auto[StInvalid]	auto[OpGenId]	11	1			T1	1		T43	1		T49	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	18	1			T257	1		T229	1		T255	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T109	2		T172	1		T229	1
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T294	1		T222	1		T226	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	8	1			T97	1		T131	1		T295	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	13	1			T59	1		T263	1		T264	1
auto[4]	auto[StInit]	auto[OpAdvance]	6	1			T296	1		T297	1		T298	2
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T225	1		T179	1		T130	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	5	1			T45	1		T299	1		T300	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	9	1			T2	1		T252	1		T301	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T302	1		T303	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T116	1		T135	1		T304	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T4	1		T178	1		T119	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T174	1		T305	1		T76	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T231	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T57	1		T284	1		T306	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T180	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	12	1			T220	1		T307	1		T124	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T308	1		T233	1		T309	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	6	1			T285	1		T310	1		T132	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T5	1		T121	1		T311	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T301	1		T312	1		T284	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	8	1			T136	1		T281	1		T313	1
auto[4]	auto[StDisabled]	auto[OpGenId]	37	1			T6	1		T175	1		T250	2
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	26	1			T5	1		T137	1		T60	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T15	1		T5	1		T57	1
auto[4]	auto[StDisabled]	auto[OpDisable]	5	1			T111	1		T63	1		T314	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T315	1		T316	1		T317	1
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T20	1		T257	1		T49	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T42	1		T318	1		T255	2
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T53	1		T316	1		T278	1
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T5	1		T19	1		T126	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	11	1			T112	1		T281	1		T177	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	21	1			T5	1		T220	2		T319	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T119	1		T35	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T5	1		T254	1		T132	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	10	1			T84	3		T249	1		T239	2
auto[5]	auto[StInit]	auto[OpGenHwOut]	9	1			T4	1		T111	1		T320	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T321	1		T271	1		T50	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T75	1		T322	1		T323	2
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T208	1		T119	1		T324	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T185	1		T272	1		T319	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T325	1		T326	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T327	1		T328	1		T329	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T11	1		T330	1		T178	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T184	1		T223	1		T331	2
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T120	1		-	-		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	7	1			T4	1		T332	1		T284	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T296	1		T333	1		T119	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T97	1		T334	1		T208	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	8	1			T98	3		T289	1		T230	1
auto[5]	auto[StDisabled]	auto[OpGenId]	27	1			T4	1		T11	1		T57	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	30	1			T3	2		T5	2		T57	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T3	1		T12	1		T137	1
auto[5]	auto[StDisabled]	auto[OpDisable]	6	1			T127	1		T284	1		T324	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	6	1			T229	1		T315	1		T299	1
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T53	1		T335	1		T336	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T275	1		T315	1		T279	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T1	1		T337	1		T338	1
auto[6]	auto[StReset]	auto[OpGenId]	12	1			T137	1		T241	1		T74	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	8	1			T97	1		T281	1		T339	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	23	1			T2	1		T4	1		T59	1
auto[6]	auto[StInit]	auto[OpAdvance]	1	1			T340	1		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T290	1		T27	1		T110	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	3	1			T324	1		T47	1		T181	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	5	1			T268	1		T341	1		T342	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T122	1		T343	1		T344	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T340	1		T180	1		T135	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T5	1		T345	1		T346	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T5	1		T19	1		T347	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T214	1		T348	1		T349	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T248	1		T350	1		T351	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T178	1		T343	1		T203	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	23	1			T12	1		T185	1		T352	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T353	1		T271	1		T354	4
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T5	1		T80	1		T355	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T212	1		T356	1		T357	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	24	1			T4	2		T12	1		T264	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	10	1			T284	1		T178	1		T358	1
auto[6]	auto[StDisabled]	auto[OpGenId]	20	1			T5	1		T228	1		T38	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T3	1		T281	1		T359	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T12	1		T14	1		T15	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T294	1		T360	1		T135	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	5	1			T337	1		T361	1		T362	1
auto[6]	auto[StInvalid]	auto[OpGenId]	8	1			T109	1		T258	1		T335	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T257	1		T363	1		T364	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T39	1		T338	1		T365	1
auto[7]	auto[StReset]	auto[OpGenId]	14	1			T325	1		T82	1		T80	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	13	1			T83	1		T253	1		T88	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	11	1			T185	1		T223	1		T366	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T88	1		T367	1		T368	1
auto[7]	auto[StInit]	auto[OpGenId]	3	1			T41	1		T133	1		T344	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T360	1		T302	1		T369	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	10	1			T219	1		T370	1		T371	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T372	1		T373	1		T374	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T29	1		T46	1		T368	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T11	1		T330	1		T100	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	27	1			T15	1		T188	1		T186	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T375	1		T343	1		T166	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	4	1			T376	1		T211	1		T377	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T74	1		T45	1		T293	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	17	1			T74	1		T290	1		T301	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T5	1		T120	1		T295	2
auto[7]	auto[StOwnerKey]	auto[OpGenId]	8	1			T378	1		T379	1		T132	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T178	1		T119	1		T328	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	27	1			T6	1		T174	1		T307	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	14	1			T119	1		T372	1		T131	1
auto[7]	auto[StDisabled]	auto[OpGenId]	23	1			T177	1		T124	1		T284	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T4	2		T5	1		T225	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	97	1			T12	1		T15	1		T136	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T221	1		T178	1		T119	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T318	1		T275	1		T337	1
auto[7]	auto[StInvalid]	auto[OpGenId]	9	1			T49	1		T365	1		T256	2
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T20	1		T380	1		T381	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T42	1		T115	1		T229	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1386

1

T1

1

T2

2

T3

4

clear_one[1]

auto[0]

auto[0]

auto[0]

392

1

T4

3

T11

2

T22

1

clear_one[1]

auto[0]

auto[0]

auto[1]

124

1

T4

3

T5

1

T140

1

clear_one[1]

auto[0]

auto[1]

auto[0]

118

1

T4

1

T12

1

T15

1

clear_one[1]

auto[0]

auto[1]

auto[1]

38

1

T5

2

T19

1

T74

1

clear_one[2]

auto[0]

auto[0]

auto[0]

372

1

T4

6

T12

1

T13

1

clear_one[2]

auto[0]

auto[0]

auto[1]

121

1

T4

1

T14

1

T5

1

clear_one[2]

auto[1]

auto[0]

auto[0]

125

1

T5

3

T127

1

T187

1

clear_one[2]

auto[1]

auto[0]

auto[1]

35

1

T4

1

T5

1

T140

1

clear_one[3]

auto[0]

auto[0]

auto[0]

420

1

T1

1

T2

1

T11

1

clear_one[3]

auto[0]

auto[1]

auto[0]

125

1

T15

2

T111

1

T139

3

clear_one[3]

auto[1]

auto[0]

auto[0]

111

1

T5

1

T64

1

T187

1

clear_one[3]

auto[1]

auto[1]

auto[0]

42

1

T4

1

T22

1

T5

1

clear_none

auto[0]

auto[0]

auto[0]

1249

1

T1

1

T2

2

T3

10

clear_none

auto[0]

auto[0]

auto[1]

121

1

T136

1

T62

2

T127

1

clear_none

auto[0]

auto[1]

auto[0]

116

1

T14

1

T137

1

T139

2

clear_none

auto[0]

auto[1]

auto[1]

36

1

T4

1

T5

2

T177

1

clear_none

auto[1]

auto[0]

auto[0]

132

1

T4

1

T22

1

T5

1

clear_none

auto[1]

auto[0]

auto[1]

39

1

T5

1

T184

1

T75

1

clear_none

auto[1]

auto[1]

auto[0]

27

1

T4

2

T74

1

T121

1

clear_none

auto[1]

auto[1]

auto[1]

19

1

T5

1

T62

2

T121

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1324	1			T1	1		T2	2		T3	1
clear_all	auto[1]	62	1			T3	3		T98	2		T84	3
clear_one[1]	auto[0]	616	1			T4	7		T11	2		T12	1
clear_one[1]	auto[1]	56	1			T84	5		T249	1		T309	1
clear_one[2]	auto[0]	620	1			T4	8		T12	1		T13	1
clear_one[2]	auto[1]	33	1			T98	4		T82	1		T249	1
clear_one[3]	auto[0]	647	1			T1	1		T2	1		T4	1
clear_one[3]	auto[1]	51	1			T14	6		T98	1		T82	2
clear_none	auto[0]	1668	1			T1	1		T2	2		T3	2
clear_none	auto[1]	71	1			T3	8		T14	6		T62	4