Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11199

1

T2

21

T3

10

T4

127

auto[Attestation]

7243

1

T2

4

T3

12

T4

106

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2650	1			T2	5		T3	7		T4	33
auto[Aes]	3320	1			T2	6		T3	3		T4	41
auto[Kmac]	3259	1			T2	7		T3	1		T4	35
auto[Otbn]	3388	1			T2	4		T3	4		T4	47

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7522	1			T1	1		T2	3		T3	8
auto[OpGenId]	5825	1			T2	3		T3	7		T4	77
auto[OpGenSwOut]	5971	1			T2	10		T3	11		T4	82
auto[OpGenHwOut]	6646	1			T2	12		T3	4		T4	74
auto[OpDisable]	126	1			T4	2		T5	3		T64	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10550

1

T1

1

T2

14

T3

11

auto[OpDoneFail]

15540

1

T2

14

T3

19

T4

196

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6349	1			T1	1		T2	10		T3	1
auto[StInit]	3522	1			T2	6		T3	6		T4	38
auto[StCreatorRootKey]	3160	1			T2	4		T3	4		T4	39
auto[StOwnerIntKey]	2840	1			T2	8		T3	4		T4	30
auto[StOwnerKey]	2406	1			T3	1		T4	32		T11	3
auto[StDisabled]	7813	1			T3	14		T4	109		T11	8

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	342	1			T2	1		T4	4		T11	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	82	1			T2	1		T5	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	88	1			T4	1		T5	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	83	1			T4	1		T14	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	72	1			T5	1		T137	1		T121	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	255	1			T3	3		T4	6		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	339	1			T2	2		T4	3		T11	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	97	1			T3	1		T4	2		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T3	1		T4	1		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	76	1			T3	1		T5	2		T32	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	64	1			T4	2		T5	1		T57	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	236	1			T4	6		T14	1		T5	5
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	348	1			T2	1		T4	3		T11	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	106	1			T4	1		T5	1		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T5	2		T56	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T2	1		T11	1		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	59	1			T14	1		T5	1		T140	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	193	1			T4	3		T11	1		T5	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	351	1			T2	1		T4	3		T11	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	91	1			T4	2		T5	2		T30	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	104	1			T4	2		T11	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	77	1			T2	1		T4	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	55	1			T5	2		T101	1		T173	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	230	1			T4	4		T14	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	55	1			T4	1		T5	4		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	113	1			T4	5		T13	1		T14	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	69	1			T3	1		T5	2		T30	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	69	1			T2	1		T3	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	68	1			T4	1		T14	1		T5	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	196	1			T3	1		T4	1		T5	6
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	62	1			T4	3		T5	7		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	96	1			T4	1		T11	1		T5	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	70	1			T4	1		T11	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	68	1			T4	1		T19	1		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	80	1			T4	2		T5	2		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	178	1			T4	2		T14	1		T5	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	72	1			T4	1		T5	5		T74	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	104	1			T2	1		T4	2		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T4	2		T5	3		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	83	1			T4	1		T14	1		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	63	1			T19	1		T101	1		T170	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	228	1			T4	2		T22	2		T5	7
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	82	1			T4	5		T5	5		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	97	1			T4	1		T11	1		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	84	1			T4	1		T11	1		T5	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T5	1		T61	1		T74	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	47	1			T4	2		T5	1		T57	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	219	1			T3	2		T4	2		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	270	1			T4	3		T11	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	74	1			T2	1		T5	2		T183	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	72	1			T2	1		T4	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	52	1			T60	1		T74	1		T184	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	51	1			T136	1		T140	1		T121	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	173	1			T4	5		T5	1		T61	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	452	1			T2	1		T11	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	112	1			T2	2		T13	2		T5	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	126	1			T4	1		T5	2		T30	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	117	1			T2	1		T4	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	83	1			T4	1		T185	1		T74	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	295	1			T4	2		T14	1		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	415	1			T4	5		T15	6		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	128	1			T4	3		T11	1		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	98	1			T4	1		T5	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T2	2		T15	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	75	1			T4	1		T12	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	264	1			T3	1		T4	5		T12	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	409	1			T2	1		T4	3		T11	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	121	1			T3	1		T4	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	135	1			T2	1		T4	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	102	1			T4	2		T5	1		T64	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	89	1			T4	2		T136	1		T186	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	311	1			T4	6		T22	1		T5	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	42	1			T4	1		T5	3		T177	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	65	1			T14	1		T5	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T4	1		T5	2		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	87	1			T4	1		T22	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T5	1		T57	1		T97	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	143	1			T3	1		T5	2		T136	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	38	1			T4	2		T5	3		T57	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	101	1			T4	1		T14	1		T140	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	98	1			T4	3		T22	1		T187	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	101	1			T4	1		T19	1		T59	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	73	1			T4	2		T5	1		T140	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	267	1			T4	3		T14	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	39	1			T5	2		T177	1		T78	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	106	1			T5	1		T136	1		T31	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	103	1			T12	1		T15	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T2	2		T4	2		T12	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	78	1			T15	1		T5	1		T139	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	263	1			T4	3		T12	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	44	1			T5	3		T57	1		T177	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	108	1			T4	1		T5	1		T137	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	96	1			T4	1		T5	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	109	1			T4	2		T30	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	68	1			T4	1		T136	1		T188	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	284	1			T3	1		T4	4		T14	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	219	1			T4	2		T14	1		T5	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	703	1			T2	2		T3	3		T4	10
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	216	1			T3	2		T4	3		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	687	1			T2	2		T3	1		T4	11
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	206	1			T2	1		T11	1		T14	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	663	1			T2	1		T4	7		T11	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	218	1			T2	1		T4	3		T11	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	690	1			T2	1		T4	9		T11	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	193	1			T2	1		T3	2		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	377	1			T3	1		T4	7		T13	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	202	1			T4	3		T11	1		T5	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	352	1			T4	7		T11	1		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	220	1			T4	3		T14	1		T5	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	421	1			T2	1		T4	5		T22	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	191	1			T4	3		T11	1		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	413	1			T3	2		T4	8		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	164	1			T2	1		T4	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	528	1			T2	1		T4	8		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	310	1			T2	1		T4	3		T5	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	875	1			T2	3		T4	2		T11	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	252	1			T2	2		T4	2		T12	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	819	1			T3	1		T4	13		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	302	1			T2	1		T4	5		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	865	1			T2	1		T3	1		T4	10
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	198	1			T4	2		T5	3		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	268	1			T3	1		T4	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	258	1			T4	6		T22	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	420	1			T4	6		T14	2		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	252	1			T2	2		T4	1		T12	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	426	1			T4	4		T12	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	260	1			T4	3		T5	1		T30	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	449	1			T3	1		T4	6		T14	1