Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32131

1

T1

31

T2

30

T3

33

auto[1]

307

1

T3

15

T14

12

T62

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32140	1			T1	31		T2	30		T3	33
auto[134217728:268435455]	13	1			T3	1		T82	1		T397	1
auto[268435456:402653183]	12	1			T3	1		T239	1		T286	1
auto[402653184:536870911]	11	1			T14	1		T84	1		T340	1
auto[536870912:671088639]	8	1			T3	1		T14	1		T286	1
auto[671088640:805306367]	7	1			T14	1		T62	1		T249	1
auto[805306368:939524095]	9	1			T98	1		T394	1		T396	1
auto[939524096:1073741823]	8	1			T84	1		T397	1		T392	1
auto[1073741824:1207959551]	12	1			T331	1		T287	1		T395	1
auto[1207959552:1342177279]	3	1			T262	1		T246	1		T216	1
auto[1342177280:1476395007]	7	1			T98	1		T262	1		T410	1
auto[1476395008:1610612735]	11	1			T98	1		T84	2		T397	1
auto[1610612736:1744830463]	12	1			T3	2		T84	1		T249	1
auto[1744830464:1879048191]	9	1			T14	1		T62	1		T88	1
auto[1879048192:2013265919]	9	1			T331	1		T287	1		T410	1
auto[2013265920:2147483647]	12	1			T3	2		T88	1		T396	1
auto[2147483648:2281701375]	4	1			T84	1		T374	1		T411	1
auto[2281701376:2415919103]	9	1			T14	1		T410	2		T354	1
auto[2415919104:2550136831]	13	1			T358	1		T287	1		T343	1
auto[2550136832:2684354559]	11	1			T249	2		T394	1		T287	1
auto[2684354560:2818572287]	8	1			T3	1		T310	1		T287	1
auto[2818572288:2952790015]	3	1			T3	1		T239	1		T412	1
auto[2952790016:3087007743]	12	1			T3	1		T14	1		T98	1
auto[3087007744:3221225471]	16	1			T3	1		T88	1		T392	1
auto[3221225472:3355443199]	4	1			T14	1		T98	1		T84	1
auto[3355443200:3489660927]	2	1			T14	1		T295	1		-	-
auto[3489660928:3623878655]	10	1			T397	1		T88	1		T396	1
auto[3623878656:3758096383]	14	1			T3	1		T14	1		T88	1
auto[3758096384:3892314111]	13	1			T14	1		T82	1		T88	1
auto[3892314112:4026531839]	9	1			T14	1		T84	1		T396	1
auto[4026531840:4160749567]	17	1			T3	2		T14	1		T84	1
auto[4160749568:4294967295]	10	1			T3	1		T84	1		T397	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32131	1			T1	31		T2	30		T3	33
auto[0:134217727]	auto[1]	9	1			T98	1		T84	1		T88	1
auto[134217728:268435455]	auto[1]	13	1			T3	1		T82	1		T397	1
auto[268435456:402653183]	auto[1]	12	1			T3	1		T239	1		T286	1
auto[402653184:536870911]	auto[1]	11	1			T14	1		T84	1		T340	1
auto[536870912:671088639]	auto[1]	8	1			T3	1		T14	1		T286	1
auto[671088640:805306367]	auto[1]	7	1			T14	1		T62	1		T249	1
auto[805306368:939524095]	auto[1]	9	1			T98	1		T394	1		T396	1
auto[939524096:1073741823]	auto[1]	8	1			T84	1		T397	1		T392	1
auto[1073741824:1207959551]	auto[1]	12	1			T331	1		T287	1		T395	1
auto[1207959552:1342177279]	auto[1]	3	1			T262	1		T246	1		T216	1
auto[1342177280:1476395007]	auto[1]	7	1			T98	1		T262	1		T410	1
auto[1476395008:1610612735]	auto[1]	11	1			T98	1		T84	2		T397	1
auto[1610612736:1744830463]	auto[1]	12	1			T3	2		T84	1		T249	1
auto[1744830464:1879048191]	auto[1]	9	1			T14	1		T62	1		T88	1
auto[1879048192:2013265919]	auto[1]	9	1			T331	1		T287	1		T410	1
auto[2013265920:2147483647]	auto[1]	12	1			T3	2		T88	1		T396	1
auto[2147483648:2281701375]	auto[1]	4	1			T84	1		T374	1		T411	1
auto[2281701376:2415919103]	auto[1]	9	1			T14	1		T410	2		T354	1
auto[2415919104:2550136831]	auto[1]	13	1			T358	1		T287	1		T343	1
auto[2550136832:2684354559]	auto[1]	11	1			T249	2		T394	1		T287	1
auto[2684354560:2818572287]	auto[1]	8	1			T3	1		T310	1		T287	1
auto[2818572288:2952790015]	auto[1]	3	1			T3	1		T239	1		T412	1
auto[2952790016:3087007743]	auto[1]	12	1			T3	1		T14	1		T98	1
auto[3087007744:3221225471]	auto[1]	16	1			T3	1		T88	1		T392	1
auto[3221225472:3355443199]	auto[1]	4	1			T14	1		T98	1		T84	1
auto[3355443200:3489660927]	auto[1]	2	1			T14	1		T295	1		-	-
auto[3489660928:3623878655]	auto[1]	10	1			T397	1		T88	1		T396	1
auto[3623878656:3758096383]	auto[1]	14	1			T3	1		T14	1		T88	1
auto[3758096384:3892314111]	auto[1]	13	1			T14	1		T82	1		T88	1
auto[3892314112:4026531839]	auto[1]	9	1			T14	1		T84	1		T396	1
auto[4026531840:4160749567]	auto[1]	17	1			T3	2		T14	1		T84	1
auto[4160749568:4294967295]	auto[1]	10	1			T3	1		T84	1		T397	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1473

1

T1

3

T2

2

T3

3

auto[1]

1789

1

T1

1

T2

1

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	85	1			T4	1		T14	1		T308	1
auto[134217728:268435455]	102	1			T4	1		T11	1		T5	5
auto[268435456:402653183]	109	1			T11	1		T13	1		T14	1
auto[402653184:536870911]	90	1			T22	1		T42	1		T52	1
auto[536870912:671088639]	124	1			T3	1		T4	1		T22	1
auto[671088640:805306367]	93	1			T2	1		T5	3		T56	1
auto[805306368:939524095]	93	1			T4	1		T5	1		T20	1
auto[939524096:1073741823]	109	1			T4	1		T5	2		T64	1
auto[1073741824:1207959551]	95	1			T4	1		T22	1		T20	1
auto[1207959552:1342177279]	96	1			T111	1		T109	1		T97	1
auto[1342177280:1476395007]	97	1			T4	1		T5	2		T59	1
auto[1476395008:1610612735]	92	1			T4	4		T11	1		T5	2
auto[1610612736:1744830463]	106	1			T4	1		T5	3		T56	1
auto[1744830464:1879048191]	102	1			T5	1		T111	1		T59	1
auto[1879048192:2013265919]	91	1			T4	1		T5	2		T42	1
auto[2013265920:2147483647]	84	1			T4	1		T56	1		T19	2
auto[2147483648:2281701375]	105	1			T1	1		T5	4		T20	1
auto[2281701376:2415919103]	96	1			T3	1		T11	2		T5	1
auto[2415919104:2550136831]	105	1			T3	1		T4	2		T22	1
auto[2550136832:2684354559]	96	1			T5	3		T20	1		T140	1
auto[2684354560:2818572287]	111	1			T4	1		T5	3		T56	1
auto[2818572288:2952790015]	119	1			T1	1		T14	1		T5	4
auto[2952790016:3087007743]	109	1			T4	1		T13	1		T5	2
auto[3087007744:3221225471]	109	1			T4	2		T22	1		T5	1
auto[3221225472:3355443199]	115	1			T2	1		T4	2		T13	1
auto[3355443200:3489660927]	109	1			T5	3		T109	1		T99	1
auto[3489660928:3623878655]	104	1			T14	1		T5	2		T20	1
auto[3623878656:3758096383]	106	1			T1	1		T2	1		T4	3
auto[3758096384:3892314111]	111	1			T1	1		T3	1		T4	1
auto[3892314112:4026531839]	78	1			T4	1		T5	2		T20	1
auto[4026531840:4160749567]	116	1			T4	1		T5	2		T56	1
auto[4160749568:4294967295]	105	1			T4	2		T22	1		T5	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	34	1			T4	1		T308	1		T124	1
auto[0:134217727]	auto[1]	51	1			T14	1		T177	1		T244	1
auto[134217728:268435455]	auto[0]	51	1			T4	1		T5	4		T56	1
auto[134217728:268435455]	auto[1]	51	1			T11	1		T5	1		T57	1
auto[268435456:402653183]	auto[0]	47	1			T13	1		T43	1		T172	1
auto[268435456:402653183]	auto[1]	62	1			T11	1		T14	1		T5	2
auto[402653184:536870911]	auto[0]	35	1			T22	1		T42	1		T43	1
auto[402653184:536870911]	auto[1]	55	1			T52	1		T44	1		T74	1
auto[536870912:671088639]	auto[0]	54	1			T3	1		T5	3		T56	1
auto[536870912:671088639]	auto[1]	70	1			T4	1		T22	1		T136	1
auto[671088640:805306367]	auto[0]	50	1			T2	1		T5	2		T59	1
auto[671088640:805306367]	auto[1]	43	1			T5	1		T56	1		T74	1
auto[805306368:939524095]	auto[0]	38	1			T20	1		T53	1		T281	1
auto[805306368:939524095]	auto[1]	55	1			T4	1		T5	1		T171	1
auto[939524096:1073741823]	auto[0]	55	1			T64	1		T74	1		T121	1
auto[939524096:1073741823]	auto[1]	54	1			T4	1		T5	2		T57	1
auto[1073741824:1207959551]	auto[0]	43	1			T20	1		T44	1		T6	1
auto[1073741824:1207959551]	auto[1]	52	1			T4	1		T22	1		T121	1
auto[1207959552:1342177279]	auto[0]	38	1			T111	1		T109	1		T53	1
auto[1207959552:1342177279]	auto[1]	58	1			T97	1		T112	1		T291	1
auto[1342177280:1476395007]	auto[0]	45	1			T4	1		T5	2		T59	1
auto[1342177280:1476395007]	auto[1]	52	1			T57	1		T63	1		T98	1
auto[1476395008:1610612735]	auto[0]	48	1			T4	1		T5	2		T111	1
auto[1476395008:1610612735]	auto[1]	44	1			T4	3		T11	1		T61	1
auto[1610612736:1744830463]	auto[0]	52	1			T4	1		T5	1		T56	1
auto[1610612736:1744830463]	auto[1]	54	1			T5	2		T121	1		T281	1
auto[1744830464:1879048191]	auto[0]	41	1			T5	1		T111	1		T6	1
auto[1744830464:1879048191]	auto[1]	61	1			T59	1		T52	1		T6	1
auto[1879048192:2013265919]	auto[0]	50	1			T4	1		T42	1		T43	1
auto[1879048192:2013265919]	auto[1]	41	1			T5	2		T6	1		T221	1
auto[2013265920:2147483647]	auto[0]	36	1			T56	1		T19	1		T74	1
auto[2013265920:2147483647]	auto[1]	48	1			T4	1		T19	1		T265	1
auto[2147483648:2281701375]	auto[0]	52	1			T1	1		T5	2		T20	1
auto[2147483648:2281701375]	auto[1]	53	1			T5	2		T62	1		T325	1
auto[2281701376:2415919103]	auto[0]	42	1			T11	1		T40	1		T41	1
auto[2281701376:2415919103]	auto[1]	54	1			T3	1		T11	1		T5	1
auto[2415919104:2550136831]	auto[0]	43	1			T3	1		T4	1		T5	1
auto[2415919104:2550136831]	auto[1]	62	1			T4	1		T22	1		T5	1
auto[2550136832:2684354559]	auto[0]	33	1			T5	2		T20	1		T42	1
auto[2550136832:2684354559]	auto[1]	63	1			T5	1		T140	1		T325	1
auto[2684354560:2818572287]	auto[0]	54	1			T4	1		T5	3		T64	1
auto[2684354560:2818572287]	auto[1]	57	1			T56	1		T98	1		T281	1
auto[2818572288:2952790015]	auto[0]	49	1			T5	3		T74	2		T6	1
auto[2818572288:2952790015]	auto[1]	70	1			T1	1		T14	1		T5	1
auto[2952790016:3087007743]	auto[0]	48	1			T4	1		T13	1		T5	2
auto[2952790016:3087007743]	auto[1]	61	1			T42	1		T241	1		T44	1
auto[3087007744:3221225471]	auto[0]	47	1			T22	1		T121	1		T43	1
auto[3087007744:3221225471]	auto[1]	62	1			T4	2		T5	1		T61	2
auto[3221225472:3355443199]	auto[0]	59	1			T4	2		T13	1		T111	1
auto[3221225472:3355443199]	auto[1]	56	1			T2	1		T30	1		T62	1
auto[3355443200:3489660927]	auto[0]	51	1			T5	2		T109	1		T121	1
auto[3355443200:3489660927]	auto[1]	58	1			T5	1		T99	1		T74	1
auto[3489660928:3623878655]	auto[0]	50	1			T5	1		T6	1		T112	1
auto[3489660928:3623878655]	auto[1]	54	1			T14	1		T5	1		T20	1
auto[3623878656:3758096383]	auto[0]	49	1			T1	1		T2	1		T11	1
auto[3623878656:3758096383]	auto[1]	57	1			T4	3		T13	1		T5	1
auto[3758096384:3892314111]	auto[0]	48	1			T1	1		T3	1		T5	1
auto[3758096384:3892314111]	auto[1]	63	1			T4	1		T136	1		T52	1
auto[3892314112:4026531839]	auto[0]	35	1			T20	1		T121	1		T43	1
auto[3892314112:4026531839]	auto[1]	43	1			T4	1		T5	2		T101	1
auto[4026531840:4160749567]	auto[0]	48	1			T4	1		T5	2		T59	1
auto[4026531840:4160749567]	auto[1]	68	1			T56	1		T60	1		T57	1
auto[4160749568:4294967295]	auto[0]	48	1			T5	1		T59	1		T62	1
auto[4160749568:4294967295]	auto[1]	57	1			T4	2		T22	1		T97	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1463

1

T1

4

T2

2

T3

3

auto[1]

1800

1

T2

1

T3

1

T4

19

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T4	1		T13	1		T5	1
auto[134217728:268435455]	115	1			T4	1		T11	1		T5	1
auto[268435456:402653183]	117	1			T4	1		T5	1		T136	1
auto[402653184:536870911]	108	1			T11	1		T5	2		T56	1
auto[536870912:671088639]	97	1			T4	1		T22	1		T5	4
auto[671088640:805306367]	106	1			T1	1		T4	1		T19	1
auto[805306368:939524095]	89	1			T14	1		T5	1		T20	1
auto[939524096:1073741823]	106	1			T3	1		T5	2		T62	1
auto[1073741824:1207959551]	90	1			T4	2		T13	1		T5	1
auto[1207959552:1342177279]	120	1			T4	1		T5	4		T59	1
auto[1342177280:1476395007]	93	1			T3	1		T5	4		T136	1
auto[1476395008:1610612735]	103	1			T1	1		T4	1		T5	3
auto[1610612736:1744830463]	96	1			T4	2		T11	1		T5	4
auto[1744830464:1879048191]	101	1			T4	1		T11	2		T19	1
auto[1879048192:2013265919]	105	1			T4	2		T13	1		T74	2
auto[2013265920:2147483647]	84	1			T22	1		T20	1		T111	1
auto[2147483648:2281701375]	121	1			T4	1		T22	1		T56	1
auto[2281701376:2415919103]	107	1			T4	2		T14	1		T5	2
auto[2415919104:2550136831]	97	1			T2	1		T5	3		T64	1
auto[2550136832:2684354559]	96	1			T4	3		T11	1		T325	1
auto[2684354560:2818572287]	96	1			T1	1		T4	1		T56	1
auto[2818572288:2952790015]	102	1			T22	1		T5	3		T20	1
auto[2952790016:3087007743]	92	1			T3	1		T5	2		T20	1
auto[3087007744:3221225471]	115	1			T1	1		T3	1		T4	3
auto[3221225472:3355443199]	91	1			T4	1		T22	1		T241	1
auto[3355443200:3489660927]	110	1			T2	2		T4	1		T22	1
auto[3489660928:3623878655]	113	1			T4	1		T5	4		T56	1
auto[3623878656:3758096383]	111	1			T4	1		T5	6		T111	1
auto[3758096384:3892314111]	94	1			T13	1		T64	1		T61	1
auto[3892314112:4026531839]	104	1			T4	1		T5	2		T42	1
auto[4026531840:4160749567]	100	1			T5	1		T56	1		T60	1
auto[4160749568:4294967295]	82	1			T4	1		T14	1		T5	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T13	1		T5	1		T56	1
auto[0:134217727]	auto[1]	55	1			T4	1		T241	1		T121	1
auto[134217728:268435455]	auto[0]	52	1			T4	1		T11	1		T109	1
auto[134217728:268435455]	auto[1]	63	1			T5	1		T52	1		T101	1
auto[268435456:402653183]	auto[0]	45	1			T5	1		T241	1		T99	1
auto[268435456:402653183]	auto[1]	72	1			T4	1		T136	1		T52	2
auto[402653184:536870911]	auto[0]	51	1			T11	1		T5	1		T56	1
auto[402653184:536870911]	auto[1]	57	1			T5	1		T98	1		T99	1
auto[536870912:671088639]	auto[0]	38	1			T5	2		T19	1		T109	1
auto[536870912:671088639]	auto[1]	59	1			T4	1		T22	1		T5	2
auto[671088640:805306367]	auto[0]	43	1			T1	1		T4	1		T127	1
auto[671088640:805306367]	auto[1]	63	1			T19	1		T57	1		T62	1
auto[805306368:939524095]	auto[0]	46	1			T20	1		T111	1		T6	1
auto[805306368:939524095]	auto[1]	43	1			T14	1		T5	1		T61	1
auto[939524096:1073741823]	auto[0]	50	1			T3	1		T5	1		T265	1
auto[939524096:1073741823]	auto[1]	56	1			T5	1		T62	1		T109	1
auto[1073741824:1207959551]	auto[0]	38	1			T13	1		T5	1		T59	1
auto[1073741824:1207959551]	auto[1]	52	1			T4	2		T30	1		T56	1
auto[1207959552:1342177279]	auto[0]	54	1			T5	3		T59	1		T62	1
auto[1207959552:1342177279]	auto[1]	66	1			T4	1		T5	1		T63	1
auto[1342177280:1476395007]	auto[0]	45	1			T3	1		T5	1		T171	1
auto[1342177280:1476395007]	auto[1]	48	1			T5	3		T136	1		T43	1
auto[1476395008:1610612735]	auto[0]	42	1			T1	1		T4	1		T5	1
auto[1476395008:1610612735]	auto[1]	61	1			T5	2		T57	1		T98	1
auto[1610612736:1744830463]	auto[0]	47	1			T11	1		T5	3		T20	1
auto[1610612736:1744830463]	auto[1]	49	1			T4	2		T5	1		T19	1
auto[1744830464:1879048191]	auto[0]	44	1			T4	1		T19	1		T64	1
auto[1744830464:1879048191]	auto[1]	57	1			T11	2		T99	1		T6	1
auto[1879048192:2013265919]	auto[0]	44	1			T4	1		T74	1		T124	1
auto[1879048192:2013265919]	auto[1]	61	1			T4	1		T13	1		T74	1
auto[2013265920:2147483647]	auto[0]	42	1			T20	1		T111	1		T42	1
auto[2013265920:2147483647]	auto[1]	42	1			T22	1		T74	1		T121	1
auto[2147483648:2281701375]	auto[0]	54	1			T22	1		T56	1		T6	1
auto[2147483648:2281701375]	auto[1]	67	1			T4	1		T17	1		T97	1
auto[2281701376:2415919103]	auto[0]	42	1			T4	1		T14	1		T27	1
auto[2281701376:2415919103]	auto[1]	65	1			T4	1		T5	2		T140	1
auto[2415919104:2550136831]	auto[0]	38	1			T2	1		T5	1		T64	1
auto[2415919104:2550136831]	auto[1]	59	1			T5	2		T57	1		T74	1
auto[2550136832:2684354559]	auto[0]	40	1			T4	2		T11	1		T124	2
auto[2550136832:2684354559]	auto[1]	56	1			T4	1		T325	1		T74	1
auto[2684354560:2818572287]	auto[0]	48	1			T1	1		T19	1		T59	1
auto[2684354560:2818572287]	auto[1]	48	1			T4	1		T56	1		T6	1
auto[2818572288:2952790015]	auto[0]	44	1			T5	2		T140	1		T42	1
auto[2818572288:2952790015]	auto[1]	58	1			T22	1		T5	1		T20	1
auto[2952790016:3087007743]	auto[0]	47	1			T20	1		T97	1		T98	1
auto[2952790016:3087007743]	auto[1]	45	1			T3	1		T5	2		T140	1
auto[3087007744:3221225471]	auto[0]	55	1			T1	1		T3	1		T4	1
auto[3087007744:3221225471]	auto[1]	60	1			T4	2		T14	1		T56	1
auto[3221225472:3355443199]	auto[0]	45	1			T4	1		T241	1		T121	1
auto[3221225472:3355443199]	auto[1]	46	1			T22	1		T223	1		T217	1
auto[3355443200:3489660927]	auto[0]	50	1			T2	1		T5	3		T57	1
auto[3355443200:3489660927]	auto[1]	60	1			T2	1		T4	1		T22	1
auto[3489660928:3623878655]	auto[0]	50	1			T5	3		T42	1		T44	1
auto[3489660928:3623878655]	auto[1]	63	1			T4	1		T5	1		T56	1
auto[3623878656:3758096383]	auto[0]	55	1			T5	5		T111	1		T42	1
auto[3623878656:3758096383]	auto[1]	56	1			T4	1		T5	1		T44	1
auto[3758096384:3892314111]	auto[0]	39	1			T13	1		T64	1		T6	1
auto[3758096384:3892314111]	auto[1]	55	1			T61	1		T127	1		T228	1
auto[3892314112:4026531839]	auto[0]	46	1			T4	1		T5	1		T42	1
auto[3892314112:4026531839]	auto[1]	58	1			T5	1		T97	1		T208	1
auto[4026531840:4160749567]	auto[0]	44	1			T5	1		T57	1		T53	1
auto[4026531840:4160749567]	auto[1]	56	1			T56	1		T60	1		T57	1
auto[4160749568:4294967295]	auto[0]	38	1			T14	1		T5	1		T194	1
auto[4160749568:4294967295]	auto[1]	44	1			T4	1		T5	1		T74	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1444

1

T1

3

T2

2

T3

3

auto[1]

1820

1

T1

1

T2

1

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	117	1			T5	2		T19	1		T97	1
auto[134217728:268435455]	101	1			T11	1		T13	1		T5	2
auto[268435456:402653183]	92	1			T42	1		T97	1		T44	1
auto[402653184:536870911]	92	1			T3	1		T4	2		T22	1
auto[536870912:671088639]	109	1			T5	1		T19	1		T112	1
auto[671088640:805306367]	94	1			T1	1		T4	3		T5	2
auto[805306368:939524095]	113	1			T3	1		T5	3		T64	1
auto[939524096:1073741823]	104	1			T4	2		T13	1		T5	4
auto[1073741824:1207959551]	90	1			T4	1		T61	1		T42	1
auto[1207959552:1342177279]	102	1			T1	2		T11	1		T14	1
auto[1342177280:1476395007]	98	1			T2	1		T4	1		T5	3
auto[1476395008:1610612735]	104	1			T14	2		T60	1		T325	1
auto[1610612736:1744830463]	115	1			T4	1		T5	3		T20	1
auto[1744830464:1879048191]	91	1			T14	1		T5	3		T57	1
auto[1879048192:2013265919]	100	1			T4	1		T5	1		T56	2
auto[2013265920:2147483647]	103	1			T4	1		T5	2		T20	1
auto[2147483648:2281701375]	93	1			T4	2		T22	1		T74	1
auto[2281701376:2415919103]	111	1			T2	1		T4	1		T5	2
auto[2415919104:2550136831]	93	1			T4	2		T11	1		T5	3
auto[2550136832:2684354559]	107	1			T136	2		T111	1		T59	1
auto[2684354560:2818572287]	103	1			T1	1		T4	1		T22	1
auto[2818572288:2952790015]	106	1			T4	2		T22	1		T5	2
auto[2952790016:3087007743]	99	1			T4	1		T11	1		T5	2
auto[3087007744:3221225471]	89	1			T4	1		T13	1		T56	1
auto[3221225472:3355443199]	103	1			T2	1		T4	2		T5	2
auto[3355443200:3489660927]	100	1			T4	1		T11	1		T5	5
auto[3489660928:3623878655]	107	1			T11	1		T5	1		T56	1
auto[3623878656:3758096383]	112	1			T3	2		T4	2		T5	3
auto[3758096384:3892314111]	112	1			T4	1		T13	1		T22	1
auto[3892314112:4026531839]	94	1			T5	3		T111	1		T59	1
auto[4026531840:4160749567]	101	1			T4	2		T59	1		T57	1
auto[4160749568:4294967295]	109	1			T22	1		T5	4		T19	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T5	1		T19	1		T44	1
auto[0:134217727]	auto[1]	64	1			T5	1		T97	1		T44	1
auto[134217728:268435455]	auto[0]	42	1			T13	1		T5	2		T136	1
auto[134217728:268435455]	auto[1]	59	1			T11	1		T56	1		T61	1
auto[268435456:402653183]	auto[0]	48	1			T42	1		T97	1		T74	1
auto[268435456:402653183]	auto[1]	44	1			T44	1		T74	1		T112	1
auto[402653184:536870911]	auto[0]	43	1			T3	1		T4	1		T22	1
auto[402653184:536870911]	auto[1]	49	1			T4	1		T5	1		T121	1
auto[536870912:671088639]	auto[0]	53	1			T112	1		T23	1		T253	1
auto[536870912:671088639]	auto[1]	56	1			T5	1		T19	1		T273	1
auto[671088640:805306367]	auto[0]	39	1			T1	1		T4	2		T5	1
auto[671088640:805306367]	auto[1]	55	1			T4	1		T5	1		T56	2
auto[805306368:939524095]	auto[0]	56	1			T3	1		T5	2		T64	1
auto[805306368:939524095]	auto[1]	57	1			T5	1		T171	1		T6	1
auto[939524096:1073741823]	auto[0]	47	1			T13	1		T5	1		T43	1
auto[939524096:1073741823]	auto[1]	57	1			T4	2		T5	3		T98	1
auto[1073741824:1207959551]	auto[0]	42	1			T42	1		T74	1		T43	2
auto[1073741824:1207959551]	auto[1]	48	1			T4	1		T61	1		T98	1
auto[1207959552:1342177279]	auto[0]	45	1			T1	2		T11	1		T64	1
auto[1207959552:1342177279]	auto[1]	57	1			T14	1		T5	1		T62	1
auto[1342177280:1476395007]	auto[0]	46	1			T5	1		T20	1		T42	1
auto[1342177280:1476395007]	auto[1]	52	1			T2	1		T4	1		T5	2
auto[1476395008:1610612735]	auto[0]	40	1			T14	1		T43	1		T172	2
auto[1476395008:1610612735]	auto[1]	64	1			T14	1		T60	1		T325	1
auto[1610612736:1744830463]	auto[0]	46	1			T5	1		T20	1		T109	1
auto[1610612736:1744830463]	auto[1]	69	1			T4	1		T5	2		T121	1
auto[1744830464:1879048191]	auto[0]	40	1			T5	2		T57	1		T42	1
auto[1744830464:1879048191]	auto[1]	51	1			T14	1		T5	1		T74	1
auto[1879048192:2013265919]	auto[0]	32	1			T5	1		T56	1		T20	1
auto[1879048192:2013265919]	auto[1]	68	1			T4	1		T56	1		T121	1
auto[2013265920:2147483647]	auto[0]	45	1			T5	2		T20	1		T53	1
auto[2013265920:2147483647]	auto[1]	58	1			T4	1		T52	1		T74	2
auto[2147483648:2281701375]	auto[0]	38	1			T74	1		T184	1		T83	1
auto[2147483648:2281701375]	auto[1]	55	1			T4	2		T22	1		T75	1
auto[2281701376:2415919103]	auto[0]	47	1			T2	1		T5	2		T99	1
auto[2281701376:2415919103]	auto[1]	64	1			T4	1		T57	1		T62	1
auto[2415919104:2550136831]	auto[0]	40	1			T5	2		T20	1		T325	1
auto[2415919104:2550136831]	auto[1]	53	1			T4	2		T11	1		T5	1
auto[2550136832:2684354559]	auto[0]	53	1			T136	1		T111	1		T59	1
auto[2550136832:2684354559]	auto[1]	54	1			T136	1		T273	1		T76	1
auto[2684354560:2818572287]	auto[0]	44	1			T4	1		T30	1		T27	1
auto[2684354560:2818572287]	auto[1]	59	1			T1	1		T22	1		T59	1
auto[2818572288:2952790015]	auto[0]	43	1			T4	2		T5	1		T56	1
auto[2818572288:2952790015]	auto[1]	63	1			T22	1		T5	1		T121	1
auto[2952790016:3087007743]	auto[0]	37	1			T5	1		T57	1		T241	1
auto[2952790016:3087007743]	auto[1]	62	1			T4	1		T11	1		T5	1
auto[3087007744:3221225471]	auto[0]	36	1			T4	1		T124	1		T84	2
auto[3087007744:3221225471]	auto[1]	53	1			T13	1		T56	1		T127	1
auto[3221225472:3355443199]	auto[0]	51	1			T2	1		T4	1		T5	2
auto[3221225472:3355443199]	auto[1]	52	1			T4	1		T20	1		T57	1
auto[3355443200:3489660927]	auto[0]	47	1			T5	4		T99	1		T43	1
auto[3355443200:3489660927]	auto[1]	53	1			T4	1		T11	1		T5	1
auto[3489660928:3623878655]	auto[0]	50	1			T11	1		T56	1		T111	1
auto[3489660928:3623878655]	auto[1]	57	1			T5	1		T19	1		T61	1
auto[3623878656:3758096383]	auto[0]	56	1			T3	1		T4	1		T5	2
auto[3623878656:3758096383]	auto[1]	56	1			T3	1		T4	1		T5	1
auto[3758096384:3892314111]	auto[0]	48	1			T13	1		T5	1		T59	1
auto[3758096384:3892314111]	auto[1]	64	1			T4	1		T22	1		T5	1
auto[3892314112:4026531839]	auto[0]	47	1			T111	1		T59	1		T74	1
auto[3892314112:4026531839]	auto[1]	47	1			T5	3		T57	1		T325	1
auto[4026531840:4160749567]	auto[0]	50	1			T4	2		T59	1		T57	1
auto[4026531840:4160749567]	auto[1]	51	1			T42	1		T101	2		T124	1
auto[4160749568:4294967295]	auto[0]	40	1			T5	3		T19	1		T74	1
auto[4160749568:4294967295]	auto[1]	69	1			T22	1		T5	1		T74	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1483

1

T1

3

T2

2

T3

2

auto[1]

1781

1

T1

1

T2

1

T3

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	92	1			T11	1		T42	1		T241	1
auto[134217728:268435455]	98	1			T5	5		T42	1		T127	1
auto[268435456:402653183]	93	1			T4	2		T5	2		T74	1
auto[402653184:536870911]	119	1			T11	1		T22	1		T5	3
auto[536870912:671088639]	114	1			T5	1		T64	1		T98	1
auto[671088640:805306367]	101	1			T4	1		T5	2		T59	1
auto[805306368:939524095]	109	1			T2	1		T4	1		T5	2
auto[939524096:1073741823]	101	1			T4	4		T13	1		T5	3
auto[1073741824:1207959551]	92	1			T1	1		T4	1		T5	3
auto[1207959552:1342177279]	118	1			T1	1		T2	1		T5	1
auto[1342177280:1476395007]	102	1			T22	1		T5	2		T56	1
auto[1476395008:1610612735]	97	1			T3	1		T111	1		T57	1
auto[1610612736:1744830463]	99	1			T4	2		T5	1		T56	2
auto[1744830464:1879048191]	100	1			T11	1		T5	1		T44	1
auto[1879048192:2013265919]	83	1			T4	1		T14	1		T22	1
auto[2013265920:2147483647]	111	1			T1	1		T3	1		T4	1
auto[2147483648:2281701375]	96	1			T14	1		T5	2		T140	1
auto[2281701376:2415919103]	117	1			T3	1		T4	3		T5	2
auto[2415919104:2550136831]	102	1			T4	1		T13	1		T14	1
auto[2550136832:2684354559]	105	1			T14	1		T111	1		T241	1
auto[2684354560:2818572287]	117	1			T5	4		T20	1		T121	1
auto[2818572288:2952790015]	110	1			T4	2		T22	1		T5	1
auto[2952790016:3087007743]	103	1			T11	2		T22	1		T5	2
auto[3087007744:3221225471]	73	1			T4	3		T5	1		T140	1
auto[3221225472:3355443199]	94	1			T4	1		T5	1		T136	1
auto[3355443200:3489660927]	112	1			T1	1		T4	2		T5	4
auto[3489660928:3623878655]	88	1			T2	1		T4	1		T42	1
auto[3623878656:3758096383]	99	1			T5	1		T56	1		T109	1
auto[3758096384:3892314111]	106	1			T4	1		T13	1		T5	3
auto[3892314112:4026531839]	95	1			T4	1		T13	1		T5	2
auto[4026531840:4160749567]	106	1			T22	1		T5	2		T56	1
auto[4160749568:4294967295]	112	1			T3	1		T4	2		T11	1