Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2902

1

T1

4

T2

3

T3

4

auto[1]

293

1

T3

14

T14

13

T62

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	112	1			T3	1		T5	2		T59	1
auto[134217728:268435455]	94	1			T1	1		T20	1		T62	1
auto[268435456:402653183]	107	1			T3	1		T4	2		T11	2
auto[402653184:536870911]	93	1			T2	1		T14	1		T5	1
auto[536870912:671088639]	90	1			T11	1		T5	2		T140	1
auto[671088640:805306367]	94	1			T3	1		T5	1		T59	1
auto[805306368:939524095]	86	1			T3	1		T4	1		T11	1
auto[939524096:1073741823]	96	1			T5	1		T241	1		T98	1
auto[1073741824:1207959551]	124	1			T13	2		T22	1		T19	1
auto[1207959552:1342177279]	109	1			T4	1		T14	1		T5	3
auto[1342177280:1476395007]	105	1			T14	1		T5	2		T20	1
auto[1476395008:1610612735]	96	1			T4	2		T14	1		T5	3
auto[1610612736:1744830463]	86	1			T5	2		T97	1		T74	1
auto[1744830464:1879048191]	106	1			T3	1		T5	2		T19	1
auto[1879048192:2013265919]	88	1			T14	2		T64	1		T325	1
auto[2013265920:2147483647]	92	1			T1	1		T4	1		T14	1
auto[2147483648:2281701375]	82	1			T4	3		T5	1		T43	1
auto[2281701376:2415919103]	111	1			T4	2		T11	1		T14	2
auto[2415919104:2550136831]	91	1			T3	2		T4	3		T59	1
auto[2550136832:2684354559]	112	1			T3	1		T4	2		T22	1
auto[2684354560:2818572287]	95	1			T2	1		T3	2		T5	1
auto[2818572288:2952790015]	106	1			T3	1		T4	1		T11	1
auto[2952790016:3087007743]	105	1			T3	1		T13	1		T14	1
auto[3087007744:3221225471]	82	1			T20	1		T64	1		T59	1
auto[3221225472:3355443199]	96	1			T1	1		T3	2		T4	2
auto[3355443200:3489660927]	95	1			T1	1		T4	1		T5	1
auto[3489660928:3623878655]	121	1			T3	3		T4	4		T5	3
auto[3623878656:3758096383]	99	1			T2	1		T59	1		T57	2
auto[3758096384:3892314111]	103	1			T4	1		T5	1		T56	1
auto[3892314112:4026531839]	108	1			T3	1		T4	1		T5	2
auto[4026531840:4160749567]	108	1			T14	1		T22	1		T19	1
auto[4160749568:4294967295]	103	1			T4	1		T5	4		T56	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	106	1			T5	2		T59	1		T109	1
auto[0:134217727]	auto[1]	6	1			T3	1		T249	1		T392	1
auto[134217728:268435455]	auto[0]	84	1			T1	1		T20	1		T62	1
auto[134217728:268435455]	auto[1]	10	1			T84	1		T394	1		T286	1
auto[268435456:402653183]	auto[0]	96	1			T4	2		T11	2		T14	1
auto[268435456:402653183]	auto[1]	11	1			T3	1		T14	3		T331	1
auto[402653184:536870911]	auto[0]	83	1			T2	1		T5	1		T241	1
auto[402653184:536870911]	auto[1]	10	1			T14	1		T397	1		T249	1
auto[536870912:671088639]	auto[0]	83	1			T11	1		T5	2		T140	1
auto[536870912:671088639]	auto[1]	7	1			T249	1		T354	1		T295	1
auto[671088640:805306367]	auto[0]	87	1			T5	1		T59	1		T57	1
auto[671088640:805306367]	auto[1]	7	1			T3	1		T340	1		T396	1
auto[805306368:939524095]	auto[0]	82	1			T3	1		T4	1		T11	1
auto[805306368:939524095]	auto[1]	4	1			T239	1		T286	1		T262	1
auto[939524096:1073741823]	auto[0]	88	1			T5	1		T241	1		T99	1
auto[939524096:1073741823]	auto[1]	8	1			T98	1		T88	1		T249	1
auto[1073741824:1207959551]	auto[0]	113	1			T13	2		T22	1		T19	1
auto[1073741824:1207959551]	auto[1]	11	1			T84	1		T88	1		T394	1
auto[1207959552:1342177279]	auto[0]	100	1			T4	1		T5	3		T20	1
auto[1207959552:1342177279]	auto[1]	9	1			T14	1		T397	1		T88	1
auto[1342177280:1476395007]	auto[0]	94	1			T5	2		T20	1		T17	1
auto[1342177280:1476395007]	auto[1]	11	1			T14	1		T394	1		T239	1
auto[1476395008:1610612735]	auto[0]	87	1			T4	2		T5	3		T20	1
auto[1476395008:1610612735]	auto[1]	9	1			T14	1		T394	1		T343	1
auto[1610612736:1744830463]	auto[0]	76	1			T5	2		T97	1		T74	1
auto[1610612736:1744830463]	auto[1]	10	1			T392	1		T239	1		T286	2
auto[1744830464:1879048191]	auto[0]	97	1			T5	2		T19	1		T57	1
auto[1744830464:1879048191]	auto[1]	9	1			T3	1		T62	1		T239	1
auto[1879048192:2013265919]	auto[0]	75	1			T14	1		T64	1		T325	1
auto[1879048192:2013265919]	auto[1]	13	1			T14	1		T84	1		T249	1
auto[2013265920:2147483647]	auto[0]	80	1			T1	1		T4	1		T22	1
auto[2013265920:2147483647]	auto[1]	12	1			T14	1		T98	1		T84	1
auto[2147483648:2281701375]	auto[0]	75	1			T4	3		T5	1		T43	1
auto[2147483648:2281701375]	auto[1]	7	1			T310	1		T323	1		T416	1
auto[2281701376:2415919103]	auto[0]	98	1			T4	2		T11	1		T14	1
auto[2281701376:2415919103]	auto[1]	13	1			T14	1		T98	1		T88	1
auto[2415919104:2550136831]	auto[0]	82	1			T4	3		T59	1		T74	1
auto[2415919104:2550136831]	auto[1]	9	1			T3	2		T84	1		T287	1
auto[2550136832:2684354559]	auto[0]	103	1			T4	2		T22	1		T5	2
auto[2550136832:2684354559]	auto[1]	9	1			T3	1		T397	1		T239	1
auto[2684354560:2818572287]	auto[0]	82	1			T2	1		T5	1		T56	1
auto[2684354560:2818572287]	auto[1]	13	1			T3	2		T82	1		T84	1
auto[2818572288:2952790015]	auto[0]	93	1			T4	1		T11	1		T5	1
auto[2818572288:2952790015]	auto[1]	13	1			T3	1		T14	2		T82	1
auto[2952790016:3087007743]	auto[0]	97	1			T13	1		T14	1		T5	1
auto[2952790016:3087007743]	auto[1]	8	1			T3	1		T397	1		T340	1
auto[3087007744:3221225471]	auto[0]	74	1			T20	1		T64	1		T59	1
auto[3087007744:3221225471]	auto[1]	8	1			T397	1		T249	1		T392	1
auto[3221225472:3355443199]	auto[0]	90	1			T1	1		T3	1		T4	2
auto[3221225472:3355443199]	auto[1]	6	1			T3	1		T392	1		T331	1
auto[3355443200:3489660927]	auto[0]	87	1			T1	1		T4	1		T5	1
auto[3355443200:3489660927]	auto[1]	8	1			T82	1		T249	1		T262	1
auto[3489660928:3623878655]	auto[0]	110	1			T3	2		T4	4		T5	3
auto[3489660928:3623878655]	auto[1]	11	1			T3	1		T84	1		T392	1
auto[3623878656:3758096383]	auto[0]	93	1			T2	1		T59	1		T57	2
auto[3623878656:3758096383]	auto[1]	6	1			T397	1		T88	1		T286	1
auto[3758096384:3892314111]	auto[0]	91	1			T4	1		T5	1		T56	1
auto[3758096384:3892314111]	auto[1]	12	1			T84	1		T249	1		T392	1
auto[3892314112:4026531839]	auto[0]	97	1			T4	1		T5	2		T61	1
auto[3892314112:4026531839]	auto[1]	11	1			T3	1		T98	1		T82	1
auto[4026531840:4160749567]	auto[0]	100	1			T22	1		T19	1		T98	1
auto[4026531840:4160749567]	auto[1]	8	1			T14	1		T249	1		T262	1
auto[4160749568:4294967295]	auto[0]	99	1			T4	1		T5	4		T56	1
auto[4160749568:4294967295]	auto[1]	4	1			T397	1		T421	1		T368	2