Unified Coverage Report :: Group Instance : sealing_sw_binding_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1470

1

T1

3

T2

2

T3

3

auto[1]

1793

1

T1

1

T2

1

T3

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T5	4		T56	1		T59	1
auto[134217728:268435455]	101	1			T5	1		T20	1		T64	1
auto[268435456:402653183]	108	1			T4	2		T11	1		T5	1
auto[402653184:536870911]	109	1			T4	1		T22	2		T5	2
auto[536870912:671088639]	114	1			T11	1		T14	1		T5	3
auto[671088640:805306367]	91	1			T1	2		T14	1		T5	1
auto[805306368:939524095]	95	1			T4	1		T11	1		T5	1
auto[939524096:1073741823]	92	1			T5	1		T30	1		T109	1
auto[1073741824:1207959551]	98	1			T11	1		T5	1		T56	1
auto[1207959552:1342177279]	86	1			T11	1		T5	1		T140	1
auto[1342177280:1476395007]	94	1			T4	2		T13	1		T5	2
auto[1476395008:1610612735]	96	1			T4	2		T5	3		T56	1
auto[1610612736:1744830463]	98	1			T3	1		T4	2		T5	5
auto[1744830464:1879048191]	114	1			T2	1		T5	2		T20	1
auto[1879048192:2013265919]	98	1			T57	1		T109	1		T74	2
auto[2013265920:2147483647]	107	1			T4	2		T5	1		T56	1
auto[2147483648:2281701375]	99	1			T2	1		T4	4		T5	1
auto[2281701376:2415919103]	109	1			T1	1		T5	2		T64	1
auto[2415919104:2550136831]	115	1			T4	2		T13	1		T14	1
auto[2550136832:2684354559]	87	1			T4	1		T13	1		T5	4
auto[2684354560:2818572287]	87	1			T1	1		T4	2		T5	2
auto[2818572288:2952790015]	113	1			T4	1		T11	1		T62	1
auto[2952790016:3087007743]	97	1			T4	1		T5	1		T111	1
auto[3087007744:3221225471]	102	1			T4	2		T14	1		T5	2
auto[3221225472:3355443199]	110	1			T4	1		T22	1		T5	4
auto[3355443200:3489660927]	108	1			T2	1		T3	1		T22	1
auto[3489660928:3623878655]	109	1			T13	1		T5	3		T19	2
auto[3623878656:3758096383]	101	1			T5	3		T111	1		T61	1
auto[3758096384:3892314111]	105	1			T4	1		T22	1		T56	1
auto[3892314112:4026531839]	97	1			T3	1		T22	1		T5	3
auto[4026531840:4160749567]	115	1			T3	1		T4	2		T5	1
auto[4160749568:4294967295]	102	1			T4	1		T5	1		T62	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T5	3		T59	1		T42	1
auto[0:134217727]	auto[1]	59	1			T5	1		T56	1		T63	1
auto[134217728:268435455]	auto[0]	52	1			T64	1		T109	1		T43	1
auto[134217728:268435455]	auto[1]	49	1			T5	1		T20	1		T44	1
auto[268435456:402653183]	auto[0]	46	1			T11	1		T5	1		T127	1
auto[268435456:402653183]	auto[1]	62	1			T4	2		T325	1		T44	1
auto[402653184:536870911]	auto[0]	52	1			T22	1		T5	2		T20	1
auto[402653184:536870911]	auto[1]	57	1			T4	1		T22	1		T62	1
auto[536870912:671088639]	auto[0]	52	1			T20	1		T325	1		T43	2
auto[536870912:671088639]	auto[1]	62	1			T11	1		T14	1		T5	3
auto[671088640:805306367]	auto[0]	36	1			T1	2		T325	1		T428	1
auto[671088640:805306367]	auto[1]	55	1			T14	1		T5	1		T44	1
auto[805306368:939524095]	auto[0]	37	1			T11	1		T5	1		T42	1
auto[805306368:939524095]	auto[1]	58	1			T4	1		T99	1		T43	1
auto[939524096:1073741823]	auto[0]	43	1			T30	1		T121	1		T228	1
auto[939524096:1073741823]	auto[1]	49	1			T5	1		T109	1		T74	1
auto[1073741824:1207959551]	auto[0]	50	1			T56	1		T140	1		T42	1
auto[1073741824:1207959551]	auto[1]	48	1			T11	1		T5	1		T59	1
auto[1207959552:1342177279]	auto[0]	38	1			T11	1		T98	1		T224	1
auto[1207959552:1342177279]	auto[1]	48	1			T5	1		T140	1		T121	1
auto[1342177280:1476395007]	auto[0]	49	1			T4	1		T13	1		T5	2
auto[1342177280:1476395007]	auto[1]	45	1			T4	1		T223	1		T177	1
auto[1476395008:1610612735]	auto[0]	41	1			T5	3		T59	1		T99	1
auto[1476395008:1610612735]	auto[1]	55	1			T4	2		T56	1		T97	1
auto[1610612736:1744830463]	auto[0]	47	1			T5	3		T172	1		T112	1
auto[1610612736:1744830463]	auto[1]	51	1			T3	1		T4	2		T5	2
auto[1744830464:1879048191]	auto[0]	54	1			T5	1		T20	1		T42	1
auto[1744830464:1879048191]	auto[1]	60	1			T2	1		T5	1		T97	2
auto[1879048192:2013265919]	auto[0]	47	1			T57	1		T109	1		T74	1
auto[1879048192:2013265919]	auto[1]	51	1			T74	1		T6	1		T225	1
auto[2013265920:2147483647]	auto[0]	46	1			T111	1		T112	1		T53	1
auto[2013265920:2147483647]	auto[1]	61	1			T4	2		T5	1		T56	1
auto[2147483648:2281701375]	auto[0]	47	1			T2	1		T4	3		T64	1
auto[2147483648:2281701375]	auto[1]	52	1			T4	1		T5	1		T98	1
auto[2281701376:2415919103]	auto[0]	37	1			T1	1		T5	1		T64	1
auto[2281701376:2415919103]	auto[1]	72	1			T5	1		T97	1		T44	1
auto[2415919104:2550136831]	auto[0]	52	1			T13	1		T5	1		T59	1
auto[2415919104:2550136831]	auto[1]	63	1			T4	2		T14	1		T5	1
auto[2550136832:2684354559]	auto[0]	42	1			T4	1		T13	1		T5	4
auto[2550136832:2684354559]	auto[1]	45	1			T217	1		T41	1		T115	1
auto[2684354560:2818572287]	auto[0]	34	1			T4	1		T5	1		T57	1
auto[2684354560:2818572287]	auto[1]	53	1			T1	1		T4	1		T5	1
auto[2818572288:2952790015]	auto[0]	47	1			T4	1		T62	1		T44	1
auto[2818572288:2952790015]	auto[1]	66	1			T11	1		T52	1		T121	1
auto[2952790016:3087007743]	auto[0]	49	1			T4	1		T111	1		T43	2
auto[2952790016:3087007743]	auto[1]	48	1			T5	1		T57	1		T308	1
auto[3087007744:3221225471]	auto[0]	44	1			T4	1		T5	1		T56	1
auto[3087007744:3221225471]	auto[1]	58	1			T4	1		T14	1		T5	1
auto[3221225472:3355443199]	auto[0]	47	1			T5	2		T59	1		T124	1
auto[3221225472:3355443199]	auto[1]	63	1			T4	1		T22	1		T5	2
auto[3355443200:3489660927]	auto[0]	47	1			T2	1		T3	1		T5	1
auto[3355443200:3489660927]	auto[1]	61	1			T22	1		T20	1		T140	1
auto[3489660928:3623878655]	auto[0]	44	1			T5	1		T19	2		T98	1
auto[3489660928:3623878655]	auto[1]	65	1			T13	1		T5	2		T171	1
auto[3623878656:3758096383]	auto[0]	45	1			T5	3		T111	1		T241	1
auto[3623878656:3758096383]	auto[1]	56	1			T61	1		T98	2		T101	2
auto[3758096384:3892314111]	auto[0]	45	1			T111	1		T121	1		T112	1
auto[3758096384:3892314111]	auto[1]	60	1			T4	1		T22	1		T56	1
auto[3892314112:4026531839]	auto[0]	43	1			T3	1		T5	2		T42	1
auto[3892314112:4026531839]	auto[1]	54	1			T22	1		T5	1		T57	1
auto[4026531840:4160749567]	auto[0]	61	1			T3	1		T4	1		T5	1
auto[4026531840:4160749567]	auto[1]	54	1			T4	1		T74	2		T121	1
auto[4160749568:4294967295]	auto[0]	49	1			T42	1		T74	1		T172	1
auto[4160749568:4294967295]	auto[1]	53	1			T4	1		T5	1		T62	1