Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4478

1

T1

8

T2

6

T4

42

auto[1]

2046

1

T3

8

T4

18

T11

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	216	1			T4	6		T5	2		T136	2
auto[134217728:268435455]	274	1			T4	2		T11	2		T5	2
auto[268435456:402653183]	198	1			T3	2		T5	6		T111	2
auto[402653184:536870911]	170	1			T5	8		T56	2		T52	2
auto[536870912:671088639]	192	1			T11	4		T14	2		T5	6
auto[671088640:805306367]	178	1			T13	2		T22	2		T5	2
auto[805306368:939524095]	194	1			T3	2		T4	2		T5	4
auto[939524096:1073741823]	200	1			T4	2		T14	2		T22	2
auto[1073741824:1207959551]	230	1			T4	4		T5	6		T56	2
auto[1207959552:1342177279]	172	1			T4	2		T172	2		T257	2
auto[1342177280:1476395007]	172	1			T2	2		T4	6		T5	2
auto[1476395008:1610612735]	186	1			T5	2		T20	2		T171	2
auto[1610612736:1744830463]	180	1			T4	2		T5	6		T30	2
auto[1744830464:1879048191]	196	1			T1	2		T2	2		T4	2
auto[1879048192:2013265919]	214	1			T1	2		T3	2		T4	4
auto[2013265920:2147483647]	208	1			T22	2		T5	8		T59	2
auto[2147483648:2281701375]	202	1			T5	4		T19	2		T62	2
auto[2281701376:2415919103]	266	1			T4	2		T13	2		T22	4
auto[2415919104:2550136831]	202	1			T3	2		T4	2		T5	2
auto[2550136832:2684354559]	226	1			T2	2		T4	2		T5	2
auto[2684354560:2818572287]	190	1			T20	2		T111	2		T57	2
auto[2818572288:2952790015]	238	1			T4	4		T11	2		T14	2
auto[2952790016:3087007743]	218	1			T5	2		T97	2		T98	2
auto[3087007744:3221225471]	216	1			T1	2		T5	4		T56	2
auto[3221225472:3355443199]	186	1			T5	2		T56	2		T140	2
auto[3355443200:3489660927]	174	1			T4	4		T13	2		T5	4
auto[3489660928:3623878655]	230	1			T1	2		T4	2		T5	2
auto[3623878656:3758096383]	180	1			T5	4		T64	2		T57	2
auto[3758096384:3892314111]	214	1			T4	6		T11	2		T5	4
auto[3892314112:4026531839]	200	1			T11	2		T5	2		T62	2
auto[4026531840:4160749567]	192	1			T4	2		T14	2		T5	4
auto[4160749568:4294967295]	210	1			T4	4		T5	2		T56	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	142	1			T4	6		T5	2		T136	2
auto[0:134217727]	auto[1]	74	1			T111	2		T74	2		T6	6
auto[134217728:268435455]	auto[0]	200	1			T4	2		T11	2		T5	2
auto[134217728:268435455]	auto[1]	74	1			T136	2		T98	2		T23	2
auto[268435456:402653183]	auto[0]	150	1			T5	4		T61	2		T97	2
auto[268435456:402653183]	auto[1]	48	1			T3	2		T5	2		T111	2
auto[402653184:536870911]	auto[0]	130	1			T5	8		T56	2		T124	2
auto[402653184:536870911]	auto[1]	40	1			T52	2		T124	4		T293	2
auto[536870912:671088639]	auto[0]	128	1			T5	6		T171	2		T253	2
auto[536870912:671088639]	auto[1]	64	1			T11	4		T14	2		T121	2
auto[671088640:805306367]	auto[0]	122	1			T22	2		T184	2		T198	2
auto[671088640:805306367]	auto[1]	56	1			T13	2		T5	2		T325	2
auto[805306368:939524095]	auto[0]	126	1			T5	4		T99	2		T43	2
auto[805306368:939524095]	auto[1]	68	1			T3	2		T4	2		T19	2
auto[939524096:1073741823]	auto[0]	142	1			T14	2		T5	2		T74	2
auto[939524096:1073741823]	auto[1]	58	1			T4	2		T22	2		T5	2
auto[1073741824:1207959551]	auto[0]	150	1			T4	2		T5	4		T57	2
auto[1073741824:1207959551]	auto[1]	80	1			T4	2		T5	2		T56	2
auto[1207959552:1342177279]	auto[0]	110	1			T172	2		T112	2		T223	2
auto[1207959552:1342177279]	auto[1]	62	1			T4	2		T257	2		T39	2
auto[1342177280:1476395007]	auto[0]	120	1			T2	2		T4	2		T5	2
auto[1342177280:1476395007]	auto[1]	52	1			T4	4		T98	2		T121	2
auto[1476395008:1610612735]	auto[0]	132	1			T5	2		T20	2		T172	2
auto[1476395008:1610612735]	auto[1]	54	1			T171	2		T284	2		T417	2
auto[1610612736:1744830463]	auto[0]	126	1			T4	2		T5	4		T30	2
auto[1610612736:1744830463]	auto[1]	54	1			T5	2		T57	2		T127	2
auto[1744830464:1879048191]	auto[0]	128	1			T1	2		T2	2		T4	2
auto[1744830464:1879048191]	auto[1]	68	1			T19	2		T121	2		T43	2
auto[1879048192:2013265919]	auto[0]	166	1			T1	2		T4	4		T5	12
auto[1879048192:2013265919]	auto[1]	48	1			T3	2		T257	2		T194	2
auto[2013265920:2147483647]	auto[0]	134	1			T22	2		T5	2		T59	2
auto[2013265920:2147483647]	auto[1]	74	1			T5	6		T60	2		T63	2
auto[2147483648:2281701375]	auto[0]	156	1			T5	4		T19	2		T62	2
auto[2147483648:2281701375]	auto[1]	46	1			T44	2		T121	2		T6	2
auto[2281701376:2415919103]	auto[0]	180	1			T22	2		T5	6		T42	2
auto[2281701376:2415919103]	auto[1]	86	1			T4	2		T13	2		T22	2
auto[2415919104:2550136831]	auto[0]	126	1			T4	2		T5	2		T57	2
auto[2415919104:2550136831]	auto[1]	76	1			T3	2		T111	2		T177	2
auto[2550136832:2684354559]	auto[0]	156	1			T2	2		T4	2		T5	2
auto[2550136832:2684354559]	auto[1]	70	1			T64	2		T121	2		T217	2
auto[2684354560:2818572287]	auto[0]	118	1			T20	2		T111	2		T109	2
auto[2684354560:2818572287]	auto[1]	72	1			T57	2		T62	2		T241	2
auto[2818572288:2952790015]	auto[0]	168	1			T4	2		T22	2		T19	2
auto[2818572288:2952790015]	auto[1]	70	1			T4	2		T11	2		T14	2
auto[2952790016:3087007743]	auto[0]	158	1			T5	2		T98	2		T175	2
auto[2952790016:3087007743]	auto[1]	60	1			T97	2		T74	2		T75	2
auto[3087007744:3221225471]	auto[0]	144	1			T1	2		T56	2		T325	2
auto[3087007744:3221225471]	auto[1]	72	1			T5	4		T59	2		T52	2
auto[3221225472:3355443199]	auto[0]	124	1			T140	2		T241	2		T101	2
auto[3221225472:3355443199]	auto[1]	62	1			T5	2		T56	2		T325	2
auto[3355443200:3489660927]	auto[0]	110	1			T4	4		T13	2		T5	4
auto[3355443200:3489660927]	auto[1]	64	1			T17	2		T74	2		T177	2
auto[3489660928:3623878655]	auto[0]	164	1			T1	2		T4	2		T5	2
auto[3489660928:3623878655]	auto[1]	66	1			T74	2		T121	2		T217	2
auto[3623878656:3758096383]	auto[0]	128	1			T5	4		T98	2		T171	2
auto[3623878656:3758096383]	auto[1]	52	1			T64	2		T57	2		T296	2
auto[3758096384:3892314111]	auto[0]	144	1			T4	6		T11	2		T5	4
auto[3758096384:3892314111]	auto[1]	70	1			T59	2		T42	2		T241	2
auto[3892314112:4026531839]	auto[0]	124	1			T5	2		T62	2		T109	2
auto[3892314112:4026531839]	auto[1]	76	1			T11	2		T42	2		T325	2
auto[4026531840:4160749567]	auto[0]	134	1			T4	2		T5	2		T99	2
auto[4026531840:4160749567]	auto[1]	58	1			T14	2		T5	2		T43	2
auto[4160749568:4294967295]	auto[0]	138	1			T4	2		T5	2		T140	2
auto[4160749568:4294967295]	auto[1]	72	1			T4	2		T56	2		T57	2