Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.78 99.04 97.91 98.66 100.00 99.02 98.63 91.22


Total test records in report: 1084
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T1009 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.679895589 Aug 19 04:29:20 PM PDT 24 Aug 19 04:29:23 PM PDT 24 274665255 ps
T1010 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.952649489 Aug 19 04:29:15 PM PDT 24 Aug 19 04:29:16 PM PDT 24 90995980 ps
T1011 /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3214322990 Aug 19 04:29:25 PM PDT 24 Aug 19 04:29:26 PM PDT 24 43107893 ps
T1012 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.636929285 Aug 19 04:29:28 PM PDT 24 Aug 19 04:29:31 PM PDT 24 101622303 ps
T1013 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1853495189 Aug 19 04:29:12 PM PDT 24 Aug 19 04:29:14 PM PDT 24 175940772 ps
T1014 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.956963456 Aug 19 04:29:02 PM PDT 24 Aug 19 04:29:13 PM PDT 24 98673581 ps
T1015 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2027699356 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:31 PM PDT 24 17094185 ps
T1016 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3843725811 Aug 19 04:28:41 PM PDT 24 Aug 19 04:28:56 PM PDT 24 577152383 ps
T1017 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3280303767 Aug 19 04:29:02 PM PDT 24 Aug 19 04:29:05 PM PDT 24 75609395 ps
T1018 /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.295000616 Aug 19 04:28:58 PM PDT 24 Aug 19 04:28:59 PM PDT 24 32370801 ps
T1019 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3214807744 Aug 19 04:29:23 PM PDT 24 Aug 19 04:29:23 PM PDT 24 50460388 ps
T1020 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4053843640 Aug 19 04:29:00 PM PDT 24 Aug 19 04:29:03 PM PDT 24 257467588 ps
T1021 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3719985425 Aug 19 04:28:58 PM PDT 24 Aug 19 04:29:00 PM PDT 24 94513218 ps
T1022 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2022637103 Aug 19 04:29:07 PM PDT 24 Aug 19 04:29:09 PM PDT 24 94987978 ps
T1023 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1520481292 Aug 19 04:29:06 PM PDT 24 Aug 19 04:29:10 PM PDT 24 169156418 ps
T1024 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.405256899 Aug 19 04:28:49 PM PDT 24 Aug 19 04:28:51 PM PDT 24 26226329 ps
T1025 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3484089889 Aug 19 04:29:16 PM PDT 24 Aug 19 04:29:17 PM PDT 24 48443375 ps
T1026 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3410403226 Aug 19 04:29:24 PM PDT 24 Aug 19 04:29:25 PM PDT 24 29258810 ps
T152 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.999428131 Aug 19 04:29:03 PM PDT 24 Aug 19 04:29:06 PM PDT 24 64428708 ps
T1027 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2394816829 Aug 19 04:29:17 PM PDT 24 Aug 19 04:29:23 PM PDT 24 13263617 ps
T1028 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3864489349 Aug 19 04:29:11 PM PDT 24 Aug 19 04:29:12 PM PDT 24 46224849 ps
T1029 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1381360116 Aug 19 04:29:14 PM PDT 24 Aug 19 04:29:16 PM PDT 24 17868270 ps
T1030 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2620196973 Aug 19 04:28:50 PM PDT 24 Aug 19 04:28:51 PM PDT 24 139841792 ps
T1031 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1331494570 Aug 19 04:29:31 PM PDT 24 Aug 19 04:29:33 PM PDT 24 273889800 ps
T1032 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3649281658 Aug 19 04:29:23 PM PDT 24 Aug 19 04:29:24 PM PDT 24 31221366 ps
T1033 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3457885169 Aug 19 04:29:32 PM PDT 24 Aug 19 04:29:34 PM PDT 24 80376224 ps
T1034 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3981122839 Aug 19 04:29:01 PM PDT 24 Aug 19 04:29:03 PM PDT 24 62725880 ps
T147 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.967463094 Aug 19 04:28:50 PM PDT 24 Aug 19 04:28:54 PM PDT 24 126099951 ps
T1035 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1069398124 Aug 19 04:28:47 PM PDT 24 Aug 19 04:28:48 PM PDT 24 112432612 ps
T148 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2293945314 Aug 19 04:28:57 PM PDT 24 Aug 19 04:29:02 PM PDT 24 237823462 ps
T1036 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2812085510 Aug 19 04:29:05 PM PDT 24 Aug 19 04:29:06 PM PDT 24 42820316 ps
T151 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.238198033 Aug 19 04:28:42 PM PDT 24 Aug 19 04:28:50 PM PDT 24 840857712 ps
T1037 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2849729363 Aug 19 04:28:48 PM PDT 24 Aug 19 04:28:52 PM PDT 24 122005855 ps
T1038 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.695965484 Aug 19 04:28:50 PM PDT 24 Aug 19 04:28:52 PM PDT 24 81352992 ps
T1039 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2888843092 Aug 19 04:28:51 PM PDT 24 Aug 19 04:28:53 PM PDT 24 28208016 ps
T1040 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.506377117 Aug 19 04:28:58 PM PDT 24 Aug 19 04:28:59 PM PDT 24 31681628 ps
T155 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3109267968 Aug 19 04:28:42 PM PDT 24 Aug 19 04:28:52 PM PDT 24 276858061 ps
T1041 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3977706572 Aug 19 04:28:51 PM PDT 24 Aug 19 04:28:53 PM PDT 24 10263028 ps
T1042 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.4004184748 Aug 19 04:29:02 PM PDT 24 Aug 19 04:29:07 PM PDT 24 1160677753 ps
T1043 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.58053235 Aug 19 04:29:21 PM PDT 24 Aug 19 04:29:22 PM PDT 24 22329006 ps
T1044 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3754456196 Aug 19 04:29:29 PM PDT 24 Aug 19 04:29:29 PM PDT 24 49440037 ps
T1045 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.4113589833 Aug 19 04:29:26 PM PDT 24 Aug 19 04:29:26 PM PDT 24 35952325 ps
T1046 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.297684263 Aug 19 04:28:57 PM PDT 24 Aug 19 04:28:59 PM PDT 24 34464038 ps
T1047 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2848138741 Aug 19 04:29:30 PM PDT 24 Aug 19 04:29:33 PM PDT 24 35782745 ps
T1048 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1590282047 Aug 19 04:29:03 PM PDT 24 Aug 19 04:29:04 PM PDT 24 8977359 ps
T1049 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2290098590 Aug 19 04:28:59 PM PDT 24 Aug 19 04:29:01 PM PDT 24 35104127 ps
T1050 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2839325108 Aug 19 04:29:03 PM PDT 24 Aug 19 04:29:05 PM PDT 24 318979933 ps
T1051 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1709679949 Aug 19 04:29:27 PM PDT 24 Aug 19 04:29:28 PM PDT 24 69796122 ps
T1052 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.641096324 Aug 19 04:29:01 PM PDT 24 Aug 19 04:29:02 PM PDT 24 42781428 ps
T1053 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.4120249697 Aug 19 04:28:49 PM PDT 24 Aug 19 04:28:52 PM PDT 24 301544223 ps
T150 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.206399851 Aug 19 04:28:59 PM PDT 24 Aug 19 04:29:03 PM PDT 24 92018955 ps
T145 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3898332329 Aug 19 04:29:22 PM PDT 24 Aug 19 04:29:27 PM PDT 24 452479354 ps
T1054 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2196740431 Aug 19 04:29:03 PM PDT 24 Aug 19 04:29:05 PM PDT 24 213782247 ps
T1055 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2900751572 Aug 19 04:29:06 PM PDT 24 Aug 19 04:29:07 PM PDT 24 12098847 ps
T1056 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2337760315 Aug 19 04:28:50 PM PDT 24 Aug 19 04:28:54 PM PDT 24 186575961 ps
T1057 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3871787294 Aug 19 04:29:00 PM PDT 24 Aug 19 04:29:02 PM PDT 24 34769062 ps
T1058 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3221548064 Aug 19 04:29:13 PM PDT 24 Aug 19 04:29:14 PM PDT 24 20965643 ps
T1059 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.691441708 Aug 19 04:28:52 PM PDT 24 Aug 19 04:28:53 PM PDT 24 18717084 ps
T1060 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1949616938 Aug 19 04:29:08 PM PDT 24 Aug 19 04:29:09 PM PDT 24 51765703 ps
T1061 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2064751004 Aug 19 04:29:02 PM PDT 24 Aug 19 04:29:05 PM PDT 24 98641749 ps
T1062 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3423307341 Aug 19 04:28:56 PM PDT 24 Aug 19 04:29:03 PM PDT 24 858272345 ps
T1063 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3547703049 Aug 19 04:29:11 PM PDT 24 Aug 19 04:29:12 PM PDT 24 65113185 ps
T1064 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3311531447 Aug 19 04:28:58 PM PDT 24 Aug 19 04:29:10 PM PDT 24 542154474 ps
T1065 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.816756723 Aug 19 04:28:48 PM PDT 24 Aug 19 04:28:56 PM PDT 24 510940090 ps
T1066 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1320123763 Aug 19 04:29:19 PM PDT 24 Aug 19 04:29:21 PM PDT 24 19245934 ps
T1067 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3909295220 Aug 19 04:29:20 PM PDT 24 Aug 19 04:29:21 PM PDT 24 25938438 ps
T159 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2373236159 Aug 19 04:28:49 PM PDT 24 Aug 19 04:28:52 PM PDT 24 99086913 ps
T1068 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2309787008 Aug 19 04:29:12 PM PDT 24 Aug 19 04:29:19 PM PDT 24 271046255 ps
T1069 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4195904827 Aug 19 04:29:03 PM PDT 24 Aug 19 04:29:05 PM PDT 24 108305216 ps
T1070 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3916538164 Aug 19 04:28:43 PM PDT 24 Aug 19 04:28:44 PM PDT 24 34584027 ps
T1071 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.609797686 Aug 19 04:29:02 PM PDT 24 Aug 19 04:29:03 PM PDT 24 19745487 ps
T1072 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.803777090 Aug 19 04:29:03 PM PDT 24 Aug 19 04:29:08 PM PDT 24 112735720 ps
T1073 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1814926806 Aug 19 04:29:06 PM PDT 24 Aug 19 04:29:07 PM PDT 24 49116872 ps
T1074 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1382961575 Aug 19 04:29:03 PM PDT 24 Aug 19 04:29:04 PM PDT 24 7294791 ps
T1075 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1228490936 Aug 19 04:29:11 PM PDT 24 Aug 19 04:29:15 PM PDT 24 604352972 ps
T1076 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.183711022 Aug 19 04:28:48 PM PDT 24 Aug 19 04:28:48 PM PDT 24 45529661 ps
T1077 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2803274102 Aug 19 04:28:50 PM PDT 24 Aug 19 04:28:51 PM PDT 24 62730086 ps
T1078 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4258679209 Aug 19 04:29:08 PM PDT 24 Aug 19 04:29:11 PM PDT 24 216954417 ps
T1079 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4215887477 Aug 19 04:28:49 PM PDT 24 Aug 19 04:28:52 PM PDT 24 175352273 ps
T1080 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2903086458 Aug 19 04:29:15 PM PDT 24 Aug 19 04:29:17 PM PDT 24 56570891 ps
T1081 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2456996690 Aug 19 04:29:04 PM PDT 24 Aug 19 04:29:05 PM PDT 24 25323346 ps
T1082 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2666419950 Aug 19 04:29:10 PM PDT 24 Aug 19 04:29:11 PM PDT 24 15128659 ps
T1083 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3661086065 Aug 19 04:29:25 PM PDT 24 Aug 19 04:29:31 PM PDT 24 688422873 ps
T1084 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3930601025 Aug 19 04:29:11 PM PDT 24 Aug 19 04:29:13 PM PDT 24 62673835 ps

Test location /workspace/coverage/default/42.keymgr_stress_all.3395052959
Short name T4
Test name
Test status
Simulation time 2237536770 ps
CPU time 31.54 seconds
Started Aug 19 05:42:13 PM PDT 24
Finished Aug 19 05:42:45 PM PDT 24
Peak memory 221332 kb
Host smart-43d92ff7-8c67-45bd-b626-02ebadcdc787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395052959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3395052959
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3986340463
Short name T5
Test name
Test status
Simulation time 11777297871 ps
CPU time 79.17 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:41:32 PM PDT 24
Peak memory 215976 kb
Host smart-4b7d45b7-f353-408e-8c66-bf4eb0f5ef3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986340463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3986340463
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2099137476
Short name T74
Test name
Test status
Simulation time 872597238 ps
CPU time 17.83 seconds
Started Aug 19 05:41:02 PM PDT 24
Finished Aug 19 05:41:20 PM PDT 24
Peak memory 223068 kb
Host smart-89390be2-5413-494d-8e28-641184218a69
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099137476 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2099137476
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2235772569
Short name T8
Test name
Test status
Simulation time 1505147950 ps
CPU time 10.13 seconds
Started Aug 19 05:40:02 PM PDT 24
Finished Aug 19 05:40:12 PM PDT 24
Peak memory 234984 kb
Host smart-8e89f71e-632f-4664-8169-6e0edeab9b8b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235772569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2235772569
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3492915081
Short name T119
Test name
Test status
Simulation time 2787553554 ps
CPU time 38.23 seconds
Started Aug 19 05:40:46 PM PDT 24
Finished Aug 19 05:41:24 PM PDT 24
Peak memory 217116 kb
Host smart-2dc259e7-ed9f-432f-96e3-8f7fa149dbc1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492915081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3492915081
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1314630785
Short name T3
Test name
Test status
Simulation time 2827843861 ps
CPU time 29.73 seconds
Started Aug 19 05:42:13 PM PDT 24
Finished Aug 19 05:42:43 PM PDT 24
Peak memory 214876 kb
Host smart-2a359871-d06d-494e-9fa6-335bf8d99592
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1314630785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1314630785
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.947485555
Short name T56
Test name
Test status
Simulation time 1984125361 ps
CPU time 11.16 seconds
Started Aug 19 05:42:00 PM PDT 24
Finished Aug 19 05:42:11 PM PDT 24
Peak memory 223084 kb
Host smart-48da5399-bf2a-4fba-9f69-63dddfafee8b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947485555 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.947485555
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3417871343
Short name T42
Test name
Test status
Simulation time 139460986 ps
CPU time 3.95 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:08 PM PDT 24
Peak memory 215012 kb
Host smart-e6428c3a-44b5-4ac9-afe8-7ddd36f09149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417871343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3417871343
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2269919608
Short name T124
Test name
Test status
Simulation time 607260015 ps
CPU time 30.06 seconds
Started Aug 19 05:40:30 PM PDT 24
Finished Aug 19 05:41:01 PM PDT 24
Peak memory 222904 kb
Host smart-8fa200ae-9b58-4097-b1c5-f255f5a0aece
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269919608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2269919608
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.776949070
Short name T65
Test name
Test status
Simulation time 1152238340 ps
CPU time 4.24 seconds
Started Aug 19 04:28:47 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 215004 kb
Host smart-84516c50-4c4e-4bb0-bbfd-7a672b415e57
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776949070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.776949070
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2306398843
Short name T7
Test name
Test status
Simulation time 216231604 ps
CPU time 2.47 seconds
Started Aug 19 05:40:14 PM PDT 24
Finished Aug 19 05:40:17 PM PDT 24
Peak memory 217680 kb
Host smart-9f4f31df-3666-43cc-a90a-3ad3971604ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306398843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2306398843
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1651574335
Short name T14
Test name
Test status
Simulation time 932850381 ps
CPU time 13.14 seconds
Started Aug 19 05:42:13 PM PDT 24
Finished Aug 19 05:42:26 PM PDT 24
Peak memory 215000 kb
Host smart-871076fb-f9ae-475a-bf05-41e231f74926
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1651574335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1651574335
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2478274099
Short name T415
Test name
Test status
Simulation time 1120515608 ps
CPU time 28.22 seconds
Started Aug 19 05:41:01 PM PDT 24
Finished Aug 19 05:41:29 PM PDT 24
Peak memory 214940 kb
Host smart-1f36858d-63eb-44a7-bdf0-2c37c505bbef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2478274099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2478274099
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2396428283
Short name T20
Test name
Test status
Simulation time 612236607 ps
CPU time 4.69 seconds
Started Aug 19 05:40:02 PM PDT 24
Finished Aug 19 05:40:07 PM PDT 24
Peak memory 222376 kb
Host smart-81d31455-b00b-42e0-8087-e78184d5e978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396428283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2396428283
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1057784359
Short name T84
Test name
Test status
Simulation time 479720173 ps
CPU time 18.09 seconds
Started Aug 19 05:41:11 PM PDT 24
Finished Aug 19 05:41:29 PM PDT 24
Peak memory 215960 kb
Host smart-d4511037-38f7-47e9-8f65-0ed541b05f63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1057784359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1057784359
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.91597182
Short name T70
Test name
Test status
Simulation time 163915975 ps
CPU time 3.06 seconds
Started Aug 19 04:29:00 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 214740 kb
Host smart-21ada642-66b3-4263-bf35-f443c5896159
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91597182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow
_reg_errors.91597182
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3880487348
Short name T18
Test name
Test status
Simulation time 272051568 ps
CPU time 3.11 seconds
Started Aug 19 05:41:53 PM PDT 24
Finished Aug 19 05:41:56 PM PDT 24
Peak memory 219456 kb
Host smart-fb03062a-9c4c-4c99-b398-59410b5ce779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880487348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3880487348
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.4152803806
Short name T284
Test name
Test status
Simulation time 9393103518 ps
CPU time 38.22 seconds
Started Aug 19 05:42:29 PM PDT 24
Finished Aug 19 05:43:08 PM PDT 24
Peak memory 221216 kb
Host smart-aec059c6-57de-4344-b7d9-5d908fa0d660
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152803806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.4152803806
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2707868282
Short name T41
Test name
Test status
Simulation time 145004125 ps
CPU time 3.73 seconds
Started Aug 19 05:42:14 PM PDT 24
Finished Aug 19 05:42:18 PM PDT 24
Peak memory 221540 kb
Host smart-c685fed9-5e3b-4b93-910c-8e0c12a123ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707868282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2707868282
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2959541810
Short name T262
Test name
Test status
Simulation time 232701669 ps
CPU time 5.58 seconds
Started Aug 19 05:40:43 PM PDT 24
Finished Aug 19 05:40:49 PM PDT 24
Peak memory 216092 kb
Host smart-e05ee9b0-18b3-4506-8b76-c2775b2de199
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2959541810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2959541810
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2431314316
Short name T44
Test name
Test status
Simulation time 67071876 ps
CPU time 3.68 seconds
Started Aug 19 05:40:54 PM PDT 24
Finished Aug 19 05:40:58 PM PDT 24
Peak memory 214800 kb
Host smart-dee8667d-41ae-4453-992d-cb65e277222d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431314316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2431314316
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2207181562
Short name T30
Test name
Test status
Simulation time 92003956 ps
CPU time 4.44 seconds
Started Aug 19 05:39:45 PM PDT 24
Finished Aug 19 05:39:50 PM PDT 24
Peak memory 223184 kb
Host smart-8f642810-b24d-4495-bb9e-531411fbda2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207181562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2207181562
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1562531775
Short name T34
Test name
Test status
Simulation time 3808600631 ps
CPU time 20.37 seconds
Started Aug 19 05:40:42 PM PDT 24
Finished Aug 19 05:41:02 PM PDT 24
Peak memory 214836 kb
Host smart-d9a90d49-e850-4e7b-b187-57de53ae267e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562531775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1562531775
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.4262801053
Short name T27
Test name
Test status
Simulation time 69683440 ps
CPU time 4.5 seconds
Started Aug 19 05:40:57 PM PDT 24
Finished Aug 19 05:41:02 PM PDT 24
Peak memory 214836 kb
Host smart-897e56ec-8431-418a-b322-caba2421bb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262801053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.4262801053
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1105847009
Short name T88
Test name
Test status
Simulation time 302673697 ps
CPU time 15.22 seconds
Started Aug 19 05:42:14 PM PDT 24
Finished Aug 19 05:42:29 PM PDT 24
Peak memory 216372 kb
Host smart-c9df1214-8618-4e81-9787-7c5c0b240840
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1105847009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1105847009
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.4032079250
Short name T130
Test name
Test status
Simulation time 518829395 ps
CPU time 8.59 seconds
Started Aug 19 05:40:43 PM PDT 24
Finished Aug 19 05:40:51 PM PDT 24
Peak memory 223128 kb
Host smart-355c17a3-f503-4825-92fe-0654e7a47324
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032079250 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.4032079250
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.323661436
Short name T149
Test name
Test status
Simulation time 1952770748 ps
CPU time 9.14 seconds
Started Aug 19 04:29:22 PM PDT 24
Finished Aug 19 04:29:31 PM PDT 24
Peak memory 214552 kb
Host smart-32afdedb-bf46-481f-8e0b-fdab5c6cff1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323661436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.323661436
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.696561963
Short name T249
Test name
Test status
Simulation time 137245419 ps
CPU time 7.49 seconds
Started Aug 19 05:42:01 PM PDT 24
Finished Aug 19 05:42:09 PM PDT 24
Peak memory 215952 kb
Host smart-2a6f102a-8664-4c35-91c9-6e9d14879f81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=696561963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.696561963
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1267117278
Short name T246
Test name
Test status
Simulation time 729222127 ps
CPU time 40.08 seconds
Started Aug 19 05:42:33 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 223056 kb
Host smart-b4f1afbd-19bb-443e-a61d-37e1a7e25dbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1267117278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1267117278
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2396290036
Short name T47
Test name
Test status
Simulation time 5692076500 ps
CPU time 15.13 seconds
Started Aug 19 05:39:52 PM PDT 24
Finished Aug 19 05:40:07 PM PDT 24
Peak memory 214856 kb
Host smart-67cd5b8a-baea-4d67-a607-6e445a8fa0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396290036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2396290036
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1624155034
Short name T178
Test name
Test status
Simulation time 11661327676 ps
CPU time 58.79 seconds
Started Aug 19 05:42:23 PM PDT 24
Finished Aug 19 05:43:22 PM PDT 24
Peak memory 222980 kb
Host smart-9e620381-8635-4262-b92c-c9c8750a7542
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624155034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1624155034
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.767001792
Short name T191
Test name
Test status
Simulation time 185234768 ps
CPU time 2.22 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:40:15 PM PDT 24
Peak memory 210640 kb
Host smart-25a28590-bb2c-4a08-be86-f97103f56c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767001792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.767001792
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2759434281
Short name T25
Test name
Test status
Simulation time 283702771 ps
CPU time 3.06 seconds
Started Aug 19 05:41:30 PM PDT 24
Finished Aug 19 05:41:33 PM PDT 24
Peak memory 222176 kb
Host smart-ea1b4ff9-50f0-457d-8473-1bd6b220a68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759434281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2759434281
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3988040153
Short name T431
Test name
Test status
Simulation time 10851925 ps
CPU time 0.73 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:39:54 PM PDT 24
Peak memory 206440 kb
Host smart-49ec8fff-0f1d-4bba-81ca-56857f455e57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988040153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3988040153
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.1804108329
Short name T226
Test name
Test status
Simulation time 149231223 ps
CPU time 3.78 seconds
Started Aug 19 05:39:54 PM PDT 24
Finished Aug 19 05:39:58 PM PDT 24
Peak memory 214936 kb
Host smart-17222ca9-582c-4f8a-b916-d26814d9bc1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804108329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.1804108329
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.2208977637
Short name T69
Test name
Test status
Simulation time 420293240 ps
CPU time 3.26 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:06 PM PDT 24
Peak memory 214784 kb
Host smart-b64e09f0-db33-439b-a155-694d939d9d9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208977637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.2208977637
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1686820222
Short name T287
Test name
Test status
Simulation time 237100866 ps
CPU time 8.31 seconds
Started Aug 19 05:40:25 PM PDT 24
Finished Aug 19 05:40:34 PM PDT 24
Peak memory 214808 kb
Host smart-c47eeae6-d14d-417c-ae62-35026ce4629f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1686820222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1686820222
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.653606459
Short name T53
Test name
Test status
Simulation time 147630839 ps
CPU time 5.92 seconds
Started Aug 19 05:41:31 PM PDT 24
Finished Aug 19 05:41:37 PM PDT 24
Peak memory 222912 kb
Host smart-37537416-16a5-44fd-8ba4-85644ab5204b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653606459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.653606459
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3109267968
Short name T155
Test name
Test status
Simulation time 276858061 ps
CPU time 9.95 seconds
Started Aug 19 04:28:42 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 214552 kb
Host smart-a10281be-cbc2-42e0-a0f5-eaa5f2c7058d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109267968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3109267968
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1635775527
Short name T302
Test name
Test status
Simulation time 527119887 ps
CPU time 21.13 seconds
Started Aug 19 05:41:38 PM PDT 24
Finished Aug 19 05:41:59 PM PDT 24
Peak memory 216168 kb
Host smart-f08a6f49-55e1-4093-8caa-f7557ccc0618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635775527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1635775527
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1569280914
Short name T185
Test name
Test status
Simulation time 1230292542 ps
CPU time 4.21 seconds
Started Aug 19 05:41:48 PM PDT 24
Finished Aug 19 05:41:52 PM PDT 24
Peak memory 209124 kb
Host smart-8ed6921e-34a1-41f7-a0ab-2ac7c303931c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569280914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1569280914
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.531652114
Short name T105
Test name
Test status
Simulation time 162769821 ps
CPU time 5.48 seconds
Started Aug 19 05:41:10 PM PDT 24
Finished Aug 19 05:41:15 PM PDT 24
Peak memory 217316 kb
Host smart-29ca7307-02a5-4b49-a157-e513cef2eef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531652114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.531652114
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3410392696
Short name T146
Test name
Test status
Simulation time 587024781 ps
CPU time 6.16 seconds
Started Aug 19 04:29:14 PM PDT 24
Finished Aug 19 04:29:20 PM PDT 24
Peak memory 214544 kb
Host smart-8abf9e72-8856-4759-9af4-c6570f64c038
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410392696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3410392696
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.884358625
Short name T49
Test name
Test status
Simulation time 244821754 ps
CPU time 3.57 seconds
Started Aug 19 05:41:10 PM PDT 24
Finished Aug 19 05:41:14 PM PDT 24
Peak memory 222860 kb
Host smart-aad3da82-7f0c-4167-ac31-ed5087bdb23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884358625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.884358625
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.4274856005
Short name T102
Test name
Test status
Simulation time 127149237 ps
CPU time 2.9 seconds
Started Aug 19 05:42:15 PM PDT 24
Finished Aug 19 05:42:18 PM PDT 24
Peak memory 218024 kb
Host smart-8249b024-975d-4316-b443-331c21e5fcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274856005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.4274856005
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2599286286
Short name T206
Test name
Test status
Simulation time 18618715993 ps
CPU time 70.1 seconds
Started Aug 19 05:41:06 PM PDT 24
Finished Aug 19 05:42:16 PM PDT 24
Peak memory 215668 kb
Host smart-8a5f1ac1-2821-4f61-90a8-4a6294f6b87d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599286286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2599286286
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.554401935
Short name T421
Test name
Test status
Simulation time 491376539 ps
CPU time 25.28 seconds
Started Aug 19 05:41:40 PM PDT 24
Finished Aug 19 05:42:05 PM PDT 24
Peak memory 214612 kb
Host smart-9505acbb-6fe6-4d1c-8d50-c8fe47b35874
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=554401935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.554401935
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.851248562
Short name T143
Test name
Test status
Simulation time 148716351 ps
CPU time 4.45 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:54 PM PDT 24
Peak memory 206344 kb
Host smart-5fbd54f3-8d3c-42e1-910b-ae7d496ebc0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851248562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
851248562
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2457302191
Short name T107
Test name
Test status
Simulation time 303717050 ps
CPU time 3 seconds
Started Aug 19 05:41:21 PM PDT 24
Finished Aug 19 05:41:24 PM PDT 24
Peak memory 218528 kb
Host smart-8b338e28-70c6-4a1d-98f9-3f8bab197c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457302191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2457302191
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.4083176686
Short name T57
Test name
Test status
Simulation time 1504430730 ps
CPU time 12.59 seconds
Started Aug 19 05:41:49 PM PDT 24
Finished Aug 19 05:42:02 PM PDT 24
Peak memory 223060 kb
Host smart-222f0712-5628-4167-8af3-f3eca196c898
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083176686 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.4083176686
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1066852051
Short name T100
Test name
Test status
Simulation time 250309696 ps
CPU time 4.4 seconds
Started Aug 19 05:42:27 PM PDT 24
Finished Aug 19 05:42:31 PM PDT 24
Peak memory 219268 kb
Host smart-0ca42681-7ca8-448a-a561-70c7fc0ea6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066852051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1066852051
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1248167353
Short name T110
Test name
Test status
Simulation time 18394607991 ps
CPU time 83.56 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:41:36 PM PDT 24
Peak memory 222952 kb
Host smart-3b366fc9-fccc-4d5e-8db4-19affbd7758c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248167353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1248167353
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3224510649
Short name T180
Test name
Test status
Simulation time 4272590619 ps
CPU time 38.76 seconds
Started Aug 19 05:40:01 PM PDT 24
Finished Aug 19 05:40:39 PM PDT 24
Peak memory 216908 kb
Host smart-1a8eb714-389c-4469-a857-040ba01ec75e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224510649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3224510649
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.649104154
Short name T343
Test name
Test status
Simulation time 42949412 ps
CPU time 3.35 seconds
Started Aug 19 05:42:21 PM PDT 24
Finished Aug 19 05:42:25 PM PDT 24
Peak memory 214788 kb
Host smart-01a8537a-781c-482a-9b7a-d6632a8b5da5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=649104154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.649104154
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.574654228
Short name T203
Test name
Test status
Simulation time 2176035997 ps
CPU time 75.07 seconds
Started Aug 19 05:42:40 PM PDT 24
Finished Aug 19 05:43:56 PM PDT 24
Peak memory 216004 kb
Host smart-9aa63985-11c8-4081-a82f-4c3845e68fa2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574654228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.574654228
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1444073398
Short name T309
Test name
Test status
Simulation time 176223612 ps
CPU time 2.83 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:07 PM PDT 24
Peak memory 214752 kb
Host smart-edeb7d56-4505-42c5-a4e2-dec20c1376c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1444073398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1444073398
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3147418757
Short name T141
Test name
Test status
Simulation time 299540416 ps
CPU time 6.99 seconds
Started Aug 19 05:40:56 PM PDT 24
Finished Aug 19 05:41:03 PM PDT 24
Peak memory 211308 kb
Host smart-51e8f9a2-4351-4bad-8134-2af4e18eff7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147418757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3147418757
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.238198033
Short name T151
Test name
Test status
Simulation time 840857712 ps
CPU time 8.54 seconds
Started Aug 19 04:28:42 PM PDT 24
Finished Aug 19 04:28:50 PM PDT 24
Peak memory 214472 kb
Host smart-ad6edb89-06f3-4e6a-b9d5-32bffea09279
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=238198033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
238198033
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.723054344
Short name T104
Test name
Test status
Simulation time 39360613 ps
CPU time 2.63 seconds
Started Aug 19 05:40:55 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 218296 kb
Host smart-0a21bae3-c08a-4fca-a677-09ed8e18e89f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723054344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.723054344
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2443158021
Short name T106
Test name
Test status
Simulation time 159735319 ps
CPU time 3.08 seconds
Started Aug 19 05:41:43 PM PDT 24
Finished Aug 19 05:41:46 PM PDT 24
Peak memory 217320 kb
Host smart-e609b086-ef03-47f4-9304-09e793096e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443158021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2443158021
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1196146681
Short name T317
Test name
Test status
Simulation time 511645936 ps
CPU time 2.64 seconds
Started Aug 19 05:39:41 PM PDT 24
Finished Aug 19 05:39:44 PM PDT 24
Peak memory 214744 kb
Host smart-cc853031-9909-4be3-87e1-38ed0fd5681a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196146681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1196146681
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1102421889
Short name T221
Test name
Test status
Simulation time 5313682115 ps
CPU time 54.08 seconds
Started Aug 19 05:40:23 PM PDT 24
Finished Aug 19 05:41:17 PM PDT 24
Peak memory 217184 kb
Host smart-1b6777bb-1353-4980-b537-4ab3447adaf0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102421889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1102421889
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3438280432
Short name T6
Test name
Test status
Simulation time 8178366583 ps
CPU time 134.08 seconds
Started Aug 19 05:40:26 PM PDT 24
Finished Aug 19 05:42:40 PM PDT 24
Peak memory 216980 kb
Host smart-257be439-c507-4c38-823d-f2e70850f59e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438280432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3438280432
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.748943757
Short name T584
Test name
Test status
Simulation time 327600891 ps
CPU time 3.4 seconds
Started Aug 19 05:40:59 PM PDT 24
Finished Aug 19 05:41:03 PM PDT 24
Peak memory 214632 kb
Host smart-c81d4d5a-b4ab-4911-aa97-380d5e346ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748943757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.748943757
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3355241292
Short name T830
Test name
Test status
Simulation time 4815170276 ps
CPU time 14.93 seconds
Started Aug 19 05:41:12 PM PDT 24
Finished Aug 19 05:41:27 PM PDT 24
Peak memory 222668 kb
Host smart-b01d9bec-5857-4d34-853f-e1b5dbced00b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355241292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3355241292
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.394519564
Short name T260
Test name
Test status
Simulation time 924380899 ps
CPU time 16.53 seconds
Started Aug 19 05:42:00 PM PDT 24
Finished Aug 19 05:42:17 PM PDT 24
Peak memory 214548 kb
Host smart-730beaf0-7adb-43d3-9dab-f652e5087959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394519564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.394519564
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.348723533
Short name T304
Test name
Test status
Simulation time 592661190 ps
CPU time 7.9 seconds
Started Aug 19 05:42:29 PM PDT 24
Finished Aug 19 05:42:37 PM PDT 24
Peak memory 214804 kb
Host smart-a5dd1e4e-e1f0-4309-b631-9e45841f0e0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348723533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.348723533
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.119758940
Short name T103
Test name
Test status
Simulation time 314127155 ps
CPU time 5.29 seconds
Started Aug 19 05:40:56 PM PDT 24
Finished Aug 19 05:41:01 PM PDT 24
Peak memory 218988 kb
Host smart-9cf3195a-703f-410c-b4e9-f99fea625b49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119758940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.119758940
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1645706258
Short name T297
Test name
Test status
Simulation time 416975168 ps
CPU time 3.76 seconds
Started Aug 19 05:39:41 PM PDT 24
Finished Aug 19 05:39:45 PM PDT 24
Peak memory 215520 kb
Host smart-e7722420-8b5d-4177-84ce-fb0e10b9c596
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1645706258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1645706258
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1729161844
Short name T607
Test name
Test status
Simulation time 52492565 ps
CPU time 1.94 seconds
Started Aug 19 05:40:25 PM PDT 24
Finished Aug 19 05:40:27 PM PDT 24
Peak memory 210052 kb
Host smart-ec7217c5-30b7-4ac6-a251-2c790d661764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729161844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1729161844
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2605755533
Short name T392
Test name
Test status
Simulation time 158586689 ps
CPU time 3.21 seconds
Started Aug 19 05:40:27 PM PDT 24
Finished Aug 19 05:40:30 PM PDT 24
Peak memory 214964 kb
Host smart-e47ee9d7-4e26-47a5-8d98-e331d964607b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605755533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2605755533
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3263161251
Short name T211
Test name
Test status
Simulation time 432919248 ps
CPU time 3.62 seconds
Started Aug 19 05:40:22 PM PDT 24
Finished Aug 19 05:40:26 PM PDT 24
Peak memory 222948 kb
Host smart-8b16e19b-04b5-41ec-8e64-c96985970a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263161251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3263161251
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.308491241
Short name T322
Test name
Test status
Simulation time 62478853 ps
CPU time 2.6 seconds
Started Aug 19 05:40:30 PM PDT 24
Finished Aug 19 05:40:32 PM PDT 24
Peak memory 218624 kb
Host smart-e75fcb2f-88d9-4973-94ec-3b63e4d55978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308491241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.308491241
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2855361681
Short name T351
Test name
Test status
Simulation time 380715021 ps
CPU time 13.83 seconds
Started Aug 19 05:40:46 PM PDT 24
Finished Aug 19 05:40:59 PM PDT 24
Peak memory 223036 kb
Host smart-d2c4bf1d-f8a7-4588-b293-067f1bb68520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855361681 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2855361681
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3978198148
Short name T338
Test name
Test status
Simulation time 35296932 ps
CPU time 1.97 seconds
Started Aug 19 05:40:56 PM PDT 24
Finished Aug 19 05:40:58 PM PDT 24
Peak memory 214792 kb
Host smart-eac57c05-94cb-4260-906d-465fb8415da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978198148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3978198148
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1169214589
Short name T268
Test name
Test status
Simulation time 159891992 ps
CPU time 3.97 seconds
Started Aug 19 05:41:02 PM PDT 24
Finished Aug 19 05:41:06 PM PDT 24
Peak memory 209296 kb
Host smart-d8ef57fb-e980-4a0e-ac41-251d3aa1ee9a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169214589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1169214589
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1057745630
Short name T19
Test name
Test status
Simulation time 117877606 ps
CPU time 3.66 seconds
Started Aug 19 05:41:53 PM PDT 24
Finished Aug 19 05:41:56 PM PDT 24
Peak memory 214828 kb
Host smart-1956888b-975b-4761-878f-f2ce6bf2b7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057745630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1057745630
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.4112117201
Short name T865
Test name
Test status
Simulation time 215329780 ps
CPU time 2.03 seconds
Started Aug 19 05:42:11 PM PDT 24
Finished Aug 19 05:42:13 PM PDT 24
Peak memory 214792 kb
Host smart-d9c7ea5b-2d98-45be-94bd-82e0141fac98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112117201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.4112117201
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.1859766797
Short name T120
Test name
Test status
Simulation time 4535742656 ps
CPU time 20.75 seconds
Started Aug 19 05:42:26 PM PDT 24
Finished Aug 19 05:42:47 PM PDT 24
Peak memory 215648 kb
Host smart-d85e09a9-043e-480c-82de-e7179cc0f834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859766797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.1859766797
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.755856537
Short name T162
Test name
Test status
Simulation time 582287710 ps
CPU time 10.87 seconds
Started Aug 19 04:28:39 PM PDT 24
Finished Aug 19 04:28:50 PM PDT 24
Peak memory 214456 kb
Host smart-77501c5d-d527-4d7d-a5e4-9469c8359b6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755856537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
755856537
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2866835210
Short name T156
Test name
Test status
Simulation time 1665609624 ps
CPU time 8.6 seconds
Started Aug 19 04:29:11 PM PDT 24
Finished Aug 19 04:29:20 PM PDT 24
Peak memory 214432 kb
Host smart-dd06908c-92d7-44c4-832a-10a3cc6cf283
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866835210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2866835210
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1631252119
Short name T10
Test name
Test status
Simulation time 2290446798 ps
CPU time 12.4 seconds
Started Aug 19 05:39:58 PM PDT 24
Finished Aug 19 05:40:11 PM PDT 24
Peak memory 235540 kb
Host smart-cdd572b7-5274-49c3-b37f-a1bde438d7c9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631252119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1631252119
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.3120597531
Short name T157
Test name
Test status
Simulation time 368401973 ps
CPU time 2.44 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:39:56 PM PDT 24
Peak memory 210244 kb
Host smart-7e47da70-3a79-41aa-9bbc-07fa67ea8752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120597531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.3120597531
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1476371419
Short name T158
Test name
Test status
Simulation time 121710096 ps
CPU time 1.63 seconds
Started Aug 19 05:41:54 PM PDT 24
Finished Aug 19 05:41:56 PM PDT 24
Peak memory 209888 kb
Host smart-6347f042-cf5b-41c5-be16-60b0b0b63746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476371419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1476371419
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1666676959
Short name T101
Test name
Test status
Simulation time 132545570 ps
CPU time 3.69 seconds
Started Aug 19 05:40:55 PM PDT 24
Finished Aug 19 05:40:59 PM PDT 24
Peak memory 218904 kb
Host smart-5922a72f-0ea2-43e6-ac20-ed8d81906a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666676959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1666676959
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.304445410
Short name T108
Test name
Test status
Simulation time 315593404 ps
CPU time 3.17 seconds
Started Aug 19 05:41:00 PM PDT 24
Finished Aug 19 05:41:04 PM PDT 24
Peak memory 217840 kb
Host smart-887d37a2-cf1b-404b-9770-01594b340925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304445410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.304445410
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.972945723
Short name T85
Test name
Test status
Simulation time 113035845 ps
CPU time 4.69 seconds
Started Aug 19 05:42:29 PM PDT 24
Finished Aug 19 05:42:33 PM PDT 24
Peak memory 218312 kb
Host smart-e01eeb24-e528-4869-90c2-fc7eb30ddcd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972945723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.972945723
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.4093931025
Short name T330
Test name
Test status
Simulation time 77840732 ps
CPU time 2.69 seconds
Started Aug 19 05:40:23 PM PDT 24
Finished Aug 19 05:40:25 PM PDT 24
Peak memory 214780 kb
Host smart-48116c9e-d8df-4f7b-9c67-077732f860c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093931025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.4093931025
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3683331741
Short name T676
Test name
Test status
Simulation time 206810472 ps
CPU time 3.58 seconds
Started Aug 19 05:40:21 PM PDT 24
Finished Aug 19 05:40:25 PM PDT 24
Peak memory 223076 kb
Host smart-8f4e864a-ae6c-4a96-b4ab-63de8184df12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683331741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3683331741
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2892840105
Short name T275
Test name
Test status
Simulation time 98459366 ps
CPU time 2.87 seconds
Started Aug 19 05:40:38 PM PDT 24
Finished Aug 19 05:40:41 PM PDT 24
Peak memory 214828 kb
Host smart-1142d0c4-4758-4bfb-9d5c-663efc3054fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892840105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2892840105
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1300667955
Short name T887
Test name
Test status
Simulation time 611677514 ps
CPU time 23.12 seconds
Started Aug 19 05:40:32 PM PDT 24
Finished Aug 19 05:40:56 PM PDT 24
Peak memory 222900 kb
Host smart-0c9c2c25-c27d-4127-a7be-e3a7486171bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300667955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1300667955
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1728194573
Short name T405
Test name
Test status
Simulation time 56440995 ps
CPU time 1.84 seconds
Started Aug 19 05:40:48 PM PDT 24
Finished Aug 19 05:40:50 PM PDT 24
Peak memory 210284 kb
Host smart-b5d1a2a6-09e4-46dd-a7f2-92f0807edb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728194573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1728194573
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_random.3059285392
Short name T325
Test name
Test status
Simulation time 206480288 ps
CPU time 4.32 seconds
Started Aug 19 05:40:46 PM PDT 24
Finished Aug 19 05:40:50 PM PDT 24
Peak memory 210292 kb
Host smart-791956ac-9873-43b1-ae25-6d858e74f35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059285392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3059285392
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.2675840650
Short name T240
Test name
Test status
Simulation time 438646860 ps
CPU time 3.7 seconds
Started Aug 19 05:40:44 PM PDT 24
Finished Aug 19 05:40:48 PM PDT 24
Peak memory 214784 kb
Host smart-36f2678c-78da-45bf-b0bd-f28e38d5c7f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675840650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.2675840650
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3518139119
Short name T394
Test name
Test status
Simulation time 57611311 ps
CPU time 3.81 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:39:56 PM PDT 24
Peak memory 214780 kb
Host smart-bf33d4cb-b949-4f02-a1a7-d10708e46c9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3518139119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3518139119
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1878316225
Short name T349
Test name
Test status
Simulation time 460020213 ps
CPU time 13 seconds
Started Aug 19 05:40:56 PM PDT 24
Finished Aug 19 05:41:09 PM PDT 24
Peak memory 214900 kb
Host smart-c88449fd-4146-4306-a34f-3ed03a7d14d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878316225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1878316225
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1427739471
Short name T321
Test name
Test status
Simulation time 346138861 ps
CPU time 2.5 seconds
Started Aug 19 05:41:15 PM PDT 24
Finished Aug 19 05:41:17 PM PDT 24
Peak memory 209824 kb
Host smart-3ea83992-32f0-4daf-9ca0-54cae1baa07d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427739471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1427739471
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.359359695
Short name T122
Test name
Test status
Simulation time 324251100 ps
CPU time 3.52 seconds
Started Aug 19 05:41:10 PM PDT 24
Finished Aug 19 05:41:13 PM PDT 24
Peak memory 208584 kb
Host smart-b735ec42-51a4-4b55-ac3a-e6ec4bcfde88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359359695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.359359695
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.2202546297
Short name T372
Test name
Test status
Simulation time 702646106 ps
CPU time 14.92 seconds
Started Aug 19 05:41:10 PM PDT 24
Finished Aug 19 05:41:25 PM PDT 24
Peak memory 221144 kb
Host smart-fd4b7550-0b6d-4363-91cc-c052588f1475
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202546297 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.2202546297
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2437569558
Short name T340
Test name
Test status
Simulation time 235141553 ps
CPU time 4.42 seconds
Started Aug 19 05:41:09 PM PDT 24
Finished Aug 19 05:41:14 PM PDT 24
Peak memory 222936 kb
Host smart-2e48463d-b876-4eaf-a89c-36f0201fee70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2437569558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2437569558
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1421339415
Short name T219
Test name
Test status
Simulation time 78373161 ps
CPU time 3.8 seconds
Started Aug 19 05:41:13 PM PDT 24
Finished Aug 19 05:41:17 PM PDT 24
Peak memory 208880 kb
Host smart-4edbd2cc-e4e5-4499-ab4f-efc9a147a741
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421339415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1421339415
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3577024354
Short name T231
Test name
Test status
Simulation time 523711370 ps
CPU time 6.5 seconds
Started Aug 19 05:42:23 PM PDT 24
Finished Aug 19 05:42:29 PM PDT 24
Peak memory 215080 kb
Host smart-dbb8f782-a3f7-49ed-a06d-af9dbc5eca62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577024354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3577024354
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2241369753
Short name T200
Test name
Test status
Simulation time 68703440 ps
CPU time 2.92 seconds
Started Aug 19 05:42:24 PM PDT 24
Finished Aug 19 05:42:28 PM PDT 24
Peak memory 220948 kb
Host smart-9e9cb4b7-fb71-4a7e-8bf7-526d77bac863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241369753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2241369753
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.924919327
Short name T209
Test name
Test status
Simulation time 214601160 ps
CPU time 14.81 seconds
Started Aug 19 05:42:27 PM PDT 24
Finished Aug 19 05:42:42 PM PDT 24
Peak memory 223060 kb
Host smart-46a2a909-84b6-4ddc-92ba-10a6a73594c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924919327 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.924919327
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.4018757226
Short name T133
Test name
Test status
Simulation time 419420896 ps
CPU time 17.27 seconds
Started Aug 19 05:42:30 PM PDT 24
Finished Aug 19 05:42:47 PM PDT 24
Peak memory 221556 kb
Host smart-ba59d67c-26c6-401b-9fd8-1a9c0a2269c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018757226 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.4018757226
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.816756723
Short name T1065
Test name
Test status
Simulation time 510940090 ps
CPU time 7.89 seconds
Started Aug 19 04:28:48 PM PDT 24
Finished Aug 19 04:28:56 PM PDT 24
Peak memory 206352 kb
Host smart-e3e1b8e1-f95f-432e-ab03-67e5a93982bf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816756723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.816756723
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3423307341
Short name T1062
Test name
Test status
Simulation time 858272345 ps
CPU time 6.54 seconds
Started Aug 19 04:28:56 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 206232 kb
Host smart-caebac34-16a8-4455-b4b1-cd7c6297ca09
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423307341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
423307341
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1069398124
Short name T1035
Test name
Test status
Simulation time 112432612 ps
CPU time 1.2 seconds
Started Aug 19 04:28:47 PM PDT 24
Finished Aug 19 04:28:48 PM PDT 24
Peak memory 206352 kb
Host smart-1f5f24e8-fc99-4bb3-a1c5-f944aa53eb5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069398124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
069398124
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3130891699
Short name T1004
Test name
Test status
Simulation time 91557814 ps
CPU time 1.11 seconds
Started Aug 19 04:28:37 PM PDT 24
Finished Aug 19 04:28:38 PM PDT 24
Peak memory 206320 kb
Host smart-37853d56-e013-4b5b-baa4-d7573800cc59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130891699 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3130891699
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2509083833
Short name T984
Test name
Test status
Simulation time 16220074 ps
CPU time 0.94 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:09 PM PDT 24
Peak memory 206108 kb
Host smart-8cb6a48c-928e-4e7f-bc03-bd871b10ae7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509083833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2509083833
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1049557792
Short name T945
Test name
Test status
Simulation time 11460248 ps
CPU time 0.8 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:50 PM PDT 24
Peak memory 206116 kb
Host smart-23121653-20b2-404f-be58-43ce939cfd06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049557792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1049557792
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4053843640
Short name T1020
Test name
Test status
Simulation time 257467588 ps
CPU time 2.78 seconds
Started Aug 19 04:29:00 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 206296 kb
Host smart-7652f937-924d-4de9-bcb5-d57ed0a2110f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053843640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.4053843640
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2064751004
Short name T1061
Test name
Test status
Simulation time 98641749 ps
CPU time 3.46 seconds
Started Aug 19 04:29:02 PM PDT 24
Finished Aug 19 04:29:05 PM PDT 24
Peak memory 214816 kb
Host smart-08e378dc-8a2f-4f7c-9c8c-88dbb547aa72
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064751004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2064751004
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2915926029
Short name T941
Test name
Test status
Simulation time 713738660 ps
CPU time 3.58 seconds
Started Aug 19 04:28:56 PM PDT 24
Finished Aug 19 04:29:00 PM PDT 24
Peak memory 214832 kb
Host smart-a3dbe479-996e-4da2-8618-f96a7089f886
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915926029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2915926029
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2063755790
Short name T934
Test name
Test status
Simulation time 707908387 ps
CPU time 3.92 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:07 PM PDT 24
Peak memory 214516 kb
Host smart-548b2b14-16c7-42d1-9162-557be1012d13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063755790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2063755790
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.585610084
Short name T947
Test name
Test status
Simulation time 982380648 ps
CPU time 7.39 seconds
Started Aug 19 04:28:48 PM PDT 24
Finished Aug 19 04:28:55 PM PDT 24
Peak memory 206356 kb
Host smart-e123850b-afb8-494f-a2c7-717d7da73e57
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585610084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.585610084
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2503396248
Short name T1002
Test name
Test status
Simulation time 4479682012 ps
CPU time 16.32 seconds
Started Aug 19 04:28:47 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 206444 kb
Host smart-9c324807-c6e9-4ffc-888c-4b4cd9b3f74e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503396248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
503396248
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3719985425
Short name T1021
Test name
Test status
Simulation time 94513218 ps
CPU time 1.14 seconds
Started Aug 19 04:28:58 PM PDT 24
Finished Aug 19 04:29:00 PM PDT 24
Peak memory 206252 kb
Host smart-b9c9c7d1-5fc5-4643-8256-51eaecac24bf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719985425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
719985425
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3496581180
Short name T958
Test name
Test status
Simulation time 44741087 ps
CPU time 2 seconds
Started Aug 19 04:28:40 PM PDT 24
Finished Aug 19 04:28:42 PM PDT 24
Peak memory 214580 kb
Host smart-925ba0dc-97c2-4144-9637-07f23727b0e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496581180 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3496581180
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2620196973
Short name T1030
Test name
Test status
Simulation time 139841792 ps
CPU time 0.92 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 206024 kb
Host smart-0dc5f554-8740-4d42-b095-6083f86729e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620196973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2620196973
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1277545073
Short name T968
Test name
Test status
Simulation time 45781994 ps
CPU time 0.7 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 206056 kb
Host smart-b8f8cc2a-52bb-49a5-bd2c-a69a36fd90d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277545073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1277545073
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1154080993
Short name T95
Test name
Test status
Simulation time 480229567 ps
CPU time 2.98 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:54 PM PDT 24
Peak memory 206260 kb
Host smart-343df110-be86-4039-b2e2-deba1a886316
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154080993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1154080993
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3930601025
Short name T1084
Test name
Test status
Simulation time 62673835 ps
CPU time 1.39 seconds
Started Aug 19 04:29:11 PM PDT 24
Finished Aug 19 04:29:13 PM PDT 24
Peak memory 214900 kb
Host smart-1b233f37-1f86-48af-869f-cce4d4fc5d15
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930601025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3930601025
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1872762381
Short name T966
Test name
Test status
Simulation time 539536578 ps
CPU time 2.79 seconds
Started Aug 19 04:28:59 PM PDT 24
Finished Aug 19 04:29:02 PM PDT 24
Peak memory 214444 kb
Host smart-b40ca149-d053-4911-b11f-8b7118cac60c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872762381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1872762381
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3981122839
Short name T1034
Test name
Test status
Simulation time 62725880 ps
CPU time 1.72 seconds
Started Aug 19 04:29:01 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 206484 kb
Host smart-a8d0f488-72c2-4326-bd5a-46ccff490a26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981122839 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3981122839
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2225858661
Short name T997
Test name
Test status
Simulation time 31428097 ps
CPU time 1.17 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 206288 kb
Host smart-9b440ab6-12ac-4263-b0d9-4df745187f25
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225858661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2225858661
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.1590282047
Short name T1048
Test name
Test status
Simulation time 8977359 ps
CPU time 0.87 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:04 PM PDT 24
Peak memory 206052 kb
Host smart-60865f65-cc0f-4530-96e0-3497fc9b106c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590282047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1590282047
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.988118426
Short name T976
Test name
Test status
Simulation time 217472610 ps
CPU time 3.69 seconds
Started Aug 19 04:29:00 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 206252 kb
Host smart-c39c4916-dff1-4508-bde7-f810b144b23a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988118426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.988118426
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3808024306
Short name T927
Test name
Test status
Simulation time 93506948 ps
CPU time 1.34 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 214812 kb
Host smart-c4724525-1d1e-4950-8d5a-814a20f0a5f2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808024306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3808024306
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3819847190
Short name T1003
Test name
Test status
Simulation time 1828958066 ps
CPU time 7.13 seconds
Started Aug 19 04:28:52 PM PDT 24
Finished Aug 19 04:28:59 PM PDT 24
Peak memory 223084 kb
Host smart-423326f7-c6e7-4d2e-9558-7fe75a9822f4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819847190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3819847190
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.154420600
Short name T920
Test name
Test status
Simulation time 53284200 ps
CPU time 2.2 seconds
Started Aug 19 04:29:01 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 214632 kb
Host smart-7d866b97-c67e-414f-bcea-640e6d3abbf0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154420600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.154420600
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.803777090
Short name T1072
Test name
Test status
Simulation time 112735720 ps
CPU time 4.6 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:08 PM PDT 24
Peak memory 215396 kb
Host smart-09594498-cb5e-435e-a485-87d5929dff93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803777090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err
.803777090
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.706298581
Short name T952
Test name
Test status
Simulation time 198126846 ps
CPU time 1.53 seconds
Started Aug 19 04:28:57 PM PDT 24
Finished Aug 19 04:28:58 PM PDT 24
Peak memory 214520 kb
Host smart-814c61ae-1dc7-451c-a729-f1e852f93c16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706298581 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.706298581
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3465071538
Short name T980
Test name
Test status
Simulation time 29579411 ps
CPU time 1.53 seconds
Started Aug 19 04:28:56 PM PDT 24
Finished Aug 19 04:28:57 PM PDT 24
Peak memory 206340 kb
Host smart-1aec8846-0222-4dd0-940c-6b43aeca6264
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465071538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3465071538
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2900751572
Short name T1055
Test name
Test status
Simulation time 12098847 ps
CPU time 0.7 seconds
Started Aug 19 04:29:06 PM PDT 24
Finished Aug 19 04:29:07 PM PDT 24
Peak memory 206052 kb
Host smart-767591ea-883a-4f79-b9a7-312d7698df73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900751572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2900751572
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.297684263
Short name T1046
Test name
Test status
Simulation time 34464038 ps
CPU time 1.97 seconds
Started Aug 19 04:28:57 PM PDT 24
Finished Aug 19 04:28:59 PM PDT 24
Peak memory 206300 kb
Host smart-a8ff6146-41af-44de-98f3-bc56bf570a74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297684263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.297684263
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.522295569
Short name T957
Test name
Test status
Simulation time 182338761 ps
CPU time 4.08 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:55 PM PDT 24
Peak memory 214900 kb
Host smart-f96e3c89-2010-489c-8fdc-ef5d0c6b8ce1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522295569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.522295569
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1019641076
Short name T931
Test name
Test status
Simulation time 546821205 ps
CPU time 5.2 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:57 PM PDT 24
Peak memory 217536 kb
Host smart-20ff5201-d2ee-4a05-bcfd-36cc75b32a86
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019641076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1019641076
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2293945314
Short name T148
Test name
Test status
Simulation time 237823462 ps
CPU time 5.01 seconds
Started Aug 19 04:28:57 PM PDT 24
Finished Aug 19 04:29:02 PM PDT 24
Peak memory 214544 kb
Host smart-7a5a8fa1-e2eb-4b9a-9ae2-0ca4c16d3c1c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293945314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2293945314
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.506377117
Short name T1040
Test name
Test status
Simulation time 31681628 ps
CPU time 1.02 seconds
Started Aug 19 04:28:58 PM PDT 24
Finished Aug 19 04:28:59 PM PDT 24
Peak memory 206168 kb
Host smart-cb756942-13a6-4905-8904-9ec777b37fb0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506377117 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.506377117
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1078061169
Short name T94
Test name
Test status
Simulation time 28899340 ps
CPU time 1.43 seconds
Started Aug 19 04:28:58 PM PDT 24
Finished Aug 19 04:28:59 PM PDT 24
Peak memory 206292 kb
Host smart-83a3dff6-83bc-4012-91f5-d2872be66812
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1078061169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1078061169
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3213630750
Short name T953
Test name
Test status
Simulation time 11147221 ps
CPU time 0.71 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 206028 kb
Host smart-c685f950-aece-4407-b410-46ad56cac335
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213630750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3213630750
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.742366547
Short name T986
Test name
Test status
Simulation time 78246726 ps
CPU time 1.44 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:04 PM PDT 24
Peak memory 206300 kb
Host smart-fb7b0d43-918f-4367-903a-e3dacf2dfb89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742366547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_sa
me_csr_outstanding.742366547
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.971135197
Short name T951
Test name
Test status
Simulation time 464748618 ps
CPU time 8.54 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:59 PM PDT 24
Peak memory 214856 kb
Host smart-80dde2ee-1305-4a3a-933b-c2a03d5d3180
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=971135197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.971135197
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2290098590
Short name T1049
Test name
Test status
Simulation time 35104127 ps
CPU time 2.42 seconds
Started Aug 19 04:28:59 PM PDT 24
Finished Aug 19 04:29:01 PM PDT 24
Peak memory 214540 kb
Host smart-2487e438-15ce-4788-bf79-33d47c0b094c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290098590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2290098590
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4195904827
Short name T1069
Test name
Test status
Simulation time 108305216 ps
CPU time 2.49 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:05 PM PDT 24
Peak memory 215776 kb
Host smart-a8af3902-1ea7-4fe9-be58-9a8f755a8c4c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195904827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.4195904827
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3706867890
Short name T978
Test name
Test status
Simulation time 51368958 ps
CPU time 1.02 seconds
Started Aug 19 04:29:06 PM PDT 24
Finished Aug 19 04:29:08 PM PDT 24
Peak memory 206296 kb
Host smart-21c9fb1a-dd6d-4e54-95ef-1c15bd6dc889
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706867890 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3706867890
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3214807744
Short name T1019
Test name
Test status
Simulation time 50460388 ps
CPU time 0.83 seconds
Started Aug 19 04:29:23 PM PDT 24
Finished Aug 19 04:29:23 PM PDT 24
Peak memory 206188 kb
Host smart-1046d340-3f07-4545-8b40-94ed808b329f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214807744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3214807744
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.4093435717
Short name T962
Test name
Test status
Simulation time 10972384 ps
CPU time 0.8 seconds
Started Aug 19 04:29:27 PM PDT 24
Finished Aug 19 04:29:28 PM PDT 24
Peak memory 206040 kb
Host smart-023d45fe-e620-46d3-af34-923b80da91c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093435717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.4093435717
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2903086458
Short name T1080
Test name
Test status
Simulation time 56570891 ps
CPU time 1.58 seconds
Started Aug 19 04:29:15 PM PDT 24
Finished Aug 19 04:29:17 PM PDT 24
Peak memory 206324 kb
Host smart-f17cc39d-36f1-4283-a41d-6a131b48f165
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903086458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2903086458
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2210269698
Short name T940
Test name
Test status
Simulation time 85419253 ps
CPU time 1.51 seconds
Started Aug 19 04:28:59 PM PDT 24
Finished Aug 19 04:29:00 PM PDT 24
Peak memory 214744 kb
Host smart-5e08ef29-0ba9-4ab8-9202-e0e52f688fc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210269698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2210269698
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2075966658
Short name T948
Test name
Test status
Simulation time 4068458856 ps
CPU time 12.1 seconds
Started Aug 19 04:29:11 PM PDT 24
Finished Aug 19 04:29:23 PM PDT 24
Peak memory 221508 kb
Host smart-2b8cdf28-62fc-404a-a2d3-440dc72258b9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075966658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2075966658
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1676042543
Short name T971
Test name
Test status
Simulation time 115715656 ps
CPU time 2.02 seconds
Started Aug 19 04:29:05 PM PDT 24
Finished Aug 19 04:29:07 PM PDT 24
Peak memory 214416 kb
Host smart-ba47fe3e-4808-42d5-9fd1-f8b99ae6f545
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676042543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1676042543
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1952248121
Short name T933
Test name
Test status
Simulation time 134599995 ps
CPU time 4.76 seconds
Started Aug 19 04:29:28 PM PDT 24
Finished Aug 19 04:29:33 PM PDT 24
Peak memory 214456 kb
Host smart-2c645dee-025b-41f2-a937-6f5d6d608be2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952248121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1952248121
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2555995408
Short name T924
Test name
Test status
Simulation time 47126544 ps
CPU time 1.56 seconds
Started Aug 19 04:29:27 PM PDT 24
Finished Aug 19 04:29:29 PM PDT 24
Peak memory 214636 kb
Host smart-5e84433d-5590-4ea7-bf76-07cc391818b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2555995408 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2555995408
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2666419950
Short name T1082
Test name
Test status
Simulation time 15128659 ps
CPU time 1 seconds
Started Aug 19 04:29:10 PM PDT 24
Finished Aug 19 04:29:11 PM PDT 24
Peak memory 206292 kb
Host smart-95cd9525-a7ce-4b8d-8d08-cbb98e8c3f92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666419950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2666419950
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.2812085510
Short name T1036
Test name
Test status
Simulation time 42820316 ps
CPU time 0.79 seconds
Started Aug 19 04:29:05 PM PDT 24
Finished Aug 19 04:29:06 PM PDT 24
Peak memory 206048 kb
Host smart-ffac0118-26d0-4773-8f62-4d25cd907536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812085510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2812085510
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.712885221
Short name T977
Test name
Test status
Simulation time 171642653 ps
CPU time 2.61 seconds
Started Aug 19 04:29:24 PM PDT 24
Finished Aug 19 04:29:26 PM PDT 24
Peak memory 206336 kb
Host smart-645d406c-aba1-46d7-9298-eb4deece6744
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712885221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.712885221
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.636929285
Short name T1012
Test name
Test status
Simulation time 101622303 ps
CPU time 2.55 seconds
Started Aug 19 04:29:28 PM PDT 24
Finished Aug 19 04:29:31 PM PDT 24
Peak memory 214812 kb
Host smart-75229912-d1ea-42e0-8cdd-6e5671b5b8cc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636929285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.636929285
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3089990913
Short name T969
Test name
Test status
Simulation time 78173326 ps
CPU time 4.44 seconds
Started Aug 19 04:29:24 PM PDT 24
Finished Aug 19 04:29:34 PM PDT 24
Peak memory 214936 kb
Host smart-27bde6ec-afdf-46ec-b554-79aaf5bced2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089990913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3089990913
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1520481292
Short name T1023
Test name
Test status
Simulation time 169156418 ps
CPU time 3.91 seconds
Started Aug 19 04:29:06 PM PDT 24
Finished Aug 19 04:29:10 PM PDT 24
Peak memory 214560 kb
Host smart-fc5741bd-f582-4262-be42-245504ad23ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520481292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1520481292
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3898332329
Short name T145
Test name
Test status
Simulation time 452479354 ps
CPU time 4.54 seconds
Started Aug 19 04:29:22 PM PDT 24
Finished Aug 19 04:29:27 PM PDT 24
Peak memory 216040 kb
Host smart-d8ff5d25-e66a-400e-a4c6-a6ce195d9e36
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898332329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3898332329
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1422459481
Short name T990
Test name
Test status
Simulation time 228135878 ps
CPU time 1.55 seconds
Started Aug 19 04:29:10 PM PDT 24
Finished Aug 19 04:29:17 PM PDT 24
Peak memory 214532 kb
Host smart-a3191f51-9d69-4a66-8481-96c7e22e6cd5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422459481 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1422459481
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.748579988
Short name T91
Test name
Test status
Simulation time 16450892 ps
CPU time 0.99 seconds
Started Aug 19 04:29:24 PM PDT 24
Finished Aug 19 04:29:25 PM PDT 24
Peak memory 206092 kb
Host smart-838581ae-27f6-4781-981b-45cd1ab621c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748579988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.748579988
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2739984305
Short name T989
Test name
Test status
Simulation time 20174172 ps
CPU time 0.85 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:31 PM PDT 24
Peak memory 206036 kb
Host smart-32976ab9-e71f-4da1-b392-e1be0a3beec8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739984305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2739984305
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2835968121
Short name T90
Test name
Test status
Simulation time 26625711 ps
CPU time 1.33 seconds
Started Aug 19 04:29:08 PM PDT 24
Finished Aug 19 04:29:10 PM PDT 24
Peak memory 206264 kb
Host smart-0546d6c2-f10f-44b8-8708-e5981dd8043c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835968121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2835968121
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1465372778
Short name T960
Test name
Test status
Simulation time 119197489 ps
CPU time 2.22 seconds
Started Aug 19 04:29:27 PM PDT 24
Finished Aug 19 04:29:29 PM PDT 24
Peak memory 214884 kb
Host smart-1d944a54-8c2a-42a8-a69c-8640c3c284a0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465372778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1465372778
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1228490936
Short name T1075
Test name
Test status
Simulation time 604352972 ps
CPU time 4.53 seconds
Started Aug 19 04:29:11 PM PDT 24
Finished Aug 19 04:29:15 PM PDT 24
Peak memory 220836 kb
Host smart-16d0bbaa-49e6-4943-8363-480943499b7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228490936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1228490936
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.4034632155
Short name T970
Test name
Test status
Simulation time 31772330 ps
CPU time 2.46 seconds
Started Aug 19 04:29:17 PM PDT 24
Finished Aug 19 04:29:20 PM PDT 24
Peak memory 217536 kb
Host smart-8c55f5e7-5095-4bae-98e1-a66b2246aa03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034632155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.4034632155
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3980594758
Short name T929
Test name
Test status
Simulation time 29842002 ps
CPU time 2.02 seconds
Started Aug 19 04:29:14 PM PDT 24
Finished Aug 19 04:29:16 PM PDT 24
Peak memory 214604 kb
Host smart-ac45e59c-cc81-473f-b821-a7006ba8aa31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980594758 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3980594758
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3547703049
Short name T1063
Test name
Test status
Simulation time 65113185 ps
CPU time 1.2 seconds
Started Aug 19 04:29:11 PM PDT 24
Finished Aug 19 04:29:12 PM PDT 24
Peak memory 206272 kb
Host smart-c3b97150-7500-4d14-a0b4-074bc7a0cbe9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3547703049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3547703049
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1320123763
Short name T1066
Test name
Test status
Simulation time 19245934 ps
CPU time 0.97 seconds
Started Aug 19 04:29:19 PM PDT 24
Finished Aug 19 04:29:21 PM PDT 24
Peak memory 206148 kb
Host smart-f704bd04-a977-4084-af2a-2e2bdb0793f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320123763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1320123763
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2848138741
Short name T1047
Test name
Test status
Simulation time 35782745 ps
CPU time 2.56 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:33 PM PDT 24
Peak memory 206288 kb
Host smart-70faeed7-f246-4f29-bce0-5ecee397f769
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848138741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2848138741
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2309787008
Short name T1068
Test name
Test status
Simulation time 271046255 ps
CPU time 2.01 seconds
Started Aug 19 04:29:12 PM PDT 24
Finished Aug 19 04:29:19 PM PDT 24
Peak memory 214800 kb
Host smart-29ed7f23-20d8-4687-bb24-fabc3c1cf0f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309787008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2309787008
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1419747365
Short name T67
Test name
Test status
Simulation time 796329043 ps
CPU time 13.39 seconds
Started Aug 19 04:29:23 PM PDT 24
Finished Aug 19 04:29:37 PM PDT 24
Peak memory 214892 kb
Host smart-79476c8c-cf39-4f91-a9cd-c45456bcfa0d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419747365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1419747365
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.1853495189
Short name T1013
Test name
Test status
Simulation time 175940772 ps
CPU time 1.5 seconds
Started Aug 19 04:29:12 PM PDT 24
Finished Aug 19 04:29:14 PM PDT 24
Peak memory 214608 kb
Host smart-c10845f9-8073-43f3-abdb-bf5c746703d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853495189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1853495189
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3909295220
Short name T1067
Test name
Test status
Simulation time 25938438 ps
CPU time 1.38 seconds
Started Aug 19 04:29:20 PM PDT 24
Finished Aug 19 04:29:21 PM PDT 24
Peak memory 206340 kb
Host smart-a2e43979-b33a-40ce-8160-3c4a1ddf6532
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909295220 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3909295220
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1912682555
Short name T96
Test name
Test status
Simulation time 26374749 ps
CPU time 1.32 seconds
Started Aug 19 04:29:15 PM PDT 24
Finished Aug 19 04:29:17 PM PDT 24
Peak memory 206256 kb
Host smart-d889b349-1038-4c87-9040-7cf00fb78bf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912682555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1912682555
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3469193818
Short name T921
Test name
Test status
Simulation time 32902858 ps
CPU time 0.76 seconds
Started Aug 19 04:29:11 PM PDT 24
Finished Aug 19 04:29:11 PM PDT 24
Peak memory 206036 kb
Host smart-775e2f85-a7d3-451f-b8c0-ec379b6f5526
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469193818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3469193818
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2249302410
Short name T92
Test name
Test status
Simulation time 34762388 ps
CPU time 1.85 seconds
Started Aug 19 04:29:11 PM PDT 24
Finished Aug 19 04:29:18 PM PDT 24
Peak memory 206264 kb
Host smart-af4ac4e1-7dc1-4992-8033-854c2fc61395
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249302410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2249302410
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2022637103
Short name T1022
Test name
Test status
Simulation time 94987978 ps
CPU time 1.9 seconds
Started Aug 19 04:29:07 PM PDT 24
Finished Aug 19 04:29:09 PM PDT 24
Peak memory 214904 kb
Host smart-b4ab2a83-1bb8-4f7d-b372-794629084fc5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022637103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2022637103
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.923879477
Short name T979
Test name
Test status
Simulation time 342700111 ps
CPU time 4.95 seconds
Started Aug 19 04:29:26 PM PDT 24
Finished Aug 19 04:29:31 PM PDT 24
Peak memory 214812 kb
Host smart-7665cc1a-efe2-4289-ba98-e33a8316a53c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923879477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.923879477
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3661086065
Short name T1083
Test name
Test status
Simulation time 688422873 ps
CPU time 6.09 seconds
Started Aug 19 04:29:25 PM PDT 24
Finished Aug 19 04:29:31 PM PDT 24
Peak memory 214568 kb
Host smart-ffbc5b28-49c3-498b-9b67-657393668dad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661086065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3661086065
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1162240914
Short name T964
Test name
Test status
Simulation time 29760476 ps
CPU time 1.14 seconds
Started Aug 19 04:29:27 PM PDT 24
Finished Aug 19 04:29:28 PM PDT 24
Peak memory 214540 kb
Host smart-75f2fb03-6a75-4d18-9386-de46c916b65d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162240914 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1162240914
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3221548064
Short name T1058
Test name
Test status
Simulation time 20965643 ps
CPU time 1.16 seconds
Started Aug 19 04:29:13 PM PDT 24
Finished Aug 19 04:29:14 PM PDT 24
Peak memory 206260 kb
Host smart-8240b4ce-d475-4714-94e2-7bfc79ccaf77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3221548064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3221548064
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2027699356
Short name T1015
Test name
Test status
Simulation time 17094185 ps
CPU time 0.91 seconds
Started Aug 19 04:29:30 PM PDT 24
Finished Aug 19 04:29:31 PM PDT 24
Peak memory 206276 kb
Host smart-d1a8af48-a0c0-43d8-a180-173406131055
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027699356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2027699356
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1645561228
Short name T93
Test name
Test status
Simulation time 281754781 ps
CPU time 1.94 seconds
Started Aug 19 04:29:12 PM PDT 24
Finished Aug 19 04:29:14 PM PDT 24
Peak memory 206228 kb
Host smart-5c71db8e-a1d3-455c-8a95-5987adb8009c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645561228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1645561228
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.679895589
Short name T1009
Test name
Test status
Simulation time 274665255 ps
CPU time 2.76 seconds
Started Aug 19 04:29:20 PM PDT 24
Finished Aug 19 04:29:23 PM PDT 24
Peak memory 214836 kb
Host smart-057eb153-5351-4296-ad14-73d4f81b284c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679895589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shado
w_reg_errors.679895589
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2204342161
Short name T992
Test name
Test status
Simulation time 477620672 ps
CPU time 8.75 seconds
Started Aug 19 04:29:10 PM PDT 24
Finished Aug 19 04:29:19 PM PDT 24
Peak memory 215024 kb
Host smart-a4dc8aa9-07b9-4840-a90d-7d969f0d55cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204342161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2204342161
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1331494570
Short name T1031
Test name
Test status
Simulation time 273889800 ps
CPU time 2.04 seconds
Started Aug 19 04:29:31 PM PDT 24
Finished Aug 19 04:29:33 PM PDT 24
Peak memory 214528 kb
Host smart-f725f12a-fb4f-433a-9ece-81dc27070cc0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331494570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1331494570
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.922230958
Short name T944
Test name
Test status
Simulation time 815331348 ps
CPU time 5.29 seconds
Started Aug 19 04:29:17 PM PDT 24
Finished Aug 19 04:29:23 PM PDT 24
Peak memory 214444 kb
Host smart-fcd0f7e9-cc47-46ef-852e-e47505fc1f64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922230958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err
.922230958
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1381360116
Short name T1029
Test name
Test status
Simulation time 17868270 ps
CPU time 1.4 seconds
Started Aug 19 04:29:14 PM PDT 24
Finished Aug 19 04:29:16 PM PDT 24
Peak memory 214520 kb
Host smart-16796c69-1d99-444a-b26e-62d8de778c45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381360116 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1381360116
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2810490805
Short name T982
Test name
Test status
Simulation time 38084817 ps
CPU time 0.91 seconds
Started Aug 19 04:29:08 PM PDT 24
Finished Aug 19 04:29:09 PM PDT 24
Peak memory 206100 kb
Host smart-ebe7d09f-9f75-4f24-a4af-1f164b14a009
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810490805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2810490805
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3649281658
Short name T1032
Test name
Test status
Simulation time 31221366 ps
CPU time 0.74 seconds
Started Aug 19 04:29:23 PM PDT 24
Finished Aug 19 04:29:24 PM PDT 24
Peak memory 205996 kb
Host smart-6bd6f13c-db30-41f2-a7f2-10b542cc9765
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649281658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3649281658
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.4258679209
Short name T1078
Test name
Test status
Simulation time 216954417 ps
CPU time 2.79 seconds
Started Aug 19 04:29:08 PM PDT 24
Finished Aug 19 04:29:11 PM PDT 24
Peak memory 206300 kb
Host smart-85d5597f-0d41-4889-a5e9-0b55feac343f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258679209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.4258679209
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3864489349
Short name T1028
Test name
Test status
Simulation time 46224849 ps
CPU time 1.46 seconds
Started Aug 19 04:29:11 PM PDT 24
Finished Aug 19 04:29:12 PM PDT 24
Peak memory 214712 kb
Host smart-376b62fa-68fd-49eb-8ed0-0f9802df61c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864489349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3864489349
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3960697134
Short name T71
Test name
Test status
Simulation time 1207500354 ps
CPU time 7.22 seconds
Started Aug 19 04:29:08 PM PDT 24
Finished Aug 19 04:29:16 PM PDT 24
Peak memory 214804 kb
Host smart-f9a7f96e-b6b5-4208-b48b-8d8693135abb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960697134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3960697134
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3457885169
Short name T1033
Test name
Test status
Simulation time 80376224 ps
CPU time 1.63 seconds
Started Aug 19 04:29:32 PM PDT 24
Finished Aug 19 04:29:34 PM PDT 24
Peak memory 206408 kb
Host smart-7117d410-7903-4a95-bc46-7d4a72fef691
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457885169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3457885169
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3745913461
Short name T142
Test name
Test status
Simulation time 820685012 ps
CPU time 6.79 seconds
Started Aug 19 04:29:23 PM PDT 24
Finished Aug 19 04:29:29 PM PDT 24
Peak memory 206320 kb
Host smart-8f6db2a7-28ad-4d7e-9a89-009a67f97df2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745913461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3745913461
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.202519468
Short name T176
Test name
Test status
Simulation time 926571227 ps
CPU time 5.91 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:56 PM PDT 24
Peak memory 206328 kb
Host smart-6b019d3a-902d-483c-80c6-d033570b1089
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202519468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.202519468
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3843725811
Short name T1016
Test name
Test status
Simulation time 577152383 ps
CPU time 14.81 seconds
Started Aug 19 04:28:41 PM PDT 24
Finished Aug 19 04:28:56 PM PDT 24
Peak memory 206260 kb
Host smart-fa067b89-c59f-4e58-87df-c089827b6330
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843725811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
843725811
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.569591915
Short name T961
Test name
Test status
Simulation time 115352793 ps
CPU time 1.17 seconds
Started Aug 19 04:29:01 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 206388 kb
Host smart-78cabc1d-c1ea-403c-916f-2738afe255f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569591915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.569591915
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.951093518
Short name T1007
Test name
Test status
Simulation time 93278859 ps
CPU time 1.25 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:04 PM PDT 24
Peak memory 214476 kb
Host smart-32fe0972-6f24-479e-adde-0aa5c6cf7719
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951093518 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.951093518
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3896718243
Short name T168
Test name
Test status
Simulation time 23207820 ps
CPU time 1 seconds
Started Aug 19 04:28:48 PM PDT 24
Finished Aug 19 04:28:49 PM PDT 24
Peak memory 206084 kb
Host smart-eafba8fa-4351-4ac4-84b9-8d43cd488772
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896718243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3896718243
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4145222754
Short name T1008
Test name
Test status
Simulation time 36866500 ps
CPU time 0.81 seconds
Started Aug 19 04:28:48 PM PDT 24
Finished Aug 19 04:28:49 PM PDT 24
Peak memory 206040 kb
Host smart-654104bf-b013-480d-b447-563147f4fb3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145222754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4145222754
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1959685230
Short name T926
Test name
Test status
Simulation time 74719961 ps
CPU time 1.3 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 206404 kb
Host smart-ee5017c2-3fe6-405c-91e8-cea912411b8a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959685230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.1959685230
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2494491021
Short name T72
Test name
Test status
Simulation time 150640206 ps
CPU time 1.88 seconds
Started Aug 19 04:28:45 PM PDT 24
Finished Aug 19 04:28:47 PM PDT 24
Peak memory 214804 kb
Host smart-93f31632-3702-4b2c-8a22-77ae4149ef24
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494491021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2494491021
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1612246803
Short name T993
Test name
Test status
Simulation time 1561986702 ps
CPU time 10.39 seconds
Started Aug 19 04:28:55 PM PDT 24
Finished Aug 19 04:29:06 PM PDT 24
Peak memory 220916 kb
Host smart-7b60cdf4-3b7a-4d11-b272-1cd97947a11e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612246803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1612246803
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2849729363
Short name T1037
Test name
Test status
Simulation time 122005855 ps
CPU time 3.88 seconds
Started Aug 19 04:28:48 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 217700 kb
Host smart-48b40e0b-25e9-4c76-bc35-203dbfa4cc66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849729363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2849729363
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2896193289
Short name T153
Test name
Test status
Simulation time 191501683 ps
CPU time 2.97 seconds
Started Aug 19 04:28:53 PM PDT 24
Finished Aug 19 04:28:56 PM PDT 24
Peak memory 214440 kb
Host smart-c05ef34e-8570-4190-b8fb-3a5714025b73
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896193289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2896193289
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.4113589833
Short name T1045
Test name
Test status
Simulation time 35952325 ps
CPU time 0.82 seconds
Started Aug 19 04:29:26 PM PDT 24
Finished Aug 19 04:29:26 PM PDT 24
Peak memory 206032 kb
Host smart-eae7e184-9269-428e-9394-8a09dadb9eaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113589833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.4113589833
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.3191800583
Short name T981
Test name
Test status
Simulation time 31502438 ps
CPU time 0.78 seconds
Started Aug 19 04:29:22 PM PDT 24
Finished Aug 19 04:29:23 PM PDT 24
Peak memory 205988 kb
Host smart-246691b2-0aed-46cb-b5f9-1b39eace2e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191800583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.3191800583
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1814926806
Short name T1073
Test name
Test status
Simulation time 49116872 ps
CPU time 0.88 seconds
Started Aug 19 04:29:06 PM PDT 24
Finished Aug 19 04:29:07 PM PDT 24
Peak memory 206056 kb
Host smart-31521480-bfc5-4ba9-8016-59be40c2f001
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814926806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1814926806
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2394816829
Short name T1027
Test name
Test status
Simulation time 13263617 ps
CPU time 0.8 seconds
Started Aug 19 04:29:17 PM PDT 24
Finished Aug 19 04:29:23 PM PDT 24
Peak memory 205960 kb
Host smart-d9dc5fe8-a103-4da7-92c1-d0847985ef31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394816829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2394816829
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.4202381302
Short name T988
Test name
Test status
Simulation time 35776403 ps
CPU time 0.83 seconds
Started Aug 19 04:29:16 PM PDT 24
Finished Aug 19 04:29:17 PM PDT 24
Peak memory 205988 kb
Host smart-7eaf98a4-7071-4852-ba68-3b54dff5c468
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202381302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.4202381302
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.467336520
Short name T938
Test name
Test status
Simulation time 8447508 ps
CPU time 0.77 seconds
Started Aug 19 04:29:08 PM PDT 24
Finished Aug 19 04:29:09 PM PDT 24
Peak memory 206056 kb
Host smart-45ae4fa6-ce9e-4948-951b-6bccae25d8e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467336520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.467336520
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2817729973
Short name T1006
Test name
Test status
Simulation time 84932212 ps
CPU time 0.7 seconds
Started Aug 19 04:29:06 PM PDT 24
Finished Aug 19 04:29:07 PM PDT 24
Peak memory 206120 kb
Host smart-b50b0e82-d2e4-4c03-9303-768495fe531c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817729973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2817729973
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3736369703
Short name T954
Test name
Test status
Simulation time 8550762 ps
CPU time 0.76 seconds
Started Aug 19 04:29:09 PM PDT 24
Finished Aug 19 04:29:10 PM PDT 24
Peak memory 205972 kb
Host smart-973250b9-1038-46cb-a842-7b86d833d724
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736369703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3736369703
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.322408188
Short name T1000
Test name
Test status
Simulation time 25914079 ps
CPU time 0.85 seconds
Started Aug 19 04:29:31 PM PDT 24
Finished Aug 19 04:29:32 PM PDT 24
Peak memory 206124 kb
Host smart-5ef85426-db5b-4762-bb59-a1b4867eec8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322408188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.322408188
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.204801957
Short name T963
Test name
Test status
Simulation time 69248618 ps
CPU time 0.79 seconds
Started Aug 19 04:29:12 PM PDT 24
Finished Aug 19 04:29:13 PM PDT 24
Peak memory 206032 kb
Host smart-c2f501b6-fa61-4a95-87b2-733e059063a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204801957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.204801957
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3165993703
Short name T169
Test name
Test status
Simulation time 1065246389 ps
CPU time 9.61 seconds
Started Aug 19 04:28:40 PM PDT 24
Finished Aug 19 04:28:49 PM PDT 24
Peak memory 206360 kb
Host smart-9c3ecd37-18d1-4688-9d07-a3f12d1aaec8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165993703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
165993703
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3311531447
Short name T1064
Test name
Test status
Simulation time 542154474 ps
CPU time 11.2 seconds
Started Aug 19 04:28:58 PM PDT 24
Finished Aug 19 04:29:10 PM PDT 24
Peak memory 206372 kb
Host smart-1679db16-a5bd-4235-a08d-a07785ff17f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311531447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
311531447
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.295000616
Short name T1018
Test name
Test status
Simulation time 32370801 ps
CPU time 1.13 seconds
Started Aug 19 04:28:58 PM PDT 24
Finished Aug 19 04:28:59 PM PDT 24
Peak memory 206268 kb
Host smart-ccd93971-343f-43a7-a23d-2347d91901fa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295000616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.295000616
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3026611157
Short name T930
Test name
Test status
Simulation time 88669837 ps
CPU time 1.71 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 222640 kb
Host smart-a698f323-5780-4c88-b276-3d33e04f5848
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026611157 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3026611157
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3916538164
Short name T1070
Test name
Test status
Simulation time 34584027 ps
CPU time 1.23 seconds
Started Aug 19 04:28:43 PM PDT 24
Finished Aug 19 04:28:44 PM PDT 24
Peak memory 206212 kb
Host smart-d7262dfc-1374-4b0b-90f2-a265c79deb12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916538164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3916538164
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2642698420
Short name T937
Test name
Test status
Simulation time 53572547 ps
CPU time 0.76 seconds
Started Aug 19 04:28:57 PM PDT 24
Finished Aug 19 04:28:58 PM PDT 24
Peak memory 206096 kb
Host smart-7b491bc6-6c7e-4eeb-9eb5-e6ed4987f1d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642698420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2642698420
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2123275846
Short name T922
Test name
Test status
Simulation time 87289072 ps
CPU time 1.36 seconds
Started Aug 19 04:28:56 PM PDT 24
Finished Aug 19 04:28:57 PM PDT 24
Peak memory 206288 kb
Host smart-7aedba04-2f65-4804-b76a-2fc47d1e3ecf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123275846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2123275846
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2907770328
Short name T68
Test name
Test status
Simulation time 224692901 ps
CPU time 3.17 seconds
Started Aug 19 04:28:42 PM PDT 24
Finished Aug 19 04:28:45 PM PDT 24
Peak memory 214888 kb
Host smart-6c349190-57a1-4419-9011-f14c0fff574a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907770328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2907770328
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2165876120
Short name T66
Test name
Test status
Simulation time 250253879 ps
CPU time 5.08 seconds
Started Aug 19 04:28:39 PM PDT 24
Finished Aug 19 04:28:45 PM PDT 24
Peak memory 220784 kb
Host smart-788cf1e1-a5d2-4d65-b645-9d7b1e4cdb3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165876120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2165876120
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.597721270
Short name T975
Test name
Test status
Simulation time 84378901 ps
CPU time 2.59 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 214624 kb
Host smart-7c72f43e-3253-4e2a-aae2-ad713a3448bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597721270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.597721270
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3484089889
Short name T1025
Test name
Test status
Simulation time 48443375 ps
CPU time 0.92 seconds
Started Aug 19 04:29:16 PM PDT 24
Finished Aug 19 04:29:17 PM PDT 24
Peak memory 206116 kb
Host smart-2bf7dcee-bb75-4998-a634-5bd8d3216884
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484089889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3484089889
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3754456196
Short name T1044
Test name
Test status
Simulation time 49440037 ps
CPU time 0.68 seconds
Started Aug 19 04:29:29 PM PDT 24
Finished Aug 19 04:29:29 PM PDT 24
Peak memory 206040 kb
Host smart-4db52d36-7ff5-4b7d-8417-c270c3dc1f5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754456196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3754456196
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.58053235
Short name T1043
Test name
Test status
Simulation time 22329006 ps
CPU time 0.71 seconds
Started Aug 19 04:29:21 PM PDT 24
Finished Aug 19 04:29:22 PM PDT 24
Peak memory 206116 kb
Host smart-dfd060f9-a530-43fc-a5f3-81e6efe582e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58053235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.58053235
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1709679949
Short name T1051
Test name
Test status
Simulation time 69796122 ps
CPU time 0.75 seconds
Started Aug 19 04:29:27 PM PDT 24
Finished Aug 19 04:29:28 PM PDT 24
Peak memory 206012 kb
Host smart-aba89830-d237-497a-a9e1-63221b52fde6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709679949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1709679949
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2619313735
Short name T995
Test name
Test status
Simulation time 9965158 ps
CPU time 0.8 seconds
Started Aug 19 04:29:28 PM PDT 24
Finished Aug 19 04:29:29 PM PDT 24
Peak memory 206116 kb
Host smart-55e4b59d-2d3c-4b55-9113-bb3db9779a04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619313735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2619313735
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3259815726
Short name T917
Test name
Test status
Simulation time 49383653 ps
CPU time 0.85 seconds
Started Aug 19 04:29:21 PM PDT 24
Finished Aug 19 04:29:22 PM PDT 24
Peak memory 205936 kb
Host smart-c5a3a42a-d282-47d2-a737-8f7f2e33ce2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259815726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3259815726
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3214322990
Short name T1011
Test name
Test status
Simulation time 43107893 ps
CPU time 0.75 seconds
Started Aug 19 04:29:25 PM PDT 24
Finished Aug 19 04:29:26 PM PDT 24
Peak memory 206012 kb
Host smart-5ba4c373-91c2-4af3-91e1-e74d8b1850bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214322990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3214322990
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3707058
Short name T919
Test name
Test status
Simulation time 40599897 ps
CPU time 0.71 seconds
Started Aug 19 04:29:09 PM PDT 24
Finished Aug 19 04:29:10 PM PDT 24
Peak memory 206060 kb
Host smart-9fc0169a-a0e8-46e4-84b9-129b6f6a5d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3707058
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1615173515
Short name T928
Test name
Test status
Simulation time 31108337 ps
CPU time 0.68 seconds
Started Aug 19 04:29:11 PM PDT 24
Finished Aug 19 04:29:12 PM PDT 24
Peak memory 205960 kb
Host smart-b923f89a-9f7b-419b-b256-e77cec10229b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615173515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1615173515
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3801620341
Short name T987
Test name
Test status
Simulation time 29556807 ps
CPU time 0.75 seconds
Started Aug 19 04:29:10 PM PDT 24
Finished Aug 19 04:29:11 PM PDT 24
Peak memory 206132 kb
Host smart-4dc097f2-7a28-409c-ab55-d2be36d3c63e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801620341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3801620341
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.458552361
Short name T144
Test name
Test status
Simulation time 406983656 ps
CPU time 4.65 seconds
Started Aug 19 04:29:04 PM PDT 24
Finished Aug 19 04:29:09 PM PDT 24
Peak memory 206332 kb
Host smart-d8d5a3ef-4181-42eb-a2a6-d512d49742b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458552361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.458552361
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.4253787110
Short name T959
Test name
Test status
Simulation time 2701045039 ps
CPU time 16.17 seconds
Started Aug 19 04:28:57 PM PDT 24
Finished Aug 19 04:29:13 PM PDT 24
Peak memory 206396 kb
Host smart-17c88a17-6448-4099-8beb-5cbb1f731aa4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253787110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.4
253787110
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1965323304
Short name T935
Test name
Test status
Simulation time 48515479 ps
CPU time 1.14 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:04 PM PDT 24
Peak memory 206224 kb
Host smart-e928a1ca-be12-46d0-806b-ae0a2734d396
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965323304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
965323304
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.691441708
Short name T1059
Test name
Test status
Simulation time 18717084 ps
CPU time 1.21 seconds
Started Aug 19 04:28:52 PM PDT 24
Finished Aug 19 04:28:53 PM PDT 24
Peak memory 214672 kb
Host smart-516e788c-6b61-4c97-a467-ddc6eef4d5e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691441708 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.691441708
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3871787294
Short name T1057
Test name
Test status
Simulation time 34769062 ps
CPU time 1 seconds
Started Aug 19 04:29:00 PM PDT 24
Finished Aug 19 04:29:02 PM PDT 24
Peak memory 206172 kb
Host smart-63aa27d3-5330-4402-81dc-a57e481b2951
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871787294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3871787294
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.183711022
Short name T1076
Test name
Test status
Simulation time 45529661 ps
CPU time 0.67 seconds
Started Aug 19 04:28:48 PM PDT 24
Finished Aug 19 04:28:48 PM PDT 24
Peak memory 206032 kb
Host smart-59718950-a203-4eff-a31c-fedb1534877d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=183711022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.183711022
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.687466052
Short name T89
Test name
Test status
Simulation time 101939560 ps
CPU time 2.49 seconds
Started Aug 19 04:29:02 PM PDT 24
Finished Aug 19 04:29:04 PM PDT 24
Peak memory 206292 kb
Host smart-ac9797b0-8e0b-4480-a846-6da56313327c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687466052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.687466052
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2788593639
Short name T985
Test name
Test status
Simulation time 478087371 ps
CPU time 2.41 seconds
Started Aug 19 04:29:01 PM PDT 24
Finished Aug 19 04:29:04 PM PDT 24
Peak memory 214936 kb
Host smart-f2c4eb38-20d4-4cf2-b550-0c19407277a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788593639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2788593639
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.3943614601
Short name T983
Test name
Test status
Simulation time 247513177 ps
CPU time 7.36 seconds
Started Aug 19 04:28:41 PM PDT 24
Finished Aug 19 04:28:49 PM PDT 24
Peak memory 214816 kb
Host smart-8d2dc3c8-3c3d-4688-9323-3caa98abc99d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943614601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.3943614601
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.578293421
Short name T932
Test name
Test status
Simulation time 610346009 ps
CPU time 3.36 seconds
Started Aug 19 04:28:48 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 214596 kb
Host smart-ce77a2ac-f9f8-43a5-a1d5-c990dfd3f272
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578293421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.578293421
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3880597277
Short name T154
Test name
Test status
Simulation time 186978852 ps
CPU time 4.43 seconds
Started Aug 19 04:28:48 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 206324 kb
Host smart-d94e8952-725c-43a6-8803-bcabdeea080b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880597277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3880597277
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3164450954
Short name T974
Test name
Test status
Simulation time 146325966 ps
CPU time 0.72 seconds
Started Aug 19 04:29:13 PM PDT 24
Finished Aug 19 04:29:14 PM PDT 24
Peak memory 206044 kb
Host smart-31a87e93-005e-41ec-bd64-811483c138b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164450954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3164450954
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2725078971
Short name T939
Test name
Test status
Simulation time 13737324 ps
CPU time 0.69 seconds
Started Aug 19 04:29:08 PM PDT 24
Finished Aug 19 04:29:09 PM PDT 24
Peak memory 206132 kb
Host smart-0a997cf8-746b-40fe-81ae-4ec05ea34242
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725078971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2725078971
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3615920008
Short name T965
Test name
Test status
Simulation time 51655631 ps
CPU time 0.7 seconds
Started Aug 19 04:29:13 PM PDT 24
Finished Aug 19 04:29:14 PM PDT 24
Peak memory 206124 kb
Host smart-a81b8512-9ee2-4ce9-8b1f-1f32aac99c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615920008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3615920008
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.3410403226
Short name T1026
Test name
Test status
Simulation time 29258810 ps
CPU time 0.69 seconds
Started Aug 19 04:29:24 PM PDT 24
Finished Aug 19 04:29:25 PM PDT 24
Peak memory 206000 kb
Host smart-133b1c36-5dc6-43ec-9bcb-e0cf9108391e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410403226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.3410403226
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2208153408
Short name T923
Test name
Test status
Simulation time 64929775 ps
CPU time 0.71 seconds
Started Aug 19 04:29:21 PM PDT 24
Finished Aug 19 04:29:22 PM PDT 24
Peak memory 206032 kb
Host smart-5b6d12c9-b3cd-46c1-b4bb-26348182ce72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208153408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2208153408
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1587238525
Short name T918
Test name
Test status
Simulation time 120571440 ps
CPU time 0.82 seconds
Started Aug 19 04:29:10 PM PDT 24
Finished Aug 19 04:29:11 PM PDT 24
Peak memory 206056 kb
Host smart-400a157f-080a-4aaa-9895-6d9ae4c9e19c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587238525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1587238525
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2492810319
Short name T972
Test name
Test status
Simulation time 17997494 ps
CPU time 0.8 seconds
Started Aug 19 04:29:22 PM PDT 24
Finished Aug 19 04:29:23 PM PDT 24
Peak memory 205964 kb
Host smart-cc43727a-f667-40d7-bb79-46f5aa8626a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492810319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2492810319
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1949616938
Short name T1060
Test name
Test status
Simulation time 51765703 ps
CPU time 0.78 seconds
Started Aug 19 04:29:08 PM PDT 24
Finished Aug 19 04:29:09 PM PDT 24
Peak memory 206052 kb
Host smart-a8da0326-5119-4d59-acf0-b8958cc2cdb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949616938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1949616938
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.364866640
Short name T955
Test name
Test status
Simulation time 39455336 ps
CPU time 0.76 seconds
Started Aug 19 04:29:32 PM PDT 24
Finished Aug 19 04:29:33 PM PDT 24
Peak memory 205956 kb
Host smart-07c728af-ff19-4d5b-9ad4-6e4dbc3375de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364866640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.364866640
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.952649489
Short name T1010
Test name
Test status
Simulation time 90995980 ps
CPU time 0.73 seconds
Started Aug 19 04:29:15 PM PDT 24
Finished Aug 19 04:29:16 PM PDT 24
Peak memory 205964 kb
Host smart-8ead6175-0afc-4661-bbf6-b3f4f5e9d011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952649489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.952649489
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.676263998
Short name T973
Test name
Test status
Simulation time 46624032 ps
CPU time 1.99 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 217216 kb
Host smart-af7b7ca5-8c8f-4b1f-b5d9-27a12c6cc9c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=676263998 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.676263998
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.62536401
Short name T967
Test name
Test status
Simulation time 12159747 ps
CPU time 0.95 seconds
Started Aug 19 04:29:06 PM PDT 24
Finished Aug 19 04:29:07 PM PDT 24
Peak memory 206176 kb
Host smart-ef1591d4-5d53-480f-a29a-4136f166f9f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62536401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.62536401
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1382961575
Short name T1074
Test name
Test status
Simulation time 7294791 ps
CPU time 0.73 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:04 PM PDT 24
Peak memory 206008 kb
Host smart-4427f206-6102-49f1-9352-95e5ce64a4d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382961575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1382961575
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3877936966
Short name T996
Test name
Test status
Simulation time 79961068 ps
CPU time 2.82 seconds
Started Aug 19 04:28:58 PM PDT 24
Finished Aug 19 04:29:01 PM PDT 24
Peak memory 206292 kb
Host smart-a5f4afd4-6076-4847-9358-2db17c64fdac
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877936966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3877936966
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1663078136
Short name T946
Test name
Test status
Simulation time 1250927637 ps
CPU time 2.24 seconds
Started Aug 19 04:28:56 PM PDT 24
Finished Aug 19 04:28:58 PM PDT 24
Peak memory 214888 kb
Host smart-af2ef56e-6733-4692-9a44-5cb66e4b1668
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663078136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1663078136
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.4004184748
Short name T1042
Test name
Test status
Simulation time 1160677753 ps
CPU time 4.6 seconds
Started Aug 19 04:29:02 PM PDT 24
Finished Aug 19 04:29:07 PM PDT 24
Peak memory 223060 kb
Host smart-2f7857af-a657-4cba-b118-009b1f9aa117
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004184748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.4004184748
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3100734944
Short name T925
Test name
Test status
Simulation time 182678542 ps
CPU time 2.46 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 214440 kb
Host smart-070f3211-85ba-4838-bc9c-6b9c56cff8be
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100734944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3100734944
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1091751391
Short name T1001
Test name
Test status
Simulation time 107739873 ps
CPU time 1.5 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 214464 kb
Host smart-5df40fb5-7848-4c80-bb8b-4a7fd5f2c943
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091751391 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1091751391
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2888843092
Short name T1039
Test name
Test status
Simulation time 28208016 ps
CPU time 1.5 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:53 PM PDT 24
Peak memory 206280 kb
Host smart-e04d83f5-6928-4fe1-affd-d6ea4c8ba6e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888843092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2888843092
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.609797686
Short name T1071
Test name
Test status
Simulation time 19745487 ps
CPU time 0.76 seconds
Started Aug 19 04:29:02 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 206120 kb
Host smart-d75e839d-20f2-449b-8455-bcf41551e8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609797686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.609797686
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.695965484
Short name T1038
Test name
Test status
Simulation time 81352992 ps
CPU time 1.62 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 206224 kb
Host smart-b7a0d5b8-bf01-4c36-a2cd-00ab75bec7ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695965484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.695965484
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1269913774
Short name T936
Test name
Test status
Simulation time 476429143 ps
CPU time 3.6 seconds
Started Aug 19 04:29:04 PM PDT 24
Finished Aug 19 04:29:08 PM PDT 24
Peak memory 214776 kb
Host smart-31928e90-fdbf-481f-ae5b-b9dc854e391a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269913774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1269913774
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1774235899
Short name T999
Test name
Test status
Simulation time 760217957 ps
CPU time 4.57 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:08 PM PDT 24
Peak memory 214784 kb
Host smart-b25f2ded-5da4-4ac6-bd63-563e835da8c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774235899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.1774235899
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.4215887477
Short name T1079
Test name
Test status
Simulation time 175352273 ps
CPU time 3.29 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 214548 kb
Host smart-51b9eda3-b4ab-4f51-a81a-5dc2da9b0f37
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215887477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.4215887477
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.206399851
Short name T150
Test name
Test status
Simulation time 92018955 ps
CPU time 3.65 seconds
Started Aug 19 04:28:59 PM PDT 24
Finished Aug 19 04:29:03 PM PDT 24
Peak memory 214584 kb
Host smart-6cd1a64f-c424-4ec5-93f7-c896b55ba3ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206399851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.
206399851
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2038543905
Short name T942
Test name
Test status
Simulation time 120075577 ps
CPU time 1.24 seconds
Started Aug 19 04:28:55 PM PDT 24
Finished Aug 19 04:28:56 PM PDT 24
Peak memory 206288 kb
Host smart-4edc34a6-034e-476c-b2db-67bbffac382e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038543905 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2038543905
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2241289063
Short name T1005
Test name
Test status
Simulation time 45140750 ps
CPU time 0.95 seconds
Started Aug 19 04:29:06 PM PDT 24
Finished Aug 19 04:29:07 PM PDT 24
Peak memory 206188 kb
Host smart-b8bedec1-f2d1-4b9c-89f2-4f97060d8b20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241289063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2241289063
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2456996690
Short name T1081
Test name
Test status
Simulation time 25323346 ps
CPU time 0.83 seconds
Started Aug 19 04:29:04 PM PDT 24
Finished Aug 19 04:29:05 PM PDT 24
Peak memory 205884 kb
Host smart-749564b8-e828-46fa-a30b-a796eac8d9cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456996690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2456996690
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2839325108
Short name T1050
Test name
Test status
Simulation time 318979933 ps
CPU time 1.88 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:05 PM PDT 24
Peak memory 206456 kb
Host smart-709e3561-6499-4926-ac53-5697534cd5ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839325108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2839325108
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.351189776
Short name T998
Test name
Test status
Simulation time 557248755 ps
CPU time 3.1 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:54 PM PDT 24
Peak memory 214812 kb
Host smart-e8ed0e93-458a-419f-b0d9-e9930a301dce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351189776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.351189776
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.4018121534
Short name T956
Test name
Test status
Simulation time 648694774 ps
CPU time 4.38 seconds
Started Aug 19 04:29:02 PM PDT 24
Finished Aug 19 04:29:07 PM PDT 24
Peak memory 214936 kb
Host smart-bd289219-4bcc-4e44-824f-27a5996e9b59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018121534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.4018121534
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1208985906
Short name T991
Test name
Test status
Simulation time 588498763 ps
CPU time 5.44 seconds
Started Aug 19 04:28:59 PM PDT 24
Finished Aug 19 04:29:05 PM PDT 24
Peak memory 214524 kb
Host smart-ec3c6119-51b7-42d8-ab8f-b239c3ac2e3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208985906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1208985906
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.999428131
Short name T152
Test name
Test status
Simulation time 64428708 ps
CPU time 3.52 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:06 PM PDT 24
Peak memory 214428 kb
Host smart-e213a7fd-cc0a-467c-8bfe-0a8fd340a5b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999428131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
999428131
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2196740431
Short name T1054
Test name
Test status
Simulation time 213782247 ps
CPU time 1.51 seconds
Started Aug 19 04:29:03 PM PDT 24
Finished Aug 19 04:29:05 PM PDT 24
Peak memory 214620 kb
Host smart-ad9d5776-0c5e-4059-a03c-fe9995f58a12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196740431 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2196740431
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.3977706572
Short name T1041
Test name
Test status
Simulation time 10263028 ps
CPU time 1.1 seconds
Started Aug 19 04:28:51 PM PDT 24
Finished Aug 19 04:28:53 PM PDT 24
Peak memory 206348 kb
Host smart-1dd2eae9-9b8c-423a-8f91-fb2480de97dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977706572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.3977706572
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1983728376
Short name T950
Test name
Test status
Simulation time 9977343 ps
CPU time 0.81 seconds
Started Aug 19 04:29:05 PM PDT 24
Finished Aug 19 04:29:05 PM PDT 24
Peak memory 206164 kb
Host smart-86583685-d13d-41a4-b02a-786a4dccdef4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983728376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1983728376
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.956963456
Short name T1014
Test name
Test status
Simulation time 98673581 ps
CPU time 1.51 seconds
Started Aug 19 04:29:02 PM PDT 24
Finished Aug 19 04:29:13 PM PDT 24
Peak memory 206400 kb
Host smart-a6c2b26e-cfa1-4756-800b-d95e896802d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956963456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.956963456
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2337760315
Short name T1056
Test name
Test status
Simulation time 186575961 ps
CPU time 4.36 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:54 PM PDT 24
Peak memory 219504 kb
Host smart-ecbe8895-9013-43d4-881f-0a2c488ff02e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337760315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2337760315
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.601805490
Short name T73
Test name
Test status
Simulation time 1454035825 ps
CPU time 8.78 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:58 PM PDT 24
Peak memory 214856 kb
Host smart-b7dd3ea9-adaf-4927-b49e-42d51cc40910
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601805490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.601805490
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3280303767
Short name T1017
Test name
Test status
Simulation time 75609395 ps
CPU time 2.62 seconds
Started Aug 19 04:29:02 PM PDT 24
Finished Aug 19 04:29:05 PM PDT 24
Peak memory 214608 kb
Host smart-3c9fdde4-ad3d-40c2-b825-8df5568cb59d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280303767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3280303767
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2373236159
Short name T159
Test name
Test status
Simulation time 99086913 ps
CPU time 2.67 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 214584 kb
Host smart-d445f5f1-ecc3-4c9d-a090-4e5211c8af9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373236159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2373236159
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2803274102
Short name T1077
Test name
Test status
Simulation time 62730086 ps
CPU time 1.42 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 214512 kb
Host smart-9dd3bbc8-40cd-4f00-bf1b-e276460a58d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803274102 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2803274102
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.405256899
Short name T1024
Test name
Test status
Simulation time 26226329 ps
CPU time 1.35 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:51 PM PDT 24
Peak memory 206212 kb
Host smart-040cf944-3c55-482e-8241-f20b625ec45a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405256899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.405256899
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.641096324
Short name T1052
Test name
Test status
Simulation time 42781428 ps
CPU time 0.77 seconds
Started Aug 19 04:29:01 PM PDT 24
Finished Aug 19 04:29:02 PM PDT 24
Peak memory 206012 kb
Host smart-c8460664-25a2-41ea-bf2b-f83053e72135
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641096324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.641096324
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.889276951
Short name T943
Test name
Test status
Simulation time 178827520 ps
CPU time 2.32 seconds
Started Aug 19 04:28:57 PM PDT 24
Finished Aug 19 04:28:59 PM PDT 24
Peak memory 206236 kb
Host smart-e654bb90-3a7b-4b4d-9a7b-ef7220aaeb01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889276951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.889276951
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2828380364
Short name T949
Test name
Test status
Simulation time 168481999 ps
CPU time 1.87 seconds
Started Aug 19 04:28:52 PM PDT 24
Finished Aug 19 04:28:54 PM PDT 24
Peak memory 214896 kb
Host smart-56628fd5-17bb-4d93-acc8-82e611429eb0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828380364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2828380364
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1562049761
Short name T994
Test name
Test status
Simulation time 98151233 ps
CPU time 4.73 seconds
Started Aug 19 04:29:00 PM PDT 24
Finished Aug 19 04:29:04 PM PDT 24
Peak memory 220800 kb
Host smart-8a011f72-6826-490e-931a-d6f4a9d8883c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562049761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1562049761
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.4120249697
Short name T1053
Test name
Test status
Simulation time 301544223 ps
CPU time 2.75 seconds
Started Aug 19 04:28:49 PM PDT 24
Finished Aug 19 04:28:52 PM PDT 24
Peak memory 222772 kb
Host smart-a0d3a00c-e82f-4952-b5de-f8828a9b9641
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120249697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.4120249697
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.967463094
Short name T147
Test name
Test status
Simulation time 126099951 ps
CPU time 3.4 seconds
Started Aug 19 04:28:50 PM PDT 24
Finished Aug 19 04:28:54 PM PDT 24
Peak memory 206424 kb
Host smart-74080840-a3d0-4a5b-9218-9a03565d16d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967463094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
967463094
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1277266963
Short name T690
Test name
Test status
Simulation time 27343711 ps
CPU time 0.77 seconds
Started Aug 19 05:39:39 PM PDT 24
Finished Aug 19 05:39:40 PM PDT 24
Peak memory 206396 kb
Host smart-b82f8eab-032b-457e-873f-d4b7198cb3b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277266963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1277266963
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3607596024
Short name T366
Test name
Test status
Simulation time 25417022 ps
CPU time 1.97 seconds
Started Aug 19 05:39:49 PM PDT 24
Finished Aug 19 05:39:51 PM PDT 24
Peak memory 214804 kb
Host smart-87354c34-f0e1-4e80-b51e-2bb78c46f90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607596024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3607596024
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3620466214
Short name T715
Test name
Test status
Simulation time 66294990 ps
CPU time 2 seconds
Started Aug 19 05:39:40 PM PDT 24
Finished Aug 19 05:39:42 PM PDT 24
Peak memory 215052 kb
Host smart-16fad075-295e-4fc7-8963-bacdebcffd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620466214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3620466214
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2734022154
Short name T99
Test name
Test status
Simulation time 97524478 ps
CPU time 4.96 seconds
Started Aug 19 05:39:40 PM PDT 24
Finished Aug 19 05:39:45 PM PDT 24
Peak memory 222908 kb
Host smart-ae9dca15-1c63-45de-9d50-23e4f50bb5a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734022154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2734022154
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2571483995
Short name T828
Test name
Test status
Simulation time 230859032 ps
CPU time 6.92 seconds
Started Aug 19 05:39:49 PM PDT 24
Finished Aug 19 05:39:56 PM PDT 24
Peak memory 209072 kb
Host smart-ac1fb2aa-8657-4115-9351-56e723d7dace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571483995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2571483995
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2151561416
Short name T9
Test name
Test status
Simulation time 1227643653 ps
CPU time 7.18 seconds
Started Aug 19 05:39:43 PM PDT 24
Finished Aug 19 05:39:50 PM PDT 24
Peak memory 229868 kb
Host smart-0b7f8bbe-5a4b-47a7-94ef-67623cadc534
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151561416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2151561416
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2523308995
Short name T654
Test name
Test status
Simulation time 206185785 ps
CPU time 5.64 seconds
Started Aug 19 05:39:49 PM PDT 24
Finished Aug 19 05:39:55 PM PDT 24
Peak memory 208376 kb
Host smart-d7eaa266-829a-49b8-9e80-f9655a5178c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523308995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2523308995
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.774940102
Short name T469
Test name
Test status
Simulation time 440688033 ps
CPU time 2.65 seconds
Started Aug 19 05:39:45 PM PDT 24
Finished Aug 19 05:39:48 PM PDT 24
Peak memory 207400 kb
Host smart-3aaf6f9d-5699-490a-837c-19b88f059c0c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774940102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.774940102
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2233995711
Short name T174
Test name
Test status
Simulation time 298682770 ps
CPU time 3.9 seconds
Started Aug 19 05:39:44 PM PDT 24
Finished Aug 19 05:39:48 PM PDT 24
Peak memory 207252 kb
Host smart-a2ab42c2-82e6-4c87-a13b-ff8bb8852b59
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233995711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2233995711
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.1465338267
Short name T218
Test name
Test status
Simulation time 76341528 ps
CPU time 2.7 seconds
Started Aug 19 05:39:45 PM PDT 24
Finished Aug 19 05:39:48 PM PDT 24
Peak memory 209156 kb
Host smart-7b6ca75d-a68a-4f4c-a057-d8a13427764d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465338267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1465338267
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2150747588
Short name T241
Test name
Test status
Simulation time 126486779 ps
CPU time 2.53 seconds
Started Aug 19 05:39:44 PM PDT 24
Finished Aug 19 05:39:47 PM PDT 24
Peak memory 222948 kb
Host smart-064412de-4cce-422a-b9fb-78ce91d4baac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150747588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2150747588
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.653458539
Short name T591
Test name
Test status
Simulation time 620604333 ps
CPU time 2.52 seconds
Started Aug 19 05:39:45 PM PDT 24
Finished Aug 19 05:39:47 PM PDT 24
Peak memory 208928 kb
Host smart-fe80d05c-2a9a-4bb8-a5fc-4ba23f46f072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653458539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.653458539
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1323735211
Short name T813
Test name
Test status
Simulation time 928589605 ps
CPU time 9.57 seconds
Started Aug 19 05:39:42 PM PDT 24
Finished Aug 19 05:39:52 PM PDT 24
Peak memory 221240 kb
Host smart-1531deeb-af4f-489c-bcf1-0b611cc26d87
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323735211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1323735211
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2886317834
Short name T79
Test name
Test status
Simulation time 146479894 ps
CPU time 9.12 seconds
Started Aug 19 05:39:41 PM PDT 24
Finished Aug 19 05:39:50 PM PDT 24
Peak memory 223008 kb
Host smart-fc9a9adc-b912-4434-bdd2-21dd9609975c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886317834 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2886317834
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2539285489
Short name T245
Test name
Test status
Simulation time 236408599 ps
CPU time 3.77 seconds
Started Aug 19 05:39:43 PM PDT 24
Finished Aug 19 05:39:47 PM PDT 24
Peak memory 219816 kb
Host smart-b00d6bbe-0b49-4f90-8f16-fc39657f06fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539285489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2539285489
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3596567327
Short name T632
Test name
Test status
Simulation time 225270058 ps
CPU time 1.67 seconds
Started Aug 19 05:39:42 PM PDT 24
Finished Aug 19 05:39:44 PM PDT 24
Peak memory 210372 kb
Host smart-dfb5bca3-29a8-47fb-8521-7dbb94a27df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3596567327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3596567327
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3556197334
Short name T368
Test name
Test status
Simulation time 181845664 ps
CPU time 9.82 seconds
Started Aug 19 05:39:41 PM PDT 24
Finished Aug 19 05:39:52 PM PDT 24
Peak memory 214876 kb
Host smart-60179bc0-3b5b-434e-bcd0-95efd6bc05a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3556197334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3556197334
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1073556530
Short name T683
Test name
Test status
Simulation time 1138363304 ps
CPU time 4.27 seconds
Started Aug 19 05:39:49 PM PDT 24
Finished Aug 19 05:39:53 PM PDT 24
Peak memory 223220 kb
Host smart-8eefedd1-e425-4c10-b4ac-b970b627b5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073556530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1073556530
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.94088406
Short name T426
Test name
Test status
Simulation time 246985452 ps
CPU time 2.78 seconds
Started Aug 19 05:39:40 PM PDT 24
Finished Aug 19 05:39:43 PM PDT 24
Peak memory 210616 kb
Host smart-b143f4c7-5023-434d-a4a2-37a0ab8ad414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94088406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.94088406
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2967810861
Short name T696
Test name
Test status
Simulation time 1371234053 ps
CPU time 2.61 seconds
Started Aug 19 05:39:42 PM PDT 24
Finished Aug 19 05:39:45 PM PDT 24
Peak memory 214812 kb
Host smart-59cffc44-c35a-4903-9543-0ecae6b51ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967810861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2967810861
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2192766542
Short name T227
Test name
Test status
Simulation time 50806874 ps
CPU time 2.74 seconds
Started Aug 19 05:39:42 PM PDT 24
Finished Aug 19 05:39:45 PM PDT 24
Peak memory 214784 kb
Host smart-1a020a90-f4e8-43df-acee-f62752b9a38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192766542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2192766542
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.133233669
Short name T230
Test name
Test status
Simulation time 1136150222 ps
CPU time 4.89 seconds
Started Aug 19 05:39:41 PM PDT 24
Finished Aug 19 05:39:46 PM PDT 24
Peak memory 214820 kb
Host smart-fdc53ead-abdf-42e4-8397-0cfd3aa96172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133233669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.133233669
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.14708975
Short name T564
Test name
Test status
Simulation time 433845568 ps
CPU time 3.15 seconds
Started Aug 19 05:39:39 PM PDT 24
Finished Aug 19 05:39:42 PM PDT 24
Peak memory 208260 kb
Host smart-f17e4e69-46ba-450e-a0c8-efc79f53ea2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14708975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.14708975
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3387868761
Short name T657
Test name
Test status
Simulation time 448083463 ps
CPU time 9.02 seconds
Started Aug 19 05:39:42 PM PDT 24
Finished Aug 19 05:39:52 PM PDT 24
Peak memory 209544 kb
Host smart-733c9f0a-7e56-4c9f-b30e-a2a0f421c5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387868761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3387868761
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1949918001
Short name T701
Test name
Test status
Simulation time 494133455 ps
CPU time 6.92 seconds
Started Aug 19 05:39:43 PM PDT 24
Finished Aug 19 05:39:50 PM PDT 24
Peak memory 208336 kb
Host smart-3eaebafb-aaac-42db-9cc4-4aa46ab74c49
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949918001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1949918001
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3176408324
Short name T235
Test name
Test status
Simulation time 299352558 ps
CPU time 3.61 seconds
Started Aug 19 05:39:42 PM PDT 24
Finished Aug 19 05:39:46 PM PDT 24
Peak memory 209364 kb
Host smart-6417a659-5c0b-42ce-aaa6-c37813d28f03
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176408324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3176408324
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.623037728
Short name T487
Test name
Test status
Simulation time 704340525 ps
CPU time 16.49 seconds
Started Aug 19 05:39:45 PM PDT 24
Finished Aug 19 05:40:01 PM PDT 24
Peak memory 208556 kb
Host smart-fbc24ef9-4841-4f2f-8d11-968435d781cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623037728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.623037728
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2367574740
Short name T217
Test name
Test status
Simulation time 321202358 ps
CPU time 10.13 seconds
Started Aug 19 05:39:48 PM PDT 24
Finished Aug 19 05:39:59 PM PDT 24
Peak memory 208976 kb
Host smart-5f58f119-f9a3-4eed-87d9-b3166b691595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367574740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2367574740
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.666910237
Short name T872
Test name
Test status
Simulation time 165454700 ps
CPU time 3.32 seconds
Started Aug 19 05:39:44 PM PDT 24
Finished Aug 19 05:39:47 PM PDT 24
Peak memory 209344 kb
Host smart-65222551-5a49-4dba-86f8-9ee849fdb85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666910237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.666910237
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3548740609
Short name T192
Test name
Test status
Simulation time 12581704537 ps
CPU time 379.13 seconds
Started Aug 19 05:39:52 PM PDT 24
Finished Aug 19 05:46:11 PM PDT 24
Peak memory 217360 kb
Host smart-03ef6f7d-a6e2-4df7-8884-b4890390d4ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548740609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3548740609
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1028622127
Short name T171
Test name
Test status
Simulation time 376792568 ps
CPU time 4.66 seconds
Started Aug 19 05:39:48 PM PDT 24
Finished Aug 19 05:39:52 PM PDT 24
Peak memory 209808 kb
Host smart-8e97ec4c-f890-4032-ab1a-c76dddf85dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1028622127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1028622127
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3558627592
Short name T163
Test name
Test status
Simulation time 126024297 ps
CPU time 2.71 seconds
Started Aug 19 05:39:40 PM PDT 24
Finished Aug 19 05:39:43 PM PDT 24
Peak memory 210904 kb
Host smart-6ee96fbd-f3c0-46d6-a5ed-e4b4860fb4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558627592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3558627592
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1096466184
Short name T451
Test name
Test status
Simulation time 12928971 ps
CPU time 0.77 seconds
Started Aug 19 05:40:23 PM PDT 24
Finished Aug 19 05:40:24 PM PDT 24
Peak memory 206444 kb
Host smart-bcdb70e3-fb29-4b35-af88-9c570ea71e69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096466184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1096466184
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.261735302
Short name T331
Test name
Test status
Simulation time 231523213 ps
CPU time 13.1 seconds
Started Aug 19 05:40:24 PM PDT 24
Finished Aug 19 05:40:37 PM PDT 24
Peak memory 215768 kb
Host smart-c290cb26-9591-40cf-9d23-39dcde94bac8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=261735302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.261735302
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2892733921
Short name T125
Test name
Test status
Simulation time 203782556 ps
CPU time 1.78 seconds
Started Aug 19 05:40:26 PM PDT 24
Finished Aug 19 05:40:27 PM PDT 24
Peak memory 209348 kb
Host smart-fe50f9d1-1d8f-4956-b5c9-d95dc80cbb63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892733921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2892733921
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.427513786
Short name T129
Test name
Test status
Simulation time 284699943 ps
CPU time 7.05 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:38 PM PDT 24
Peak memory 207652 kb
Host smart-c93a39f9-ebc2-4539-b66a-d4745b798125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427513786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.427513786
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.796418868
Short name T695
Test name
Test status
Simulation time 135424404 ps
CPU time 4.16 seconds
Started Aug 19 05:40:24 PM PDT 24
Finished Aug 19 05:40:28 PM PDT 24
Peak memory 214784 kb
Host smart-eadb626b-7067-4762-89de-98cde01f8fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796418868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.796418868
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1338658310
Short name T278
Test name
Test status
Simulation time 99113219 ps
CPU time 2.9 seconds
Started Aug 19 05:40:22 PM PDT 24
Finished Aug 19 05:40:25 PM PDT 24
Peak memory 211944 kb
Host smart-e7fff809-ea5a-45d1-aeaa-636b1f01b914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338658310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1338658310
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1296108637
Short name T470
Test name
Test status
Simulation time 248527166 ps
CPU time 2.6 seconds
Started Aug 19 05:40:28 PM PDT 24
Finished Aug 19 05:40:30 PM PDT 24
Peak memory 209552 kb
Host smart-09e95f21-2dc8-4852-b720-6ae906c7bc63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296108637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1296108637
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2395039038
Short name T642
Test name
Test status
Simulation time 99084306 ps
CPU time 4.62 seconds
Started Aug 19 05:40:26 PM PDT 24
Finished Aug 19 05:40:31 PM PDT 24
Peak memory 210532 kb
Host smart-a7b4f141-306d-4f91-9a48-aba87bf24ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395039038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2395039038
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.909009790
Short name T589
Test name
Test status
Simulation time 412134203 ps
CPU time 7.55 seconds
Started Aug 19 05:40:15 PM PDT 24
Finished Aug 19 05:40:23 PM PDT 24
Peak memory 208568 kb
Host smart-c5133a2b-aabc-40f0-9547-f2d8eca270f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909009790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.909009790
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1755330939
Short name T542
Test name
Test status
Simulation time 66543679 ps
CPU time 3.46 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:34 PM PDT 24
Peak memory 207484 kb
Host smart-3abf35d5-6ab8-4ec0-b0ad-bb03b0f8dfd8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755330939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1755330939
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.4044372063
Short name T634
Test name
Test status
Simulation time 95258418 ps
CPU time 2.51 seconds
Started Aug 19 05:40:15 PM PDT 24
Finished Aug 19 05:40:18 PM PDT 24
Peak memory 207548 kb
Host smart-6397cec6-8462-434d-a2c7-12648cae0228
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044372063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.4044372063
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2596273611
Short name T352
Test name
Test status
Simulation time 59871742 ps
CPU time 3.1 seconds
Started Aug 19 05:40:26 PM PDT 24
Finished Aug 19 05:40:30 PM PDT 24
Peak memory 207424 kb
Host smart-3b5394f4-b52c-4319-9370-abb278dfeec9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596273611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2596273611
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1600961507
Short name T539
Test name
Test status
Simulation time 46468151 ps
CPU time 2.24 seconds
Started Aug 19 05:40:28 PM PDT 24
Finished Aug 19 05:40:30 PM PDT 24
Peak memory 208616 kb
Host smart-16614c5c-4186-4491-8714-3ec393089614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600961507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1600961507
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2981270510
Short name T504
Test name
Test status
Simulation time 63175947 ps
CPU time 3.12 seconds
Started Aug 19 05:40:15 PM PDT 24
Finished Aug 19 05:40:18 PM PDT 24
Peak memory 208868 kb
Host smart-d38fc0ec-1866-4f7f-bfae-08d1bcbcf8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981270510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2981270510
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3749592699
Short name T81
Test name
Test status
Simulation time 191527034 ps
CPU time 8.87 seconds
Started Aug 19 05:40:26 PM PDT 24
Finished Aug 19 05:40:35 PM PDT 24
Peak memory 222276 kb
Host smart-c6af0459-b3a2-4b2d-a31c-36e13514401f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749592699 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3749592699
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3255855023
Short name T499
Test name
Test status
Simulation time 1360899551 ps
CPU time 17.16 seconds
Started Aug 19 05:40:26 PM PDT 24
Finished Aug 19 05:40:44 PM PDT 24
Peak memory 209800 kb
Host smart-38ba2635-6aab-4d95-87f8-f6ea80911687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3255855023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3255855023
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3871259113
Short name T437
Test name
Test status
Simulation time 17603128 ps
CPU time 0.99 seconds
Started Aug 19 05:40:24 PM PDT 24
Finished Aug 19 05:40:25 PM PDT 24
Peak memory 206616 kb
Host smart-054fae43-04c9-45c1-aa98-dc6fcfe17297
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871259113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3871259113
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.868109046
Short name T123
Test name
Test status
Simulation time 2856488787 ps
CPU time 28.88 seconds
Started Aug 19 05:40:28 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 223372 kb
Host smart-f921c2bc-f489-4977-bb4c-719e9862f2a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868109046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.868109046
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3258416293
Short name T510
Test name
Test status
Simulation time 93191029 ps
CPU time 3.3 seconds
Started Aug 19 05:40:22 PM PDT 24
Finished Aug 19 05:40:25 PM PDT 24
Peak memory 215096 kb
Host smart-095b8a54-2fc1-443f-a1b8-77a39851609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258416293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3258416293
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.493944586
Short name T891
Test name
Test status
Simulation time 901518827 ps
CPU time 5.67 seconds
Started Aug 19 05:40:25 PM PDT 24
Finished Aug 19 05:40:30 PM PDT 24
Peak memory 209736 kb
Host smart-f19cb2b6-ff7e-4e43-b3fa-88f9bc3557a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493944586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.493944586
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2579204713
Short name T61
Test name
Test status
Simulation time 93909061 ps
CPU time 3.79 seconds
Started Aug 19 05:40:25 PM PDT 24
Finished Aug 19 05:40:29 PM PDT 24
Peak memory 209172 kb
Host smart-907ebace-3639-4f40-a424-bcb949463bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579204713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2579204713
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3679302273
Short name T726
Test name
Test status
Simulation time 196513689 ps
CPU time 3.23 seconds
Started Aug 19 05:40:25 PM PDT 24
Finished Aug 19 05:40:29 PM PDT 24
Peak memory 209020 kb
Host smart-6ff759cb-1746-43ea-9ace-6821c558fb32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679302273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3679302273
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.1796142346
Short name T677
Test name
Test status
Simulation time 3032926043 ps
CPU time 5.06 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:37 PM PDT 24
Peak memory 208572 kb
Host smart-d7870b3d-427b-423b-802c-7cfb35b5a6c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796142346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.1796142346
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3849342224
Short name T576
Test name
Test status
Simulation time 1481804314 ps
CPU time 18.32 seconds
Started Aug 19 05:40:26 PM PDT 24
Finished Aug 19 05:40:44 PM PDT 24
Peak memory 209640 kb
Host smart-ce5e3923-c7cf-44bf-9652-ef97a2b44f07
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849342224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3849342224
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3482519935
Short name T593
Test name
Test status
Simulation time 173391362 ps
CPU time 2.46 seconds
Started Aug 19 05:40:26 PM PDT 24
Finished Aug 19 05:40:29 PM PDT 24
Peak memory 207432 kb
Host smart-27da7fb6-b1bd-47f7-ac92-6ee138bc2d8c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482519935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3482519935
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3428117959
Short name T814
Test name
Test status
Simulation time 824743543 ps
CPU time 4.47 seconds
Started Aug 19 05:40:27 PM PDT 24
Finished Aug 19 05:40:31 PM PDT 24
Peak memory 209940 kb
Host smart-476aea19-867c-45c1-ac87-56c706a45735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428117959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3428117959
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.811301416
Short name T747
Test name
Test status
Simulation time 39049675 ps
CPU time 2.17 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:33 PM PDT 24
Peak memory 207344 kb
Host smart-8e4a3c00-4262-4b2d-af02-c7e1f724264d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811301416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.811301416
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3414517381
Short name T559
Test name
Test status
Simulation time 81055740 ps
CPU time 3.74 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:34 PM PDT 24
Peak memory 218988 kb
Host smart-2c9bb830-3692-4e79-a016-45be5b8c5c75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414517381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3414517381
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2866953233
Short name T775
Test name
Test status
Simulation time 646234993 ps
CPU time 12.8 seconds
Started Aug 19 05:40:26 PM PDT 24
Finished Aug 19 05:40:38 PM PDT 24
Peak memory 211508 kb
Host smart-322fe948-982e-43b7-b846-1c2c9d92b1c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866953233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2866953233
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2938633636
Short name T517
Test name
Test status
Simulation time 23717645 ps
CPU time 0.82 seconds
Started Aug 19 05:40:34 PM PDT 24
Finished Aug 19 05:40:35 PM PDT 24
Peak memory 206416 kb
Host smart-8724a756-0749-436d-8c8b-c4fd795da799
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938633636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2938633636
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3524257067
Short name T17
Test name
Test status
Simulation time 496044806 ps
CPU time 5.81 seconds
Started Aug 19 05:40:35 PM PDT 24
Finished Aug 19 05:40:41 PM PDT 24
Peak memory 208948 kb
Host smart-e6617c8f-5262-4911-a113-adc73b3d0b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524257067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3524257067
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2123077710
Short name T614
Test name
Test status
Simulation time 71456672 ps
CPU time 1.66 seconds
Started Aug 19 05:40:30 PM PDT 24
Finished Aug 19 05:40:32 PM PDT 24
Peak memory 208900 kb
Host smart-ccb473de-f2c0-4c19-bfa7-25591c701798
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123077710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2123077710
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.850633146
Short name T851
Test name
Test status
Simulation time 152170463 ps
CPU time 5.78 seconds
Started Aug 19 05:40:32 PM PDT 24
Finished Aug 19 05:40:38 PM PDT 24
Peak memory 207516 kb
Host smart-f52dba76-902c-4dce-9f12-b733afac3368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850633146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.850633146
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.1493869912
Short name T787
Test name
Test status
Simulation time 25905721497 ps
CPU time 37.45 seconds
Started Aug 19 05:40:28 PM PDT 24
Finished Aug 19 05:41:05 PM PDT 24
Peak memory 214936 kb
Host smart-2d1141b7-314a-45d6-a607-78f7fe762f2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493869912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1493869912
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2372181597
Short name T699
Test name
Test status
Simulation time 102040864 ps
CPU time 4.15 seconds
Started Aug 19 05:40:27 PM PDT 24
Finished Aug 19 05:40:32 PM PDT 24
Peak memory 207468 kb
Host smart-895e843c-c8af-4201-991c-fc467a4a7052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372181597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2372181597
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.732794548
Short name T527
Test name
Test status
Simulation time 248758008 ps
CPU time 1.9 seconds
Started Aug 19 05:40:26 PM PDT 24
Finished Aug 19 05:40:28 PM PDT 24
Peak memory 207428 kb
Host smart-1e059cb1-cf7e-42de-81c3-e18934104d14
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732794548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.732794548
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1418280091
Short name T531
Test name
Test status
Simulation time 117574751 ps
CPU time 3.14 seconds
Started Aug 19 05:40:25 PM PDT 24
Finished Aug 19 05:40:29 PM PDT 24
Peak memory 209320 kb
Host smart-05c20e15-4a70-4de2-9e13-9e624c6304b8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418280091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1418280091
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.13717117
Short name T408
Test name
Test status
Simulation time 486289612 ps
CPU time 3.31 seconds
Started Aug 19 05:40:22 PM PDT 24
Finished Aug 19 05:40:26 PM PDT 24
Peak memory 208912 kb
Host smart-22af9b5b-65e7-47cd-94e1-4e562ab0399a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13717117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.13717117
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_smoke.4021952056
Short name T577
Test name
Test status
Simulation time 236570937 ps
CPU time 4.87 seconds
Started Aug 19 05:40:25 PM PDT 24
Finished Aug 19 05:40:30 PM PDT 24
Peak memory 208756 kb
Host smart-b279bef2-0714-4e7c-8281-6f221b1d4707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021952056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.4021952056
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.266756894
Short name T658
Test name
Test status
Simulation time 4904825278 ps
CPU time 45.93 seconds
Started Aug 19 05:40:35 PM PDT 24
Finished Aug 19 05:41:21 PM PDT 24
Peak memory 220296 kb
Host smart-b028c653-dfb0-4de0-a67b-59cb73a8821e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266756894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.266756894
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3176312301
Short name T175
Test name
Test status
Simulation time 94731700 ps
CPU time 4.45 seconds
Started Aug 19 05:40:28 PM PDT 24
Finished Aug 19 05:40:32 PM PDT 24
Peak memory 210668 kb
Host smart-f89f18df-71f2-4324-87d4-d0c89c6aaf91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176312301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3176312301
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.4065933295
Short name T77
Test name
Test status
Simulation time 350920644 ps
CPU time 4.05 seconds
Started Aug 19 05:40:38 PM PDT 24
Finished Aug 19 05:40:42 PM PDT 24
Peak memory 210544 kb
Host smart-5200b58c-ed3b-482b-b264-cf1421acff76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065933295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4065933295
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.706346545
Short name T472
Test name
Test status
Simulation time 13773496 ps
CPU time 0.87 seconds
Started Aug 19 05:40:33 PM PDT 24
Finished Aug 19 05:40:34 PM PDT 24
Peak memory 206440 kb
Host smart-b9981e0e-afa5-40c8-9ee8-f5bd92efaa21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706346545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.706346545
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2486062249
Short name T416
Test name
Test status
Simulation time 160842165 ps
CPU time 4.85 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:36 PM PDT 24
Peak memory 214820 kb
Host smart-78d580ef-ef5b-4ab8-8ff5-fb22dbfdb930
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2486062249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2486062249
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.72336172
Short name T369
Test name
Test status
Simulation time 72311275 ps
CPU time 4.23 seconds
Started Aug 19 05:40:34 PM PDT 24
Finished Aug 19 05:40:39 PM PDT 24
Peak memory 211028 kb
Host smart-d764285b-1b4e-4c11-b41d-eb8d1ddfd7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72336172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.72336172
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.437952718
Short name T755
Test name
Test status
Simulation time 121634720 ps
CPU time 2.83 seconds
Started Aug 19 05:40:32 PM PDT 24
Finished Aug 19 05:40:35 PM PDT 24
Peak memory 208764 kb
Host smart-00e6b63d-2433-475c-9743-c5d08d56bc2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437952718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.437952718
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2159381376
Short name T608
Test name
Test status
Simulation time 90584284 ps
CPU time 4.05 seconds
Started Aug 19 05:40:32 PM PDT 24
Finished Aug 19 05:40:36 PM PDT 24
Peak memory 209336 kb
Host smart-71697648-2d26-443f-99de-d3ce9715ef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159381376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2159381376
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1741609685
Short name T732
Test name
Test status
Simulation time 265823755 ps
CPU time 5.04 seconds
Started Aug 19 05:40:34 PM PDT 24
Finished Aug 19 05:40:39 PM PDT 24
Peak memory 214712 kb
Host smart-07c61dce-bc89-46d0-992d-2b8a4041a2ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741609685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1741609685
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1316878447
Short name T788
Test name
Test status
Simulation time 299501277 ps
CPU time 3.86 seconds
Started Aug 19 05:40:34 PM PDT 24
Finished Aug 19 05:40:38 PM PDT 24
Peak memory 214804 kb
Host smart-7013297b-ebd7-4318-a169-4ac2259edb5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316878447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1316878447
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1080225005
Short name T713
Test name
Test status
Simulation time 516979932 ps
CPU time 3.62 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:35 PM PDT 24
Peak memory 214876 kb
Host smart-afda62b8-1bfc-48a9-b1d2-658a49210310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080225005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1080225005
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.1184420412
Short name T399
Test name
Test status
Simulation time 461549448 ps
CPU time 4.15 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:35 PM PDT 24
Peak memory 209164 kb
Host smart-0664106b-71d7-41ee-b3d0-9a4c8afec0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184420412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.1184420412
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3230848016
Short name T595
Test name
Test status
Simulation time 179034008 ps
CPU time 2.9 seconds
Started Aug 19 05:40:30 PM PDT 24
Finished Aug 19 05:40:33 PM PDT 24
Peak memory 207332 kb
Host smart-7bd9596a-b523-4c6e-875e-10249dccbe5d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230848016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3230848016
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.624762974
Short name T902
Test name
Test status
Simulation time 186627885 ps
CPU time 2.85 seconds
Started Aug 19 05:40:35 PM PDT 24
Finished Aug 19 05:40:38 PM PDT 24
Peak memory 207600 kb
Host smart-f0c7356f-c8fe-4686-b147-721c3ccaf10d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624762974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.624762974
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.798618358
Short name T243
Test name
Test status
Simulation time 1086797160 ps
CPU time 21.76 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:53 PM PDT 24
Peak memory 209012 kb
Host smart-d51bbfc4-1eaf-4ea6-b81d-f2caa7873cbd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798618358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.798618358
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2836361403
Short name T429
Test name
Test status
Simulation time 385695758 ps
CPU time 2.81 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:34 PM PDT 24
Peak memory 208236 kb
Host smart-595ee626-0a5b-429b-aefa-52ed9444bd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836361403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2836361403
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.28569878
Short name T558
Test name
Test status
Simulation time 506139878 ps
CPU time 3.24 seconds
Started Aug 19 05:40:38 PM PDT 24
Finished Aug 19 05:40:41 PM PDT 24
Peak memory 207344 kb
Host smart-5aaa712a-e494-4185-9a6c-2210a6ea5bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28569878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.28569878
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1824511617
Short name T22
Test name
Test status
Simulation time 241315407 ps
CPU time 7.21 seconds
Started Aug 19 05:40:53 PM PDT 24
Finished Aug 19 05:41:00 PM PDT 24
Peak memory 210508 kb
Host smart-85cd390e-3412-436c-a2ae-033d957759e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824511617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1824511617
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.863120157
Short name T391
Test name
Test status
Simulation time 952798266 ps
CPU time 6.21 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:37 PM PDT 24
Peak memory 210916 kb
Host smart-ec338a38-6a43-48fd-afcf-46beb98e408d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863120157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.863120157
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2943290531
Short name T873
Test name
Test status
Simulation time 22118650 ps
CPU time 0.76 seconds
Started Aug 19 05:40:46 PM PDT 24
Finished Aug 19 05:40:47 PM PDT 24
Peak memory 206392 kb
Host smart-b265004c-dfad-47e6-b44c-3971902aba2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943290531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2943290531
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.368708140
Short name T420
Test name
Test status
Simulation time 2813188171 ps
CPU time 57.74 seconds
Started Aug 19 05:40:32 PM PDT 24
Finished Aug 19 05:41:30 PM PDT 24
Peak memory 215028 kb
Host smart-7456c9d6-e61c-4ae6-bb3c-9533b1e58210
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=368708140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.368708140
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1180303710
Short name T675
Test name
Test status
Simulation time 61851932 ps
CPU time 3.4 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:35 PM PDT 24
Peak memory 218100 kb
Host smart-282ab036-c271-4d07-a55d-0f0a60dd6661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180303710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1180303710
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.561562847
Short name T809
Test name
Test status
Simulation time 75384824 ps
CPU time 3.07 seconds
Started Aug 19 05:40:32 PM PDT 24
Finished Aug 19 05:40:35 PM PDT 24
Peak memory 214768 kb
Host smart-6b20cc93-6fab-414a-8ea2-12dc7e4b7f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561562847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.561562847
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2126141409
Short name T728
Test name
Test status
Simulation time 1261855187 ps
CPU time 5.18 seconds
Started Aug 19 05:40:33 PM PDT 24
Finished Aug 19 05:40:39 PM PDT 24
Peak memory 209720 kb
Host smart-d87c2d7f-ce82-4b02-bdd8-52584857a3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126141409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2126141409
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1375311526
Short name T299
Test name
Test status
Simulation time 96968561 ps
CPU time 2.93 seconds
Started Aug 19 05:40:40 PM PDT 24
Finished Aug 19 05:40:43 PM PDT 24
Peak memory 214812 kb
Host smart-8101be76-fca9-415a-b7e1-8049f2433288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375311526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1375311526
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1810684156
Short name T687
Test name
Test status
Simulation time 100672197 ps
CPU time 2.61 seconds
Started Aug 19 05:40:31 PM PDT 24
Finished Aug 19 05:40:34 PM PDT 24
Peak memory 220704 kb
Host smart-b8e09bf0-2f7e-4c50-a215-268844df0640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810684156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1810684156
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2510416752
Short name T643
Test name
Test status
Simulation time 2261813472 ps
CPU time 68.91 seconds
Started Aug 19 05:40:32 PM PDT 24
Finished Aug 19 05:41:41 PM PDT 24
Peak memory 209268 kb
Host smart-0adcec1f-227a-4118-bbb6-9c273b5c09dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510416752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2510416752
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3878893883
Short name T540
Test name
Test status
Simulation time 40500169 ps
CPU time 2.26 seconds
Started Aug 19 05:40:33 PM PDT 24
Finished Aug 19 05:40:35 PM PDT 24
Peak memory 207272 kb
Host smart-72d6681b-4cb0-4ab2-a63d-e0efc853fb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878893883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3878893883
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2387103356
Short name T679
Test name
Test status
Simulation time 149582006 ps
CPU time 2.54 seconds
Started Aug 19 05:40:32 PM PDT 24
Finished Aug 19 05:40:35 PM PDT 24
Peak memory 207468 kb
Host smart-f0b8335a-fa4d-43be-9c1c-0b6e5702d676
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387103356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2387103356
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3707204273
Short name T546
Test name
Test status
Simulation time 6165836648 ps
CPU time 67.8 seconds
Started Aug 19 05:40:32 PM PDT 24
Finished Aug 19 05:41:40 PM PDT 24
Peak memory 209796 kb
Host smart-f5069729-6305-48a7-ab0c-7ba04ea21aae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707204273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3707204273
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.360966665
Short name T574
Test name
Test status
Simulation time 446332432 ps
CPU time 2.45 seconds
Started Aug 19 05:40:34 PM PDT 24
Finished Aug 19 05:40:37 PM PDT 24
Peak memory 207160 kb
Host smart-336d0eb3-4372-422d-9770-d43a65a466bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360966665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.360966665
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3714364477
Short name T346
Test name
Test status
Simulation time 34358261 ps
CPU time 2.32 seconds
Started Aug 19 05:40:32 PM PDT 24
Finished Aug 19 05:40:35 PM PDT 24
Peak memory 208644 kb
Host smart-79fb64a5-3356-459e-88ae-c861285b308f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714364477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3714364477
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.149301976
Short name T821
Test name
Test status
Simulation time 218981866 ps
CPU time 6.46 seconds
Started Aug 19 05:40:32 PM PDT 24
Finished Aug 19 05:40:38 PM PDT 24
Peak memory 208900 kb
Host smart-c9340226-d94a-40f4-a1e6-ec9715de1865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149301976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.149301976
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2072229692
Short name T843
Test name
Test status
Simulation time 724403050 ps
CPU time 8.37 seconds
Started Aug 19 05:40:33 PM PDT 24
Finished Aug 19 05:40:42 PM PDT 24
Peak memory 210032 kb
Host smart-8142ec94-7044-4e15-bc18-fec486b6e409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072229692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2072229692
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.144347229
Short name T791
Test name
Test status
Simulation time 233456962 ps
CPU time 2.35 seconds
Started Aug 19 05:40:32 PM PDT 24
Finished Aug 19 05:40:35 PM PDT 24
Peak memory 210580 kb
Host smart-a056a499-5ae9-456f-87ae-8bbff0aced0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144347229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.144347229
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1427442043
Short name T478
Test name
Test status
Simulation time 21238684 ps
CPU time 0.71 seconds
Started Aug 19 05:40:45 PM PDT 24
Finished Aug 19 05:40:46 PM PDT 24
Peak memory 206392 kb
Host smart-c6b93b43-f3cc-49f8-8789-4f5b4d71fe3e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427442043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1427442043
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1817321447
Short name T419
Test name
Test status
Simulation time 88026571 ps
CPU time 3.31 seconds
Started Aug 19 05:40:44 PM PDT 24
Finished Aug 19 05:40:47 PM PDT 24
Peak memory 216108 kb
Host smart-5da99953-e134-4565-a087-8720bd012fe6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1817321447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1817321447
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.4279197619
Short name T46
Test name
Test status
Simulation time 995573871 ps
CPU time 7.31 seconds
Started Aug 19 05:40:43 PM PDT 24
Finished Aug 19 05:40:51 PM PDT 24
Peak memory 210052 kb
Host smart-624aeec4-b7da-4b68-afce-3f011eeff0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279197619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.4279197619
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.739320010
Short name T636
Test name
Test status
Simulation time 46865723 ps
CPU time 2.85 seconds
Started Aug 19 05:40:44 PM PDT 24
Finished Aug 19 05:40:46 PM PDT 24
Peak memory 214928 kb
Host smart-798d98bf-ae8e-4962-aff9-b4e9e15153f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739320010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.739320010
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1069966770
Short name T97
Test name
Test status
Simulation time 422295908 ps
CPU time 6.71 seconds
Started Aug 19 05:40:47 PM PDT 24
Finished Aug 19 05:40:53 PM PDT 24
Peak memory 222964 kb
Host smart-1baa0d00-dc68-4aaa-b158-3c218c4e154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069966770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1069966770
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2838370892
Short name T495
Test name
Test status
Simulation time 104569504 ps
CPU time 2.8 seconds
Started Aug 19 05:40:44 PM PDT 24
Finished Aug 19 05:40:47 PM PDT 24
Peak memory 207520 kb
Host smart-e8b220fd-cb60-4daf-8d62-cef1d58683ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838370892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2838370892
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.3703451000
Short name T307
Test name
Test status
Simulation time 157477705 ps
CPU time 2.24 seconds
Started Aug 19 05:40:46 PM PDT 24
Finished Aug 19 05:40:49 PM PDT 24
Peak memory 207432 kb
Host smart-716901de-ef81-4803-90e4-02ff9e2bec0c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703451000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.3703451000
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.4253009726
Short name T220
Test name
Test status
Simulation time 1005001199 ps
CPU time 11.16 seconds
Started Aug 19 05:40:47 PM PDT 24
Finished Aug 19 05:40:58 PM PDT 24
Peak memory 209080 kb
Host smart-9d09aa7c-f724-4aed-bd8f-f1913e4fe4fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253009726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.4253009726
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3475514668
Short name T711
Test name
Test status
Simulation time 209998509 ps
CPU time 1.76 seconds
Started Aug 19 05:40:43 PM PDT 24
Finished Aug 19 05:40:45 PM PDT 24
Peak memory 207300 kb
Host smart-b13b61c3-1629-4327-9fb9-2b938bd22d85
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475514668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3475514668
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2059872505
Short name T2
Test name
Test status
Simulation time 103522313 ps
CPU time 4.49 seconds
Started Aug 19 05:40:46 PM PDT 24
Finished Aug 19 05:40:50 PM PDT 24
Peak memory 219036 kb
Host smart-6b32274d-8850-42cb-92d6-1b630a750a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059872505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2059872505
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.4205619441
Short name T692
Test name
Test status
Simulation time 245894356 ps
CPU time 2.69 seconds
Started Aug 19 05:40:44 PM PDT 24
Finished Aug 19 05:40:47 PM PDT 24
Peak memory 207232 kb
Host smart-47a60d80-830b-4f3b-b0b1-246603cd0095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205619441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.4205619441
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2411131808
Short name T556
Test name
Test status
Simulation time 107833260 ps
CPU time 4.33 seconds
Started Aug 19 05:40:45 PM PDT 24
Finished Aug 19 05:40:49 PM PDT 24
Peak memory 209844 kb
Host smart-c4368269-1c0f-4f4b-a482-9f918d99978e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411131808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2411131808
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.4142975072
Short name T384
Test name
Test status
Simulation time 40218958 ps
CPU time 1.73 seconds
Started Aug 19 05:40:46 PM PDT 24
Finished Aug 19 05:40:48 PM PDT 24
Peak memory 210296 kb
Host smart-d60d1bfd-8334-485b-b1ab-d69673132e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142975072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.4142975072
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1542108747
Short name T455
Test name
Test status
Simulation time 48493402 ps
CPU time 0.9 seconds
Started Aug 19 05:40:44 PM PDT 24
Finished Aug 19 05:40:45 PM PDT 24
Peak memory 206396 kb
Host smart-6769d004-0023-4793-8633-67d503058331
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542108747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1542108747
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.367123414
Short name T604
Test name
Test status
Simulation time 71258412 ps
CPU time 1.88 seconds
Started Aug 19 05:40:43 PM PDT 24
Finished Aug 19 05:40:45 PM PDT 24
Peak memory 217256 kb
Host smart-a818f0d3-cfbf-4543-a7a6-8978c5262602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367123414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.367123414
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3905923586
Short name T404
Test name
Test status
Simulation time 213208799 ps
CPU time 3.05 seconds
Started Aug 19 05:40:42 PM PDT 24
Finished Aug 19 05:40:45 PM PDT 24
Peak memory 207448 kb
Host smart-08a398f9-8f7f-45bf-8fd7-7f5ccec381d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905923586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3905923586
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.2355749532
Short name T48
Test name
Test status
Simulation time 208870545 ps
CPU time 4.53 seconds
Started Aug 19 05:40:46 PM PDT 24
Finished Aug 19 05:40:50 PM PDT 24
Peak memory 209740 kb
Host smart-2d371185-6163-4364-b2be-5b4898dd7168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355749532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.2355749532
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3816293008
Short name T315
Test name
Test status
Simulation time 207173312 ps
CPU time 2.4 seconds
Started Aug 19 05:40:45 PM PDT 24
Finished Aug 19 05:40:48 PM PDT 24
Peak memory 217252 kb
Host smart-5c450d89-4522-4269-8837-407cabdd4e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816293008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3816293008
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2038156693
Short name T197
Test name
Test status
Simulation time 112158353 ps
CPU time 2.58 seconds
Started Aug 19 05:40:46 PM PDT 24
Finished Aug 19 05:40:49 PM PDT 24
Peak memory 209476 kb
Host smart-c3a306b8-912f-42ea-a654-e48309322b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038156693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2038156693
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.409015542
Short name T506
Test name
Test status
Simulation time 562831129 ps
CPU time 4.11 seconds
Started Aug 19 05:40:45 PM PDT 24
Finished Aug 19 05:40:49 PM PDT 24
Peak memory 218912 kb
Host smart-76123602-057a-461a-ae71-2c8e1a62d7da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409015542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.409015542
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3123760251
Short name T449
Test name
Test status
Simulation time 83413293 ps
CPU time 2.35 seconds
Started Aug 19 05:40:42 PM PDT 24
Finished Aug 19 05:40:44 PM PDT 24
Peak memory 208624 kb
Host smart-69bcdead-f14e-4ad6-bf7e-f1233d9aa38a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123760251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3123760251
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1051519809
Short name T664
Test name
Test status
Simulation time 122463602 ps
CPU time 2.26 seconds
Started Aug 19 05:40:48 PM PDT 24
Finished Aug 19 05:40:50 PM PDT 24
Peak memory 207332 kb
Host smart-5ad656b3-53a9-4178-9d8f-52a6189e9e72
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051519809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1051519809
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2995760106
Short name T334
Test name
Test status
Simulation time 64414961 ps
CPU time 3 seconds
Started Aug 19 05:40:43 PM PDT 24
Finished Aug 19 05:40:46 PM PDT 24
Peak memory 208440 kb
Host smart-7c19fde8-4147-4bc3-8084-19701e6ec502
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995760106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2995760106
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2754232241
Short name T588
Test name
Test status
Simulation time 415889692 ps
CPU time 3.63 seconds
Started Aug 19 05:40:44 PM PDT 24
Finished Aug 19 05:40:48 PM PDT 24
Peak memory 207524 kb
Host smart-c688a05d-b7aa-4c8d-b1a4-f2908d2beee6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754232241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2754232241
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2097306799
Short name T400
Test name
Test status
Simulation time 633935046 ps
CPU time 3.39 seconds
Started Aug 19 05:40:43 PM PDT 24
Finished Aug 19 05:40:47 PM PDT 24
Peak memory 209100 kb
Host smart-d507edea-0b60-4e18-9bc9-2495cb8cd26d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097306799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2097306799
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.4119307585
Short name T135
Test name
Test status
Simulation time 686535840 ps
CPU time 21.41 seconds
Started Aug 19 05:40:47 PM PDT 24
Finished Aug 19 05:41:09 PM PDT 24
Peak memory 217788 kb
Host smart-b82aa50c-84d7-4e7e-bdb0-f5d69bad2600
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119307585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.4119307585
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1305092000
Short name T650
Test name
Test status
Simulation time 3139150599 ps
CPU time 11.63 seconds
Started Aug 19 05:40:43 PM PDT 24
Finished Aug 19 05:40:54 PM PDT 24
Peak memory 209988 kb
Host smart-df95e13e-5675-4d7a-82bd-4fd1cb852664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305092000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1305092000
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2987185117
Short name T387
Test name
Test status
Simulation time 513386706 ps
CPU time 2.84 seconds
Started Aug 19 05:40:45 PM PDT 24
Finished Aug 19 05:40:48 PM PDT 24
Peak memory 210760 kb
Host smart-181bd04a-19f8-4d2b-8b9e-35cafa911a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987185117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2987185117
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1517247821
Short name T762
Test name
Test status
Simulation time 127508276 ps
CPU time 0.78 seconds
Started Aug 19 05:40:50 PM PDT 24
Finished Aug 19 05:40:51 PM PDT 24
Peak memory 206384 kb
Host smart-4b50cf1e-05d6-4b7f-88de-4544dae35120
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517247821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1517247821
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3345730681
Short name T266
Test name
Test status
Simulation time 40925919 ps
CPU time 2.85 seconds
Started Aug 19 05:40:44 PM PDT 24
Finished Aug 19 05:40:47 PM PDT 24
Peak memory 214820 kb
Host smart-db690c93-9fcd-459b-8df7-072c81a10e9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3345730681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3345730681
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.877776187
Short name T273
Test name
Test status
Simulation time 188719349 ps
CPU time 3.4 seconds
Started Aug 19 05:40:45 PM PDT 24
Finished Aug 19 05:40:48 PM PDT 24
Peak memory 210924 kb
Host smart-c5362ab4-600a-4f09-94d9-692b376152a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877776187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.877776187
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3942847689
Short name T274
Test name
Test status
Simulation time 106999643 ps
CPU time 5.14 seconds
Started Aug 19 05:40:52 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 214780 kb
Host smart-a72ed961-d052-495e-9416-3728e75d77aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942847689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3942847689
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2890496095
Short name T380
Test name
Test status
Simulation time 398249156 ps
CPU time 3.55 seconds
Started Aug 19 05:40:53 PM PDT 24
Finished Aug 19 05:40:56 PM PDT 24
Peak memory 214832 kb
Host smart-aa39ab50-c2db-4907-8f73-e3f9d522160a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890496095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2890496095
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.257620451
Short name T202
Test name
Test status
Simulation time 580012776 ps
CPU time 10.79 seconds
Started Aug 19 05:40:47 PM PDT 24
Finished Aug 19 05:40:58 PM PDT 24
Peak memory 220836 kb
Host smart-0720054c-eb58-4fd3-9562-02e371365ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257620451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.257620451
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1193171518
Short name T342
Test name
Test status
Simulation time 180902121 ps
CPU time 3.3 seconds
Started Aug 19 05:40:44 PM PDT 24
Finished Aug 19 05:40:48 PM PDT 24
Peak memory 208708 kb
Host smart-2f9d797a-0190-42be-8878-e34fe07494c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193171518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1193171518
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.1510467356
Short name T703
Test name
Test status
Simulation time 2865030956 ps
CPU time 30.54 seconds
Started Aug 19 05:40:47 PM PDT 24
Finished Aug 19 05:41:17 PM PDT 24
Peak memory 208856 kb
Host smart-e7594724-3d13-458b-a4b9-12ef39342f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510467356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.1510467356
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1870886372
Short name T320
Test name
Test status
Simulation time 850691447 ps
CPU time 6.43 seconds
Started Aug 19 05:40:45 PM PDT 24
Finished Aug 19 05:40:52 PM PDT 24
Peak memory 209344 kb
Host smart-1992a5c3-1ca6-46da-a675-e7992187716a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870886372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1870886372
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3265333889
Short name T263
Test name
Test status
Simulation time 948838472 ps
CPU time 3.68 seconds
Started Aug 19 05:40:48 PM PDT 24
Finished Aug 19 05:40:52 PM PDT 24
Peak memory 209092 kb
Host smart-f17f341d-2b30-49f1-9340-d895dc32d275
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265333889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3265333889
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1553270654
Short name T347
Test name
Test status
Simulation time 4528171339 ps
CPU time 33.49 seconds
Started Aug 19 05:40:44 PM PDT 24
Finished Aug 19 05:41:17 PM PDT 24
Peak memory 208548 kb
Host smart-8601646e-aae1-4849-9d71-523e90d15008
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553270654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1553270654
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.70072932
Short name T808
Test name
Test status
Simulation time 79623406 ps
CPU time 3.54 seconds
Started Aug 19 05:40:57 PM PDT 24
Finished Aug 19 05:41:01 PM PDT 24
Peak memory 214800 kb
Host smart-065e3f49-af6f-494e-aecf-42394115d588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70072932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.70072932
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.1194760225
Short name T818
Test name
Test status
Simulation time 864792697 ps
CPU time 4.87 seconds
Started Aug 19 05:40:45 PM PDT 24
Finished Aug 19 05:40:50 PM PDT 24
Peak memory 208476 kb
Host smart-10584896-213e-473e-9a12-de86a15295e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194760225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.1194760225
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1924142206
Short name T208
Test name
Test status
Simulation time 10089905843 ps
CPU time 16.26 seconds
Started Aug 19 05:40:53 PM PDT 24
Finished Aug 19 05:41:09 PM PDT 24
Peak memory 223044 kb
Host smart-a4d1b0f7-4fbf-4003-bba4-a150d2314610
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924142206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1924142206
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2131094808
Short name T764
Test name
Test status
Simulation time 131674818 ps
CPU time 3.84 seconds
Started Aug 19 05:40:52 PM PDT 24
Finished Aug 19 05:40:56 PM PDT 24
Peak memory 208104 kb
Host smart-5dad12fd-64d2-4447-bcbb-8c27a2837f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131094808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2131094808
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1355505050
Short name T793
Test name
Test status
Simulation time 171688927 ps
CPU time 2.18 seconds
Started Aug 19 05:40:55 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 210468 kb
Host smart-11fdd302-be48-44fd-9019-bee21a2e72a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355505050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1355505050
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2760678499
Short name T597
Test name
Test status
Simulation time 8822173 ps
CPU time 0.72 seconds
Started Aug 19 05:40:55 PM PDT 24
Finished Aug 19 05:40:56 PM PDT 24
Peak memory 206392 kb
Host smart-f5cd7ca5-e043-4d0b-8af8-5c4522c10b3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760678499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2760678499
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.854414449
Short name T295
Test name
Test status
Simulation time 305213007 ps
CPU time 12 seconds
Started Aug 19 05:40:55 PM PDT 24
Finished Aug 19 05:41:07 PM PDT 24
Peak memory 216088 kb
Host smart-c7eb8c7a-5503-43fd-a38e-563de91b7f35
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854414449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.854414449
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2681137651
Short name T533
Test name
Test status
Simulation time 54682191 ps
CPU time 1.77 seconds
Started Aug 19 05:40:57 PM PDT 24
Finished Aug 19 05:40:59 PM PDT 24
Peak memory 207900 kb
Host smart-a06543f2-ca3a-48aa-8591-a23a48c58223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681137651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2681137651
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1039290192
Short name T854
Test name
Test status
Simulation time 35336279 ps
CPU time 2.76 seconds
Started Aug 19 05:40:54 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 214852 kb
Host smart-1cd8deab-e1c4-4c94-8e39-6f5c69aaca40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039290192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1039290192
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2454694821
Short name T819
Test name
Test status
Simulation time 46929141 ps
CPU time 3.39 seconds
Started Aug 19 05:40:54 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 214792 kb
Host smart-32a35c3a-faad-4bfe-ad36-c083b7a15966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454694821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2454694821
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.623310416
Short name T620
Test name
Test status
Simulation time 4358778634 ps
CPU time 63.85 seconds
Started Aug 19 05:40:52 PM PDT 24
Finished Aug 19 05:41:56 PM PDT 24
Peak memory 211240 kb
Host smart-86967dd3-25c2-4a38-8b5c-92507f8684fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623310416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.623310416
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3565383093
Short name T752
Test name
Test status
Simulation time 94707880 ps
CPU time 2.53 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:41:01 PM PDT 24
Peak memory 207208 kb
Host smart-a0e389c8-95c8-4e64-a4f4-1fa52a18146b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565383093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3565383093
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1682215172
Short name T707
Test name
Test status
Simulation time 66534142 ps
CPU time 2.33 seconds
Started Aug 19 05:40:53 PM PDT 24
Finished Aug 19 05:40:56 PM PDT 24
Peak memory 207400 kb
Host smart-91770457-ef38-4e48-af16-0815641a12a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682215172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1682215172
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.506765965
Short name T754
Test name
Test status
Simulation time 592186056 ps
CPU time 4.88 seconds
Started Aug 19 05:40:50 PM PDT 24
Finished Aug 19 05:40:55 PM PDT 24
Peak memory 209144 kb
Host smart-c8dace3e-72c8-42e1-889a-f0d434dd0abb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506765965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.506765965
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.604778096
Short name T186
Test name
Test status
Simulation time 157085035 ps
CPU time 2.82 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:41:01 PM PDT 24
Peak memory 207380 kb
Host smart-c9bf0d51-a246-40fb-917e-0b5ce40a2b14
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604778096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.604778096
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.4146271258
Short name T480
Test name
Test status
Simulation time 170964955 ps
CPU time 3.1 seconds
Started Aug 19 05:40:54 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 216424 kb
Host smart-0d6b0364-2bca-472e-b3a7-8bfb7dc52b02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146271258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.4146271258
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.455916943
Short name T794
Test name
Test status
Simulation time 274579008 ps
CPU time 2.6 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:41:00 PM PDT 24
Peak memory 209000 kb
Host smart-c0bb2e2c-6653-4f7b-bebf-3aa6488a9604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455916943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.455916943
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2096319319
Short name T285
Test name
Test status
Simulation time 101674235 ps
CPU time 3.87 seconds
Started Aug 19 05:40:51 PM PDT 24
Finished Aug 19 05:40:55 PM PDT 24
Peak memory 209260 kb
Host smart-f1a145fe-6aa8-44c4-97c8-8d034ab01d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096319319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2096319319
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.508382731
Short name T780
Test name
Test status
Simulation time 34208993 ps
CPU time 0.86 seconds
Started Aug 19 05:40:56 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 206432 kb
Host smart-81c799f3-63aa-40c1-8b33-d0c0ba05718e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508382731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.508382731
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2230305273
Short name T286
Test name
Test status
Simulation time 686812162 ps
CPU time 10.1 seconds
Started Aug 19 05:40:54 PM PDT 24
Finished Aug 19 05:41:04 PM PDT 24
Peak memory 215836 kb
Host smart-ffea8059-3227-4ace-bad9-0a8f2a32d6ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2230305273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2230305273
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3957674994
Short name T113
Test name
Test status
Simulation time 31759240 ps
CPU time 1.81 seconds
Started Aug 19 05:40:55 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 218692 kb
Host smart-2f8ee675-2ed7-4457-9189-1288235aefb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957674994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3957674994
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.4006085072
Short name T684
Test name
Test status
Simulation time 43319737 ps
CPU time 2 seconds
Started Aug 19 05:40:57 PM PDT 24
Finished Aug 19 05:40:59 PM PDT 24
Peak memory 214784 kb
Host smart-b3dbed13-e4ed-453b-afe4-1fc950d97cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006085072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.4006085072
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.4121628247
Short name T484
Test name
Test status
Simulation time 234330719 ps
CPU time 3.43 seconds
Started Aug 19 05:40:52 PM PDT 24
Finished Aug 19 05:40:56 PM PDT 24
Peak memory 214748 kb
Host smart-0f892e58-28c2-4200-9d06-9a5bd354ab84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121628247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.4121628247
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1158249867
Short name T651
Test name
Test status
Simulation time 359462129 ps
CPU time 4.42 seconds
Started Aug 19 05:40:53 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 219440 kb
Host smart-55548ed9-9554-4a2c-b449-0cce94907698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158249867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1158249867
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.2416673157
Short name T870
Test name
Test status
Simulation time 148326330 ps
CPU time 6.41 seconds
Started Aug 19 05:40:57 PM PDT 24
Finished Aug 19 05:41:03 PM PDT 24
Peak memory 209380 kb
Host smart-62778ab3-d4dc-4bfd-902c-c808e9659fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416673157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2416673157
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.4265728678
Short name T745
Test name
Test status
Simulation time 1293433395 ps
CPU time 4.43 seconds
Started Aug 19 05:40:52 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 207300 kb
Host smart-da3d6f87-0795-4413-8aa0-408334670acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265728678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4265728678
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.460091433
Short name T264
Test name
Test status
Simulation time 76752535 ps
CPU time 3.52 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:41:02 PM PDT 24
Peak memory 209052 kb
Host smart-534bf2a2-5dc9-48de-a195-4cd19f172ebe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=460091433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.460091433
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1501840384
Short name T571
Test name
Test status
Simulation time 133119757 ps
CPU time 2.45 seconds
Started Aug 19 05:40:56 PM PDT 24
Finished Aug 19 05:40:59 PM PDT 24
Peak memory 207532 kb
Host smart-11366454-acac-4ac6-ba4b-24380f69cf27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501840384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1501840384
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3271620224
Short name T915
Test name
Test status
Simulation time 176864569 ps
CPU time 4.05 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:41:02 PM PDT 24
Peak memory 207512 kb
Host smart-d7d32645-7b26-4dd2-83d0-9b13ec675b87
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271620224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3271620224
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1735082767
Short name T59
Test name
Test status
Simulation time 155810174 ps
CPU time 3.73 seconds
Started Aug 19 05:40:56 PM PDT 24
Finished Aug 19 05:40:59 PM PDT 24
Peak memory 214716 kb
Host smart-764a065a-3f98-4687-8122-0b88377392cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735082767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1735082767
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3707107313
Short name T611
Test name
Test status
Simulation time 250858921 ps
CPU time 2.94 seconds
Started Aug 19 05:40:54 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 207468 kb
Host smart-14b395a2-295d-4913-8886-d54a0d11b58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707107313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3707107313
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1421036170
Short name T541
Test name
Test status
Simulation time 73642997 ps
CPU time 0.96 seconds
Started Aug 19 05:40:55 PM PDT 24
Finished Aug 19 05:40:56 PM PDT 24
Peak memory 206592 kb
Host smart-3c6e9b93-e5a0-4255-bb9a-9d9373bdd139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421036170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1421036170
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.4171226944
Short name T167
Test name
Test status
Simulation time 269737212 ps
CPU time 10.77 seconds
Started Aug 19 05:40:56 PM PDT 24
Finished Aug 19 05:41:07 PM PDT 24
Peak memory 223100 kb
Host smart-ae0e53f6-7a77-4534-a912-0820dd106e00
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171226944 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.4171226944
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.4201820476
Short name T367
Test name
Test status
Simulation time 302461951 ps
CPU time 3.36 seconds
Started Aug 19 05:40:53 PM PDT 24
Finished Aug 19 05:40:56 PM PDT 24
Peak memory 222956 kb
Host smart-10aa3ff4-0f6c-414d-8683-46a515bd70a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201820476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4201820476
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2415117955
Short name T669
Test name
Test status
Simulation time 45407281 ps
CPU time 2.54 seconds
Started Aug 19 05:40:54 PM PDT 24
Finished Aug 19 05:40:57 PM PDT 24
Peak memory 210844 kb
Host smart-99142df6-64b6-48ed-a456-e9371f820a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415117955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2415117955
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3709376657
Short name T435
Test name
Test status
Simulation time 59627611 ps
CPU time 0.81 seconds
Started Aug 19 05:39:57 PM PDT 24
Finished Aug 19 05:39:58 PM PDT 24
Peak memory 206408 kb
Host smart-d70eecdc-cecc-4405-8023-c5cdbbc313df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3709376657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3709376657
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3496790183
Short name T845
Test name
Test status
Simulation time 132361109 ps
CPU time 1.52 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:39:55 PM PDT 24
Peak memory 216812 kb
Host smart-697a9860-1e66-49e9-9635-ad922347214f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496790183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3496790183
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1158319143
Short name T111
Test name
Test status
Simulation time 211096085 ps
CPU time 2.76 seconds
Started Aug 19 05:39:51 PM PDT 24
Finished Aug 19 05:39:54 PM PDT 24
Peak memory 214788 kb
Host smart-1f1cedeb-ab6b-4088-a163-617fd4fc301c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158319143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1158319143
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3442731587
Short name T904
Test name
Test status
Simulation time 202944842 ps
CPU time 4.77 seconds
Started Aug 19 05:39:52 PM PDT 24
Finished Aug 19 05:39:57 PM PDT 24
Peak memory 214740 kb
Host smart-d133377f-3457-40ce-bea0-86b1546467fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442731587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3442731587
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3716580857
Short name T199
Test name
Test status
Simulation time 459687739 ps
CPU time 2.85 seconds
Started Aug 19 05:39:55 PM PDT 24
Finished Aug 19 05:39:58 PM PDT 24
Peak memory 220716 kb
Host smart-c3bb591b-fde4-4666-a4bd-7ca70aa568d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716580857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3716580857
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3657209221
Short name T895
Test name
Test status
Simulation time 886468412 ps
CPU time 10.62 seconds
Started Aug 19 05:39:52 PM PDT 24
Finished Aug 19 05:40:02 PM PDT 24
Peak memory 209596 kb
Host smart-c5e58c0e-79aa-44a2-a1a6-5a25b769f8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3657209221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3657209221
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2447989574
Short name T58
Test name
Test status
Simulation time 2069123020 ps
CPU time 7.27 seconds
Started Aug 19 05:39:51 PM PDT 24
Finished Aug 19 05:39:58 PM PDT 24
Peak memory 238260 kb
Host smart-e4bc26ac-815a-4e8f-9096-3168a81e308b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447989574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2447989574
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1398523945
Short name T671
Test name
Test status
Simulation time 76819629 ps
CPU time 2.29 seconds
Started Aug 19 05:39:54 PM PDT 24
Finished Aug 19 05:39:56 PM PDT 24
Peak memory 207440 kb
Host smart-1440e34f-e364-409f-938f-85bbb84553e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398523945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1398523945
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2269618237
Short name T686
Test name
Test status
Simulation time 215962728 ps
CPU time 2.37 seconds
Started Aug 19 05:39:55 PM PDT 24
Finished Aug 19 05:39:57 PM PDT 24
Peak memory 207940 kb
Host smart-290125a9-5647-49a2-99bf-47abf9b5d76d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269618237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2269618237
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2923379546
Short name T547
Test name
Test status
Simulation time 84865669 ps
CPU time 2.84 seconds
Started Aug 19 05:39:55 PM PDT 24
Finished Aug 19 05:39:58 PM PDT 24
Peak memory 209304 kb
Host smart-21b6fad6-cc49-4dea-9b3a-f01e45dae9fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923379546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2923379546
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3042219510
Short name T509
Test name
Test status
Simulation time 351724193 ps
CPU time 3.41 seconds
Started Aug 19 05:39:52 PM PDT 24
Finished Aug 19 05:39:55 PM PDT 24
Peak memory 207504 kb
Host smart-ebc43b43-197c-4f1c-b665-aefe12c3b2c2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042219510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3042219510
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.782666089
Short name T718
Test name
Test status
Simulation time 356579954 ps
CPU time 3.07 seconds
Started Aug 19 05:39:51 PM PDT 24
Finished Aug 19 05:39:54 PM PDT 24
Peak memory 216276 kb
Host smart-2424a30c-31f7-4064-8a0d-fa1817d245a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782666089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.782666089
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2408341850
Short name T467
Test name
Test status
Simulation time 156434284 ps
CPU time 2.63 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:39:56 PM PDT 24
Peak memory 209020 kb
Host smart-79475983-9f16-4ac5-8f9d-54fc8cdc84b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408341850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2408341850
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3262298527
Short name T132
Test name
Test status
Simulation time 28463138398 ps
CPU time 68.56 seconds
Started Aug 19 05:39:52 PM PDT 24
Finished Aug 19 05:41:00 PM PDT 24
Peak memory 216196 kb
Host smart-10ccfebe-9981-4e9c-9a7f-423520f8c9db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262298527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3262298527
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.103924053
Short name T710
Test name
Test status
Simulation time 123818218 ps
CPU time 3.44 seconds
Started Aug 19 05:39:52 PM PDT 24
Finished Aug 19 05:39:55 PM PDT 24
Peak memory 208696 kb
Host smart-45f16ae0-3bd5-4350-a797-31903d5db50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103924053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.103924053
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2697030485
Short name T598
Test name
Test status
Simulation time 51666904 ps
CPU time 0.8 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:40:59 PM PDT 24
Peak memory 206440 kb
Host smart-3be55003-c9d4-4c08-8047-208373975486
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697030485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2697030485
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3422236321
Short name T412
Test name
Test status
Simulation time 288314829 ps
CPU time 4.71 seconds
Started Aug 19 05:40:54 PM PDT 24
Finished Aug 19 05:40:58 PM PDT 24
Peak memory 214820 kb
Host smart-5ff5200d-b684-4d69-b604-3faf6f62bdb9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3422236321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3422236321
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1072197222
Short name T560
Test name
Test status
Simulation time 75288638 ps
CPU time 3.65 seconds
Started Aug 19 05:40:56 PM PDT 24
Finished Aug 19 05:41:00 PM PDT 24
Peak memory 209904 kb
Host smart-46be4938-b436-4184-8a11-9b340cf2f01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072197222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1072197222
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2313179421
Short name T731
Test name
Test status
Simulation time 149700868 ps
CPU time 2.67 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:41:00 PM PDT 24
Peak memory 222616 kb
Host smart-6a9e875d-3321-4dd3-98be-51da11aff13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313179421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2313179421
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3126708912
Short name T339
Test name
Test status
Simulation time 322388232 ps
CPU time 3.55 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:41:02 PM PDT 24
Peak memory 214756 kb
Host smart-b07ab732-480a-4b89-85ef-6adbd8419b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126708912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3126708912
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1108764869
Short name T646
Test name
Test status
Simulation time 171978372 ps
CPU time 5.9 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:41:04 PM PDT 24
Peak memory 214752 kb
Host smart-1faf898a-252a-435f-9025-386b56b6291c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108764869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1108764869
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.4248877447
Short name T883
Test name
Test status
Simulation time 1317918537 ps
CPU time 4.24 seconds
Started Aug 19 05:40:55 PM PDT 24
Finished Aug 19 05:40:59 PM PDT 24
Peak memory 207236 kb
Host smart-d832d9d7-11be-450c-ae19-41831b463122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248877447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.4248877447
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1522333790
Short name T529
Test name
Test status
Simulation time 5568885136 ps
CPU time 70.36 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:42:08 PM PDT 24
Peak memory 209192 kb
Host smart-716f7597-57a9-4255-8075-cc4b52f2e8c6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522333790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1522333790
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1151679234
Short name T875
Test name
Test status
Simulation time 65601796 ps
CPU time 3.31 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:41:01 PM PDT 24
Peak memory 209072 kb
Host smart-5b5d5e6a-0eba-4ee6-b4e7-09486ab89e0d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151679234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1151679234
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1364911046
Short name T579
Test name
Test status
Simulation time 858288694 ps
CPU time 6.73 seconds
Started Aug 19 05:40:54 PM PDT 24
Finished Aug 19 05:41:01 PM PDT 24
Peak memory 208480 kb
Host smart-b287ae81-d550-4d02-ba88-d4e0a0e3b932
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364911046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1364911046
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3851162722
Short name T730
Test name
Test status
Simulation time 160847495 ps
CPU time 3.64 seconds
Started Aug 19 05:40:57 PM PDT 24
Finished Aug 19 05:41:01 PM PDT 24
Peak memory 209636 kb
Host smart-7b794161-d8e2-4077-b515-f36cde831b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851162722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3851162722
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.412833188
Short name T652
Test name
Test status
Simulation time 704174731 ps
CPU time 6.3 seconds
Started Aug 19 05:40:55 PM PDT 24
Finished Aug 19 05:41:01 PM PDT 24
Peak memory 208932 kb
Host smart-90037e60-d9b4-47be-b7d4-79f4c3600297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412833188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.412833188
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3337859883
Short name T407
Test name
Test status
Simulation time 1155246054 ps
CPU time 37.46 seconds
Started Aug 19 05:40:56 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 209132 kb
Host smart-41d53611-f45b-4d22-af46-34394facf06d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337859883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3337859883
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2273729839
Short name T649
Test name
Test status
Simulation time 271252619 ps
CPU time 3 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:41:01 PM PDT 24
Peak memory 210356 kb
Host smart-d3787f62-7583-48df-9a6a-dc61f4df6019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2273729839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2273729839
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2326138520
Short name T439
Test name
Test status
Simulation time 50181900 ps
CPU time 0.76 seconds
Started Aug 19 05:40:59 PM PDT 24
Finished Aug 19 05:41:00 PM PDT 24
Peak memory 206444 kb
Host smart-3e3debe3-7a30-42bd-9d5b-34b9fe1de235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326138520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2326138520
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.955071701
Short name T763
Test name
Test status
Simulation time 39242847 ps
CPU time 2.77 seconds
Started Aug 19 05:41:03 PM PDT 24
Finished Aug 19 05:41:06 PM PDT 24
Peak memory 215776 kb
Host smart-6dba36b0-a0b3-4ad3-971d-7ebdef7f1cbe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=955071701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.955071701
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.239334474
Short name T468
Test name
Test status
Simulation time 343908617 ps
CPU time 2.92 seconds
Started Aug 19 05:41:00 PM PDT 24
Finished Aug 19 05:41:03 PM PDT 24
Peak memory 208788 kb
Host smart-abe50cea-cad9-465d-ad5c-3fe77a45dafb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239334474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.239334474
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.4043935264
Short name T109
Test name
Test status
Simulation time 94833587 ps
CPU time 2.09 seconds
Started Aug 19 05:41:02 PM PDT 24
Finished Aug 19 05:41:04 PM PDT 24
Peak memory 214776 kb
Host smart-8acaf4e4-07d5-4183-9198-12dc9890d511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043935264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.4043935264
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.4188244308
Short name T545
Test name
Test status
Simulation time 198938414 ps
CPU time 3.72 seconds
Started Aug 19 05:40:58 PM PDT 24
Finished Aug 19 05:41:02 PM PDT 24
Peak memory 214808 kb
Host smart-3f004447-3f64-4f4b-9fb1-3195bfef4318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188244308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.4188244308
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2101035120
Short name T647
Test name
Test status
Simulation time 976545497 ps
CPU time 12.89 seconds
Started Aug 19 05:40:59 PM PDT 24
Finished Aug 19 05:41:12 PM PDT 24
Peak memory 209244 kb
Host smart-35f6ef63-fa2d-4a54-814a-46b134b2b3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101035120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2101035120
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.948331770
Short name T332
Test name
Test status
Simulation time 289318362 ps
CPU time 4.72 seconds
Started Aug 19 05:41:00 PM PDT 24
Finished Aug 19 05:41:05 PM PDT 24
Peak memory 209168 kb
Host smart-c0124d5e-4dee-489e-8d51-4c36d81afdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948331770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.948331770
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1115100911
Short name T580
Test name
Test status
Simulation time 542299856 ps
CPU time 3.88 seconds
Started Aug 19 05:41:03 PM PDT 24
Finished Aug 19 05:41:07 PM PDT 24
Peak memory 209216 kb
Host smart-c856ccc9-a0c9-4351-9006-4fa99aba408b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115100911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1115100911
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3939002880
Short name T502
Test name
Test status
Simulation time 159833658 ps
CPU time 6.37 seconds
Started Aug 19 05:41:02 PM PDT 24
Finished Aug 19 05:41:08 PM PDT 24
Peak memory 208552 kb
Host smart-e14aa065-0b42-4175-a67f-80b17b314401
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939002880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3939002880
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2895317108
Short name T505
Test name
Test status
Simulation time 1864428961 ps
CPU time 14.22 seconds
Started Aug 19 05:41:00 PM PDT 24
Finished Aug 19 05:41:14 PM PDT 24
Peak memory 208420 kb
Host smart-5d2b6038-ae83-4f4f-be20-fcaeba2bc8a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895317108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2895317108
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.921672352
Short name T653
Test name
Test status
Simulation time 56361779 ps
CPU time 2.46 seconds
Started Aug 19 05:41:02 PM PDT 24
Finished Aug 19 05:41:05 PM PDT 24
Peak memory 207944 kb
Host smart-cfcce8cd-e4e3-4a3c-893a-3db2832301d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921672352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.921672352
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.333965858
Short name T722
Test name
Test status
Simulation time 1333600029 ps
CPU time 3.69 seconds
Started Aug 19 05:41:05 PM PDT 24
Finished Aug 19 05:41:09 PM PDT 24
Peak memory 208888 kb
Host smart-b201dff7-0355-43d4-9cde-48538bacc7ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333965858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.333965858
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1353963074
Short name T804
Test name
Test status
Simulation time 17301255408 ps
CPU time 47.31 seconds
Started Aug 19 05:41:00 PM PDT 24
Finished Aug 19 05:41:48 PM PDT 24
Peak memory 214936 kb
Host smart-8a09a252-18f5-4b1f-ae06-f4c2ad93c2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353963074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1353963074
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.169831053
Short name T388
Test name
Test status
Simulation time 707034136 ps
CPU time 9.59 seconds
Started Aug 19 05:41:03 PM PDT 24
Finished Aug 19 05:41:12 PM PDT 24
Peak memory 211228 kb
Host smart-c0cfd0d6-444d-4144-95f7-05bf6e7a257f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169831053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.169831053
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.3434517175
Short name T441
Test name
Test status
Simulation time 293745696 ps
CPU time 1.04 seconds
Started Aug 19 05:41:04 PM PDT 24
Finished Aug 19 05:41:05 PM PDT 24
Peak memory 206576 kb
Host smart-f1b06d92-a1ef-4955-bc0e-c4e55f14d2b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434517175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.3434517175
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3539100328
Short name T196
Test name
Test status
Simulation time 61259545 ps
CPU time 2.88 seconds
Started Aug 19 05:40:59 PM PDT 24
Finished Aug 19 05:41:03 PM PDT 24
Peak memory 220244 kb
Host smart-57ee85f1-e3a8-497b-a978-0fb7af76a1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539100328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3539100328
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.192478832
Short name T414
Test name
Test status
Simulation time 104545781 ps
CPU time 3.73 seconds
Started Aug 19 05:41:04 PM PDT 24
Finished Aug 19 05:41:08 PM PDT 24
Peak memory 209232 kb
Host smart-620fa03d-3d56-4f27-a257-e0d5e5c4a267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192478832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.192478832
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.47517441
Short name T39
Test name
Test status
Simulation time 542453014 ps
CPU time 2.12 seconds
Started Aug 19 05:41:00 PM PDT 24
Finished Aug 19 05:41:03 PM PDT 24
Peak memory 214812 kb
Host smart-21af2481-fe37-4ea5-85c8-853c7c793cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47517441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.47517441
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1072825945
Short name T365
Test name
Test status
Simulation time 41521995 ps
CPU time 2.21 seconds
Started Aug 19 05:41:01 PM PDT 24
Finished Aug 19 05:41:04 PM PDT 24
Peak memory 215020 kb
Host smart-115f0152-0a45-4a78-9e89-aa91db7b92f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072825945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1072825945
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3805280161
Short name T624
Test name
Test status
Simulation time 139863062 ps
CPU time 2.81 seconds
Started Aug 19 05:41:05 PM PDT 24
Finished Aug 19 05:41:08 PM PDT 24
Peak memory 210368 kb
Host smart-e29d449a-de2a-4c9a-a628-7da269de54b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805280161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3805280161
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2427784658
Short name T474
Test name
Test status
Simulation time 775204411 ps
CPU time 9.39 seconds
Started Aug 19 05:41:00 PM PDT 24
Finished Aug 19 05:41:10 PM PDT 24
Peak memory 214748 kb
Host smart-06e30860-c8ce-4c5a-a30f-b8d78e65ab3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427784658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2427784658
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2371835066
Short name T481
Test name
Test status
Simulation time 155724359 ps
CPU time 5.3 seconds
Started Aug 19 05:40:59 PM PDT 24
Finished Aug 19 05:41:04 PM PDT 24
Peak memory 209168 kb
Host smart-8014ccd7-e70c-4b1d-8b64-773fc238699c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371835066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2371835066
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.576819201
Short name T446
Test name
Test status
Simulation time 137070669 ps
CPU time 2.17 seconds
Started Aug 19 05:41:02 PM PDT 24
Finished Aug 19 05:41:04 PM PDT 24
Peak memory 207332 kb
Host smart-03f4c051-7f0c-42a6-b50a-3a117e81a518
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576819201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.576819201
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3648821500
Short name T513
Test name
Test status
Simulation time 161757431 ps
CPU time 5.07 seconds
Started Aug 19 05:41:02 PM PDT 24
Finished Aug 19 05:41:07 PM PDT 24
Peak memory 208640 kb
Host smart-51516b70-7ac4-4881-a6ac-2090ac35b83b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648821500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3648821500
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.4036863118
Short name T878
Test name
Test status
Simulation time 1710771601 ps
CPU time 12.26 seconds
Started Aug 19 05:41:05 PM PDT 24
Finished Aug 19 05:41:17 PM PDT 24
Peak memory 208480 kb
Host smart-171efd23-8816-47aa-a5f2-ae4d5535acce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036863118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.4036863118
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2823777782
Short name T613
Test name
Test status
Simulation time 830040188 ps
CPU time 12.44 seconds
Started Aug 19 05:40:59 PM PDT 24
Finished Aug 19 05:41:12 PM PDT 24
Peak memory 209924 kb
Host smart-4d942fb5-0d63-4e91-8178-795aa1be5e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823777782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2823777782
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3166127989
Short name T466
Test name
Test status
Simulation time 559905827 ps
CPU time 2.77 seconds
Started Aug 19 05:41:01 PM PDT 24
Finished Aug 19 05:41:04 PM PDT 24
Peak memory 208992 kb
Host smart-72a577f8-d5e8-43df-b42d-4abb141c631d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166127989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3166127989
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2943209674
Short name T590
Test name
Test status
Simulation time 441835902 ps
CPU time 20.42 seconds
Started Aug 19 05:41:05 PM PDT 24
Finished Aug 19 05:41:26 PM PDT 24
Peak memory 222736 kb
Host smart-53c2f950-2248-42ca-9fa6-abd406064615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943209674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2943209674
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.4275782679
Short name T562
Test name
Test status
Simulation time 90729162 ps
CPU time 4.9 seconds
Started Aug 19 05:41:02 PM PDT 24
Finished Aug 19 05:41:07 PM PDT 24
Peak memory 214832 kb
Host smart-a23d60df-58c4-4d23-8a8d-558a2bdf3a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275782679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.4275782679
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2002937957
Short name T844
Test name
Test status
Simulation time 117496716 ps
CPU time 1.98 seconds
Started Aug 19 05:41:00 PM PDT 24
Finished Aug 19 05:41:02 PM PDT 24
Peak memory 210156 kb
Host smart-1b0f87cd-a000-4180-8497-f73124e6eeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002937957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2002937957
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3107754114
Short name T490
Test name
Test status
Simulation time 70264213 ps
CPU time 0.87 seconds
Started Aug 19 05:41:10 PM PDT 24
Finished Aug 19 05:41:11 PM PDT 24
Peak memory 206432 kb
Host smart-3a52616f-25f5-42a6-8ec0-dc73302a021f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107754114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3107754114
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1004759862
Short name T395
Test name
Test status
Simulation time 160694266 ps
CPU time 2.61 seconds
Started Aug 19 05:41:04 PM PDT 24
Finished Aug 19 05:41:07 PM PDT 24
Peak memory 214752 kb
Host smart-8719bda0-0474-4430-8cd8-82b13dde65d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004759862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1004759862
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2493223300
Short name T638
Test name
Test status
Simulation time 156413901 ps
CPU time 2.91 seconds
Started Aug 19 05:41:06 PM PDT 24
Finished Aug 19 05:41:09 PM PDT 24
Peak memory 210684 kb
Host smart-e634215c-7b11-48c1-bca6-7fd5c1d74714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493223300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2493223300
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.449263053
Short name T551
Test name
Test status
Simulation time 436902539 ps
CPU time 5.22 seconds
Started Aug 19 05:41:11 PM PDT 24
Finished Aug 19 05:41:16 PM PDT 24
Peak memory 214796 kb
Host smart-e8571a23-5562-4713-b3f5-5d2e3df59cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449263053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.449263053
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.1063570432
Short name T897
Test name
Test status
Simulation time 95757146 ps
CPU time 3.68 seconds
Started Aug 19 05:41:04 PM PDT 24
Finished Aug 19 05:41:07 PM PDT 24
Peak memory 219328 kb
Host smart-6d57d2ee-4e43-42ae-b517-0a6991b1b54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063570432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.1063570432
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3758210420
Short name T376
Test name
Test status
Simulation time 691198872 ps
CPU time 5.3 seconds
Started Aug 19 05:41:00 PM PDT 24
Finished Aug 19 05:41:06 PM PDT 24
Peak memory 208056 kb
Host smart-ca0f7cb7-f9bd-4db6-8454-e94d4bcf7981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758210420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3758210420
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1809548716
Short name T888
Test name
Test status
Simulation time 49662041 ps
CPU time 3.03 seconds
Started Aug 19 05:41:03 PM PDT 24
Finished Aug 19 05:41:06 PM PDT 24
Peak memory 207296 kb
Host smart-e849e00e-aa6a-4eba-b380-b5bda150906f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809548716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1809548716
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2369842706
Short name T592
Test name
Test status
Simulation time 74421037 ps
CPU time 2.79 seconds
Started Aug 19 05:41:00 PM PDT 24
Finished Aug 19 05:41:03 PM PDT 24
Peak memory 209544 kb
Host smart-a85717be-ce1b-40b8-b17c-8927b51cf242
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369842706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2369842706
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1984104318
Short name T853
Test name
Test status
Simulation time 2706304833 ps
CPU time 17.04 seconds
Started Aug 19 05:41:01 PM PDT 24
Finished Aug 19 05:41:18 PM PDT 24
Peak memory 208436 kb
Host smart-19c48595-d071-42d5-87c9-f3aaa30def41
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984104318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1984104318
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2459537554
Short name T885
Test name
Test status
Simulation time 58719230 ps
CPU time 2.59 seconds
Started Aug 19 05:41:03 PM PDT 24
Finished Aug 19 05:41:06 PM PDT 24
Peak memory 208972 kb
Host smart-d9f2dcdd-02eb-492c-b4f3-37a2d884d65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459537554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2459537554
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.18571086
Short name T194
Test name
Test status
Simulation time 826967031 ps
CPU time 8.62 seconds
Started Aug 19 05:41:08 PM PDT 24
Finished Aug 19 05:41:17 PM PDT 24
Peak memory 218592 kb
Host smart-2cac823f-c678-487d-8dcc-68162819c599
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18571086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.18571086
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1916958794
Short name T326
Test name
Test status
Simulation time 47395223 ps
CPU time 3.14 seconds
Started Aug 19 05:41:11 PM PDT 24
Finished Aug 19 05:41:14 PM PDT 24
Peak memory 208428 kb
Host smart-0eb53d5d-4eb9-4a00-8213-fdb4d2cd6126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916958794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1916958794
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2613754128
Short name T508
Test name
Test status
Simulation time 58479600 ps
CPU time 1.67 seconds
Started Aug 19 05:41:12 PM PDT 24
Finished Aug 19 05:41:14 PM PDT 24
Peak memory 210196 kb
Host smart-e72d00f5-2bc0-473c-a66a-6b01b6898cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613754128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2613754128
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2038842981
Short name T835
Test name
Test status
Simulation time 20909080 ps
CPU time 0.84 seconds
Started Aug 19 05:41:10 PM PDT 24
Finished Aug 19 05:41:11 PM PDT 24
Peak memory 206388 kb
Host smart-af7e8fc4-a90e-452c-9bdd-f0b188ca31bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038842981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2038842981
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.27410078
Short name T128
Test name
Test status
Simulation time 58107938 ps
CPU time 2.53 seconds
Started Aug 19 05:41:13 PM PDT 24
Finished Aug 19 05:41:15 PM PDT 24
Peak memory 208868 kb
Host smart-ef8a8700-1940-4981-a9aa-f1e10a389dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27410078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.27410078
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1325991940
Short name T1
Test name
Test status
Simulation time 56185421 ps
CPU time 2.33 seconds
Started Aug 19 05:41:11 PM PDT 24
Finished Aug 19 05:41:13 PM PDT 24
Peak memory 214844 kb
Host smart-4d02318d-8674-4103-a2dd-23552db5dd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325991940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1325991940
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3299991043
Short name T258
Test name
Test status
Simulation time 299987066 ps
CPU time 5.19 seconds
Started Aug 19 05:41:15 PM PDT 24
Finished Aug 19 05:41:20 PM PDT 24
Peak memory 214724 kb
Host smart-6f6a2402-321a-414c-9e58-986a18b32bf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299991043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3299991043
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1873089629
Short name T116
Test name
Test status
Simulation time 132755342 ps
CPU time 3.54 seconds
Started Aug 19 05:41:14 PM PDT 24
Finished Aug 19 05:41:18 PM PDT 24
Peak memory 216684 kb
Host smart-aa335700-fd0d-43e6-a2ad-edf641243450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1873089629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1873089629
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.66161220
Short name T418
Test name
Test status
Simulation time 11110926175 ps
CPU time 28.42 seconds
Started Aug 19 05:41:15 PM PDT 24
Finished Aug 19 05:41:43 PM PDT 24
Peak memory 220216 kb
Host smart-06e33a93-e701-4bd2-8d14-696b58454f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66161220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.66161220
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.3037007516
Short name T311
Test name
Test status
Simulation time 50904309 ps
CPU time 2.18 seconds
Started Aug 19 05:41:13 PM PDT 24
Finished Aug 19 05:41:15 PM PDT 24
Peak memory 207344 kb
Host smart-69e3aa98-71c7-44d7-979b-69b02cfea885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037007516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.3037007516
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3894476875
Short name T520
Test name
Test status
Simulation time 133760972 ps
CPU time 4.58 seconds
Started Aug 19 05:41:11 PM PDT 24
Finished Aug 19 05:41:16 PM PDT 24
Peak memory 207332 kb
Host smart-1bcf54c5-57aa-4c2d-84fc-48d11533e9c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894476875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3894476875
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1106252678
Short name T444
Test name
Test status
Simulation time 4428258584 ps
CPU time 47.32 seconds
Started Aug 19 05:41:10 PM PDT 24
Finished Aug 19 05:41:57 PM PDT 24
Peak memory 208940 kb
Host smart-c4a34fcd-b077-435d-97cb-4e0c74bcec56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106252678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1106252678
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4293414189
Short name T723
Test name
Test status
Simulation time 157021030 ps
CPU time 3.83 seconds
Started Aug 19 05:41:13 PM PDT 24
Finished Aug 19 05:41:17 PM PDT 24
Peak memory 207412 kb
Host smart-101cb622-440d-4bf0-9e9e-e5cd5a10b0ef
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293414189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4293414189
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3676820862
Short name T283
Test name
Test status
Simulation time 185978620 ps
CPU time 2.29 seconds
Started Aug 19 05:41:12 PM PDT 24
Finished Aug 19 05:41:14 PM PDT 24
Peak memory 210360 kb
Host smart-413462b1-52a9-4ac3-b1da-84cbd7e5a61f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676820862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3676820862
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1349065610
Short name T398
Test name
Test status
Simulation time 97186343 ps
CPU time 2.59 seconds
Started Aug 19 05:41:12 PM PDT 24
Finished Aug 19 05:41:15 PM PDT 24
Peak memory 207304 kb
Host smart-566e56cc-7fcb-4e88-aad0-26e03dd20189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349065610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1349065610
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2232832753
Short name T600
Test name
Test status
Simulation time 84925674 ps
CPU time 4 seconds
Started Aug 19 05:41:15 PM PDT 24
Finished Aug 19 05:41:19 PM PDT 24
Peak memory 214800 kb
Host smart-22b4eb29-8274-4892-905d-29ae1fadaf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232832753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2232832753
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.1988588506
Short name T390
Test name
Test status
Simulation time 53386736 ps
CPU time 2.8 seconds
Started Aug 19 05:41:13 PM PDT 24
Finished Aug 19 05:41:16 PM PDT 24
Peak memory 210592 kb
Host smart-fa19c7e0-4d49-4dde-8c54-9be12e486e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988588506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.1988588506
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.1167368135
Short name T436
Test name
Test status
Simulation time 24498791 ps
CPU time 0.87 seconds
Started Aug 19 05:41:23 PM PDT 24
Finished Aug 19 05:41:24 PM PDT 24
Peak memory 206376 kb
Host smart-d79b6e55-60f2-400d-8913-d50b106d3e7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167368135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1167368135
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.332303432
Short name T382
Test name
Test status
Simulation time 664159646 ps
CPU time 8 seconds
Started Aug 19 05:41:10 PM PDT 24
Finished Aug 19 05:41:18 PM PDT 24
Peak memory 222040 kb
Host smart-d77bb72d-0405-434f-a007-7af1830dcc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332303432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.332303432
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3905180399
Short name T314
Test name
Test status
Simulation time 30462379 ps
CPU time 2.12 seconds
Started Aug 19 05:41:10 PM PDT 24
Finished Aug 19 05:41:12 PM PDT 24
Peak memory 208484 kb
Host smart-bc7cfe45-4c03-492e-b86f-87110eaf11a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905180399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3905180399
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1936772851
Short name T38
Test name
Test status
Simulation time 364258690 ps
CPU time 3.97 seconds
Started Aug 19 05:41:11 PM PDT 24
Finished Aug 19 05:41:15 PM PDT 24
Peak memory 209744 kb
Host smart-2ad855b8-ff97-4eb9-83da-27ed6b9179a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936772851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1936772851
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3396832590
Short name T627
Test name
Test status
Simulation time 728466967 ps
CPU time 3.19 seconds
Started Aug 19 05:41:11 PM PDT 24
Finished Aug 19 05:41:15 PM PDT 24
Peak memory 222904 kb
Host smart-74cfd383-2a2e-4898-82a6-0ea3b6fcd69b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396832590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3396832590
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3240451695
Short name T236
Test name
Test status
Simulation time 76070220 ps
CPU time 4.47 seconds
Started Aug 19 05:41:13 PM PDT 24
Finished Aug 19 05:41:17 PM PDT 24
Peak memory 210756 kb
Host smart-f645b186-c661-444f-af88-6ef783a98c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240451695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3240451695
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.201187557
Short name T866
Test name
Test status
Simulation time 145933163 ps
CPU time 5.98 seconds
Started Aug 19 05:41:14 PM PDT 24
Finished Aug 19 05:41:20 PM PDT 24
Peak memory 208656 kb
Host smart-caf2f0c6-1252-4f20-8f87-8cc9e463455f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201187557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.201187557
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2770311034
Short name T801
Test name
Test status
Simulation time 111249352 ps
CPU time 2.31 seconds
Started Aug 19 05:41:13 PM PDT 24
Finished Aug 19 05:41:15 PM PDT 24
Peak memory 207452 kb
Host smart-c9a8fc41-2dd7-4afb-a677-94bb720bf2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770311034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2770311034
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2613110691
Short name T789
Test name
Test status
Simulation time 302537620 ps
CPU time 2.97 seconds
Started Aug 19 05:41:14 PM PDT 24
Finished Aug 19 05:41:17 PM PDT 24
Peak memory 207356 kb
Host smart-9cabc343-6ad1-4a89-9c7c-6be4d4729e4a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613110691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2613110691
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.95545850
Short name T341
Test name
Test status
Simulation time 87672296 ps
CPU time 1.9 seconds
Started Aug 19 05:41:12 PM PDT 24
Finished Aug 19 05:41:14 PM PDT 24
Peak memory 208204 kb
Host smart-2282d53c-be4c-4519-ad59-bd7c39a7531f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95545850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.95545850
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3479996417
Short name T867
Test name
Test status
Simulation time 95527148 ps
CPU time 1.92 seconds
Started Aug 19 05:41:15 PM PDT 24
Finished Aug 19 05:41:17 PM PDT 24
Peak memory 208604 kb
Host smart-c3a198c2-1e26-4bba-a8ee-71989382d9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479996417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3479996417
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3571035872
Short name T810
Test name
Test status
Simulation time 933088383 ps
CPU time 6.88 seconds
Started Aug 19 05:41:12 PM PDT 24
Finished Aug 19 05:41:19 PM PDT 24
Peak memory 209144 kb
Host smart-944ad673-a14d-478f-8e8e-8e6c7ec1ba86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571035872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3571035872
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2573173636
Short name T254
Test name
Test status
Simulation time 206980367 ps
CPU time 11.5 seconds
Started Aug 19 05:41:10 PM PDT 24
Finished Aug 19 05:41:22 PM PDT 24
Peak memory 222972 kb
Host smart-85446223-5a63-4ad0-bf74-7b747d49fb2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573173636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2573173636
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.66093904
Short name T80
Test name
Test status
Simulation time 278940479 ps
CPU time 18.05 seconds
Started Aug 19 05:41:08 PM PDT 24
Finished Aug 19 05:41:26 PM PDT 24
Peak memory 222992 kb
Host smart-2f2feeea-b04a-4bf6-bc8c-4f236ae4b867
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66093904 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.66093904
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.688173589
Short name T880
Test name
Test status
Simulation time 241619500 ps
CPU time 8.15 seconds
Started Aug 19 05:41:13 PM PDT 24
Finished Aug 19 05:41:22 PM PDT 24
Peak memory 210332 kb
Host smart-120fd1d3-f42f-499a-a33c-f4a4396902fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688173589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.688173589
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.4066672980
Short name T498
Test name
Test status
Simulation time 64450040 ps
CPU time 1.04 seconds
Started Aug 19 05:41:20 PM PDT 24
Finished Aug 19 05:41:22 PM PDT 24
Peak memory 206588 kb
Host smart-88c91c58-5869-4806-9c80-43d2cd59f868
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066672980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.4066672980
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3495454494
Short name T303
Test name
Test status
Simulation time 2881906841 ps
CPU time 38.78 seconds
Started Aug 19 05:41:17 PM PDT 24
Finished Aug 19 05:41:56 PM PDT 24
Peak memory 215572 kb
Host smart-e019893c-7e2b-4762-83a5-ad93673e059b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3495454494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3495454494
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2797531876
Short name T33
Test name
Test status
Simulation time 294562193 ps
CPU time 2.66 seconds
Started Aug 19 05:41:19 PM PDT 24
Finished Aug 19 05:41:22 PM PDT 24
Peak memory 209564 kb
Host smart-4ceb1b1b-afb2-45d1-acbd-6ea432ff4b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797531876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2797531876
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3498447511
Short name T868
Test name
Test status
Simulation time 313964501 ps
CPU time 1.99 seconds
Started Aug 19 05:41:21 PM PDT 24
Finished Aug 19 05:41:23 PM PDT 24
Peak memory 207892 kb
Host smart-5d4b868c-808f-4c11-aee2-178bf6b8165f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498447511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3498447511
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2646735603
Short name T52
Test name
Test status
Simulation time 834839217 ps
CPU time 3.96 seconds
Started Aug 19 05:41:26 PM PDT 24
Finished Aug 19 05:41:30 PM PDT 24
Peak memory 220768 kb
Host smart-1b328236-779d-467d-9c52-c7d8326b44ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646735603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2646735603
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.425162629
Short name T256
Test name
Test status
Simulation time 452118128 ps
CPU time 4.68 seconds
Started Aug 19 05:41:22 PM PDT 24
Finished Aug 19 05:41:27 PM PDT 24
Peak memory 222868 kb
Host smart-6fab808b-8e21-4d40-a571-961ad649f1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425162629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.425162629
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2309815649
Short name T214
Test name
Test status
Simulation time 127632453 ps
CPU time 3.13 seconds
Started Aug 19 05:41:18 PM PDT 24
Finished Aug 19 05:41:22 PM PDT 24
Peak memory 220860 kb
Host smart-f93066ce-da9a-4ad2-adaa-f04bf1d7d6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309815649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2309815649
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.4234156453
Short name T136
Test name
Test status
Simulation time 1192969908 ps
CPU time 13.32 seconds
Started Aug 19 05:41:23 PM PDT 24
Finished Aug 19 05:41:37 PM PDT 24
Peak memory 209732 kb
Host smart-e530515e-fa09-4162-99cb-2af304d984a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234156453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.4234156453
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.400787562
Short name T497
Test name
Test status
Simulation time 2040273781 ps
CPU time 4.34 seconds
Started Aug 19 05:41:21 PM PDT 24
Finished Aug 19 05:41:25 PM PDT 24
Peak memory 208960 kb
Host smart-aa611aac-eafe-458b-b52b-f2b98f2f0669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400787562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.400787562
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3357495602
Short name T660
Test name
Test status
Simulation time 237833148 ps
CPU time 6.56 seconds
Started Aug 19 05:41:19 PM PDT 24
Finished Aug 19 05:41:26 PM PDT 24
Peak memory 208484 kb
Host smart-5720e3e1-a370-4357-aa36-d7bf6808808a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357495602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3357495602
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3125119211
Short name T482
Test name
Test status
Simulation time 71699942 ps
CPU time 2.39 seconds
Started Aug 19 05:41:20 PM PDT 24
Finished Aug 19 05:41:22 PM PDT 24
Peak memory 207492 kb
Host smart-7b279d1a-4e9e-4eac-bd05-21aac927d871
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125119211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3125119211
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.169268669
Short name T886
Test name
Test status
Simulation time 301422701 ps
CPU time 4.99 seconds
Started Aug 19 05:41:21 PM PDT 24
Finished Aug 19 05:41:26 PM PDT 24
Peak memory 208544 kb
Host smart-aba72d50-2f4b-4090-b6e3-885d5d658031
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169268669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.169268669
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.736574152
Short name T914
Test name
Test status
Simulation time 30330834 ps
CPU time 2.26 seconds
Started Aug 19 05:41:22 PM PDT 24
Finished Aug 19 05:41:24 PM PDT 24
Peak memory 216568 kb
Host smart-87414208-a0a8-4ea1-a76b-84c22b6df901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736574152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.736574152
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2234586719
Short name T603
Test name
Test status
Simulation time 48224414 ps
CPU time 2.41 seconds
Started Aug 19 05:41:23 PM PDT 24
Finished Aug 19 05:41:26 PM PDT 24
Peak memory 207260 kb
Host smart-6f16714c-2d7f-4c61-a2c9-d63a86ec90e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234586719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2234586719
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2773945403
Short name T233
Test name
Test status
Simulation time 11254511090 ps
CPU time 105.12 seconds
Started Aug 19 05:41:20 PM PDT 24
Finished Aug 19 05:43:05 PM PDT 24
Peak memory 223032 kb
Host smart-549d8c97-889c-4276-9796-783e3c625628
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773945403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2773945403
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1818656316
Short name T413
Test name
Test status
Simulation time 97562566 ps
CPU time 4.64 seconds
Started Aug 19 05:41:21 PM PDT 24
Finished Aug 19 05:41:26 PM PDT 24
Peak memory 209460 kb
Host smart-78e69b22-711a-47a2-8267-c42cafe90820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818656316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1818656316
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.375921413
Short name T164
Test name
Test status
Simulation time 81838928 ps
CPU time 2.47 seconds
Started Aug 19 05:41:25 PM PDT 24
Finished Aug 19 05:41:27 PM PDT 24
Peak memory 210392 kb
Host smart-85fedf30-b4b4-4f6d-87bb-f9aeba11d99e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375921413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.375921413
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.480150678
Short name T512
Test name
Test status
Simulation time 11515044 ps
CPU time 0.84 seconds
Started Aug 19 05:41:21 PM PDT 24
Finished Aug 19 05:41:22 PM PDT 24
Peak memory 206420 kb
Host smart-30b2c594-6053-4873-823b-f3cb74ffa123
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480150678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.480150678
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1866588052
Short name T425
Test name
Test status
Simulation time 50618146 ps
CPU time 2.18 seconds
Started Aug 19 05:41:18 PM PDT 24
Finished Aug 19 05:41:20 PM PDT 24
Peak memory 214784 kb
Host smart-2742b657-1382-497e-8a98-14c270bbeb9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1866588052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1866588052
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3047518626
Short name T225
Test name
Test status
Simulation time 287414157 ps
CPU time 2.58 seconds
Started Aug 19 05:41:19 PM PDT 24
Finished Aug 19 05:41:22 PM PDT 24
Peak memory 214800 kb
Host smart-278b017f-e9cc-4099-8faa-7889a965ce8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047518626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3047518626
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1098556873
Short name T725
Test name
Test status
Simulation time 184835775 ps
CPU time 4.8 seconds
Started Aug 19 05:41:25 PM PDT 24
Finished Aug 19 05:41:29 PM PDT 24
Peak memory 222896 kb
Host smart-52429151-3470-47b2-9e02-9492f24a3511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098556873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1098556873
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1249116333
Short name T316
Test name
Test status
Simulation time 417324513 ps
CPU time 3.39 seconds
Started Aug 19 05:41:19 PM PDT 24
Finished Aug 19 05:41:23 PM PDT 24
Peak memory 206568 kb
Host smart-512b7564-cd65-431e-b5c5-ca34807d4659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249116333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1249116333
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3891470438
Short name T198
Test name
Test status
Simulation time 49147186 ps
CPU time 2.35 seconds
Started Aug 19 05:41:22 PM PDT 24
Finished Aug 19 05:41:24 PM PDT 24
Peak memory 222924 kb
Host smart-f78d3978-cb0c-47dc-90f6-6c124cfb2763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891470438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3891470438
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3537168473
Short name T265
Test name
Test status
Simulation time 1044802420 ps
CPU time 7.79 seconds
Started Aug 19 05:41:19 PM PDT 24
Finished Aug 19 05:41:28 PM PDT 24
Peak memory 214812 kb
Host smart-bbd23421-a8dc-493d-bbe3-9ad3e9073b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537168473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3537168473
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.4218258520
Short name T689
Test name
Test status
Simulation time 81173448 ps
CPU time 1.82 seconds
Started Aug 19 05:41:17 PM PDT 24
Finished Aug 19 05:41:19 PM PDT 24
Peak memory 207480 kb
Host smart-e63a7534-9bd2-480f-9ddb-aba196331101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218258520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.4218258520
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.864403671
Short name T760
Test name
Test status
Simulation time 182553759 ps
CPU time 2.57 seconds
Started Aug 19 05:41:20 PM PDT 24
Finished Aug 19 05:41:23 PM PDT 24
Peak memory 209024 kb
Host smart-0c600fcc-b10f-483e-8999-7e766e0ec3c0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864403671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.864403671
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.761841250
Short name T637
Test name
Test status
Simulation time 55123986 ps
CPU time 2.62 seconds
Started Aug 19 05:41:22 PM PDT 24
Finished Aug 19 05:41:25 PM PDT 24
Peak memory 208996 kb
Host smart-09f5ee72-069d-45e9-aff2-e0afcf9591c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761841250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.761841250
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2345037753
Short name T857
Test name
Test status
Simulation time 2110114462 ps
CPU time 5.07 seconds
Started Aug 19 05:41:19 PM PDT 24
Finished Aug 19 05:41:24 PM PDT 24
Peak memory 207480 kb
Host smart-10089c28-7453-4ad6-aa2e-6a1cb47ecaa0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345037753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2345037753
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.4165932191
Short name T581
Test name
Test status
Simulation time 136554964 ps
CPU time 2.11 seconds
Started Aug 19 05:41:20 PM PDT 24
Finished Aug 19 05:41:22 PM PDT 24
Peak memory 216488 kb
Host smart-8f3e3a49-365b-417f-aace-30e255d15845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165932191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.4165932191
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.531846791
Short name T572
Test name
Test status
Simulation time 346158804 ps
CPU time 3.34 seconds
Started Aug 19 05:41:21 PM PDT 24
Finished Aug 19 05:41:24 PM PDT 24
Peak memory 207180 kb
Host smart-f7ba304b-3de1-4c33-982b-c4e7f02ea4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531846791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.531846791
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2050964824
Short name T344
Test name
Test status
Simulation time 6431857948 ps
CPU time 23.41 seconds
Started Aug 19 05:41:22 PM PDT 24
Finished Aug 19 05:41:45 PM PDT 24
Peak memory 220196 kb
Host smart-d23e213c-5b4b-46d5-983a-ad286e1a010c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050964824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2050964824
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.3702959425
Short name T11
Test name
Test status
Simulation time 202040614 ps
CPU time 7.15 seconds
Started Aug 19 05:41:23 PM PDT 24
Finished Aug 19 05:41:30 PM PDT 24
Peak memory 220408 kb
Host smart-3902c1aa-6193-429d-9f3d-6cf00867f09c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702959425 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.3702959425
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3820958873
Short name T427
Test name
Test status
Simulation time 7948111023 ps
CPU time 41.44 seconds
Started Aug 19 05:41:21 PM PDT 24
Finished Aug 19 05:42:03 PM PDT 24
Peak memory 209604 kb
Host smart-5ef347bf-8c40-4b8c-aeb2-f9bf1acd0688
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820958873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3820958873
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3758673618
Short name T719
Test name
Test status
Simulation time 472318008 ps
CPU time 3.68 seconds
Started Aug 19 05:41:22 PM PDT 24
Finished Aug 19 05:41:26 PM PDT 24
Peak memory 210964 kb
Host smart-89325cbf-d988-4871-b04f-36fb73fcb029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758673618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3758673618
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.109409157
Short name T440
Test name
Test status
Simulation time 28936437 ps
CPU time 0.85 seconds
Started Aug 19 05:41:31 PM PDT 24
Finished Aug 19 05:41:32 PM PDT 24
Peak memory 206420 kb
Host smart-b3ee09ea-1ec0-4055-8b82-183be60af290
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109409157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.109409157
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.853991549
Short name T298
Test name
Test status
Simulation time 625208138 ps
CPU time 11 seconds
Started Aug 19 05:41:20 PM PDT 24
Finished Aug 19 05:41:32 PM PDT 24
Peak memory 216100 kb
Host smart-40d840de-a180-4780-9ba5-1c609e4ffca1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853991549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.853991549
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1231697522
Short name T60
Test name
Test status
Simulation time 46704379 ps
CPU time 2.43 seconds
Started Aug 19 05:41:30 PM PDT 24
Finished Aug 19 05:41:33 PM PDT 24
Peak memory 209808 kb
Host smart-f655a376-dcdc-4f83-88d3-0265d11b313f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231697522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1231697522
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1483791365
Short name T40
Test name
Test status
Simulation time 466910397 ps
CPU time 7.16 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:40 PM PDT 24
Peak memory 209132 kb
Host smart-a9fee65d-410b-44d8-b3a6-be55a836f164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483791365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1483791365
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1126306705
Short name T630
Test name
Test status
Simulation time 47820566 ps
CPU time 1.8 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 214896 kb
Host smart-3641997f-cb70-4bdd-b0aa-2131ebd2187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126306705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1126306705
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3955573003
Short name T355
Test name
Test status
Simulation time 1059729715 ps
CPU time 8.75 seconds
Started Aug 19 05:41:22 PM PDT 24
Finished Aug 19 05:41:31 PM PDT 24
Peak memory 209840 kb
Host smart-a740efbb-7cf6-40f9-9108-ea390c6990e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955573003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3955573003
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1478857916
Short name T528
Test name
Test status
Simulation time 760932341 ps
CPU time 5.41 seconds
Started Aug 19 05:41:22 PM PDT 24
Finished Aug 19 05:41:27 PM PDT 24
Peak memory 209156 kb
Host smart-5a68d3d5-4606-4510-aa0e-29cdf7531e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478857916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1478857916
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2614924866
Short name T908
Test name
Test status
Simulation time 626659019 ps
CPU time 4.48 seconds
Started Aug 19 05:41:18 PM PDT 24
Finished Aug 19 05:41:23 PM PDT 24
Peak memory 207496 kb
Host smart-2df5ef2b-7bed-4d0b-bf9a-d6d543cb0cae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614924866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2614924866
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1453265838
Short name T861
Test name
Test status
Simulation time 92340280 ps
CPU time 3.62 seconds
Started Aug 19 05:41:23 PM PDT 24
Finished Aug 19 05:41:27 PM PDT 24
Peak memory 209304 kb
Host smart-69b797ae-2b68-47e2-9d9f-21bfdb185f89
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453265838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1453265838
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2270836305
Short name T312
Test name
Test status
Simulation time 116061859 ps
CPU time 3.25 seconds
Started Aug 19 05:41:26 PM PDT 24
Finished Aug 19 05:41:29 PM PDT 24
Peak memory 207448 kb
Host smart-6ebfcf09-56c0-4faa-a72b-96525a122cdd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270836305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2270836305
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3761757836
Short name T889
Test name
Test status
Simulation time 148476117 ps
CPU time 2.58 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:35 PM PDT 24
Peak memory 208960 kb
Host smart-d44d365a-87d5-4382-9417-a69993c45f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761757836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3761757836
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.42921052
Short name T798
Test name
Test status
Simulation time 1009683754 ps
CPU time 2.94 seconds
Started Aug 19 05:41:21 PM PDT 24
Finished Aug 19 05:41:24 PM PDT 24
Peak memory 209204 kb
Host smart-9a02daf2-43b3-433a-989e-bf601c2f8158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42921052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.42921052
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1465113754
Short name T356
Test name
Test status
Simulation time 127761141 ps
CPU time 5.52 seconds
Started Aug 19 05:41:31 PM PDT 24
Finished Aug 19 05:41:36 PM PDT 24
Peak memory 210600 kb
Host smart-a30401a5-fc1f-41d6-b9e1-e4752e4aa3f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465113754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1465113754
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3293276580
Short name T300
Test name
Test status
Simulation time 230983916 ps
CPU time 8.58 seconds
Started Aug 19 05:41:30 PM PDT 24
Finished Aug 19 05:41:38 PM PDT 24
Peak memory 223040 kb
Host smart-1dc87023-fe96-40c7-955e-c0abd77eb53a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293276580 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3293276580
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.712934777
Short name T292
Test name
Test status
Simulation time 370212166 ps
CPU time 3.86 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:36 PM PDT 24
Peak memory 208072 kb
Host smart-da908267-b28b-4746-9ae3-623f1a2bb0b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712934777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.712934777
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3989471277
Short name T521
Test name
Test status
Simulation time 1106361290 ps
CPU time 3.11 seconds
Started Aug 19 05:41:30 PM PDT 24
Finished Aug 19 05:41:33 PM PDT 24
Peak memory 210488 kb
Host smart-a7a5a026-f612-4b8d-a634-bc5191c6b74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989471277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3989471277
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1609236390
Short name T803
Test name
Test status
Simulation time 43676377 ps
CPU time 0.93 seconds
Started Aug 19 05:41:33 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 206484 kb
Host smart-06d88da6-952a-4ddb-a9e3-81285dbc9f3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609236390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1609236390
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.1010481054
Short name T410
Test name
Test status
Simulation time 162263341 ps
CPU time 4.85 seconds
Started Aug 19 05:41:34 PM PDT 24
Finished Aug 19 05:41:39 PM PDT 24
Peak memory 215932 kb
Host smart-8055fb5b-1e67-4628-b26b-2a40343e86b2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010481054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1010481054
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3176769991
Short name T28
Test name
Test status
Simulation time 91608311 ps
CPU time 2.71 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:35 PM PDT 24
Peak memory 218776 kb
Host smart-a28d9cef-dcd7-4794-8e8b-3739cc40000e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176769991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3176769991
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1493280091
Short name T668
Test name
Test status
Simulation time 480518514 ps
CPU time 3.95 seconds
Started Aug 19 05:41:29 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 211000 kb
Host smart-6cbf3a0f-8646-4bbc-b960-f93c0ef0ab93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493280091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1493280091
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3831521930
Short name T277
Test name
Test status
Simulation time 254227593 ps
CPU time 3.44 seconds
Started Aug 19 05:41:31 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 214888 kb
Host smart-00a9f6f9-16d4-4c70-b4f8-ad62586ca210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831521930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3831521930
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.4116613593
Short name T639
Test name
Test status
Simulation time 121063811 ps
CPU time 2.18 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 214744 kb
Host smart-1525c264-ff35-40e3-ae16-1152d34e732d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116613593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.4116613593
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3914169848
Short name T205
Test name
Test status
Simulation time 54938914 ps
CPU time 2.91 seconds
Started Aug 19 05:41:27 PM PDT 24
Finished Aug 19 05:41:30 PM PDT 24
Peak memory 214808 kb
Host smart-42a2071f-5647-4246-83ee-c4edd83f0d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914169848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3914169848
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1081825113
Short name T615
Test name
Test status
Simulation time 107787777 ps
CPU time 2.42 seconds
Started Aug 19 05:41:31 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 207992 kb
Host smart-0b1f4192-faf8-466c-9463-522ab7a1d557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081825113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1081825113
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1086698374
Short name T691
Test name
Test status
Simulation time 210793438 ps
CPU time 5.93 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:38 PM PDT 24
Peak memory 209276 kb
Host smart-ae33b9bc-ac86-4b4f-b137-625323a7b6d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086698374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1086698374
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.905525291
Short name T717
Test name
Test status
Simulation time 131408892 ps
CPU time 4.25 seconds
Started Aug 19 05:41:31 PM PDT 24
Finished Aug 19 05:41:35 PM PDT 24
Peak memory 208524 kb
Host smart-500ea74a-bba5-4d51-b9ac-98a7403c89ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905525291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.905525291
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2760713763
Short name T252
Test name
Test status
Simulation time 110110985 ps
CPU time 3.76 seconds
Started Aug 19 05:41:30 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 209188 kb
Host smart-b27dc36d-19ef-473e-af01-cb5450f8ebbf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760713763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2760713763
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.360618760
Short name T802
Test name
Test status
Simulation time 53511112 ps
CPU time 2.78 seconds
Started Aug 19 05:41:29 PM PDT 24
Finished Aug 19 05:41:32 PM PDT 24
Peak memory 208536 kb
Host smart-76f6b1a3-40bb-4614-973b-ea399dbbf200
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360618760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.360618760
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2323825414
Short name T532
Test name
Test status
Simulation time 179549633 ps
CPU time 2.85 seconds
Started Aug 19 05:41:33 PM PDT 24
Finished Aug 19 05:41:35 PM PDT 24
Peak memory 215980 kb
Host smart-b5778a17-2864-4b03-ade4-0c9707983264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323825414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2323825414
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.4096974500
Short name T456
Test name
Test status
Simulation time 122242538 ps
CPU time 3.53 seconds
Started Aug 19 05:41:31 PM PDT 24
Finished Aug 19 05:41:35 PM PDT 24
Peak memory 209088 kb
Host smart-64c6c4f2-9f25-45e4-919d-4bf7177df723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096974500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.4096974500
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3689524964
Short name T131
Test name
Test status
Simulation time 3306069588 ps
CPU time 26.93 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:59 PM PDT 24
Peak memory 223008 kb
Host smart-11a24f3a-255b-42e5-a748-b52dfe56e235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689524964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3689524964
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1721855368
Short name T876
Test name
Test status
Simulation time 131248699 ps
CPU time 6.26 seconds
Started Aug 19 05:41:29 PM PDT 24
Finished Aug 19 05:41:36 PM PDT 24
Peak memory 223200 kb
Host smart-81de1d97-c01e-4a99-b054-58608f8ed309
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721855368 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1721855368
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1540301996
Short name T289
Test name
Test status
Simulation time 806868759 ps
CPU time 8.85 seconds
Started Aug 19 05:41:30 PM PDT 24
Finished Aug 19 05:41:39 PM PDT 24
Peak memory 209284 kb
Host smart-56ca58f3-7cfe-49ae-bdbe-85eae3523e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540301996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1540301996
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3953750646
Short name T462
Test name
Test status
Simulation time 305330965 ps
CPU time 2.26 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 210492 kb
Host smart-8cd5abcf-2ff8-4824-bb2d-b8c56b516db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953750646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3953750646
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.954483751
Short name T709
Test name
Test status
Simulation time 12009395 ps
CPU time 0.82 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:39:54 PM PDT 24
Peak memory 206396 kb
Host smart-932714d7-3e39-4270-9839-8bf29704fa97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954483751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.954483751
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1190319995
Short name T411
Test name
Test status
Simulation time 263296771 ps
CPU time 7.8 seconds
Started Aug 19 05:39:52 PM PDT 24
Finished Aug 19 05:40:00 PM PDT 24
Peak memory 222824 kb
Host smart-f69e0615-397d-4e59-930e-fbad7127bbdc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1190319995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1190319995
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1062786090
Short name T823
Test name
Test status
Simulation time 3578040624 ps
CPU time 33.75 seconds
Started Aug 19 05:39:57 PM PDT 24
Finished Aug 19 05:40:31 PM PDT 24
Peak memory 209916 kb
Host smart-cdbb4cda-b644-4e99-9376-8747d0feca8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062786090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1062786090
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1995943424
Short name T566
Test name
Test status
Simulation time 87598853 ps
CPU time 3.73 seconds
Started Aug 19 05:39:51 PM PDT 24
Finished Aug 19 05:39:55 PM PDT 24
Peak memory 209260 kb
Host smart-2a535cdf-912b-41d1-ba4e-f1018d74581e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995943424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1995943424
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.4239719158
Short name T257
Test name
Test status
Simulation time 309962262 ps
CPU time 3.16 seconds
Started Aug 19 05:39:51 PM PDT 24
Finished Aug 19 05:39:54 PM PDT 24
Peak memory 214760 kb
Host smart-ec5d71bd-6f43-4e91-8e26-fb029c36ae31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239719158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.4239719158
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3316559319
Short name T586
Test name
Test status
Simulation time 113879029 ps
CPU time 3.57 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:39:57 PM PDT 24
Peak memory 214816 kb
Host smart-347aa9ae-a911-4dd2-872d-d36995e962a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316559319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3316559319
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3812610135
Short name T877
Test name
Test status
Simulation time 269444146 ps
CPU time 7.93 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:40:01 PM PDT 24
Peak memory 214792 kb
Host smart-dbc2febb-9ef2-4dc2-b7fa-7c8810e84fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812610135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3812610135
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2765239167
Short name T37
Test name
Test status
Simulation time 486925639 ps
CPU time 10.27 seconds
Started Aug 19 05:39:51 PM PDT 24
Finished Aug 19 05:40:01 PM PDT 24
Peak memory 231860 kb
Host smart-8a9fa006-d784-42d5-801a-379d7b50f4c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765239167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2765239167
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.317291637
Short name T450
Test name
Test status
Simulation time 126061012 ps
CPU time 3.66 seconds
Started Aug 19 05:39:52 PM PDT 24
Finished Aug 19 05:39:56 PM PDT 24
Peak memory 208652 kb
Host smart-70462b13-044a-438d-a1a5-b4a77f9e8eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317291637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.317291637
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2705618423
Short name T812
Test name
Test status
Simulation time 121644712 ps
CPU time 2.27 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:39:56 PM PDT 24
Peak memory 207328 kb
Host smart-65d85909-d53d-4aef-889b-b327ce64f542
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705618423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2705618423
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2132532738
Short name T522
Test name
Test status
Simulation time 932549181 ps
CPU time 5.12 seconds
Started Aug 19 05:39:57 PM PDT 24
Finished Aug 19 05:40:02 PM PDT 24
Peak memory 209296 kb
Host smart-94d87d37-bb85-40fa-9200-e1631b565e21
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132532738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2132532738
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.884975419
Short name T751
Test name
Test status
Simulation time 696473178 ps
CPU time 6.86 seconds
Started Aug 19 05:39:54 PM PDT 24
Finished Aug 19 05:40:01 PM PDT 24
Peak memory 208724 kb
Host smart-55823732-0804-4c82-b098-62d4d32c08ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884975419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.884975419
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1238625681
Short name T503
Test name
Test status
Simulation time 110598498 ps
CPU time 2.63 seconds
Started Aug 19 05:39:51 PM PDT 24
Finished Aug 19 05:39:53 PM PDT 24
Peak memory 209604 kb
Host smart-510cb1fa-b141-4f78-80a3-c5dee17a326d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238625681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1238625681
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.1968460390
Short name T475
Test name
Test status
Simulation time 66279161 ps
CPU time 2.81 seconds
Started Aug 19 05:39:55 PM PDT 24
Finished Aug 19 05:39:57 PM PDT 24
Peak memory 207264 kb
Host smart-29f307e3-3484-46fa-bf2d-4567791feff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968460390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1968460390
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1844698602
Short name T271
Test name
Test status
Simulation time 1164552671 ps
CPU time 39.3 seconds
Started Aug 19 05:39:51 PM PDT 24
Finished Aug 19 05:40:30 PM PDT 24
Peak memory 216416 kb
Host smart-fe6a09b9-c917-486f-afcc-246ca2a151cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844698602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1844698602
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2146657109
Short name T253
Test name
Test status
Simulation time 569541177 ps
CPU time 5.67 seconds
Started Aug 19 05:39:55 PM PDT 24
Finished Aug 19 05:40:01 PM PDT 24
Peak memory 214828 kb
Host smart-f872f6b3-2643-4323-9b1d-7b2113327aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146657109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2146657109
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2038007169
Short name T383
Test name
Test status
Simulation time 287767750 ps
CPU time 4.76 seconds
Started Aug 19 05:39:56 PM PDT 24
Finished Aug 19 05:40:01 PM PDT 24
Peak memory 211388 kb
Host smart-80dab36f-1462-457b-a628-05255c9acf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038007169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2038007169
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.4046872804
Short name T729
Test name
Test status
Simulation time 7749392 ps
CPU time 0.76 seconds
Started Aug 19 05:41:30 PM PDT 24
Finished Aug 19 05:41:31 PM PDT 24
Peak memory 206420 kb
Host smart-8c756f80-aaa8-469c-a869-e84db74ea98e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046872804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.4046872804
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1687885152
Short name T310
Test name
Test status
Simulation time 114244553 ps
CPU time 5.4 seconds
Started Aug 19 05:41:30 PM PDT 24
Finished Aug 19 05:41:36 PM PDT 24
Peak memory 214860 kb
Host smart-cffa7c56-6de9-4baa-97d0-76c2efd24dba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1687885152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1687885152
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4159952885
Short name T842
Test name
Test status
Simulation time 98906817 ps
CPU time 2.26 seconds
Started Aug 19 05:41:34 PM PDT 24
Finished Aug 19 05:41:36 PM PDT 24
Peak memory 223188 kb
Host smart-7e3a12b6-a6cf-49ac-8c1d-b57c11655fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159952885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4159952885
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2970272567
Short name T666
Test name
Test status
Simulation time 108529490 ps
CPU time 1.83 seconds
Started Aug 19 05:41:34 PM PDT 24
Finished Aug 19 05:41:36 PM PDT 24
Peak memory 207440 kb
Host smart-2b2d2b6e-c85a-4a9c-af59-eb3af1d5d4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970272567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2970272567
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3353604230
Short name T796
Test name
Test status
Simulation time 247422738 ps
CPU time 6.98 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:39 PM PDT 24
Peak memory 214736 kb
Host smart-1279591c-17d0-43e1-9bd3-149d2c91d598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353604230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3353604230
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3221038662
Short name T712
Test name
Test status
Simulation time 962766266 ps
CPU time 3.23 seconds
Started Aug 19 05:41:34 PM PDT 24
Finished Aug 19 05:41:37 PM PDT 24
Peak memory 214772 kb
Host smart-bb8b69ce-7def-4af5-be20-62a7cb732aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221038662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3221038662
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.653891546
Short name T204
Test name
Test status
Simulation time 338188323 ps
CPU time 3.78 seconds
Started Aug 19 05:41:30 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 209236 kb
Host smart-d01e1176-6168-4239-8525-418e05bfe71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653891546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.653891546
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3755976069
Short name T184
Test name
Test status
Simulation time 91938868 ps
CPU time 4.55 seconds
Started Aug 19 05:41:30 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 207592 kb
Host smart-c06ff566-d4ed-41ac-930a-56a19dd84fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3755976069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3755976069
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.198752449
Short name T757
Test name
Test status
Simulation time 120839073 ps
CPU time 3.71 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:36 PM PDT 24
Peak memory 207260 kb
Host smart-191e235a-50d8-44c7-baec-7af44d7323cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198752449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.198752449
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1330317672
Short name T847
Test name
Test status
Simulation time 44692685 ps
CPU time 2.66 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 209068 kb
Host smart-355ecd49-e220-42db-b730-634ea46aa137
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330317672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1330317672
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1359707681
Short name T903
Test name
Test status
Simulation time 228213107 ps
CPU time 2.84 seconds
Started Aug 19 05:41:33 PM PDT 24
Finished Aug 19 05:41:36 PM PDT 24
Peak memory 207812 kb
Host smart-cba5210d-8e72-455c-a1ff-683168d54b4c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359707681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1359707681
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2638573806
Short name T301
Test name
Test status
Simulation time 129303122 ps
CPU time 3.13 seconds
Started Aug 19 05:41:32 PM PDT 24
Finished Aug 19 05:41:35 PM PDT 24
Peak memory 209436 kb
Host smart-ccc9abab-56f0-417a-9063-b63ed27f7740
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638573806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2638573806
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.480416137
Short name T863
Test name
Test status
Simulation time 239010361 ps
CPU time 4.09 seconds
Started Aug 19 05:41:30 PM PDT 24
Finished Aug 19 05:41:34 PM PDT 24
Peak memory 218812 kb
Host smart-f6aa191a-1707-4d14-a85f-d6ffbb590297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480416137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.480416137
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.435854857
Short name T442
Test name
Test status
Simulation time 120737276 ps
CPU time 2.75 seconds
Started Aug 19 05:41:31 PM PDT 24
Finished Aug 19 05:41:35 PM PDT 24
Peak memory 207336 kb
Host smart-681bb98f-3e80-4025-9494-383d57257a58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435854857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.435854857
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.421162979
Short name T306
Test name
Test status
Simulation time 175100289 ps
CPU time 6.52 seconds
Started Aug 19 05:41:35 PM PDT 24
Finished Aug 19 05:41:42 PM PDT 24
Peak memory 216952 kb
Host smart-ce706b77-016e-4ff0-b3c6-f8af7d83d8c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421162979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.421162979
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1348178048
Short name T515
Test name
Test status
Simulation time 3717544255 ps
CPU time 23.81 seconds
Started Aug 19 05:41:35 PM PDT 24
Finished Aug 19 05:41:59 PM PDT 24
Peak memory 223168 kb
Host smart-bc410169-6490-4e18-bdf6-2a409d64cdc6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348178048 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1348178048
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3624706848
Short name T328
Test name
Test status
Simulation time 151827420 ps
CPU time 2.72 seconds
Started Aug 19 05:41:29 PM PDT 24
Finished Aug 19 05:41:32 PM PDT 24
Peak memory 210348 kb
Host smart-ecbbca37-a702-4bbe-8031-87732df1b8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624706848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3624706848
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1620805806
Short name T32
Test name
Test status
Simulation time 850645783 ps
CPU time 5.42 seconds
Started Aug 19 05:41:33 PM PDT 24
Finished Aug 19 05:41:39 PM PDT 24
Peak memory 211404 kb
Host smart-9bba4ac8-9796-4320-b603-ebee7926585e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620805806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1620805806
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.372655117
Short name T777
Test name
Test status
Simulation time 23071670 ps
CPU time 0.72 seconds
Started Aug 19 05:41:39 PM PDT 24
Finished Aug 19 05:41:39 PM PDT 24
Peak memory 206412 kb
Host smart-cd8b7ab2-1d6a-4949-9279-7f1bf7742d12
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372655117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.372655117
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3741779009
Short name T82
Test name
Test status
Simulation time 52147279 ps
CPU time 3.93 seconds
Started Aug 19 05:41:40 PM PDT 24
Finished Aug 19 05:41:44 PM PDT 24
Peak memory 215568 kb
Host smart-96f05780-ed58-4578-9abe-e2bf480b1867
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3741779009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3741779009
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2484706361
Short name T29
Test name
Test status
Simulation time 2149353257 ps
CPU time 4.52 seconds
Started Aug 19 05:41:39 PM PDT 24
Finished Aug 19 05:41:44 PM PDT 24
Peak memory 220876 kb
Host smart-37d10b8e-be5c-46a0-8bff-dc55a430965f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484706361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2484706361
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3127511462
Short name T294
Test name
Test status
Simulation time 537271785 ps
CPU time 3.95 seconds
Started Aug 19 05:41:49 PM PDT 24
Finished Aug 19 05:41:53 PM PDT 24
Peak memory 220396 kb
Host smart-dfa37308-21c0-4582-9848-25a3b72a22a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127511462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3127511462
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.1766321617
Short name T247
Test name
Test status
Simulation time 118611752 ps
CPU time 5.4 seconds
Started Aug 19 05:41:40 PM PDT 24
Finished Aug 19 05:41:45 PM PDT 24
Peak memory 214836 kb
Host smart-ce7a5018-b470-4ca1-808a-b265e9c61488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766321617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.1766321617
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2695069092
Short name T336
Test name
Test status
Simulation time 217621050 ps
CPU time 3.08 seconds
Started Aug 19 05:41:37 PM PDT 24
Finished Aug 19 05:41:40 PM PDT 24
Peak memory 214724 kb
Host smart-3e24d72e-22b9-4957-93c5-17ee2bf24bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695069092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2695069092
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.3392672346
Short name T86
Test name
Test status
Simulation time 939509451 ps
CPU time 4.29 seconds
Started Aug 19 05:41:50 PM PDT 24
Finished Aug 19 05:41:54 PM PDT 24
Peak memory 222980 kb
Host smart-06cca174-1f22-4775-9f53-9096fd1f37fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392672346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.3392672346
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1070010016
Short name T617
Test name
Test status
Simulation time 160067554 ps
CPU time 6.77 seconds
Started Aug 19 05:41:47 PM PDT 24
Finished Aug 19 05:41:54 PM PDT 24
Peak memory 214784 kb
Host smart-b29cb1e7-0b79-4922-b6f9-e6b78011a68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070010016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1070010016
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1286848128
Short name T507
Test name
Test status
Simulation time 278275608 ps
CPU time 3.35 seconds
Started Aug 19 05:41:42 PM PDT 24
Finished Aug 19 05:41:45 PM PDT 24
Peak memory 207364 kb
Host smart-30078a89-b05e-4a77-b380-9e66e4444671
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286848128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1286848128
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.4207562541
Short name T874
Test name
Test status
Simulation time 153953243 ps
CPU time 2.4 seconds
Started Aug 19 05:41:43 PM PDT 24
Finished Aug 19 05:41:45 PM PDT 24
Peak memory 207308 kb
Host smart-ddda0bc7-efa0-4ea0-98c6-2ca6b40c62e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207562541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.4207562541
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3851109782
Short name T759
Test name
Test status
Simulation time 6072745288 ps
CPU time 64.03 seconds
Started Aug 19 05:41:38 PM PDT 24
Finished Aug 19 05:42:42 PM PDT 24
Peak memory 208636 kb
Host smart-801f6a43-18e2-4b7c-9b04-5727a24b7b40
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851109782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3851109782
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2013588757
Short name T864
Test name
Test status
Simulation time 161838818 ps
CPU time 4.52 seconds
Started Aug 19 05:41:49 PM PDT 24
Finished Aug 19 05:41:54 PM PDT 24
Peak memory 208428 kb
Host smart-0512a74d-f89c-457b-9498-f77f661b026a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013588757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2013588757
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1511163195
Short name T805
Test name
Test status
Simulation time 69002925 ps
CPU time 3.3 seconds
Started Aug 19 05:41:45 PM PDT 24
Finished Aug 19 05:41:49 PM PDT 24
Peak memory 210420 kb
Host smart-13a16057-b31d-4de3-91d2-4eb6c97708cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511163195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1511163195
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.4123755060
Short name T769
Test name
Test status
Simulation time 109074988 ps
CPU time 2.63 seconds
Started Aug 19 05:41:37 PM PDT 24
Finished Aug 19 05:41:40 PM PDT 24
Peak memory 208584 kb
Host smart-5ad1008d-d7bc-43bd-a2d8-507e9319c1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123755060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.4123755060
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.978400967
Short name T181
Test name
Test status
Simulation time 774837895 ps
CPU time 24.1 seconds
Started Aug 19 05:41:37 PM PDT 24
Finished Aug 19 05:42:01 PM PDT 24
Peak memory 217280 kb
Host smart-2777536e-0dc3-4e71-906a-83ac159b8b4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978400967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.978400967
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1779722958
Short name T758
Test name
Test status
Simulation time 74932793 ps
CPU time 5.41 seconds
Started Aug 19 05:41:38 PM PDT 24
Finished Aug 19 05:41:44 PM PDT 24
Peak memory 220356 kb
Host smart-332ce1c4-afa7-43db-a6fa-9850542bb82c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779722958 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1779722958
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2723072609
Short name T491
Test name
Test status
Simulation time 300264261 ps
CPU time 5.37 seconds
Started Aug 19 05:41:37 PM PDT 24
Finished Aug 19 05:41:42 PM PDT 24
Peak memory 218784 kb
Host smart-8db54224-d23c-40b0-81b0-75b5b4328618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723072609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2723072609
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2858605808
Short name T182
Test name
Test status
Simulation time 50001823 ps
CPU time 2.05 seconds
Started Aug 19 05:41:49 PM PDT 24
Finished Aug 19 05:41:52 PM PDT 24
Peak memory 210456 kb
Host smart-8aade926-eb85-4752-86de-f4df6261d87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858605808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2858605808
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.669816038
Short name T55
Test name
Test status
Simulation time 16713529 ps
CPU time 0.71 seconds
Started Aug 19 05:41:48 PM PDT 24
Finished Aug 19 05:41:49 PM PDT 24
Peak memory 206416 kb
Host smart-adc1286d-a20b-4689-822a-22baf01bd6d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669816038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.669816038
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.421667922
Short name T216
Test name
Test status
Simulation time 449626058 ps
CPU time 6.07 seconds
Started Aug 19 05:41:46 PM PDT 24
Finished Aug 19 05:41:52 PM PDT 24
Peak memory 214776 kb
Host smart-e18bfc1d-c250-49d3-87d8-ba7285d552ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=421667922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.421667922
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3217432730
Short name T23
Test name
Test status
Simulation time 82829343 ps
CPU time 3.55 seconds
Started Aug 19 05:41:49 PM PDT 24
Finished Aug 19 05:41:53 PM PDT 24
Peak memory 222904 kb
Host smart-b97f6e14-1b12-4d58-a50d-982613dcf483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217432730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3217432730
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3682823766
Short name T234
Test name
Test status
Simulation time 172741223 ps
CPU time 4.62 seconds
Started Aug 19 05:41:50 PM PDT 24
Finished Aug 19 05:41:55 PM PDT 24
Peak memory 214832 kb
Host smart-450fc454-883e-48f4-8727-77de6c102481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682823766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3682823766
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.2760680649
Short name T538
Test name
Test status
Simulation time 523231306 ps
CPU time 5.35 seconds
Started Aug 19 05:41:50 PM PDT 24
Finished Aug 19 05:41:55 PM PDT 24
Peak memory 222960 kb
Host smart-a9c2dd7d-df0d-4c6c-9dc3-5f26fdfe6957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760680649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.2760680649
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.855702954
Short name T43
Test name
Test status
Simulation time 150043174 ps
CPU time 3.22 seconds
Started Aug 19 05:41:48 PM PDT 24
Finished Aug 19 05:41:51 PM PDT 24
Peak memory 222856 kb
Host smart-afcc5986-d094-445c-b340-c0c72eba24a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855702954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.855702954
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.2944677386
Short name T909
Test name
Test status
Simulation time 261474959 ps
CPU time 3.48 seconds
Started Aug 19 05:41:39 PM PDT 24
Finished Aug 19 05:41:42 PM PDT 24
Peak memory 214816 kb
Host smart-1cfb1908-8ba1-4e45-9db3-897fb2440a4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944677386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.2944677386
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1519747822
Short name T267
Test name
Test status
Simulation time 978836438 ps
CPU time 10.51 seconds
Started Aug 19 05:41:39 PM PDT 24
Finished Aug 19 05:41:50 PM PDT 24
Peak memory 209936 kb
Host smart-e84e6cd2-65e5-4ced-8be4-6ad46c17771f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519747822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1519747822
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3888370037
Short name T737
Test name
Test status
Simulation time 759964585 ps
CPU time 23.95 seconds
Started Aug 19 05:41:41 PM PDT 24
Finished Aug 19 05:42:06 PM PDT 24
Peak memory 209320 kb
Host smart-88b55761-a235-4f20-9ea5-14b530693990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888370037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3888370037
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2434108564
Short name T826
Test name
Test status
Simulation time 77714337 ps
CPU time 2.75 seconds
Started Aug 19 05:41:39 PM PDT 24
Finished Aug 19 05:41:42 PM PDT 24
Peak memory 207512 kb
Host smart-5c6a1391-b77c-4b62-9405-dae591385a2b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434108564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2434108564
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1627357220
Short name T443
Test name
Test status
Simulation time 314494866 ps
CPU time 3.69 seconds
Started Aug 19 05:41:38 PM PDT 24
Finished Aug 19 05:41:42 PM PDT 24
Peak memory 208076 kb
Host smart-3ce8a676-a32a-44d3-9863-481cff89e408
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627357220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1627357220
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1452932946
Short name T619
Test name
Test status
Simulation time 673591408 ps
CPU time 5.16 seconds
Started Aug 19 05:41:42 PM PDT 24
Finished Aug 19 05:41:47 PM PDT 24
Peak memory 208632 kb
Host smart-8fd0f9cd-500a-4d16-b272-be26553bde5d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452932946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1452932946
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1595803741
Short name T767
Test name
Test status
Simulation time 87268713 ps
CPU time 2.58 seconds
Started Aug 19 05:41:49 PM PDT 24
Finished Aug 19 05:41:52 PM PDT 24
Peak memory 210380 kb
Host smart-3ce8c6f6-ace8-4ac6-937b-589eea8948a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595803741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1595803741
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.4257362448
Short name T893
Test name
Test status
Simulation time 2242492834 ps
CPU time 32.16 seconds
Started Aug 19 05:41:37 PM PDT 24
Finished Aug 19 05:42:10 PM PDT 24
Peak memory 209376 kb
Host smart-3d5e3f82-5fe7-4027-88bf-fce284d2a800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257362448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.4257362448
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3553134278
Short name T772
Test name
Test status
Simulation time 2113731219 ps
CPU time 29.85 seconds
Started Aug 19 05:41:39 PM PDT 24
Finished Aug 19 05:42:09 PM PDT 24
Peak memory 223024 kb
Host smart-2d62c36f-687e-4aed-9a18-78cd39499a74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553134278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3553134278
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1001610817
Short name T76
Test name
Test status
Simulation time 1149189873 ps
CPU time 14.1 seconds
Started Aug 19 05:41:48 PM PDT 24
Finished Aug 19 05:42:02 PM PDT 24
Peak memory 223048 kb
Host smart-c376e0df-97b1-4227-95d8-4ae4a04d38f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001610817 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1001610817
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3002853426
Short name T288
Test name
Test status
Simulation time 738223850 ps
CPU time 6.26 seconds
Started Aug 19 05:41:51 PM PDT 24
Finished Aug 19 05:41:57 PM PDT 24
Peak memory 209948 kb
Host smart-2fc71acf-3ebe-4e5b-8535-0f694217549a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002853426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3002853426
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3253764931
Short name T496
Test name
Test status
Simulation time 127218368 ps
CPU time 1.8 seconds
Started Aug 19 05:41:37 PM PDT 24
Finished Aug 19 05:41:39 PM PDT 24
Peak memory 210584 kb
Host smart-f3ef8af2-b0cc-4765-98fa-0ca4ed8cbcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253764931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3253764931
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.285602917
Short name T786
Test name
Test status
Simulation time 41116270 ps
CPU time 0.87 seconds
Started Aug 19 05:41:42 PM PDT 24
Finished Aug 19 05:41:43 PM PDT 24
Peak memory 206440 kb
Host smart-477fa551-ff00-4e64-a30d-97150de62b7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285602917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.285602917
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.587851361
Short name T406
Test name
Test status
Simulation time 80311137 ps
CPU time 3.36 seconds
Started Aug 19 05:41:37 PM PDT 24
Finished Aug 19 05:41:41 PM PDT 24
Peak memory 216060 kb
Host smart-0d8cb142-0a79-47e9-b3cf-85538c280555
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=587851361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.587851361
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3623068632
Short name T126
Test name
Test status
Simulation time 361996247 ps
CPU time 4.56 seconds
Started Aug 19 05:41:51 PM PDT 24
Finished Aug 19 05:41:56 PM PDT 24
Peak memory 220108 kb
Host smart-8509577b-bd2a-43b4-a4d4-33a46bf83b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623068632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3623068632
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1818716442
Short name T172
Test name
Test status
Simulation time 280421586 ps
CPU time 2.26 seconds
Started Aug 19 05:41:48 PM PDT 24
Finished Aug 19 05:41:50 PM PDT 24
Peak memory 215500 kb
Host smart-ce0c7d49-ad52-4357-b259-d1c24bf66819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818716442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1818716442
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3948969145
Short name T471
Test name
Test status
Simulation time 158879299 ps
CPU time 6.03 seconds
Started Aug 19 05:41:46 PM PDT 24
Finished Aug 19 05:41:52 PM PDT 24
Peak memory 222848 kb
Host smart-a7e40e2d-7459-43d6-af51-2159647d196a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3948969145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3948969145
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3721562921
Short name T212
Test name
Test status
Simulation time 191298896 ps
CPU time 3.82 seconds
Started Aug 19 05:41:38 PM PDT 24
Finished Aug 19 05:41:43 PM PDT 24
Peak memory 210860 kb
Host smart-177adc4d-905d-47fc-a7b2-05a494267ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721562921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3721562921
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1238943208
Short name T680
Test name
Test status
Simulation time 66136187 ps
CPU time 2.82 seconds
Started Aug 19 05:41:38 PM PDT 24
Finished Aug 19 05:41:41 PM PDT 24
Peak memory 214876 kb
Host smart-139fb74f-8366-4aff-b73f-b5448ce45de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238943208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1238943208
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2570915203
Short name T665
Test name
Test status
Simulation time 504687231 ps
CPU time 5.7 seconds
Started Aug 19 05:41:37 PM PDT 24
Finished Aug 19 05:41:43 PM PDT 24
Peak memory 208652 kb
Host smart-9e652355-9f87-4b0d-9c89-fd430abf8808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570915203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2570915203
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.45283747
Short name T494
Test name
Test status
Simulation time 771021933 ps
CPU time 8.66 seconds
Started Aug 19 05:41:49 PM PDT 24
Finished Aug 19 05:41:58 PM PDT 24
Peak memory 209264 kb
Host smart-d7800e65-16e5-46e6-aaa3-bc69912fec08
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45283747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.45283747
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.776452159
Short name T761
Test name
Test status
Simulation time 1337499259 ps
CPU time 43.51 seconds
Started Aug 19 05:41:37 PM PDT 24
Finished Aug 19 05:42:21 PM PDT 24
Peak memory 209272 kb
Host smart-08066665-15e5-4387-bbc4-b6014827537f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776452159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.776452159
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2238646515
Short name T514
Test name
Test status
Simulation time 21315396 ps
CPU time 1.81 seconds
Started Aug 19 05:41:38 PM PDT 24
Finished Aug 19 05:41:40 PM PDT 24
Peak memory 207404 kb
Host smart-f515ec86-8e1c-4567-afb8-2e7de7b9d825
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238646515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2238646515
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.97397790
Short name T700
Test name
Test status
Simulation time 435599841 ps
CPU time 3.93 seconds
Started Aug 19 05:41:50 PM PDT 24
Finished Aug 19 05:41:54 PM PDT 24
Peak memory 214832 kb
Host smart-5a9287cc-86c6-468e-9a88-bf128a314c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97397790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.97397790
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.4273568749
Short name T750
Test name
Test status
Simulation time 2586988830 ps
CPU time 4.97 seconds
Started Aug 19 05:41:49 PM PDT 24
Finished Aug 19 05:41:54 PM PDT 24
Peak memory 209052 kb
Host smart-a8131479-ddca-488a-894b-73237e108cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273568749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.4273568749
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2888173603
Short name T911
Test name
Test status
Simulation time 206306107 ps
CPU time 12.18 seconds
Started Aug 19 05:41:50 PM PDT 24
Finished Aug 19 05:42:03 PM PDT 24
Peak memory 222968 kb
Host smart-32996744-7c20-420e-9256-5c5107bd9a1d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888173603 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2888173603
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.1653088763
Short name T756
Test name
Test status
Simulation time 68855195 ps
CPU time 3.64 seconds
Started Aug 19 05:41:40 PM PDT 24
Finished Aug 19 05:41:44 PM PDT 24
Peak memory 214784 kb
Host smart-2df636db-e150-427c-943d-7603dc661a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653088763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.1653088763
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2569709520
Short name T385
Test name
Test status
Simulation time 78086677 ps
CPU time 2.68 seconds
Started Aug 19 05:41:41 PM PDT 24
Finished Aug 19 05:41:44 PM PDT 24
Peak memory 210976 kb
Host smart-6610c931-3337-4cd6-9037-ec40f690c4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569709520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2569709520
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1729790771
Short name T705
Test name
Test status
Simulation time 15925166 ps
CPU time 0.78 seconds
Started Aug 19 05:41:50 PM PDT 24
Finished Aug 19 05:41:51 PM PDT 24
Peak memory 206432 kb
Host smart-2efa2a25-49e5-4e66-8e8e-9dc6f66be974
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729790771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1729790771
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1749858611
Short name T670
Test name
Test status
Simulation time 214993418 ps
CPU time 2.74 seconds
Started Aug 19 05:41:48 PM PDT 24
Finished Aug 19 05:41:51 PM PDT 24
Peak memory 207728 kb
Host smart-efa3d5ce-54f3-4f7b-a38e-abbd9f36ccae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749858611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1749858611
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3287431165
Short name T648
Test name
Test status
Simulation time 449289960 ps
CPU time 2.21 seconds
Started Aug 19 05:41:53 PM PDT 24
Finished Aug 19 05:41:55 PM PDT 24
Peak memory 214748 kb
Host smart-47d64521-2e02-4d3a-8e4f-9ba39d170375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287431165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3287431165
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1590467636
Short name T363
Test name
Test status
Simulation time 37238701 ps
CPU time 2.09 seconds
Started Aug 19 05:41:52 PM PDT 24
Finished Aug 19 05:41:55 PM PDT 24
Peak memory 214740 kb
Host smart-bd22ff9e-e538-41f8-bef6-f68ff0724900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590467636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1590467636
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.4256455612
Short name T530
Test name
Test status
Simulation time 56778284 ps
CPU time 2.98 seconds
Started Aug 19 05:41:44 PM PDT 24
Finished Aug 19 05:41:47 PM PDT 24
Peak memory 214772 kb
Host smart-2381b7eb-570e-487a-a96a-2ab35ece83ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256455612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.4256455612
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1687131820
Short name T628
Test name
Test status
Simulation time 258549511 ps
CPU time 3.01 seconds
Started Aug 19 05:41:40 PM PDT 24
Finished Aug 19 05:41:44 PM PDT 24
Peak memory 207996 kb
Host smart-f0993e10-aa67-40cf-b1ed-2f395d332b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687131820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1687131820
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2642970020
Short name T740
Test name
Test status
Simulation time 251258105 ps
CPU time 3.97 seconds
Started Aug 19 05:41:41 PM PDT 24
Finished Aug 19 05:41:45 PM PDT 24
Peak memory 208960 kb
Host smart-9c0a7bc8-af22-4fee-a0d4-6eda850bf668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642970020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2642970020
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.111752947
Short name T749
Test name
Test status
Simulation time 139731112 ps
CPU time 2.35 seconds
Started Aug 19 05:41:37 PM PDT 24
Finished Aug 19 05:41:39 PM PDT 24
Peak memory 207344 kb
Host smart-7c368d20-6a2b-4740-8921-03d04ba7e5d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111752947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.111752947
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1625775510
Short name T744
Test name
Test status
Simulation time 67555120 ps
CPU time 2.91 seconds
Started Aug 19 05:41:50 PM PDT 24
Finished Aug 19 05:41:53 PM PDT 24
Peak memory 207432 kb
Host smart-e1f37361-af12-4ef3-ab98-e0610f411ac2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625775510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1625775510
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2149038177
Short name T290
Test name
Test status
Simulation time 1196310808 ps
CPU time 30.37 seconds
Started Aug 19 05:41:52 PM PDT 24
Finished Aug 19 05:42:23 PM PDT 24
Peak memory 219032 kb
Host smart-879ed91e-d90f-44d2-8b0c-2d63c73587ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149038177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2149038177
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1487295472
Short name T138
Test name
Test status
Simulation time 476234564 ps
CPU time 4.24 seconds
Started Aug 19 05:41:38 PM PDT 24
Finished Aug 19 05:41:43 PM PDT 24
Peak memory 208864 kb
Host smart-9d82dc9d-1d90-439d-990a-f3673188f619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487295472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1487295472
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.74085266
Short name T121
Test name
Test status
Simulation time 627757569 ps
CPU time 16.35 seconds
Started Aug 19 05:41:48 PM PDT 24
Finished Aug 19 05:42:04 PM PDT 24
Peak memory 216652 kb
Host smart-014c8879-87e0-4eb0-943b-9a5e3865c276
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74085266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.74085266
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2459321518
Short name T697
Test name
Test status
Simulation time 173957781 ps
CPU time 4.57 seconds
Started Aug 19 05:41:44 PM PDT 24
Finished Aug 19 05:41:48 PM PDT 24
Peak memory 214768 kb
Host smart-ad503c27-8074-4038-9142-69604b67ce71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459321518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2459321518
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.482479417
Short name T433
Test name
Test status
Simulation time 9090968 ps
CPU time 0.76 seconds
Started Aug 19 05:41:55 PM PDT 24
Finished Aug 19 05:41:56 PM PDT 24
Peak memory 206424 kb
Host smart-eff465ab-dc32-4ade-8e59-bdfe254c05ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482479417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.482479417
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1846041657
Short name T424
Test name
Test status
Simulation time 199017395 ps
CPU time 3.86 seconds
Started Aug 19 05:41:51 PM PDT 24
Finished Aug 19 05:41:55 PM PDT 24
Peak memory 214804 kb
Host smart-3b66c3dd-e2fa-4b50-bb74-b4ad7a053611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1846041657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1846041657
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.4044460904
Short name T13
Test name
Test status
Simulation time 1734725323 ps
CPU time 4.11 seconds
Started Aug 19 05:41:52 PM PDT 24
Finished Aug 19 05:41:56 PM PDT 24
Peak memory 215088 kb
Host smart-58d13726-c983-480a-a686-fdda485d16b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044460904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.4044460904
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.169714287
Short name T282
Test name
Test status
Simulation time 96899736 ps
CPU time 3.8 seconds
Started Aug 19 05:41:52 PM PDT 24
Finished Aug 19 05:41:56 PM PDT 24
Peak memory 214788 kb
Host smart-254fcc8e-4a28-4826-9f03-00ec7ba7dd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169714287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.169714287
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1721741177
Short name T644
Test name
Test status
Simulation time 348695211 ps
CPU time 7.27 seconds
Started Aug 19 05:41:55 PM PDT 24
Finished Aug 19 05:42:02 PM PDT 24
Peak memory 222888 kb
Host smart-9d98413f-bc4b-4909-8f50-48e3d63243d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721741177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1721741177
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1045770120
Short name T519
Test name
Test status
Simulation time 469508488 ps
CPU time 2.72 seconds
Started Aug 19 05:41:56 PM PDT 24
Finished Aug 19 05:41:59 PM PDT 24
Peak memory 220444 kb
Host smart-b0896bcf-da8e-4308-87f8-1f5e5e6a882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045770120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1045770120
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3823918218
Short name T270
Test name
Test status
Simulation time 168974179 ps
CPU time 6.54 seconds
Started Aug 19 05:41:49 PM PDT 24
Finished Aug 19 05:41:56 PM PDT 24
Peak memory 209928 kb
Host smart-b7fe1d54-47da-4e10-9ee1-c27302981a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823918218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3823918218
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2339405852
Short name T623
Test name
Test status
Simulation time 143236611 ps
CPU time 3.81 seconds
Started Aug 19 05:41:50 PM PDT 24
Finished Aug 19 05:41:54 PM PDT 24
Peak memory 207268 kb
Host smart-f30d2588-9660-4025-80af-18187e10438d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339405852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2339405852
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.3647372588
Short name T782
Test name
Test status
Simulation time 66006613 ps
CPU time 3.21 seconds
Started Aug 19 05:41:47 PM PDT 24
Finished Aug 19 05:41:51 PM PDT 24
Peak memory 208540 kb
Host smart-6e6792e4-ca60-400d-b6b1-98c47647c37d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647372588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.3647372588
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2889850322
Short name T838
Test name
Test status
Simulation time 447806002 ps
CPU time 11.75 seconds
Started Aug 19 05:41:52 PM PDT 24
Finished Aug 19 05:42:03 PM PDT 24
Peak memory 208636 kb
Host smart-da9661c0-8a86-4f90-b48c-552d3fe8483b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889850322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2889850322
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1634976655
Short name T461
Test name
Test status
Simulation time 5879796799 ps
CPU time 22.05 seconds
Started Aug 19 05:41:48 PM PDT 24
Finished Aug 19 05:42:10 PM PDT 24
Peak memory 208648 kb
Host smart-d3f687ea-72b1-4ec2-b5f8-3d94e3aff930
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634976655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1634976655
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1874493557
Short name T645
Test name
Test status
Simulation time 15914882 ps
CPU time 1.44 seconds
Started Aug 19 05:41:49 PM PDT 24
Finished Aug 19 05:41:50 PM PDT 24
Peak memory 208316 kb
Host smart-9488eec0-1654-49b5-8c0a-d8a7555c5bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874493557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1874493557
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.105544333
Short name T688
Test name
Test status
Simulation time 133988755 ps
CPU time 3.09 seconds
Started Aug 19 05:41:54 PM PDT 24
Finished Aug 19 05:41:57 PM PDT 24
Peak memory 208980 kb
Host smart-ed399fc3-4b7b-4f82-86c3-82d82d2fb7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105544333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.105544333
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.691962422
Short name T890
Test name
Test status
Simulation time 1402372975 ps
CPU time 15.69 seconds
Started Aug 19 05:41:52 PM PDT 24
Finished Aug 19 05:42:08 PM PDT 24
Peak memory 217384 kb
Host smart-d1cd600e-0755-4c61-925a-4cdff6cdd120
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691962422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.691962422
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3492307249
Short name T681
Test name
Test status
Simulation time 250474778 ps
CPU time 3.28 seconds
Started Aug 19 05:41:47 PM PDT 24
Finished Aug 19 05:41:50 PM PDT 24
Peak memory 208004 kb
Host smart-922519bc-b592-47ba-85dc-8a5a85f57b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492307249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3492307249
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1879059065
Short name T389
Test name
Test status
Simulation time 43684446 ps
CPU time 2.21 seconds
Started Aug 19 05:41:54 PM PDT 24
Finished Aug 19 05:41:56 PM PDT 24
Peak memory 210364 kb
Host smart-47c7ac5e-6a43-4547-9935-6537bed10918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879059065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1879059065
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3808714833
Short name T774
Test name
Test status
Simulation time 54306729 ps
CPU time 0.91 seconds
Started Aug 19 05:41:51 PM PDT 24
Finished Aug 19 05:41:52 PM PDT 24
Peak memory 206396 kb
Host smart-8d648a15-72c1-459a-835a-9877851ad480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808714833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3808714833
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2549940122
Short name T358
Test name
Test status
Simulation time 34914145 ps
CPU time 2.56 seconds
Started Aug 19 05:41:54 PM PDT 24
Finished Aug 19 05:41:57 PM PDT 24
Peak memory 214524 kb
Host smart-2bce36d2-2e1f-48c9-8372-5889fc528edf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2549940122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2549940122
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.922652344
Short name T36
Test name
Test status
Simulation time 1506716134 ps
CPU time 4.46 seconds
Started Aug 19 05:41:47 PM PDT 24
Finished Aug 19 05:41:52 PM PDT 24
Peak memory 215140 kb
Host smart-5f8603b5-13a8-48ea-afe5-910328448ba3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922652344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.922652344
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2728689180
Short name T64
Test name
Test status
Simulation time 63045374 ps
CPU time 2.7 seconds
Started Aug 19 05:41:52 PM PDT 24
Finished Aug 19 05:41:55 PM PDT 24
Peak memory 210604 kb
Host smart-ae4e5138-bfd7-4588-8ad9-3f2416b4efff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728689180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2728689180
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1550784903
Short name T913
Test name
Test status
Simulation time 29873513 ps
CPU time 2.33 seconds
Started Aug 19 05:41:50 PM PDT 24
Finished Aug 19 05:41:53 PM PDT 24
Peak memory 214812 kb
Host smart-4191c2e4-08c7-4395-b8be-7b6df4f87c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550784903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1550784903
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1399959993
Short name T364
Test name
Test status
Simulation time 148078845 ps
CPU time 3.15 seconds
Started Aug 19 05:41:55 PM PDT 24
Finished Aug 19 05:41:59 PM PDT 24
Peak memory 214716 kb
Host smart-ae48344b-8b67-4167-9c17-807041c178a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399959993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1399959993
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1569276688
Short name T112
Test name
Test status
Simulation time 162518949 ps
CPU time 2.89 seconds
Started Aug 19 05:41:49 PM PDT 24
Finished Aug 19 05:41:52 PM PDT 24
Peak memory 214808 kb
Host smart-97e47bf1-d052-476a-a07e-186ad8382e75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569276688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1569276688
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.882605833
Short name T859
Test name
Test status
Simulation time 100086066 ps
CPU time 4.89 seconds
Started Aug 19 05:41:48 PM PDT 24
Finished Aug 19 05:41:53 PM PDT 24
Peak memory 208556 kb
Host smart-f084f0f9-8404-4d1c-8f6d-b3aabb725992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882605833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.882605833
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.4189911941
Short name T544
Test name
Test status
Simulation time 2210728894 ps
CPU time 12.82 seconds
Started Aug 19 05:41:48 PM PDT 24
Finished Aug 19 05:42:01 PM PDT 24
Peak memory 207360 kb
Host smart-6ed4b1bf-121f-496a-b6ee-535ca3ec72a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189911941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.4189911941
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2086012258
Short name T862
Test name
Test status
Simulation time 128438951 ps
CPU time 3.31 seconds
Started Aug 19 05:41:51 PM PDT 24
Finished Aug 19 05:41:55 PM PDT 24
Peak memory 209308 kb
Host smart-6adb706c-d823-4515-a1fb-64fdb609dbdb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086012258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2086012258
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2544614102
Short name T500
Test name
Test status
Simulation time 1054964386 ps
CPU time 16.89 seconds
Started Aug 19 05:41:48 PM PDT 24
Finished Aug 19 05:42:05 PM PDT 24
Peak memory 209020 kb
Host smart-3b0f60a5-7755-4b91-9a15-bc91174c65c8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544614102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2544614102
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3238645628
Short name T543
Test name
Test status
Simulation time 184213540 ps
CPU time 2.75 seconds
Started Aug 19 05:41:54 PM PDT 24
Finished Aug 19 05:41:57 PM PDT 24
Peak memory 209212 kb
Host smart-f62af811-1926-4ac6-9ac6-769fb15b20b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238645628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3238645628
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.496455973
Short name T585
Test name
Test status
Simulation time 144949782 ps
CPU time 3.4 seconds
Started Aug 19 05:41:54 PM PDT 24
Finished Aug 19 05:41:57 PM PDT 24
Peak memory 214780 kb
Host smart-735a6c11-a630-484a-8cda-2ae79034214d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496455973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.496455973
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2752343068
Short name T173
Test name
Test status
Simulation time 1271582529 ps
CPU time 5.94 seconds
Started Aug 19 05:41:52 PM PDT 24
Finished Aug 19 05:41:58 PM PDT 24
Peak memory 209044 kb
Host smart-74a7510f-310e-43e1-8ccd-32ed03f8d3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752343068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2752343068
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.3188554264
Short name T210
Test name
Test status
Simulation time 577620789 ps
CPU time 20.74 seconds
Started Aug 19 05:41:53 PM PDT 24
Finished Aug 19 05:42:14 PM PDT 24
Peak memory 217072 kb
Host smart-a993a44a-0399-40e2-b0c2-3099235db823
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188554264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.3188554264
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3505782232
Short name T78
Test name
Test status
Simulation time 234214518 ps
CPU time 10.09 seconds
Started Aug 19 05:41:53 PM PDT 24
Finished Aug 19 05:42:03 PM PDT 24
Peak memory 220288 kb
Host smart-b16baf77-92fd-4cc2-b599-9f1525e6c0f4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505782232 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3505782232
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3883915020
Short name T839
Test name
Test status
Simulation time 2250819734 ps
CPU time 15.74 seconds
Started Aug 19 05:41:51 PM PDT 24
Finished Aug 19 05:42:07 PM PDT 24
Peak memory 214820 kb
Host smart-3b063f7a-290f-4951-955c-b49d2306abc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883915020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3883915020
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2036467346
Short name T118
Test name
Test status
Simulation time 66427925 ps
CPU time 2.17 seconds
Started Aug 19 05:41:53 PM PDT 24
Finished Aug 19 05:41:55 PM PDT 24
Peak memory 210724 kb
Host smart-af89cf8b-cf84-4893-83d1-8530985a4e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036467346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2036467346
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2281584340
Short name T860
Test name
Test status
Simulation time 121248219 ps
CPU time 0.81 seconds
Started Aug 19 05:42:00 PM PDT 24
Finished Aug 19 05:42:01 PM PDT 24
Peak memory 206388 kb
Host smart-1ecfb234-de05-48da-8475-e634723f4cf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281584340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2281584340
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1557722698
Short name T422
Test name
Test status
Simulation time 527170669 ps
CPU time 30.08 seconds
Started Aug 19 05:41:52 PM PDT 24
Finished Aug 19 05:42:22 PM PDT 24
Peak memory 214940 kb
Host smart-cf9f1b27-c772-4b13-b2ab-ccea38068d71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1557722698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1557722698
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1143173008
Short name T825
Test name
Test status
Simulation time 581787997 ps
CPU time 5.38 seconds
Started Aug 19 05:42:05 PM PDT 24
Finished Aug 19 05:42:11 PM PDT 24
Peak memory 222124 kb
Host smart-e51d00a3-a14f-4ef6-8ae7-fa4ab24dd4cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143173008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1143173008
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2857548814
Short name T324
Test name
Test status
Simulation time 180059370 ps
CPU time 3.58 seconds
Started Aug 19 05:41:47 PM PDT 24
Finished Aug 19 05:41:50 PM PDT 24
Peak memory 211084 kb
Host smart-a54f0035-fa27-4840-aa25-688aa65e3ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857548814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2857548814
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.336358125
Short name T50
Test name
Test status
Simulation time 474021187 ps
CPU time 4.35 seconds
Started Aug 19 05:41:53 PM PDT 24
Finished Aug 19 05:41:58 PM PDT 24
Peak memory 210268 kb
Host smart-3fb29dd5-2af2-4328-a3e2-3b7f3b808c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336358125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.336358125
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1471404107
Short name T261
Test name
Test status
Simulation time 105360861 ps
CPU time 1.82 seconds
Started Aug 19 05:41:51 PM PDT 24
Finished Aug 19 05:41:53 PM PDT 24
Peak memory 214656 kb
Host smart-b04a9dd7-555f-4f30-b85e-fcb07e6ea2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1471404107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1471404107
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3510817554
Short name T207
Test name
Test status
Simulation time 64266670 ps
CPU time 3.01 seconds
Started Aug 19 05:41:54 PM PDT 24
Finished Aug 19 05:41:57 PM PDT 24
Peak memory 223000 kb
Host smart-884ee10d-d35e-41f0-85fa-c0705063a7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510817554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3510817554
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.4217053423
Short name T831
Test name
Test status
Simulation time 166993768 ps
CPU time 6.93 seconds
Started Aug 19 05:41:50 PM PDT 24
Finished Aug 19 05:41:57 PM PDT 24
Peak memory 210520 kb
Host smart-3039a744-f683-47ad-9cbd-63cdb5b3dc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4217053423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.4217053423
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.558733708
Short name T694
Test name
Test status
Simulation time 32341963 ps
CPU time 2.28 seconds
Started Aug 19 05:41:54 PM PDT 24
Finished Aug 19 05:41:57 PM PDT 24
Peak memory 207424 kb
Host smart-866cdeb6-84d4-4cdf-9379-2d54c0b06df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=558733708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.558733708
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3747528285
Short name T735
Test name
Test status
Simulation time 893504144 ps
CPU time 7.02 seconds
Started Aug 19 05:41:51 PM PDT 24
Finished Aug 19 05:41:58 PM PDT 24
Peak memory 208652 kb
Host smart-499e583a-5bba-4dc9-b3cc-a38b0595ba04
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747528285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3747528285
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.4144333741
Short name T371
Test name
Test status
Simulation time 187761820 ps
CPU time 2.91 seconds
Started Aug 19 05:41:47 PM PDT 24
Finished Aug 19 05:41:50 PM PDT 24
Peak memory 209008 kb
Host smart-54f2fedf-7f76-4a83-86ae-98ac92f5001b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144333741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.4144333741
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2889912345
Short name T251
Test name
Test status
Simulation time 98666061 ps
CPU time 3.04 seconds
Started Aug 19 05:41:51 PM PDT 24
Finished Aug 19 05:41:55 PM PDT 24
Peak memory 208936 kb
Host smart-8d0ce325-54d7-48ea-b798-3699b12c46f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889912345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2889912345
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.4236939690
Short name T626
Test name
Test status
Simulation time 514050842 ps
CPU time 4.1 seconds
Started Aug 19 05:41:58 PM PDT 24
Finished Aug 19 05:42:03 PM PDT 24
Peak memory 209828 kb
Host smart-f71fdfef-9d8d-4c22-84cd-4c899af44233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236939690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.4236939690
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.378455581
Short name T483
Test name
Test status
Simulation time 757142559 ps
CPU time 4.64 seconds
Started Aug 19 05:41:52 PM PDT 24
Finished Aug 19 05:41:56 PM PDT 24
Peak memory 207204 kb
Host smart-2d022ca9-a203-4764-9410-63637646ec7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378455581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.378455581
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.636091522
Short name T834
Test name
Test status
Simulation time 281862440 ps
CPU time 7.73 seconds
Started Aug 19 05:42:03 PM PDT 24
Finished Aug 19 05:42:11 PM PDT 24
Peak memory 220932 kb
Host smart-bb8d4e37-c40b-4e90-9f86-170156e89f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636091522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.636091522
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1029911041
Short name T350
Test name
Test status
Simulation time 169147018 ps
CPU time 3.44 seconds
Started Aug 19 05:41:56 PM PDT 24
Finished Aug 19 05:41:59 PM PDT 24
Peak memory 208160 kb
Host smart-68d5b4f2-80db-40e4-bbc8-f7622b2abe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029911041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1029911041
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3597583677
Short name T463
Test name
Test status
Simulation time 94732369 ps
CPU time 1.83 seconds
Started Aug 19 05:42:00 PM PDT 24
Finished Aug 19 05:42:02 PM PDT 24
Peak memory 210816 kb
Host smart-35393777-6d77-4c69-9fce-bd9560ae9781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597583677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3597583677
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1102554508
Short name T536
Test name
Test status
Simulation time 38130338 ps
CPU time 0.83 seconds
Started Aug 19 05:42:02 PM PDT 24
Finished Aug 19 05:42:03 PM PDT 24
Peak memory 206432 kb
Host smart-52b8b137-0609-4fbe-80a1-e811614221a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102554508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1102554508
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3586966658
Short name T354
Test name
Test status
Simulation time 297865099 ps
CPU time 5.05 seconds
Started Aug 19 05:42:06 PM PDT 24
Finished Aug 19 05:42:11 PM PDT 24
Peak memory 215836 kb
Host smart-071ce3fa-cdef-40df-8288-c26627d8ae0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3586966658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3586966658
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.4280795870
Short name T807
Test name
Test status
Simulation time 45908170 ps
CPU time 1.16 seconds
Started Aug 19 05:42:06 PM PDT 24
Finished Aug 19 05:42:07 PM PDT 24
Peak memory 206592 kb
Host smart-e02272b9-280c-4497-83cf-c529299751d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280795870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.4280795870
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.123761853
Short name T63
Test name
Test status
Simulation time 24104921 ps
CPU time 1.96 seconds
Started Aug 19 05:42:02 PM PDT 24
Finished Aug 19 05:42:04 PM PDT 24
Peak memory 207952 kb
Host smart-b93a957c-9739-426b-8069-7fe2c60d8563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123761853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.123761853
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2155932364
Short name T362
Test name
Test status
Simulation time 108801511 ps
CPU time 1.84 seconds
Started Aug 19 05:42:03 PM PDT 24
Finished Aug 19 05:42:05 PM PDT 24
Peak memory 214816 kb
Host smart-a3c8c742-3d76-48a6-9f0b-8ed15fc51cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155932364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2155932364
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3277145135
Short name T673
Test name
Test status
Simulation time 97078705 ps
CPU time 4.66 seconds
Started Aug 19 05:42:01 PM PDT 24
Finished Aug 19 05:42:06 PM PDT 24
Peak memory 211264 kb
Host smart-37bd095c-6361-4b1b-8fee-6b2999f2d550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277145135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3277145135
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.862306398
Short name T612
Test name
Test status
Simulation time 8943952642 ps
CPU time 79.29 seconds
Started Aug 19 05:42:01 PM PDT 24
Finished Aug 19 05:43:20 PM PDT 24
Peak memory 214832 kb
Host smart-28d4d44b-b38a-4530-976e-d6fdcffb98b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862306398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.862306398
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1142671877
Short name T840
Test name
Test status
Simulation time 117841427 ps
CPU time 3.06 seconds
Started Aug 19 05:42:03 PM PDT 24
Finished Aug 19 05:42:06 PM PDT 24
Peak memory 209312 kb
Host smart-3b2af5e5-71e5-48f4-97db-67399bc8ff95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142671877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1142671877
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.528452573
Short name T272
Test name
Test status
Simulation time 109668329 ps
CPU time 4.77 seconds
Started Aug 19 05:42:02 PM PDT 24
Finished Aug 19 05:42:07 PM PDT 24
Peak memory 207488 kb
Host smart-f06de759-e3f6-46aa-a3ff-d61f62553d9d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528452573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.528452573
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1500580712
Short name T596
Test name
Test status
Simulation time 292661986 ps
CPU time 1.8 seconds
Started Aug 19 05:42:07 PM PDT 24
Finished Aug 19 05:42:09 PM PDT 24
Peak memory 207368 kb
Host smart-5326847a-d431-4750-855f-8aa817ebc4cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500580712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1500580712
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.4178452888
Short name T910
Test name
Test status
Simulation time 257708080 ps
CPU time 3.35 seconds
Started Aug 19 05:42:01 PM PDT 24
Finished Aug 19 05:42:05 PM PDT 24
Peak memory 207328 kb
Host smart-a12a642e-bc16-4a48-89a9-fe8c87af1715
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178452888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.4178452888
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3385428634
Short name T464
Test name
Test status
Simulation time 247637007 ps
CPU time 1.78 seconds
Started Aug 19 05:42:05 PM PDT 24
Finished Aug 19 05:42:07 PM PDT 24
Peak memory 208080 kb
Host smart-6f7b1bf4-6b3f-4401-a447-b179ba321b24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385428634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3385428634
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3905016068
Short name T403
Test name
Test status
Simulation time 2841462526 ps
CPU time 16.09 seconds
Started Aug 19 05:42:03 PM PDT 24
Finished Aug 19 05:42:20 PM PDT 24
Peak memory 209540 kb
Host smart-44e6f683-a615-4a70-adf7-f9626a30abc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905016068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3905016068
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3232731069
Short name T177
Test name
Test status
Simulation time 13768022299 ps
CPU time 37.24 seconds
Started Aug 19 05:42:02 PM PDT 24
Finished Aug 19 05:42:39 PM PDT 24
Peak memory 216968 kb
Host smart-e9e722d0-837d-4c0c-8556-eeea7506b57a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232731069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3232731069
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3025579296
Short name T773
Test name
Test status
Simulation time 5517266151 ps
CPU time 37.79 seconds
Started Aug 19 05:41:59 PM PDT 24
Finished Aug 19 05:42:37 PM PDT 24
Peak memory 219200 kb
Host smart-e6ccbe23-5c31-4f17-8c71-e1a1fc3c1bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025579296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3025579296
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.459999895
Short name T114
Test name
Test status
Simulation time 320968032 ps
CPU time 3.41 seconds
Started Aug 19 05:41:59 PM PDT 24
Finished Aug 19 05:42:03 PM PDT 24
Peak memory 210632 kb
Host smart-2d28834e-899d-45f0-8f8a-7a63b4038999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459999895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.459999895
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1313060389
Short name T746
Test name
Test status
Simulation time 41768487 ps
CPU time 0.83 seconds
Started Aug 19 05:42:05 PM PDT 24
Finished Aug 19 05:42:06 PM PDT 24
Peak memory 206424 kb
Host smart-1d96bce5-50f7-4ae6-80af-33f80273d4af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313060389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1313060389
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1399332885
Short name T374
Test name
Test status
Simulation time 40746078 ps
CPU time 3.08 seconds
Started Aug 19 05:42:02 PM PDT 24
Finished Aug 19 05:42:05 PM PDT 24
Peak memory 215528 kb
Host smart-45146132-198e-4f40-bf79-1a78136fbafd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1399332885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1399332885
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3434119859
Short name T727
Test name
Test status
Simulation time 331299175 ps
CPU time 2.3 seconds
Started Aug 19 05:42:06 PM PDT 24
Finished Aug 19 05:42:09 PM PDT 24
Peak memory 223064 kb
Host smart-9cd9a12a-0c17-4903-8d3b-8d06600cab6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434119859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3434119859
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.677433175
Short name T526
Test name
Test status
Simulation time 341928137 ps
CPU time 10.42 seconds
Started Aug 19 05:42:04 PM PDT 24
Finished Aug 19 05:42:15 PM PDT 24
Peak memory 222956 kb
Host smart-2ab937df-9f5e-458c-a0c4-55f04c0e676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677433175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.677433175
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.4027497991
Short name T381
Test name
Test status
Simulation time 88796505 ps
CPU time 2.88 seconds
Started Aug 19 05:42:01 PM PDT 24
Finished Aug 19 05:42:04 PM PDT 24
Peak memory 214892 kb
Host smart-d3234ce5-6df6-493e-8343-9b2d7871894f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027497991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.4027497991
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2349303023
Short name T811
Test name
Test status
Simulation time 160076879 ps
CPU time 2.55 seconds
Started Aug 19 05:42:05 PM PDT 24
Finished Aug 19 05:42:07 PM PDT 24
Peak memory 206484 kb
Host smart-2e3584de-a401-4e5e-9b43-07bd4fdf69c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349303023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2349303023
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3638049756
Short name T631
Test name
Test status
Simulation time 60794609 ps
CPU time 2.97 seconds
Started Aug 19 05:42:02 PM PDT 24
Finished Aug 19 05:42:05 PM PDT 24
Peak memory 209728 kb
Host smart-85e42753-0fea-47fa-aec1-4378e2affa02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638049756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3638049756
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3644805999
Short name T473
Test name
Test status
Simulation time 62895306 ps
CPU time 3.48 seconds
Started Aug 19 05:42:05 PM PDT 24
Finished Aug 19 05:42:09 PM PDT 24
Peak memory 218764 kb
Host smart-410cf970-5a88-4ff9-ab04-eacd01be4fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644805999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3644805999
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2949883907
Short name T655
Test name
Test status
Simulation time 77949008 ps
CPU time 1.74 seconds
Started Aug 19 05:42:01 PM PDT 24
Finished Aug 19 05:42:03 PM PDT 24
Peak memory 207268 kb
Host smart-738d6147-dc27-4411-b2ad-a0b659ed8148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949883907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2949883907
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2511579671
Short name T537
Test name
Test status
Simulation time 720595760 ps
CPU time 3.81 seconds
Started Aug 19 05:42:01 PM PDT 24
Finished Aug 19 05:42:05 PM PDT 24
Peak memory 207528 kb
Host smart-3438e4de-774b-477e-8b80-4ca34a9de0da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511579671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2511579671
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1423731605
Short name T575
Test name
Test status
Simulation time 102775979 ps
CPU time 4.28 seconds
Started Aug 19 05:42:00 PM PDT 24
Finished Aug 19 05:42:05 PM PDT 24
Peak memory 207516 kb
Host smart-4386ae3b-db4f-46e3-8835-0231c0a0a9e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423731605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1423731605
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2940779097
Short name T846
Test name
Test status
Simulation time 123775276 ps
CPU time 2.67 seconds
Started Aug 19 05:42:01 PM PDT 24
Finished Aug 19 05:42:04 PM PDT 24
Peak memory 207568 kb
Host smart-cb38b42e-a566-4773-86e5-8df0d0812f3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940779097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2940779097
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2209622868
Short name T799
Test name
Test status
Simulation time 86020055 ps
CPU time 2.79 seconds
Started Aug 19 05:42:03 PM PDT 24
Finished Aug 19 05:42:05 PM PDT 24
Peak memory 218824 kb
Host smart-125d5235-6c1f-4e76-81d3-fc18f892558d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209622868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2209622868
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2508911789
Short name T605
Test name
Test status
Simulation time 2448436773 ps
CPU time 18.9 seconds
Started Aug 19 05:42:02 PM PDT 24
Finished Aug 19 05:42:21 PM PDT 24
Peak memory 208948 kb
Host smart-bc368a0a-f767-4aa4-8cc2-e1211770b73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508911789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2508911789
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.733971226
Short name T736
Test name
Test status
Simulation time 250946641 ps
CPU time 10.21 seconds
Started Aug 19 05:42:08 PM PDT 24
Finished Aug 19 05:42:19 PM PDT 24
Peak memory 220620 kb
Host smart-9a5b8235-5497-4604-885f-7bba7db140b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733971226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.733971226
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3836729162
Short name T674
Test name
Test status
Simulation time 975571779 ps
CPU time 20.52 seconds
Started Aug 19 05:42:05 PM PDT 24
Finished Aug 19 05:42:25 PM PDT 24
Peak memory 221636 kb
Host smart-e92708a1-0846-4481-ac9d-317adc9520e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836729162 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3836729162
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1737145855
Short name T238
Test name
Test status
Simulation time 802891535 ps
CPU time 6.8 seconds
Started Aug 19 05:42:00 PM PDT 24
Finished Aug 19 05:42:07 PM PDT 24
Peak memory 210088 kb
Host smart-9f41c7fc-350e-4bfe-94bc-2587f3cbba16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1737145855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1737145855
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3256644448
Short name T183
Test name
Test status
Simulation time 45534359 ps
CPU time 1.63 seconds
Started Aug 19 05:42:06 PM PDT 24
Finished Aug 19 05:42:07 PM PDT 24
Peak memory 210332 kb
Host smart-aa66b6b2-ab3c-4616-ad1f-278a4f7e4e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256644448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3256644448
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.3126734283
Short name T54
Test name
Test status
Simulation time 15321429 ps
CPU time 0.95 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:05 PM PDT 24
Peak memory 206496 kb
Host smart-2d5dffa9-4ec6-412a-8b7e-9642d6bf681a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126734283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.3126734283
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1199990147
Short name T397
Test name
Test status
Simulation time 41713756 ps
CPU time 3.27 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:39:57 PM PDT 24
Peak memory 215812 kb
Host smart-e4f9e70b-38e8-4a10-b364-9b58d5ab565e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1199990147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1199990147
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.721984391
Short name T549
Test name
Test status
Simulation time 407452401 ps
CPU time 2.42 seconds
Started Aug 19 05:40:02 PM PDT 24
Finished Aug 19 05:40:05 PM PDT 24
Peak memory 215968 kb
Host smart-b46ecf99-3cd6-42d8-a29e-531e3561df10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721984391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.721984391
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3805450093
Short name T856
Test name
Test status
Simulation time 34218101 ps
CPU time 1.68 seconds
Started Aug 19 05:40:05 PM PDT 24
Finished Aug 19 05:40:07 PM PDT 24
Peak memory 208028 kb
Host smart-00a3814b-b8a4-4aab-857d-e37b55b56d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805450093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3805450093
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1361000738
Short name T115
Test name
Test status
Simulation time 53888500 ps
CPU time 2.34 seconds
Started Aug 19 05:40:02 PM PDT 24
Finished Aug 19 05:40:05 PM PDT 24
Peak memory 212036 kb
Host smart-68ca09ff-927b-42b7-a3b8-329493d84c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361000738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1361000738
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2567150759
Short name T377
Test name
Test status
Simulation time 206085872 ps
CPU time 9.8 seconds
Started Aug 19 05:40:02 PM PDT 24
Finished Aug 19 05:40:11 PM PDT 24
Peak memory 220920 kb
Host smart-8405daf5-4b3f-4c48-9852-2acc96c5f55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567150759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2567150759
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.1345006617
Short name T720
Test name
Test status
Simulation time 933178018 ps
CPU time 21.35 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:40:14 PM PDT 24
Peak memory 209480 kb
Host smart-6f419456-e11e-4986-9f31-225fe2c03edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345006617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.1345006617
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1381525991
Short name T232
Test name
Test status
Simulation time 2132263841 ps
CPU time 5.51 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:39:59 PM PDT 24
Peak memory 209084 kb
Host smart-59db01be-5e73-4433-b8e3-532388a63417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381525991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1381525991
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.1740278961
Short name T319
Test name
Test status
Simulation time 1125460768 ps
CPU time 22.16 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:40:16 PM PDT 24
Peak memory 209256 kb
Host smart-62cde982-f327-461a-88a9-95b2f15bc28f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740278961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.1740278961
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.380022033
Short name T906
Test name
Test status
Simulation time 327792758 ps
CPU time 3.01 seconds
Started Aug 19 05:39:57 PM PDT 24
Finished Aug 19 05:40:00 PM PDT 24
Peak memory 207456 kb
Host smart-38dd374c-d449-4d86-b82e-08116cacf1d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380022033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.380022033
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.752482669
Short name T457
Test name
Test status
Simulation time 138936866 ps
CPU time 2.53 seconds
Started Aug 19 05:39:51 PM PDT 24
Finished Aug 19 05:39:54 PM PDT 24
Peak memory 209320 kb
Host smart-4d707c5e-ae9b-437a-a93b-503420648028
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752482669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.752482669
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.4088892708
Short name T841
Test name
Test status
Simulation time 139528817 ps
CPU time 2.22 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:06 PM PDT 24
Peak memory 216432 kb
Host smart-fc711736-81b7-4468-9284-81e4507e006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088892708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.4088892708
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3966982594
Short name T430
Test name
Test status
Simulation time 30220456 ps
CPU time 1.63 seconds
Started Aug 19 05:39:53 PM PDT 24
Finished Aug 19 05:39:55 PM PDT 24
Peak memory 207504 kb
Host smart-93447b7c-536b-45ac-aa5f-0727c87cb370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966982594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3966982594
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3375020330
Short name T165
Test name
Test status
Simulation time 727538700 ps
CPU time 29 seconds
Started Aug 19 05:40:00 PM PDT 24
Finished Aug 19 05:40:30 PM PDT 24
Peak memory 223120 kb
Host smart-8093c7b8-a4be-4f51-90fe-b1af6c0e9563
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375020330 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3375020330
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1095925647
Short name T296
Test name
Test status
Simulation time 85363323 ps
CPU time 4.65 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:08 PM PDT 24
Peak memory 214804 kb
Host smart-29ab3469-533f-40ca-b4f4-7f86b85102c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095925647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1095925647
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1113792121
Short name T486
Test name
Test status
Simulation time 47226281 ps
CPU time 2.14 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:05 PM PDT 24
Peak memory 210520 kb
Host smart-f00fbb44-aafb-4733-b1f5-8e50b39e4180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113792121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1113792121
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.151201802
Short name T573
Test name
Test status
Simulation time 37334252 ps
CPU time 0.77 seconds
Started Aug 19 05:42:17 PM PDT 24
Finished Aug 19 05:42:18 PM PDT 24
Peak memory 206416 kb
Host smart-ebbd529e-d881-46d0-8e0f-71718b5357e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151201802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.151201802
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.452059419
Short name T625
Test name
Test status
Simulation time 537964490 ps
CPU time 3.27 seconds
Started Aug 19 05:42:10 PM PDT 24
Finished Aug 19 05:42:13 PM PDT 24
Peak memory 210176 kb
Host smart-b4f6d0c6-4028-405c-a176-4df054aca11d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452059419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.452059419
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.4263719393
Short name T849
Test name
Test status
Simulation time 23833089 ps
CPU time 1.83 seconds
Started Aug 19 05:42:05 PM PDT 24
Finished Aug 19 05:42:07 PM PDT 24
Peak memory 209064 kb
Host smart-6a41216f-2f7a-43f8-ae54-4919ca26081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263719393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.4263719393
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.197091827
Short name T229
Test name
Test status
Simulation time 262899854 ps
CPU time 5.43 seconds
Started Aug 19 05:42:10 PM PDT 24
Finished Aug 19 05:42:16 PM PDT 24
Peak memory 214756 kb
Host smart-743e481d-f16a-4ab9-95cd-629f8f3f6a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197091827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.197091827
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1635562098
Short name T833
Test name
Test status
Simulation time 157283961 ps
CPU time 6.38 seconds
Started Aug 19 05:42:10 PM PDT 24
Finished Aug 19 05:42:17 PM PDT 24
Peak memory 220720 kb
Host smart-88e0e5e1-de7c-4387-9922-228cab3f3285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635562098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1635562098
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3533139280
Short name T378
Test name
Test status
Simulation time 2387659518 ps
CPU time 70.76 seconds
Started Aug 19 05:42:02 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 209352 kb
Host smart-9f512f05-1740-429c-aa50-934b1eb3bb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533139280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3533139280
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.968331803
Short name T448
Test name
Test status
Simulation time 66408916 ps
CPU time 3.19 seconds
Started Aug 19 05:42:02 PM PDT 24
Finished Aug 19 05:42:05 PM PDT 24
Peak memory 208880 kb
Host smart-2c34fba4-4bea-4404-9831-b141a89b7348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968331803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.968331803
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2062088686
Short name T800
Test name
Test status
Simulation time 197043442 ps
CPU time 5.98 seconds
Started Aug 19 05:42:00 PM PDT 24
Finished Aug 19 05:42:06 PM PDT 24
Peak memory 208520 kb
Host smart-5260bafc-e1d0-48df-9f38-6dd1f6357900
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062088686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2062088686
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3355756532
Short name T693
Test name
Test status
Simulation time 432319715 ps
CPU time 6.47 seconds
Started Aug 19 05:42:02 PM PDT 24
Finished Aug 19 05:42:09 PM PDT 24
Peak memory 209084 kb
Host smart-fd31e0ed-90aa-40e5-836d-80a3c58e2902
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355756532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3355756532
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3184970171
Short name T629
Test name
Test status
Simulation time 26712913 ps
CPU time 2.12 seconds
Started Aug 19 05:42:06 PM PDT 24
Finished Aug 19 05:42:08 PM PDT 24
Peak memory 209344 kb
Host smart-bc280cbc-f79a-43d4-abc7-bbe4c82a23ae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184970171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3184970171
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1104188956
Short name T242
Test name
Test status
Simulation time 506159594 ps
CPU time 2.17 seconds
Started Aug 19 05:42:13 PM PDT 24
Finished Aug 19 05:42:15 PM PDT 24
Peak memory 208580 kb
Host smart-87c064a7-4010-4319-b5e4-b9a82c66406d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104188956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1104188956
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3219102389
Short name T170
Test name
Test status
Simulation time 59003260 ps
CPU time 2.18 seconds
Started Aug 19 05:42:01 PM PDT 24
Finished Aug 19 05:42:04 PM PDT 24
Peak memory 207392 kb
Host smart-3346ccd8-e325-41a1-94cd-1aa65838a298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219102389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3219102389
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.411948968
Short name T179
Test name
Test status
Simulation time 1013263305 ps
CPU time 31.53 seconds
Started Aug 19 05:42:17 PM PDT 24
Finished Aug 19 05:42:49 PM PDT 24
Peak memory 222832 kb
Host smart-10b3a203-afc7-46c8-a786-e7be621ce8cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411948968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.411948968
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1717165049
Short name T768
Test name
Test status
Simulation time 1069827819 ps
CPU time 25.58 seconds
Started Aug 19 05:42:13 PM PDT 24
Finished Aug 19 05:42:38 PM PDT 24
Peak memory 209744 kb
Host smart-430e1173-e73b-4a2e-ba74-054fb3b75ae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717165049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1717165049
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2114527472
Short name T31
Test name
Test status
Simulation time 280847006 ps
CPU time 2.97 seconds
Started Aug 19 05:42:17 PM PDT 24
Finished Aug 19 05:42:20 PM PDT 24
Peak memory 210676 kb
Host smart-49b088a2-7f75-43e9-9151-bf162cecddcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114527472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2114527472
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2502886089
Short name T550
Test name
Test status
Simulation time 12547969 ps
CPU time 0.91 seconds
Started Aug 19 05:42:11 PM PDT 24
Finished Aug 19 05:42:12 PM PDT 24
Peak memory 206392 kb
Host smart-5991bf97-c231-4672-ab72-7789fbe834ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502886089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2502886089
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3469740605
Short name T24
Test name
Test status
Simulation time 188065756 ps
CPU time 4.8 seconds
Started Aug 19 05:42:13 PM PDT 24
Finished Aug 19 05:42:18 PM PDT 24
Peak memory 211160 kb
Host smart-265dd336-d76b-420b-af2b-65d719d70c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469740605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3469740605
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3050519281
Short name T832
Test name
Test status
Simulation time 82811218 ps
CPU time 3.3 seconds
Started Aug 19 05:42:17 PM PDT 24
Finished Aug 19 05:42:20 PM PDT 24
Peak memory 218752 kb
Host smart-6d620cc2-85ef-49c0-a5bc-75afdd83101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050519281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3050519281
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.4031661744
Short name T784
Test name
Test status
Simulation time 117160336 ps
CPU time 2.57 seconds
Started Aug 19 05:42:15 PM PDT 24
Finished Aug 19 05:42:17 PM PDT 24
Peak memory 214788 kb
Host smart-9d18dd6d-aef1-4c06-bd3d-c1698e983999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031661744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.4031661744
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1297094533
Short name T685
Test name
Test status
Simulation time 391666626 ps
CPU time 2.81 seconds
Started Aug 19 05:42:12 PM PDT 24
Finished Aug 19 05:42:15 PM PDT 24
Peak memory 222608 kb
Host smart-65492d31-9ef6-4dc5-9430-46f61048c7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297094533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1297094533
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.867030066
Short name T87
Test name
Test status
Simulation time 165753124 ps
CPU time 5.91 seconds
Started Aug 19 05:42:14 PM PDT 24
Finished Aug 19 05:42:20 PM PDT 24
Peak memory 210680 kb
Host smart-69585147-d390-495a-87f2-83d74e265189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867030066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.867030066
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1745898647
Short name T357
Test name
Test status
Simulation time 1723318985 ps
CPU time 42.8 seconds
Started Aug 19 05:42:12 PM PDT 24
Finished Aug 19 05:42:55 PM PDT 24
Peak memory 214780 kb
Host smart-433f6b86-5258-4670-b596-1dd81cb9d736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745898647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1745898647
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3371113108
Short name T379
Test name
Test status
Simulation time 576360638 ps
CPU time 4.67 seconds
Started Aug 19 05:42:18 PM PDT 24
Finished Aug 19 05:42:23 PM PDT 24
Peak memory 207768 kb
Host smart-a00dd620-a9dd-49d2-9585-3e48a0010e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371113108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3371113108
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1136636283
Short name T898
Test name
Test status
Simulation time 20920831467 ps
CPU time 46.59 seconds
Started Aug 19 05:42:16 PM PDT 24
Finished Aug 19 05:43:03 PM PDT 24
Peak memory 209356 kb
Host smart-2f78ec66-2bdb-4ae0-956a-9b94c467cde8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136636283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1136636283
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3535011575
Short name T477
Test name
Test status
Simulation time 49687920 ps
CPU time 2.77 seconds
Started Aug 19 05:42:12 PM PDT 24
Finished Aug 19 05:42:15 PM PDT 24
Peak memory 207428 kb
Host smart-bf23e4ae-a243-4318-813b-dac0b8f27ab2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535011575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3535011575
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.2361164752
Short name T659
Test name
Test status
Simulation time 951425213 ps
CPU time 7.46 seconds
Started Aug 19 05:42:11 PM PDT 24
Finished Aug 19 05:42:18 PM PDT 24
Peak memory 209124 kb
Host smart-7f3fca37-48d2-420c-a770-5e7f9e087710
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361164752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.2361164752
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.163147615
Short name T900
Test name
Test status
Simulation time 953273740 ps
CPU time 6.64 seconds
Started Aug 19 05:42:12 PM PDT 24
Finished Aug 19 05:42:18 PM PDT 24
Peak memory 218660 kb
Host smart-ba5adfd8-1d92-49ec-810c-677d5a331ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163147615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.163147615
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.902561107
Short name T852
Test name
Test status
Simulation time 31467816 ps
CPU time 2.29 seconds
Started Aug 19 05:42:10 PM PDT 24
Finished Aug 19 05:42:12 PM PDT 24
Peak memory 209532 kb
Host smart-a059a851-d269-48f0-9e40-a78b72d0090d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902561107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.902561107
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1533614829
Short name T353
Test name
Test status
Simulation time 233606283 ps
CPU time 8.18 seconds
Started Aug 19 05:42:13 PM PDT 24
Finished Aug 19 05:42:22 PM PDT 24
Peak memory 219176 kb
Host smart-b79acd31-1aa9-4202-962d-3bae7779503f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533614829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1533614829
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.2677270660
Short name T75
Test name
Test status
Simulation time 1360744358 ps
CPU time 16.7 seconds
Started Aug 19 05:42:14 PM PDT 24
Finished Aug 19 05:42:31 PM PDT 24
Peak memory 223084 kb
Host smart-2668b9e5-0884-4812-b0e1-b73c141cb055
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677270660 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.2677270660
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1924286491
Short name T850
Test name
Test status
Simulation time 947664462 ps
CPU time 7.91 seconds
Started Aug 19 05:42:13 PM PDT 24
Finished Aug 19 05:42:21 PM PDT 24
Peak memory 218552 kb
Host smart-07dcdcbd-d8c2-4a48-8407-45838ba4a8e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924286491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1924286491
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1170582720
Short name T795
Test name
Test status
Simulation time 35670508 ps
CPU time 2.22 seconds
Started Aug 19 05:42:14 PM PDT 24
Finished Aug 19 05:42:17 PM PDT 24
Peak memory 210608 kb
Host smart-aaff9f2f-8242-4748-885b-14c7b4f2aae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170582720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1170582720
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1871020732
Short name T523
Test name
Test status
Simulation time 39532065 ps
CPU time 0.89 seconds
Started Aug 19 05:42:14 PM PDT 24
Finished Aug 19 05:42:15 PM PDT 24
Peak memory 206620 kb
Host smart-4487469f-c6ef-4f78-8e67-726b03f818d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871020732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1871020732
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1515744859
Short name T662
Test name
Test status
Simulation time 1557117041 ps
CPU time 9.6 seconds
Started Aug 19 05:42:12 PM PDT 24
Finished Aug 19 05:42:22 PM PDT 24
Peak memory 208484 kb
Host smart-cb197cbc-39a7-48be-8300-183efe4f6d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515744859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1515744859
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3158576731
Short name T280
Test name
Test status
Simulation time 73493186 ps
CPU time 2.73 seconds
Started Aug 19 05:42:09 PM PDT 24
Finished Aug 19 05:42:12 PM PDT 24
Peak memory 220396 kb
Host smart-3f7135a5-3278-41ac-8ba3-fc5b7671b59f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158576731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3158576731
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1627590898
Short name T704
Test name
Test status
Simulation time 1971823702 ps
CPU time 4.86 seconds
Started Aug 19 05:42:15 PM PDT 24
Finished Aug 19 05:42:20 PM PDT 24
Peak memory 214812 kb
Host smart-720de471-2343-42c1-8fef-81bed55baf94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627590898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1627590898
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1545990111
Short name T308
Test name
Test status
Simulation time 168253181 ps
CPU time 3.99 seconds
Started Aug 19 05:42:14 PM PDT 24
Finished Aug 19 05:42:18 PM PDT 24
Peak memory 209948 kb
Host smart-8696e325-3ce8-413a-a8d0-ef7f1017153f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545990111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1545990111
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.4128053398
Short name T327
Test name
Test status
Simulation time 97871019 ps
CPU time 4.08 seconds
Started Aug 19 05:42:12 PM PDT 24
Finished Aug 19 05:42:16 PM PDT 24
Peak memory 208924 kb
Host smart-ffd2d134-8d00-4132-8b1d-2ade35515439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128053398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.4128053398
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1793300642
Short name T488
Test name
Test status
Simulation time 44997749 ps
CPU time 2.47 seconds
Started Aug 19 05:42:15 PM PDT 24
Finished Aug 19 05:42:18 PM PDT 24
Peak memory 207476 kb
Host smart-bd46bbf2-87fc-437f-9fdc-2c35319be01f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793300642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1793300642
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3950131754
Short name T716
Test name
Test status
Simulation time 199275260 ps
CPU time 5.66 seconds
Started Aug 19 05:42:14 PM PDT 24
Finished Aug 19 05:42:19 PM PDT 24
Peak memory 209088 kb
Host smart-a062649f-11a8-4978-9038-b7eb3e6e7748
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950131754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3950131754
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3788130653
Short name T742
Test name
Test status
Simulation time 58909611 ps
CPU time 3.06 seconds
Started Aug 19 05:42:13 PM PDT 24
Finished Aug 19 05:42:16 PM PDT 24
Peak memory 209324 kb
Host smart-6d6c6817-5f0c-474d-bb3a-89e944f71b0a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788130653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3788130653
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.4194633783
Short name T516
Test name
Test status
Simulation time 21644150 ps
CPU time 1.82 seconds
Started Aug 19 05:42:12 PM PDT 24
Finished Aug 19 05:42:13 PM PDT 24
Peak memory 210400 kb
Host smart-c27a7bc4-93d5-461b-8657-a2605530403a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194633783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4194633783
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.1375627115
Short name T622
Test name
Test status
Simulation time 72644065 ps
CPU time 2.65 seconds
Started Aug 19 05:42:14 PM PDT 24
Finished Aug 19 05:42:17 PM PDT 24
Peak memory 208928 kb
Host smart-87951c42-ebea-48cc-885f-2ca9f24f2226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375627115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.1375627115
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1625170893
Short name T555
Test name
Test status
Simulation time 259248306 ps
CPU time 6.7 seconds
Started Aug 19 05:42:10 PM PDT 24
Finished Aug 19 05:42:17 PM PDT 24
Peak memory 209576 kb
Host smart-ef705f6c-e858-478b-91a3-c67105c9e43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625170893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1625170893
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3057680573
Short name T848
Test name
Test status
Simulation time 6201362540 ps
CPU time 16.89 seconds
Started Aug 19 05:42:13 PM PDT 24
Finished Aug 19 05:42:30 PM PDT 24
Peak memory 212256 kb
Host smart-b0768793-775a-45e4-bf6f-1d60cf4c2b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057680573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3057680573
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.642588105
Short name T459
Test name
Test status
Simulation time 21589973 ps
CPU time 0.85 seconds
Started Aug 19 05:42:20 PM PDT 24
Finished Aug 19 05:42:21 PM PDT 24
Peak memory 206424 kb
Host smart-f0eec06a-09e1-4402-9b5a-2cf71b7bc2ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642588105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.642588105
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2820520927
Short name T682
Test name
Test status
Simulation time 99329775 ps
CPU time 2.23 seconds
Started Aug 19 05:42:13 PM PDT 24
Finished Aug 19 05:42:16 PM PDT 24
Peak memory 208264 kb
Host smart-f73a3c2a-7a8f-4e6f-8cd6-64c49553f104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820520927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2820520927
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3766665520
Short name T127
Test name
Test status
Simulation time 60230833 ps
CPU time 2.7 seconds
Started Aug 19 05:42:16 PM PDT 24
Finished Aug 19 05:42:19 PM PDT 24
Peak memory 209436 kb
Host smart-0e416174-66b3-487d-a4bc-da4400d2d0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766665520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3766665520
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3231942837
Short name T51
Test name
Test status
Simulation time 72032086 ps
CPU time 3.5 seconds
Started Aug 19 05:42:17 PM PDT 24
Finished Aug 19 05:42:21 PM PDT 24
Peak memory 210184 kb
Host smart-650f49b4-9039-43d3-90d9-6c670c298399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231942837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3231942837
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2526234286
Short name T663
Test name
Test status
Simulation time 240706441 ps
CPU time 4.21 seconds
Started Aug 19 05:42:12 PM PDT 24
Finished Aug 19 05:42:16 PM PDT 24
Peak memory 214868 kb
Host smart-bf262375-fa58-4eef-8f3a-bf508b41c575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526234286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2526234286
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2951867691
Short name T724
Test name
Test status
Simulation time 117878343 ps
CPU time 5.33 seconds
Started Aug 19 05:42:12 PM PDT 24
Finished Aug 19 05:42:18 PM PDT 24
Peak memory 216708 kb
Host smart-5648fd9f-2268-4203-8048-286200ce4997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951867691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2951867691
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3711446434
Short name T269
Test name
Test status
Simulation time 82220018 ps
CPU time 3.6 seconds
Started Aug 19 05:42:14 PM PDT 24
Finished Aug 19 05:42:18 PM PDT 24
Peak memory 208840 kb
Host smart-a364dbe0-a5ad-4507-8273-d5f9821ebe7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711446434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3711446434
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.2709628968
Short name T359
Test name
Test status
Simulation time 48355724 ps
CPU time 2.6 seconds
Started Aug 19 05:42:12 PM PDT 24
Finished Aug 19 05:42:15 PM PDT 24
Peak memory 209144 kb
Host smart-e017ffd4-59e3-4c36-bf4b-6a9d315fcc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709628968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.2709628968
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1228148039
Short name T563
Test name
Test status
Simulation time 29017586 ps
CPU time 2.21 seconds
Started Aug 19 05:42:13 PM PDT 24
Finished Aug 19 05:42:15 PM PDT 24
Peak memory 207388 kb
Host smart-c691c15c-6259-4ace-8ecc-6e9d352dbed9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228148039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1228148039
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1387597990
Short name T820
Test name
Test status
Simulation time 22118241 ps
CPU time 1.87 seconds
Started Aug 19 05:42:15 PM PDT 24
Finished Aug 19 05:42:17 PM PDT 24
Peak memory 207296 kb
Host smart-cb028835-49dc-452e-94f0-0eb776ab2eb8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387597990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1387597990
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1647064089
Short name T553
Test name
Test status
Simulation time 751565855 ps
CPU time 18.48 seconds
Started Aug 19 05:42:17 PM PDT 24
Finished Aug 19 05:42:35 PM PDT 24
Peak memory 208444 kb
Host smart-2278dc98-f542-4e67-9e5f-2274286b3f91
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647064089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1647064089
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.4287479337
Short name T618
Test name
Test status
Simulation time 52383789 ps
CPU time 2.76 seconds
Started Aug 19 05:42:16 PM PDT 24
Finished Aug 19 05:42:19 PM PDT 24
Peak memory 209508 kb
Host smart-0a5c9df1-b80e-4de7-991e-e868a5b2d305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287479337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.4287479337
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3777085737
Short name T792
Test name
Test status
Simulation time 181198268 ps
CPU time 4.16 seconds
Started Aug 19 05:42:14 PM PDT 24
Finished Aug 19 05:42:18 PM PDT 24
Peak memory 209256 kb
Host smart-f848bfb3-3d4a-4b8c-a10b-e7374f8ebada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777085737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3777085737
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1014612639
Short name T213
Test name
Test status
Simulation time 23364089872 ps
CPU time 671.85 seconds
Started Aug 19 05:42:18 PM PDT 24
Finished Aug 19 05:53:30 PM PDT 24
Peak memory 219172 kb
Host smart-2dc58f12-d795-4f9b-b6ad-fe3ba378a5c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014612639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1014612639
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3219881729
Short name T806
Test name
Test status
Simulation time 111743875 ps
CPU time 3.72 seconds
Started Aug 19 05:42:15 PM PDT 24
Finished Aug 19 05:42:19 PM PDT 24
Peak memory 209800 kb
Host smart-f6d28583-b8be-4cd3-969f-53807a0a7cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3219881729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3219881729
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.672477494
Short name T672
Test name
Test status
Simulation time 59843633 ps
CPU time 1.79 seconds
Started Aug 19 05:42:18 PM PDT 24
Finished Aug 19 05:42:20 PM PDT 24
Peak memory 210560 kb
Host smart-22e07c13-6ffc-4264-96e4-b7506a7515f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672477494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.672477494
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.831968355
Short name T667
Test name
Test status
Simulation time 29319609 ps
CPU time 0.83 seconds
Started Aug 19 05:42:23 PM PDT 24
Finished Aug 19 05:42:24 PM PDT 24
Peak memory 206436 kb
Host smart-d1bbeb99-e79d-425e-b4ab-6c90e0450e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831968355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.831968355
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2365040491
Short name T134
Test name
Test status
Simulation time 29723994 ps
CPU time 2.04 seconds
Started Aug 19 05:42:21 PM PDT 24
Finished Aug 19 05:42:24 PM PDT 24
Peak memory 208136 kb
Host smart-2933aafe-2dc9-4327-b2f7-7e95515ebd23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365040491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2365040491
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3329115797
Short name T836
Test name
Test status
Simulation time 406081894 ps
CPU time 6.79 seconds
Started Aug 19 05:42:20 PM PDT 24
Finished Aug 19 05:42:27 PM PDT 24
Peak memory 214800 kb
Host smart-1c2951ba-28cb-43b1-b18a-b256a96d47d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329115797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3329115797
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3144439522
Short name T335
Test name
Test status
Simulation time 125600008 ps
CPU time 4.25 seconds
Started Aug 19 05:42:23 PM PDT 24
Finished Aug 19 05:42:27 PM PDT 24
Peak memory 214764 kb
Host smart-125a4673-2748-466c-b4c3-357394f9c796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144439522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3144439522
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_random.1917119448
Short name T348
Test name
Test status
Simulation time 695495741 ps
CPU time 9.38 seconds
Started Aug 19 05:42:21 PM PDT 24
Finished Aug 19 05:42:30 PM PDT 24
Peak memory 214740 kb
Host smart-451407d2-d2ec-45d9-a5ec-4e2ab12ddaf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917119448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1917119448
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.268435172
Short name T518
Test name
Test status
Simulation time 310864364 ps
CPU time 3.14 seconds
Started Aug 19 05:42:21 PM PDT 24
Finished Aug 19 05:42:25 PM PDT 24
Peak memory 207300 kb
Host smart-8fff52a9-d8f1-4068-85c8-cc604ed2870d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268435172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.268435172
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.973445568
Short name T578
Test name
Test status
Simulation time 42302451 ps
CPU time 2.41 seconds
Started Aug 19 05:42:22 PM PDT 24
Finished Aug 19 05:42:25 PM PDT 24
Peak memory 207508 kb
Host smart-008f427c-2e9a-4303-a801-509250c7903b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=973445568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.973445568
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1545091918
Short name T15
Test name
Test status
Simulation time 4222720248 ps
CPU time 48.47 seconds
Started Aug 19 05:42:24 PM PDT 24
Finished Aug 19 05:43:13 PM PDT 24
Peak memory 209600 kb
Host smart-3619d5a3-eaca-4850-be4a-0dd548ec5110
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545091918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1545091918
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3871481192
Short name T714
Test name
Test status
Simulation time 481259448 ps
CPU time 5.92 seconds
Started Aug 19 05:42:23 PM PDT 24
Finished Aug 19 05:42:30 PM PDT 24
Peak memory 209252 kb
Host smart-c3a69f90-7727-45f0-8dc2-9cbb19dab8c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871481192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3871481192
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1395755446
Short name T501
Test name
Test status
Simulation time 393400179 ps
CPU time 3.12 seconds
Started Aug 19 05:42:23 PM PDT 24
Finished Aug 19 05:42:26 PM PDT 24
Peak memory 210408 kb
Host smart-d8fdd389-5805-42d0-b5d2-263eb8fedd19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395755446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1395755446
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3916722318
Short name T907
Test name
Test status
Simulation time 643099270 ps
CPU time 3.82 seconds
Started Aug 19 05:42:21 PM PDT 24
Finished Aug 19 05:42:25 PM PDT 24
Peak memory 208948 kb
Host smart-aebfae55-88a7-4fee-8aad-67f09cb997b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3916722318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3916722318
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2519246764
Short name T879
Test name
Test status
Simulation time 428588053 ps
CPU time 6.15 seconds
Started Aug 19 05:42:24 PM PDT 24
Finished Aug 19 05:42:31 PM PDT 24
Peak memory 207636 kb
Host smart-9ea851af-d630-4506-b1c5-452aa17358e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519246764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2519246764
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1577313267
Short name T882
Test name
Test status
Simulation time 55278922 ps
CPU time 2.68 seconds
Started Aug 19 05:42:20 PM PDT 24
Finished Aug 19 05:42:23 PM PDT 24
Peak memory 210396 kb
Host smart-a72871b0-8c31-4d0d-b78f-712df5fbcded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577313267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1577313267
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.1380707784
Short name T594
Test name
Test status
Simulation time 36268247 ps
CPU time 0.87 seconds
Started Aug 19 05:42:21 PM PDT 24
Finished Aug 19 05:42:22 PM PDT 24
Peak memory 206412 kb
Host smart-dc6923aa-0979-4485-920e-1fe3a3d1dc07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380707784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1380707784
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.4188185209
Short name T396
Test name
Test status
Simulation time 894091713 ps
CPU time 5.62 seconds
Started Aug 19 05:42:20 PM PDT 24
Finished Aug 19 05:42:25 PM PDT 24
Peak memory 214820 kb
Host smart-9f1e4abd-e1b8-42c6-940a-4777a24cae2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4188185209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.4188185209
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2819674215
Short name T189
Test name
Test status
Simulation time 36562359 ps
CPU time 2.58 seconds
Started Aug 19 05:42:20 PM PDT 24
Finished Aug 19 05:42:23 PM PDT 24
Peak memory 210012 kb
Host smart-9487925f-a51b-41ec-9643-6bd3ae3e0cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819674215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2819674215
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2984880193
Short name T244
Test name
Test status
Simulation time 436065518 ps
CPU time 3.72 seconds
Started Aug 19 05:42:22 PM PDT 24
Finished Aug 19 05:42:26 PM PDT 24
Peak memory 210332 kb
Host smart-a1036e2f-b90f-4b4a-ab15-27f0f5e04be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984880193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2984880193
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2965918479
Short name T781
Test name
Test status
Simulation time 68004416 ps
CPU time 2.57 seconds
Started Aug 19 05:42:21 PM PDT 24
Finished Aug 19 05:42:23 PM PDT 24
Peak memory 214872 kb
Host smart-66c372cc-5722-42bd-9790-8c595edbf5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965918479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2965918479
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1897122544
Short name T276
Test name
Test status
Simulation time 359762234 ps
CPU time 3 seconds
Started Aug 19 05:42:26 PM PDT 24
Finished Aug 19 05:42:29 PM PDT 24
Peak memory 206572 kb
Host smart-683b2122-063d-4f5f-92a9-2ce6a314f8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897122544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1897122544
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2423660057
Short name T765
Test name
Test status
Simulation time 174043334 ps
CPU time 3.35 seconds
Started Aug 19 05:42:28 PM PDT 24
Finished Aug 19 05:42:31 PM PDT 24
Peak memory 220864 kb
Host smart-387fe32c-6ab7-4d7b-927f-18a336430a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423660057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2423660057
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1514969595
Short name T567
Test name
Test status
Simulation time 471051899 ps
CPU time 5.47 seconds
Started Aug 19 05:42:27 PM PDT 24
Finished Aug 19 05:42:33 PM PDT 24
Peak memory 218872 kb
Host smart-b49e5cde-ab33-42ec-bc19-9c692b38daac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514969595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1514969595
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3889586096
Short name T409
Test name
Test status
Simulation time 29611549 ps
CPU time 1.68 seconds
Started Aug 19 05:42:27 PM PDT 24
Finished Aug 19 05:42:29 PM PDT 24
Peak memory 206628 kb
Host smart-377b019d-be21-4ae3-b8a2-07cc7e52acaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3889586096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3889586096
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.473757236
Short name T766
Test name
Test status
Simulation time 103575376 ps
CPU time 2.61 seconds
Started Aug 19 05:42:27 PM PDT 24
Finished Aug 19 05:42:29 PM PDT 24
Peak memory 207388 kb
Host smart-95847ab2-ae26-4a35-bac0-3a2f05d3bd75
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473757236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.473757236
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.641116805
Short name T565
Test name
Test status
Simulation time 155035606 ps
CPU time 5.51 seconds
Started Aug 19 05:42:19 PM PDT 24
Finished Aug 19 05:42:25 PM PDT 24
Peak memory 208460 kb
Host smart-83d18e45-2add-4de2-8f37-150314c7124b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641116805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.641116805
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.481810425
Short name T447
Test name
Test status
Simulation time 417320674 ps
CPU time 5.54 seconds
Started Aug 19 05:42:27 PM PDT 24
Finished Aug 19 05:42:33 PM PDT 24
Peak memory 208532 kb
Host smart-dec069be-b7c4-4681-993f-b5549ea70b81
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481810425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.481810425
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2364366411
Short name T417
Test name
Test status
Simulation time 3762482768 ps
CPU time 12.15 seconds
Started Aug 19 05:42:23 PM PDT 24
Finished Aug 19 05:42:35 PM PDT 24
Peak memory 210424 kb
Host smart-7c208062-29de-445a-a2a2-d77695240986
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364366411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2364366411
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1778633191
Short name T771
Test name
Test status
Simulation time 297788688 ps
CPU time 9.35 seconds
Started Aug 19 05:42:23 PM PDT 24
Finished Aug 19 05:42:32 PM PDT 24
Peak memory 209596 kb
Host smart-20793644-6072-4cd2-a77d-4129690caa80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778633191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1778633191
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2482072712
Short name T557
Test name
Test status
Simulation time 107238986 ps
CPU time 3.9 seconds
Started Aug 19 05:42:19 PM PDT 24
Finished Aug 19 05:42:23 PM PDT 24
Peak memory 219012 kb
Host smart-6370bc79-394c-4b82-b386-a648dc263abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482072712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2482072712
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.324481254
Short name T386
Test name
Test status
Simulation time 864813690 ps
CPU time 3.05 seconds
Started Aug 19 05:42:23 PM PDT 24
Finished Aug 19 05:42:26 PM PDT 24
Peak memory 210748 kb
Host smart-a8db1e28-5a70-4a3f-96eb-db7a9d475475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324481254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.324481254
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.280492691
Short name T569
Test name
Test status
Simulation time 19971279 ps
CPU time 1 seconds
Started Aug 19 05:42:22 PM PDT 24
Finished Aug 19 05:42:23 PM PDT 24
Peak memory 206584 kb
Host smart-1cbace0c-3911-411d-92e3-f28f0a204282
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280492691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.280492691
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.887927220
Short name T393
Test name
Test status
Simulation time 131087720 ps
CPU time 2.68 seconds
Started Aug 19 05:42:26 PM PDT 24
Finished Aug 19 05:42:29 PM PDT 24
Peak memory 214820 kb
Host smart-26754db6-987c-43ff-ae38-a55f7c5d7d16
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=887927220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.887927220
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.625012049
Short name T248
Test name
Test status
Simulation time 64846593 ps
CPU time 2.99 seconds
Started Aug 19 05:42:26 PM PDT 24
Finished Aug 19 05:42:29 PM PDT 24
Peak memory 209092 kb
Host smart-1a5f67e4-65f9-47c7-80f3-9030371edc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625012049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.625012049
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2942893279
Short name T783
Test name
Test status
Simulation time 96711197 ps
CPU time 2.26 seconds
Started Aug 19 05:42:21 PM PDT 24
Finished Aug 19 05:42:24 PM PDT 24
Peak memory 214828 kb
Host smart-f29bda7b-21b0-40d9-805a-fa8ac359789a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942893279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2942893279
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.3917802823
Short name T738
Test name
Test status
Simulation time 400727077 ps
CPU time 3.8 seconds
Started Aug 19 05:42:23 PM PDT 24
Finished Aug 19 05:42:27 PM PDT 24
Peak memory 214728 kb
Host smart-b67fbca3-2216-486d-9db3-fb4a052228a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917802823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.3917802823
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.2639120950
Short name T195
Test name
Test status
Simulation time 61736120 ps
CPU time 2.07 seconds
Started Aug 19 05:42:23 PM PDT 24
Finished Aug 19 05:42:25 PM PDT 24
Peak memory 210180 kb
Host smart-3f056514-4ed2-46ab-8e91-34953ce3533d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639120950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.2639120950
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2587260511
Short name T829
Test name
Test status
Simulation time 155937265 ps
CPU time 6.52 seconds
Started Aug 19 05:42:22 PM PDT 24
Finished Aug 19 05:42:28 PM PDT 24
Peak memory 218716 kb
Host smart-e0d3ca6a-085e-4756-9767-aeaca887a71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587260511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2587260511
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2865208258
Short name T899
Test name
Test status
Simulation time 822358157 ps
CPU time 3.96 seconds
Started Aug 19 05:42:22 PM PDT 24
Finished Aug 19 05:42:26 PM PDT 24
Peak memory 209024 kb
Host smart-0e2cd0e8-3c2e-447b-9e23-7a4c98c20b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865208258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2865208258
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.967919139
Short name T816
Test name
Test status
Simulation time 7909397496 ps
CPU time 17.92 seconds
Started Aug 19 05:42:22 PM PDT 24
Finished Aug 19 05:42:40 PM PDT 24
Peak memory 209352 kb
Host smart-6bc9e2d5-f810-488e-84be-5143fc8425cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967919139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.967919139
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3604800855
Short name T741
Test name
Test status
Simulation time 2263610528 ps
CPU time 19.36 seconds
Started Aug 19 05:42:26 PM PDT 24
Finished Aug 19 05:42:45 PM PDT 24
Peak memory 208596 kb
Host smart-8338aacb-e316-4d60-8e38-e2880055df9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604800855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3604800855
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2074981995
Short name T188
Test name
Test status
Simulation time 482026035 ps
CPU time 4.54 seconds
Started Aug 19 05:42:20 PM PDT 24
Finished Aug 19 05:42:25 PM PDT 24
Peak memory 207488 kb
Host smart-1163b5bd-db71-4fce-8226-1af4acc07de4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074981995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2074981995
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2997727141
Short name T827
Test name
Test status
Simulation time 2424887046 ps
CPU time 10.9 seconds
Started Aug 19 05:42:18 PM PDT 24
Finished Aug 19 05:42:29 PM PDT 24
Peak memory 209784 kb
Host smart-59404eaa-d83c-43c5-bc2e-80b1fdf3dfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997727141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2997727141
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1543000334
Short name T855
Test name
Test status
Simulation time 121848589 ps
CPU time 2.46 seconds
Started Aug 19 05:42:26 PM PDT 24
Finished Aug 19 05:42:28 PM PDT 24
Peak memory 207552 kb
Host smart-1c3d8d9e-0760-4bb3-8763-d8bee6238f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543000334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1543000334
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.4039677069
Short name T892
Test name
Test status
Simulation time 118905532 ps
CPU time 4.92 seconds
Started Aug 19 05:42:29 PM PDT 24
Finished Aug 19 05:42:34 PM PDT 24
Peak memory 208356 kb
Host smart-c5c0f3f8-2658-4708-a270-7c789d4ce07c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039677069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.4039677069
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.601400825
Short name T166
Test name
Test status
Simulation time 1142716593 ps
CPU time 11.26 seconds
Started Aug 19 05:42:28 PM PDT 24
Finished Aug 19 05:42:39 PM PDT 24
Peak memory 219900 kb
Host smart-a3a75359-23a1-4b61-a9e1-092365830e3e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601400825 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.601400825
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3682631238
Short name T778
Test name
Test status
Simulation time 192066695 ps
CPU time 4.38 seconds
Started Aug 19 05:42:19 PM PDT 24
Finished Aug 19 05:42:24 PM PDT 24
Peak memory 207884 kb
Host smart-5e0d0e21-245f-4020-ba99-daa33971b182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682631238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3682631238
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1159992953
Short name T606
Test name
Test status
Simulation time 251543594 ps
CPU time 7.43 seconds
Started Aug 19 05:42:22 PM PDT 24
Finished Aug 19 05:42:30 PM PDT 24
Peak memory 211284 kb
Host smart-8872ce8b-4c5c-4b1a-a06b-dfa68cfd9351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159992953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1159992953
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.986846540
Short name T452
Test name
Test status
Simulation time 52761467 ps
CPU time 0.9 seconds
Started Aug 19 05:42:29 PM PDT 24
Finished Aug 19 05:42:30 PM PDT 24
Peak memory 206552 kb
Host smart-f68b9f46-f238-40cf-a2a3-bb893d092a86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=986846540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.986846540
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2532524597
Short name T323
Test name
Test status
Simulation time 45616028 ps
CPU time 3.48 seconds
Started Aug 19 05:42:28 PM PDT 24
Finished Aug 19 05:42:31 PM PDT 24
Peak memory 215904 kb
Host smart-969f8102-5e00-4852-8ee3-1ee89d1563c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2532524597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2532524597
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1227213123
Short name T871
Test name
Test status
Simulation time 274022357 ps
CPU time 3.76 seconds
Started Aug 19 05:42:31 PM PDT 24
Finished Aug 19 05:42:35 PM PDT 24
Peak memory 221048 kb
Host smart-648682cc-5dfd-46ee-aaf7-1eacfcf9dff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227213123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1227213123
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2750681269
Short name T524
Test name
Test status
Simulation time 111143844 ps
CPU time 4.01 seconds
Started Aug 19 05:42:28 PM PDT 24
Finished Aug 19 05:42:32 PM PDT 24
Peak memory 218640 kb
Host smart-0b09a6bc-77a0-4dda-bfe3-abe60c8585ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750681269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2750681269
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3197276782
Short name T318
Test name
Test status
Simulation time 107320243 ps
CPU time 3.69 seconds
Started Aug 19 05:42:32 PM PDT 24
Finished Aug 19 05:42:36 PM PDT 24
Peak memory 222192 kb
Host smart-1ef4d3ed-46eb-485d-91e0-aae58c7884ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197276782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3197276782
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1404903061
Short name T702
Test name
Test status
Simulation time 79228633 ps
CPU time 2.22 seconds
Started Aug 19 05:42:24 PM PDT 24
Finished Aug 19 05:42:26 PM PDT 24
Peak memory 215480 kb
Host smart-4b891e33-af52-47ab-9704-a4a6dc7eb6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404903061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1404903061
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.4187985948
Short name T228
Test name
Test status
Simulation time 111206379 ps
CPU time 4.67 seconds
Started Aug 19 05:42:24 PM PDT 24
Finished Aug 19 05:42:29 PM PDT 24
Peak memory 210120 kb
Host smart-415fd788-3118-40b2-b54a-29a1b9deea27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187985948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.4187985948
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1408602401
Short name T582
Test name
Test status
Simulation time 2542326999 ps
CPU time 24.08 seconds
Started Aug 19 05:42:26 PM PDT 24
Finished Aug 19 05:42:50 PM PDT 24
Peak memory 208528 kb
Host smart-087cbdf9-6961-4b8c-bdc7-9a3b531a96a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408602401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1408602401
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1684287294
Short name T458
Test name
Test status
Simulation time 121827971 ps
CPU time 2.37 seconds
Started Aug 19 05:42:23 PM PDT 24
Finished Aug 19 05:42:25 PM PDT 24
Peak memory 207256 kb
Host smart-fdf0010f-b970-47cc-8b68-8490965d032e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684287294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1684287294
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.426516976
Short name T721
Test name
Test status
Simulation time 26815061 ps
CPU time 2.11 seconds
Started Aug 19 05:42:21 PM PDT 24
Finished Aug 19 05:42:24 PM PDT 24
Peak memory 209224 kb
Host smart-e08dccdd-19ce-4533-90a3-347ac9e48132
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426516976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.426516976
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1027869562
Short name T706
Test name
Test status
Simulation time 522094598 ps
CPU time 7.05 seconds
Started Aug 19 05:42:18 PM PDT 24
Finished Aug 19 05:42:25 PM PDT 24
Peak memory 209236 kb
Host smart-05e48bdc-0678-4481-b149-81c98657b964
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027869562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1027869562
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3459722234
Short name T489
Test name
Test status
Simulation time 1438121727 ps
CPU time 8.71 seconds
Started Aug 19 05:42:30 PM PDT 24
Finished Aug 19 05:42:39 PM PDT 24
Peak memory 209868 kb
Host smart-08467960-dcf9-4548-87d1-4731de170bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459722234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3459722234
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2202442808
Short name T661
Test name
Test status
Simulation time 112863938 ps
CPU time 3.03 seconds
Started Aug 19 05:42:28 PM PDT 24
Finished Aug 19 05:42:31 PM PDT 24
Peak memory 208692 kb
Host smart-b153fc2e-4d96-4fb3-a13f-52801c7e5230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202442808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2202442808
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2895949039
Short name T237
Test name
Test status
Simulation time 1633348056 ps
CPU time 50.72 seconds
Started Aug 19 05:42:30 PM PDT 24
Finished Aug 19 05:43:21 PM PDT 24
Peak memory 216668 kb
Host smart-d1f5c5f7-c910-4fb4-87fc-e5f55ec4cb92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895949039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2895949039
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2921317621
Short name T511
Test name
Test status
Simulation time 160710278 ps
CPU time 5.82 seconds
Started Aug 19 05:42:28 PM PDT 24
Finished Aug 19 05:42:34 PM PDT 24
Peak memory 214808 kb
Host smart-4d23668a-e97f-45c6-a734-a310388e000b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921317621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2921317621
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1924325472
Short name T785
Test name
Test status
Simulation time 335508504 ps
CPU time 3.83 seconds
Started Aug 19 05:42:34 PM PDT 24
Finished Aug 19 05:42:38 PM PDT 24
Peak memory 210956 kb
Host smart-6abdcb9b-49a5-44cc-953c-8818df0cdc99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924325472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1924325472
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1294983509
Short name T479
Test name
Test status
Simulation time 18528292 ps
CPU time 0.79 seconds
Started Aug 19 05:42:28 PM PDT 24
Finished Aug 19 05:42:29 PM PDT 24
Peak memory 206400 kb
Host smart-2821de99-2a74-467b-a85f-84e3dc4ba862
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294983509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1294983509
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3224953464
Short name T734
Test name
Test status
Simulation time 56431419 ps
CPU time 3.63 seconds
Started Aug 19 05:42:31 PM PDT 24
Finished Aug 19 05:42:35 PM PDT 24
Peak memory 216120 kb
Host smart-c6372c85-2253-44d4-b5ab-28e1ad5343a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3224953464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3224953464
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3764429236
Short name T223
Test name
Test status
Simulation time 2189953500 ps
CPU time 9.33 seconds
Started Aug 19 05:42:36 PM PDT 24
Finished Aug 19 05:42:45 PM PDT 24
Peak memory 214864 kb
Host smart-c8eb87a2-0633-4417-8092-6a55b131d795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764429236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3764429236
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3611735410
Short name T361
Test name
Test status
Simulation time 274419971 ps
CPU time 1.97 seconds
Started Aug 19 05:42:33 PM PDT 24
Finished Aug 19 05:42:35 PM PDT 24
Peak memory 214804 kb
Host smart-8ecd91cf-d6c8-4119-94f6-33f11568d527
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611735410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3611735410
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2545198928
Short name T790
Test name
Test status
Simulation time 81703468 ps
CPU time 2.98 seconds
Started Aug 19 05:42:31 PM PDT 24
Finished Aug 19 05:42:34 PM PDT 24
Peak memory 214828 kb
Host smart-8e5ef902-f8e0-4d9b-9015-ef38497cb7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545198928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2545198928
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2919179403
Short name T534
Test name
Test status
Simulation time 80752265 ps
CPU time 3.03 seconds
Started Aug 19 05:42:30 PM PDT 24
Finished Aug 19 05:42:33 PM PDT 24
Peak memory 210124 kb
Host smart-1eb446f0-36dd-474a-87af-413ef2b2537f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919179403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2919179403
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3395043716
Short name T485
Test name
Test status
Simulation time 227442611 ps
CPU time 5.5 seconds
Started Aug 19 05:42:32 PM PDT 24
Finished Aug 19 05:42:38 PM PDT 24
Peak memory 208612 kb
Host smart-5093e243-7ab4-4e55-94f5-c7f7d33a4454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395043716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3395043716
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.325577906
Short name T824
Test name
Test status
Simulation time 337609063 ps
CPU time 3.63 seconds
Started Aug 19 05:42:29 PM PDT 24
Finished Aug 19 05:42:33 PM PDT 24
Peak memory 209036 kb
Host smart-76861879-4957-45ea-989d-d61a757d781e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325577906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.325577906
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.104589879
Short name T708
Test name
Test status
Simulation time 124531360 ps
CPU time 2.46 seconds
Started Aug 19 05:42:32 PM PDT 24
Finished Aug 19 05:42:35 PM PDT 24
Peak memory 207452 kb
Host smart-9d8c80e2-f39d-4a11-bad3-3f240afc4b97
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104589879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.104589879
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.666070454
Short name T453
Test name
Test status
Simulation time 189867752 ps
CPU time 6.44 seconds
Started Aug 19 05:42:32 PM PDT 24
Finished Aug 19 05:42:39 PM PDT 24
Peak memory 208544 kb
Host smart-d33cc3a2-e3f3-4284-9e09-3e6ed7b17bac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666070454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.666070454
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2828389205
Short name T822
Test name
Test status
Simulation time 355237619 ps
CPU time 12.46 seconds
Started Aug 19 05:42:32 PM PDT 24
Finished Aug 19 05:42:44 PM PDT 24
Peak memory 208412 kb
Host smart-866d08e9-2a27-4090-9341-9d620a04cbdb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828389205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2828389205
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1511292041
Short name T561
Test name
Test status
Simulation time 105784035 ps
CPU time 2.41 seconds
Started Aug 19 05:42:29 PM PDT 24
Finished Aug 19 05:42:32 PM PDT 24
Peak memory 218864 kb
Host smart-ed895363-6457-41c9-b674-464aeb2ec362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511292041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1511292041
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2957138416
Short name T552
Test name
Test status
Simulation time 118301261 ps
CPU time 2.35 seconds
Started Aug 19 05:42:30 PM PDT 24
Finished Aug 19 05:42:32 PM PDT 24
Peak memory 207416 kb
Host smart-7223e8c2-2d18-43cf-9b26-7d629a26cd0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957138416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2957138416
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2580292610
Short name T281
Test name
Test status
Simulation time 330141725 ps
CPU time 5.45 seconds
Started Aug 19 05:42:33 PM PDT 24
Finished Aug 19 05:42:39 PM PDT 24
Peak memory 210736 kb
Host smart-59a1898e-c2b3-4149-ac72-4feeb65a3e5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580292610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2580292610
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3573712453
Short name T896
Test name
Test status
Simulation time 222668417 ps
CPU time 1.96 seconds
Started Aug 19 05:42:29 PM PDT 24
Finished Aug 19 05:42:31 PM PDT 24
Peak memory 210236 kb
Host smart-d030dcbc-6e0c-4220-81ea-3bbb3338ba8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573712453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3573712453
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1904929842
Short name T554
Test name
Test status
Simulation time 46450070 ps
CPU time 0.76 seconds
Started Aug 19 05:42:39 PM PDT 24
Finished Aug 19 05:42:40 PM PDT 24
Peak memory 206376 kb
Host smart-2de19275-5e03-4709-b261-c9fe754fe5f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904929842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1904929842
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2769208224
Short name T193
Test name
Test status
Simulation time 340631138 ps
CPU time 7.15 seconds
Started Aug 19 05:42:33 PM PDT 24
Finished Aug 19 05:42:40 PM PDT 24
Peak memory 218668 kb
Host smart-416505cc-4380-4fe6-9350-988454f99af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2769208224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2769208224
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2956679195
Short name T428
Test name
Test status
Simulation time 76938211 ps
CPU time 2.06 seconds
Started Aug 19 05:42:31 PM PDT 24
Finished Aug 19 05:42:33 PM PDT 24
Peak memory 214608 kb
Host smart-5ed81bf0-c60b-48dd-8899-d3567a3e15f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956679195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2956679195
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2091227984
Short name T640
Test name
Test status
Simulation time 83449885 ps
CPU time 1.69 seconds
Started Aug 19 05:42:28 PM PDT 24
Finished Aug 19 05:42:30 PM PDT 24
Peak memory 214856 kb
Host smart-096dda77-ccfb-4a0a-bfd3-952f37404083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091227984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2091227984
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2379371480
Short name T259
Test name
Test status
Simulation time 91586137 ps
CPU time 3.48 seconds
Started Aug 19 05:42:30 PM PDT 24
Finished Aug 19 05:42:34 PM PDT 24
Peak memory 214588 kb
Host smart-20f97c26-3bb6-4911-b94e-722ee3ad4977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379371480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2379371480
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1875245478
Short name T83
Test name
Test status
Simulation time 143288862 ps
CPU time 2.35 seconds
Started Aug 19 05:42:31 PM PDT 24
Finished Aug 19 05:42:33 PM PDT 24
Peak memory 214832 kb
Host smart-3c91b908-c3de-45cb-97b7-878bb85a82bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875245478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1875245478
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.233153539
Short name T140
Test name
Test status
Simulation time 341298344 ps
CPU time 4.24 seconds
Started Aug 19 05:42:29 PM PDT 24
Finished Aug 19 05:42:34 PM PDT 24
Peak memory 209672 kb
Host smart-3551a04a-f95d-4bd7-a888-bdd92626ad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233153539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.233153539
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3203949414
Short name T333
Test name
Test status
Simulation time 884709209 ps
CPU time 7.31 seconds
Started Aug 19 05:42:34 PM PDT 24
Finished Aug 19 05:42:42 PM PDT 24
Peak memory 207368 kb
Host smart-840ecbfe-2af4-4962-b374-668121d85517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203949414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3203949414
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2432725688
Short name T305
Test name
Test status
Simulation time 99296273 ps
CPU time 3.59 seconds
Started Aug 19 05:42:29 PM PDT 24
Finished Aug 19 05:42:33 PM PDT 24
Peak memory 207608 kb
Host smart-8e004dbf-0016-4bf2-938a-9c1be08b63ce
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432725688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2432725688
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1180891137
Short name T139
Test name
Test status
Simulation time 41502796 ps
CPU time 2.37 seconds
Started Aug 19 05:42:32 PM PDT 24
Finished Aug 19 05:42:35 PM PDT 24
Peak memory 207532 kb
Host smart-62f65862-677c-447f-b4aa-8be47968904a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180891137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1180891137
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2145434835
Short name T733
Test name
Test status
Simulation time 179217477 ps
CPU time 7.05 seconds
Started Aug 19 05:42:32 PM PDT 24
Finished Aug 19 05:42:39 PM PDT 24
Peak memory 209252 kb
Host smart-bdcf3fd7-d5dc-4c6e-b648-80461b17b89c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145434835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2145434835
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2306497793
Short name T779
Test name
Test status
Simulation time 56462818 ps
CPU time 3.12 seconds
Started Aug 19 05:42:32 PM PDT 24
Finished Aug 19 05:42:35 PM PDT 24
Peak memory 208900 kb
Host smart-cb00798a-10f8-4f36-a775-e39fe13cc62d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306497793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2306497793
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.443564939
Short name T465
Test name
Test status
Simulation time 128301153 ps
CPU time 3.31 seconds
Started Aug 19 05:42:31 PM PDT 24
Finished Aug 19 05:42:35 PM PDT 24
Peak memory 208916 kb
Host smart-7c4a169c-4083-45f5-bf91-153075d5010d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443564939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.443564939
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2401056362
Short name T445
Test name
Test status
Simulation time 532865422 ps
CPU time 4.78 seconds
Started Aug 19 05:42:33 PM PDT 24
Finished Aug 19 05:42:38 PM PDT 24
Peak memory 208216 kb
Host smart-21d5719b-7c28-4846-ad10-406e2585ac44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401056362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2401056362
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1394004978
Short name T797
Test name
Test status
Simulation time 115611567 ps
CPU time 3.26 seconds
Started Aug 19 05:42:38 PM PDT 24
Finished Aug 19 05:42:41 PM PDT 24
Peak memory 210312 kb
Host smart-17c410df-3d1e-4861-a20e-a63e7c09db63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394004978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1394004978
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2792061498
Short name T587
Test name
Test status
Simulation time 39210846 ps
CPU time 0.81 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:04 PM PDT 24
Peak memory 206408 kb
Host smart-2fdf7aeb-3c99-4704-b531-18dbb5e8ce67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792061498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2792061498
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3695356650
Short name T239
Test name
Test status
Simulation time 71881868 ps
CPU time 4.81 seconds
Started Aug 19 05:40:00 PM PDT 24
Finished Aug 19 05:40:05 PM PDT 24
Peak memory 215716 kb
Host smart-a4bb686a-1bf1-401a-862b-ceddde00d1f3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3695356650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3695356650
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3924766772
Short name T35
Test name
Test status
Simulation time 123761858 ps
CPU time 3.29 seconds
Started Aug 19 05:40:05 PM PDT 24
Finished Aug 19 05:40:08 PM PDT 24
Peak memory 214744 kb
Host smart-23c3e545-4956-4078-a6bc-db63c2d7dce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924766772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3924766772
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.102492799
Short name T224
Test name
Test status
Simulation time 91889070 ps
CPU time 2.41 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:06 PM PDT 24
Peak memory 222888 kb
Host smart-f12cb845-ba53-416d-b52f-211036efc4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102492799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.102492799
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1119949991
Short name T881
Test name
Test status
Simulation time 271840987 ps
CPU time 2.18 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:07 PM PDT 24
Peak memory 214836 kb
Host smart-7d69f9bc-573f-4d3b-9126-ac310c8d2a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119949991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1119949991
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3089848713
Short name T279
Test name
Test status
Simulation time 56966499 ps
CPU time 2.79 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:06 PM PDT 24
Peak memory 222808 kb
Host smart-35efb6b8-d466-4918-a35b-702988187281
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089848713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3089848713
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2437003588
Short name T869
Test name
Test status
Simulation time 510779443 ps
CPU time 5.59 seconds
Started Aug 19 05:40:05 PM PDT 24
Finished Aug 19 05:40:11 PM PDT 24
Peak memory 210744 kb
Host smart-95b85270-1bec-49b2-be4b-32b34b33b009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437003588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2437003588
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1113034636
Short name T583
Test name
Test status
Simulation time 129970167 ps
CPU time 4.74 seconds
Started Aug 19 05:40:01 PM PDT 24
Finished Aug 19 05:40:06 PM PDT 24
Peak memory 208684 kb
Host smart-b7dc90d2-30c0-4949-b3e3-03bfbf9e9d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113034636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1113034636
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3810068184
Short name T525
Test name
Test status
Simulation time 38148176 ps
CPU time 2.7 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:06 PM PDT 24
Peak memory 209436 kb
Host smart-50deabd5-fdd1-48dc-90c6-e262f284c0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810068184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3810068184
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.925277505
Short name T616
Test name
Test status
Simulation time 398574551 ps
CPU time 4.42 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:08 PM PDT 24
Peak memory 208992 kb
Host smart-c514bee9-ab2f-45ff-9f13-1ca748aeb2a2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925277505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.925277505
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.4027895964
Short name T370
Test name
Test status
Simulation time 143153272 ps
CPU time 3.41 seconds
Started Aug 19 05:40:05 PM PDT 24
Finished Aug 19 05:40:09 PM PDT 24
Peak memory 209060 kb
Host smart-7f849f2e-7f35-42d5-84c5-fbe3bd02a95f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027895964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.4027895964
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3515924969
Short name T492
Test name
Test status
Simulation time 219876917 ps
CPU time 6.31 seconds
Started Aug 19 05:40:02 PM PDT 24
Finished Aug 19 05:40:09 PM PDT 24
Peak memory 208576 kb
Host smart-67bb4938-c957-4130-8875-62724b24c164
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515924969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3515924969
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3372273223
Short name T401
Test name
Test status
Simulation time 1116265906 ps
CPU time 4.43 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:08 PM PDT 24
Peak memory 209056 kb
Host smart-4342efa1-c958-462a-96e7-ce75875bbd6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372273223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3372273223
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.144252082
Short name T770
Test name
Test status
Simulation time 23435651 ps
CPU time 1.93 seconds
Started Aug 19 05:40:05 PM PDT 24
Finished Aug 19 05:40:07 PM PDT 24
Peak memory 209160 kb
Host smart-82f09ed2-6971-498c-b01a-1a347023dd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144252082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.144252082
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.4056098334
Short name T190
Test name
Test status
Simulation time 4597018046 ps
CPU time 45.01 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:49 PM PDT 24
Peak memory 217744 kb
Host smart-37266f1d-9606-471a-98af-109532121b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056098334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.4056098334
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.358595624
Short name T743
Test name
Test status
Simulation time 328947094 ps
CPU time 4.6 seconds
Started Aug 19 05:40:00 PM PDT 24
Finished Aug 19 05:40:05 PM PDT 24
Peak memory 218788 kb
Host smart-496deaef-3ea3-48e5-9ca9-530877d2e7bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358595624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.358595624
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.818377238
Short name T602
Test name
Test status
Simulation time 136801003 ps
CPU time 2.34 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:05 PM PDT 24
Peak memory 210784 kb
Host smart-58d0e52f-7a19-4962-a35f-705cfb6e8d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818377238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.818377238
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3972842930
Short name T432
Test name
Test status
Simulation time 12921978 ps
CPU time 0.75 seconds
Started Aug 19 05:40:05 PM PDT 24
Finished Aug 19 05:40:06 PM PDT 24
Peak memory 206396 kb
Host smart-ae9a2a5a-3024-4d37-a8ed-e1c6fa3b87bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972842930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3972842930
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.4144924484
Short name T98
Test name
Test status
Simulation time 71609528 ps
CPU time 3.61 seconds
Started Aug 19 05:40:01 PM PDT 24
Finished Aug 19 05:40:05 PM PDT 24
Peak memory 214780 kb
Host smart-62a9b9f3-391d-47c3-85fc-e4fda92cdf53
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4144924484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.4144924484
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3623584521
Short name T817
Test name
Test status
Simulation time 198819005 ps
CPU time 3.71 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:08 PM PDT 24
Peak memory 209692 kb
Host smart-15dbd420-f234-49bf-a1e2-59c32ed76939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623584521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3623584521
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.397348414
Short name T360
Test name
Test status
Simulation time 95190858 ps
CPU time 4.25 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:08 PM PDT 24
Peak memory 210856 kb
Host smart-02e34abd-3add-470b-9ab2-8ea417655d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397348414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.397348414
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.1371178519
Short name T313
Test name
Test status
Simulation time 821562512 ps
CPU time 20.63 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:23 PM PDT 24
Peak memory 209460 kb
Host smart-42fc5e0c-389a-498a-bbbf-7617200afdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371178519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1371178519
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2026964907
Short name T698
Test name
Test status
Simulation time 58375169 ps
CPU time 3.19 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:07 PM PDT 24
Peak memory 216816 kb
Host smart-b533253b-4705-480c-a35c-7212eb4b0991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026964907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2026964907
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.722371781
Short name T373
Test name
Test status
Simulation time 1363630854 ps
CPU time 9.9 seconds
Started Aug 19 05:40:02 PM PDT 24
Finished Aug 19 05:40:12 PM PDT 24
Peak memory 218668 kb
Host smart-663c39cf-1cf6-4eb7-843d-716f49444095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722371781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.722371781
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3845406476
Short name T250
Test name
Test status
Simulation time 448320811 ps
CPU time 2.61 seconds
Started Aug 19 05:40:02 PM PDT 24
Finished Aug 19 05:40:05 PM PDT 24
Peak memory 209152 kb
Host smart-27aefafb-59f8-4477-b1f2-23b6df7ae216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845406476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3845406476
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.111394238
Short name T621
Test name
Test status
Simulation time 3451460342 ps
CPU time 66.1 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:41:10 PM PDT 24
Peak memory 209156 kb
Host smart-93429003-a4a4-4323-b221-ac9f56c1c7d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111394238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.111394238
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3026249409
Short name T548
Test name
Test status
Simulation time 6616542887 ps
CPU time 27.89 seconds
Started Aug 19 05:40:01 PM PDT 24
Finished Aug 19 05:40:29 PM PDT 24
Peak memory 209532 kb
Host smart-7ec13fbc-ce98-4ebf-be2f-7862c5a45308
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026249409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3026249409
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1702712759
Short name T678
Test name
Test status
Simulation time 1210776013 ps
CPU time 7.38 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:11 PM PDT 24
Peak memory 209384 kb
Host smart-f9a72c0a-201a-46bf-8bb5-5b5327e3e785
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702712759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1702712759
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1775731496
Short name T901
Test name
Test status
Simulation time 78386631 ps
CPU time 3.92 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:08 PM PDT 24
Peak memory 209392 kb
Host smart-85703c5e-1fd6-488d-9b7d-39930d65f164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775731496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1775731496
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3464346907
Short name T535
Test name
Test status
Simulation time 207182408 ps
CPU time 4.59 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:09 PM PDT 24
Peak memory 207392 kb
Host smart-2c23e22f-fbdb-48b9-8709-f29fcb986703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464346907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3464346907
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1563126823
Short name T402
Test name
Test status
Simulation time 167642352 ps
CPU time 2.26 seconds
Started Aug 19 05:40:05 PM PDT 24
Finished Aug 19 05:40:08 PM PDT 24
Peak memory 222916 kb
Host smart-5e097829-80e7-49aa-8ef6-02e8d4dd1c7d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563126823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1563126823
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3581579913
Short name T215
Test name
Test status
Simulation time 103538475 ps
CPU time 7.1 seconds
Started Aug 19 05:40:06 PM PDT 24
Finished Aug 19 05:40:13 PM PDT 24
Peak memory 223004 kb
Host smart-9b1bfd38-757e-4238-9684-be1f5d986106
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581579913 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3581579913
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2048595837
Short name T633
Test name
Test status
Simulation time 187703880 ps
CPU time 4.62 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:08 PM PDT 24
Peak memory 207660 kb
Host smart-f8c63d76-32fb-4e4d-ae47-77fc1a86eca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048595837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2048595837
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3018436833
Short name T117
Test name
Test status
Simulation time 145795330 ps
CPU time 2.64 seconds
Started Aug 19 05:40:05 PM PDT 24
Finished Aug 19 05:40:08 PM PDT 24
Peak memory 210404 kb
Host smart-a6ab8b2b-8a5f-4faa-a46b-3acb4a942d34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018436833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3018436833
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1185594735
Short name T912
Test name
Test status
Simulation time 203190230 ps
CPU time 0.95 seconds
Started Aug 19 05:40:15 PM PDT 24
Finished Aug 19 05:40:16 PM PDT 24
Peak memory 206552 kb
Host smart-4c52cb6f-1657-4784-b17f-e66aba95c892
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185594735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1185594735
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.1428186502
Short name T293
Test name
Test status
Simulation time 38935616 ps
CPU time 2.13 seconds
Started Aug 19 05:40:03 PM PDT 24
Finished Aug 19 05:40:05 PM PDT 24
Peak memory 210152 kb
Host smart-c4266969-990b-4798-bb4c-882a8739ce80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1428186502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.1428186502
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1283400997
Short name T45
Test name
Test status
Simulation time 156795026 ps
CPU time 3.97 seconds
Started Aug 19 05:40:15 PM PDT 24
Finished Aug 19 05:40:19 PM PDT 24
Peak memory 209412 kb
Host smart-de0dd88e-fa58-4c0b-a4da-ffb578426159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283400997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1283400997
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2928678782
Short name T255
Test name
Test status
Simulation time 139202540 ps
CPU time 3.79 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:40:17 PM PDT 24
Peak memory 214716 kb
Host smart-6022b240-f545-424f-8d0a-f3a54af83134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928678782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2928678782
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2443174559
Short name T493
Test name
Test status
Simulation time 984089628 ps
CPU time 4.62 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:09 PM PDT 24
Peak memory 220876 kb
Host smart-04721e13-0c5f-48fc-a34b-015ded88a8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443174559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2443174559
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.4208736068
Short name T375
Test name
Test status
Simulation time 393088396 ps
CPU time 4.71 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:09 PM PDT 24
Peak memory 218756 kb
Host smart-b9a34e5a-5c4e-4e7f-944d-0bf060f15661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208736068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.4208736068
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.700583267
Short name T460
Test name
Test status
Simulation time 167576581 ps
CPU time 4.71 seconds
Started Aug 19 05:40:05 PM PDT 24
Finished Aug 19 05:40:10 PM PDT 24
Peak memory 208616 kb
Host smart-c2624ec9-9ea9-4ce5-b74e-07ebaacc1f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700583267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.700583267
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.2270413726
Short name T905
Test name
Test status
Simulation time 23080749 ps
CPU time 1.85 seconds
Started Aug 19 05:40:05 PM PDT 24
Finished Aug 19 05:40:07 PM PDT 24
Peak memory 207460 kb
Host smart-cdf96bd4-28d4-4486-b840-3d6e4e526508
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270413726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.2270413726
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1182926952
Short name T641
Test name
Test status
Simulation time 288190199 ps
CPU time 3.81 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:08 PM PDT 24
Peak memory 207456 kb
Host smart-43d4303b-e61f-47c3-b3a5-2e398f799b98
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182926952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1182926952
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.225016582
Short name T837
Test name
Test status
Simulation time 3348815278 ps
CPU time 24.15 seconds
Started Aug 19 05:40:04 PM PDT 24
Finished Aug 19 05:40:29 PM PDT 24
Peak memory 208728 kb
Host smart-1c914b3a-c723-40b1-87f0-997df52bab9b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225016582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.225016582
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.1456010137
Short name T568
Test name
Test status
Simulation time 376520871 ps
CPU time 3.25 seconds
Started Aug 19 05:40:15 PM PDT 24
Finished Aug 19 05:40:19 PM PDT 24
Peak memory 208356 kb
Host smart-6967e6fe-b12f-4771-8aab-213faa213fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456010137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.1456010137
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1677737257
Short name T454
Test name
Test status
Simulation time 312488752 ps
CPU time 3.46 seconds
Started Aug 19 05:40:06 PM PDT 24
Finished Aug 19 05:40:09 PM PDT 24
Peak memory 209308 kb
Host smart-97127558-be3e-4c3d-9574-1d5dc5c8f456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677737257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1677737257
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.752693911
Short name T609
Test name
Test status
Simulation time 1485240799 ps
CPU time 30.23 seconds
Started Aug 19 05:40:14 PM PDT 24
Finished Aug 19 05:40:44 PM PDT 24
Peak memory 217636 kb
Host smart-3cd3e8ab-6030-4d02-8867-4904a3d8ca92
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752693911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.752693911
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2892524650
Short name T916
Test name
Test status
Simulation time 888879321 ps
CPU time 6.87 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:40:20 PM PDT 24
Peak memory 209120 kb
Host smart-74757996-afb6-4c4f-a0df-7dc5a8774948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892524650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2892524650
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3378874681
Short name T161
Test name
Test status
Simulation time 93175899 ps
CPU time 1.93 seconds
Started Aug 19 05:40:18 PM PDT 24
Finished Aug 19 05:40:21 PM PDT 24
Peak memory 210220 kb
Host smart-ff4be1a0-ad33-4021-9ad3-9581e0f3b102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378874681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3378874681
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2852395233
Short name T434
Test name
Test status
Simulation time 15761436 ps
CPU time 0.99 seconds
Started Aug 19 05:40:16 PM PDT 24
Finished Aug 19 05:40:17 PM PDT 24
Peak memory 206580 kb
Host smart-d4c9aa7a-d0ed-49e5-8250-37cde9da61cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852395233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2852395233
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3187108119
Short name T423
Test name
Test status
Simulation time 156386814 ps
CPU time 3.35 seconds
Started Aug 19 05:40:17 PM PDT 24
Finished Aug 19 05:40:21 PM PDT 24
Peak memory 215856 kb
Host smart-08914d5f-ae2f-41fe-9288-078fa53cad6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3187108119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3187108119
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2438566360
Short name T201
Test name
Test status
Simulation time 116710070 ps
CPU time 6.03 seconds
Started Aug 19 05:40:16 PM PDT 24
Finished Aug 19 05:40:22 PM PDT 24
Peak memory 210184 kb
Host smart-fc9f8e9a-c4bd-4f46-a136-b18c7bd6131c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438566360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2438566360
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.4237940491
Short name T635
Test name
Test status
Simulation time 92054826 ps
CPU time 3.77 seconds
Started Aug 19 05:40:14 PM PDT 24
Finished Aug 19 05:40:17 PM PDT 24
Peak memory 219308 kb
Host smart-5969109e-cc97-4564-962e-40d8a53a22bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237940491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.4237940491
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.362813309
Short name T610
Test name
Test status
Simulation time 1765244233 ps
CPU time 12.94 seconds
Started Aug 19 05:40:17 PM PDT 24
Finished Aug 19 05:40:30 PM PDT 24
Peak memory 214832 kb
Host smart-ede875b0-de7d-49ba-a327-3a956cd9d211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362813309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.362813309
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3057481965
Short name T337
Test name
Test status
Simulation time 497125618 ps
CPU time 3.1 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:40:16 PM PDT 24
Peak memory 221448 kb
Host smart-76c35247-8717-4551-9ce0-f35d7edce863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057481965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3057481965
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4230666512
Short name T776
Test name
Test status
Simulation time 919059681 ps
CPU time 13.78 seconds
Started Aug 19 05:40:14 PM PDT 24
Finished Aug 19 05:40:28 PM PDT 24
Peak memory 222924 kb
Host smart-48d73096-8abb-4dc6-876a-68c1c47a6e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230666512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4230666512
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2423570332
Short name T222
Test name
Test status
Simulation time 468177392 ps
CPU time 4.22 seconds
Started Aug 19 05:40:16 PM PDT 24
Finished Aug 19 05:40:21 PM PDT 24
Peak memory 209936 kb
Host smart-d68007b7-eb6e-4397-8504-1ca1546934db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423570332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2423570332
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.769886153
Short name T345
Test name
Test status
Simulation time 1162425078 ps
CPU time 27.39 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:40:40 PM PDT 24
Peak memory 208948 kb
Host smart-aa773c48-96ac-4c71-a9b7-075577a4e230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769886153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.769886153
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1539174044
Short name T187
Test name
Test status
Simulation time 64167470 ps
CPU time 3.11 seconds
Started Aug 19 05:40:14 PM PDT 24
Finished Aug 19 05:40:17 PM PDT 24
Peak memory 207332 kb
Host smart-1f488ae0-cae4-4a5b-99aa-3a16282e4aa9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539174044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1539174044
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.1882195951
Short name T438
Test name
Test status
Simulation time 1466813936 ps
CPU time 25.17 seconds
Started Aug 19 05:40:16 PM PDT 24
Finished Aug 19 05:40:41 PM PDT 24
Peak memory 208740 kb
Host smart-b09e17e6-d564-4352-9032-ec2f40c9ed64
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882195951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.1882195951
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.905246405
Short name T476
Test name
Test status
Simulation time 449955835 ps
CPU time 4.86 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:40:18 PM PDT 24
Peak memory 208996 kb
Host smart-ee8f7aea-4e3e-4d18-8e16-d495b99d7ee2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905246405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.905246405
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1625531678
Short name T601
Test name
Test status
Simulation time 94705625 ps
CPU time 2.48 seconds
Started Aug 19 05:40:12 PM PDT 24
Finished Aug 19 05:40:15 PM PDT 24
Peak memory 208408 kb
Host smart-43aad52c-04e0-4896-9ab1-16a33d47400f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625531678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1625531678
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1640949981
Short name T858
Test name
Test status
Simulation time 153052058 ps
CPU time 4.25 seconds
Started Aug 19 05:40:14 PM PDT 24
Finished Aug 19 05:40:18 PM PDT 24
Peak memory 208972 kb
Host smart-55590fc7-96af-4688-849a-f6fa8b3cfd5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640949981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1640949981
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2745157350
Short name T884
Test name
Test status
Simulation time 171642605 ps
CPU time 6.1 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:40:19 PM PDT 24
Peak memory 209612 kb
Host smart-f50423da-dc7a-451b-a1e0-8a1256b5e132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745157350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2745157350
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1551989386
Short name T16
Test name
Test status
Simulation time 11392499 ps
CPU time 0.9 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:40:14 PM PDT 24
Peak memory 206428 kb
Host smart-c8ea939a-065a-4212-80a8-b43cd1dab5dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551989386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1551989386
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3259880112
Short name T62
Test name
Test status
Simulation time 29186692 ps
CPU time 2.38 seconds
Started Aug 19 05:40:18 PM PDT 24
Finished Aug 19 05:40:20 PM PDT 24
Peak memory 214816 kb
Host smart-be0de7ec-69a2-4ab4-9dfc-c51341323c1d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3259880112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3259880112
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3295076833
Short name T26
Test name
Test status
Simulation time 73649947 ps
CPU time 3.7 seconds
Started Aug 19 05:40:16 PM PDT 24
Finished Aug 19 05:40:20 PM PDT 24
Peak memory 209800 kb
Host smart-34a9c09b-77d8-4d07-a17d-d101ebc9c81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295076833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3295076833
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2813306275
Short name T599
Test name
Test status
Simulation time 59441960 ps
CPU time 2.67 seconds
Started Aug 19 05:40:15 PM PDT 24
Finished Aug 19 05:40:18 PM PDT 24
Peak memory 218728 kb
Host smart-ba2e298d-4b83-4703-9b49-e508f8c4e186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813306275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2813306275
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3421363581
Short name T21
Test name
Test status
Simulation time 116598885 ps
CPU time 5.22 seconds
Started Aug 19 05:40:17 PM PDT 24
Finished Aug 19 05:40:22 PM PDT 24
Peak memory 221764 kb
Host smart-61c95125-5349-4ff2-ae5c-ecb5f26dfcac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421363581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3421363581
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.129705644
Short name T748
Test name
Test status
Simulation time 161628767 ps
CPU time 2.86 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:40:16 PM PDT 24
Peak memory 214756 kb
Host smart-336129f6-5e03-426f-8025-e4da828da26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129705644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.129705644
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.4147658046
Short name T894
Test name
Test status
Simulation time 142163760 ps
CPU time 1.64 seconds
Started Aug 19 05:40:16 PM PDT 24
Finished Aug 19 05:40:17 PM PDT 24
Peak memory 206568 kb
Host smart-34cfa302-a5ae-4d0b-b30d-50c3a2d55c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147658046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.4147658046
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2383404659
Short name T753
Test name
Test status
Simulation time 623040383 ps
CPU time 17.41 seconds
Started Aug 19 05:40:20 PM PDT 24
Finished Aug 19 05:40:38 PM PDT 24
Peak memory 209788 kb
Host smart-b5ecaa8d-acf0-4827-917c-f8dc5aa5170b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383404659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2383404659
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.267714138
Short name T137
Test name
Test status
Simulation time 229924973 ps
CPU time 6.11 seconds
Started Aug 19 05:40:15 PM PDT 24
Finished Aug 19 05:40:21 PM PDT 24
Peak memory 209068 kb
Host smart-d3843b97-b727-4d65-9a27-8762bf30b1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267714138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.267714138
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1529538740
Short name T739
Test name
Test status
Simulation time 384222033 ps
CPU time 2.8 seconds
Started Aug 19 05:40:15 PM PDT 24
Finished Aug 19 05:40:18 PM PDT 24
Peak memory 209388 kb
Host smart-c0aa858d-b6f8-4bd8-8f6f-f547a6de5770
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529538740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1529538740
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2036107288
Short name T12
Test name
Test status
Simulation time 147449303 ps
CPU time 4.11 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:40:18 PM PDT 24
Peak memory 208724 kb
Host smart-2658ac45-3f48-4cb2-9a39-b3cd59f108f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036107288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2036107288
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1755116776
Short name T570
Test name
Test status
Simulation time 19569896 ps
CPU time 1.84 seconds
Started Aug 19 05:40:15 PM PDT 24
Finished Aug 19 05:40:17 PM PDT 24
Peak memory 207272 kb
Host smart-5002c00f-e311-4ef9-9316-3c48cbefdd7c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755116776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1755116776
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3910609684
Short name T656
Test name
Test status
Simulation time 1334432501 ps
CPU time 2.63 seconds
Started Aug 19 05:40:14 PM PDT 24
Finished Aug 19 05:40:17 PM PDT 24
Peak memory 209532 kb
Host smart-677678d6-88cb-4e30-b0d5-a6e053ec620d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910609684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3910609684
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2867706186
Short name T815
Test name
Test status
Simulation time 242198098 ps
CPU time 2.57 seconds
Started Aug 19 05:40:14 PM PDT 24
Finished Aug 19 05:40:17 PM PDT 24
Peak memory 209112 kb
Host smart-6fb0981c-a462-480a-8dbf-6c8204215be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867706186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2867706186
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2648765465
Short name T329
Test name
Test status
Simulation time 493284657 ps
CPU time 13.54 seconds
Started Aug 19 05:40:16 PM PDT 24
Finished Aug 19 05:40:30 PM PDT 24
Peak memory 223104 kb
Host smart-79cb1e71-550f-4e24-a161-0a3bc581bc49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648765465 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2648765465
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3023436167
Short name T291
Test name
Test status
Simulation time 333306313 ps
CPU time 6.34 seconds
Started Aug 19 05:40:13 PM PDT 24
Finished Aug 19 05:40:20 PM PDT 24
Peak memory 208456 kb
Host smart-ab2b9f92-5f51-4405-a268-59b276531a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023436167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3023436167
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1142896433
Short name T160
Test name
Test status
Simulation time 186825889 ps
CPU time 2.5 seconds
Started Aug 19 05:40:15 PM PDT 24
Finished Aug 19 05:40:17 PM PDT 24
Peak memory 210400 kb
Host smart-647482bc-aa24-49b4-9ba7-72c78a742aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142896433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1142896433
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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