Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
76.19	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	14	35	71.43

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	13	22	62.86	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	52	1			T18	1		T123	1		T69	1
auto[OpGenId]	13	1			T32	1		T226	1		T227	1
auto[OpGenSwOut]	26	1			T64	1		T9	2		T228	1
auto[OpGenHwOut]	14	1			T7	1		T8	1		T9	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1607	1			T18	1		T12	90		T68	2
auto[StInit]	94	1			T64	1		T68	1		T78	1
auto[StCreatorRootKey]	58	1			T41	1		T68	1		T24	1
auto[StOwnerIntKey]	43	1			T21	1		T45	1		T25	1
auto[StOwnerKey]	39	1			T22	1		T116	1		T65	1
auto[StDisabled]	430	1			T17	1		T68	1		T7	1
auto[StInvalid]	49	1			T6	1		T40	1		T70	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3297

1

T1

1

T2

1

T3

1

auto[1]

105

1

T18

1

T64

1

T7

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1599	1			T12	90		T68	2		T13	180
auto[StReset]	auto[1]	8	1			T18	1		T123	1		T124	1
auto[StInit]	auto[0]	50	1			T68	1		T78	1		T8	1
auto[StInit]	auto[1]	44	1			T64	1		T8	1		T35	1
auto[StCreatorRootKey]	auto[0]	41	1			T41	1		T68	1		T24	1
auto[StCreatorRootKey]	auto[1]	17	1			T32	1		T126	1		T34	1
auto[StOwnerIntKey]	auto[0]	33	1			T21	1		T45	1		T25	1
auto[StOwnerIntKey]	auto[1]	10	1			T44	1		T229	1		T230	1
auto[StOwnerKey]	auto[0]	26	1			T22	1		T116	1		T65	1
auto[StOwnerKey]	auto[1]	13	1			T129	1		T130	1		T231	1
auto[StDisabled]	auto[0]	417	1			T17	1		T68	1		T69	11
auto[StDisabled]	auto[1]	13	1			T7	1		T69	1		T9	3
auto[StInvalid]	auto[0]	49	1			T6	1		T40	1		T70	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	13	22	62.86	13

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut]]	--	--	2
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	5

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	7	1			T18	1		T123	1		T124	1
auto[StReset]	auto[OpGenHwOut]	1	1			T10	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	24	1			T35	1		T232	1		T233	1
auto[StInit]	auto[OpGenId]	3	1			T234	1		T235	1		T236	1
auto[StInit]	auto[OpGenSwOut]	13	1			T64	1		T228	1		T108	1
auto[StInit]	auto[OpGenHwOut]	4	1			T8	1		T221	1		T127	1
auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T126	1		T127	1		T237	1
auto[StCreatorRootKey]	auto[OpGenId]	4	1			T32	1		T226	1		T238	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T127	1		T239	1		T240	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	1	1			T34	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T44	1		T181	1		T241	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T227	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	3	1			T229	1		T230	1		T242	1
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T243	2		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	5	1			T129	1		T130	1		T244	1
auto[StOwnerKey]	auto[OpGenId]	4	1			T245	1		T246	1		T247	1
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T231	1		T248	1		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T249	1		T250	1		-	-
auto[StDisabled]	auto[OpAdvance]	5	1			T69	1		T251	1		T250	1
auto[StDisabled]	auto[OpGenId]	1	1			T252	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	3	1			T9	2		T253	1		-	-
auto[StDisabled]	auto[OpGenHwOut]	4	1			T7	1		T9	1		T254	1