Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4722

1

T1

8

T2

5

T4

11

auto[1]

565

1

T15

5

T47

1

T48

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4722

1

T1

8

T2

5

T4

11

auto[1]

565

1

T15

5

T47

1

T48

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4777

1

T1

4

T2

5

T4

11

auto[1]

510

1

T1

4

T17

1

T39

4

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4777

1

T1

4

T2

5

T4

11

auto[1]

510

1

T1

4

T17

1

T39

4

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	443	1			T16	1		T6	1		T17	2
auto[OpGenId]	1097	1			T2	3		T17	1		T100	1
auto[OpGenSwOut]	1129	1			T16	1		T17	4		T38	5
auto[OpGenHwOut]	2559	1			T1	8		T2	2		T4	11
auto[OpDisable]	59	1			T100	1		T95	1		T69	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	443	1			T16	1		T6	1		T17	2
auto[OpGenId]	1097	1			T2	3		T17	1		T100	1
auto[OpGenSwOut]	1129	1			T16	1		T17	4		T38	5
auto[OpGenHwOut]	2559	1			T1	8		T2	2		T4	11
auto[OpDisable]	59	1			T100	1		T95	1		T69	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4717

1

T1

8

T2

5

T4

6

auto[1]

570

1

T4

5

T17

3

T19

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4717

1

T1

8

T2

5

T4

6

auto[1]

570

1

T4

5

T17

3

T19

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5000

1

T1

8

T2

5

T4

11

auto[1]

287

1

T77

1

T83

11

T103

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1858	1			T1	3		T2	2		T4	4
auto[1]	728	1			T4	1		T15	1		T6	1
auto[2]	677	1			T1	2		T2	1		T4	2
auto[3]	665	1			T1	2		T2	1		T16	1
auto[4]	358	1			T4	1		T16	1		T17	2
auto[5]	337	1			T4	1		T15	2		T39	1
auto[6]	340	1			T2	1		T19	1		T48	1
auto[7]	324	1			T1	1		T4	2		T15	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1359	1			T1	1		T2	1		T4	4
clear_one[1]	728	1			T4	1		T15	1		T6	1
clear_one[2]	677	1			T1	2		T2	1		T4	2
clear_one[3]	665	1			T1	2		T2	1		T16	1
clear_none	1858	1			T1	3		T2	2		T4	4

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	937	1			T4	3		T15	5		T16	2
auto[StInit]	645	1			T1	1		T2	1		T4	1
auto[StCreatorRootKey]	561	1			T1	1		T4	1		T15	1
auto[StOwnerIntKey]	518	1			T1	1		T2	1		T4	1
auto[StOwnerKey]	492	1			T1	1		T4	1		T15	1
auto[StDisabled]	1850	1			T1	4		T2	3		T4	4
auto[StInvalid]	284	1			T16	2		T6	1		T40	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	937	1			T4	3		T15	5		T16	2
auto[StInit]	645	1			T1	1		T2	1		T4	1
auto[StCreatorRootKey]	561	1			T1	1		T4	1		T15	1
auto[StOwnerIntKey]	518	1			T1	1		T2	1		T4	1
auto[StOwnerKey]	492	1			T1	1		T4	1		T15	1
auto[StDisabled]	1850	1			T1	4		T2	3		T4	4
auto[StInvalid]	284	1			T16	2		T6	1		T40	2

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[1] - auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[1] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	6	1			T255	1		T256	1		T257	1
auto[0]	auto[StReset]	auto[OpGenId]	136	1			T23	1		T217	1		T212	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	159	1			T16	1		T17	1		T19	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	238	1			T4	1		T15	2		T38	1
auto[0]	auto[StInit]	auto[OpAdvance]	46	1			T218	1		T222	1		T8	1
auto[0]	auto[StInit]	auto[OpGenId]	95	1			T2	1		T17	1		T73	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	72	1			T24	1		T219	1		T69	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	218	1			T1	1		T4	1		T15	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	23	1			T83	1		T7	1		T104	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	53	1			T77	1		T116	1		T69	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	58	1			T25	1		T104	1		T71	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	85	1			T1	1		T15	1		T22	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	17	1			T6	1		T103	1		T258	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	32	1			T83	1		T222	1		T8	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	31	1			T38	1		T142	1		T69	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	56	1			T2	1		T39	1		T259	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T83	1		T105	1		T130	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	19	1			T83	1		T104	2		T195	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	24	1			T260	1		T261	1		T262	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	60	1			T39	1		T47	1		T83	4
auto[0]	auto[StDisabled]	auto[OpAdvance]	24	1			T105	1		T106	1		T118	1
auto[0]	auto[StDisabled]	auto[OpGenId]	69	1			T95	1		T83	1		T207	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	70	1			T17	1		T23	1		T77	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T1	1		T4	2		T15	3
auto[0]	auto[StDisabled]	auto[OpDisable]	13	1			T69	1		T90	1		T130	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	16	1			T16	1		T120	1		T263	1
auto[0]	auto[StInvalid]	auto[OpGenId]	16	1			T196	1		T125	1		T264	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	25	1			T70	1		T117	1		T196	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	24	1			T40	1		T70	1		T52	1
auto[1]	auto[StReset]	auto[OpGenId]	17	1			T100	1		T69	1		T8	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	18	1			T69	1		T265	1		T266	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	51	1			T105	1		T267	1		T268	1
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T269	1		T270	1		T271	1
auto[1]	auto[StInit]	auto[OpGenId]	8	1			T20	1		T221	1		T272	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	6	1			T244	1		T234	1		T273	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	18	1			T31	1		T29	1		T71	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T274	1		T275	1		T276	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T108	1		T277	1		T278	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T9	1		T279	1		T280	2
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T17	1		T100	1		T20	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	15	1			T215	1		T105	1		T281	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T108	1		T127	1		T130	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T282	1		T283	1		T284	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T4	1		T211	1		T30	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T285	1		T184	1		T60	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	13	1			T8	1		T108	1		T91	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T17	1		T130	2		T201	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T48	1		T96	1		T205	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	22	1			T69	1		T286	1		T287	1
auto[1]	auto[StDisabled]	auto[OpGenId]	65	1			T96	1		T69	1		T194	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T47	1		T74	1		T76	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	169	1			T15	1		T48	1		T75	1
auto[1]	auto[StDisabled]	auto[OpDisable]	15	1			T71	1		T209	1		T134	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	3	1			T120	1		T288	1		T289	1
auto[1]	auto[StInvalid]	auto[OpGenId]	10	1			T290	1		T50	1		T266	2
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	16	1			T52	1		T291	1		T292	2
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T6	1		T50	1		T266	1
auto[2]	auto[StReset]	auto[OpGenId]	18	1			T293	2		T89	1		T251	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	20	1			T38	1		T100	1		T42	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	39	1			T15	1		T217	1		T214	1
auto[2]	auto[StInit]	auto[OpAdvance]	5	1			T106	1		T61	1		T294	1
auto[2]	auto[StInit]	auto[OpGenId]	7	1			T29	1		T127	1		T295	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	13	1			T100	1		T29	1		T69	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	20	1			T20	1		T214	1		T30	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	10	1			T281	1		T37	1		T296	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T297	1		T298	1		T299	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T209	1		T106	1		T118	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T4	1		T48	1		T101	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T300	1		T280	1		T301	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	18	1			T302	1		T303	1		T304	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T217	1		T212	1		T71	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T101	1		T214	1		T143	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T287	1		T118	1		T305	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	20	1			T306	1		T307	1		T265	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T217	1		T304	1		T301	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T1	1		T4	1		T15	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	25	1			T17	1		T103	1		T8	1
auto[2]	auto[StDisabled]	auto[OpGenId]	55	1			T2	1		T103	1		T215	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	53	1			T69	2		T30	1		T118	2
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	155	1			T1	1		T39	1		T214	2
auto[2]	auto[StDisabled]	auto[OpDisable]	9	1			T71	1		T79	1		T308	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	7	1			T196	1		T291	1		T53	1
auto[2]	auto[StInvalid]	auto[OpGenId]	11	1			T117	1		T51	1		T309	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T70	1		T120	1		T49	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T51	1		T288	1		T292	1
auto[3]	auto[StReset]	auto[OpAdvance]	2	1			T106	1		T310	1		-	-
auto[3]	auto[StReset]	auto[OpGenId]	17	1			T108	1		T37	1		T201	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	20	1			T122	1		T69	1		T9	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	31	1			T16	1		T214	1		T69	1
auto[3]	auto[StInit]	auto[OpAdvance]	10	1			T120	1		T9	1		T270	1
auto[3]	auto[StInit]	auto[OpGenId]	5	1			T311	1		T296	1		T312	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	12	1			T106	2		T89	1		T313	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	19	1			T145	1		T197	1		T198	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T221	1		T44	1		T310	2
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T8	1		T270	1		T201	2
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T261	1		T314	1		T315	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T145	1		T316	1		T281	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T118	1		T270	1		T58	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T221	1		T317	1		T318	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T69	2		T8	1		T99	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T1	1		T195	1		T79	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T23	1		T303	1		T108	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	22	1			T69	1		T302	1		T270	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	22	1			T38	1		T31	1		T7	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T211	1		T259	1		T69	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	30	1			T142	1		T105	1		T319	2
auto[3]	auto[StDisabled]	auto[OpGenId]	52	1			T218	1		T207	1		T8	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T8	1		T105	3		T9	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	141	1			T1	1		T2	1		T39	1
auto[3]	auto[StDisabled]	auto[OpDisable]	3	1			T201	1		T140	1		T320	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	5	1			T40	1		T321	1		T322	1
auto[3]	auto[StInvalid]	auto[OpGenId]	9	1			T120	1		T264	1		T323	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T49	1		T50	1		T324	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T196	1		T51	1		T50	1
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T131	1		T234	2		T325	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	10	1			T284	1		T108	1		T127	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	24	1			T4	1		T214	1		T69	2
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T256	1		T326	1		T252	1
auto[4]	auto[StInit]	auto[OpGenId]	6	1			T29	1		T108	1		T314	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	3	1			T327	1		T245	1		T328	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T211	1		T69	1		T329	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T330	1		T256	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T130	1		T331	1		T332	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T333	1		T127	1		T334	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T205	1		T282	1		T335	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T17	1		T336	1		T254	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T77	1		T107	1		T221	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T209	1		T336	1		T99	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T205	1		T337	1		T338	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	10	1			T107	1		T201	1		T339	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T69	1		T206	1		T269	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T222	1		T8	1		T340	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	20	1			T69	1		T286	1		T341	1
auto[4]	auto[StDisabled]	auto[OpGenId]	29	1			T83	1		T103	1		T220	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	37	1			T17	1		T38	1		T134	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	73	1			T75	1		T268	2		T107	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T342	1		T130	1		T234	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	5	1			T309	1		T343	1		T288	1
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T264	1		T344	1		T345	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T263	1		T346	1		T347	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T16	1		T70	1		T323	1
auto[5]	auto[StReset]	auto[OpGenId]	11	1			T36	1		T295	1		T348	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	6	1			T22	1		T53	1		T301	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	27	1			T4	1		T15	1		T48	1
auto[5]	auto[StInit]	auto[OpAdvance]	5	1			T107	1		T127	1		T130	1
auto[5]	auto[StInit]	auto[OpGenId]	5	1			T282	1		T349	1		T230	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T143	1		T342	1		T201	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	9	1			T48	1		T316	1		T350	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T71	1		T261	1		T351	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T23	1		T107	1		T126	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	3	1			T352	1		T353	1		T354	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T95	1		T69	1		T210	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T131	1		-	-		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	2	1			T261	1		T130	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T74	1		T69	1		T306	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T15	1		T75	1		T267	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T286	1		T355	1		T356	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	3	1			T357	1		T252	1		T190	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T301	1		T358	1		T204	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	16	1			T198	1		T118	1		T359	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	10	1			T31	1		T69	1		T91	1
auto[5]	auto[StDisabled]	auto[OpGenId]	32	1			T74	1		T218	1		T118	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T220	1		T302	1		T360	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T39	1		T214	1		T145	1
auto[5]	auto[StDisabled]	auto[OpDisable]	5	1			T108	1		T361	1		T139	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	4	1			T362	1		T363	1		T364	1
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T117	1		T263	1		T365	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T53	1		T346	1		T366	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T49	1		T292	1		T367	1
auto[6]	auto[StReset]	auto[OpGenId]	4	1			T231	1		T330	1		T368	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	7	1			T108	1		T369	1		T370	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	27	1			T116	1		T211	1		T8	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T35	1		T361	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	2	1			T308	1		T371	1		-	-
auto[6]	auto[StInit]	auto[OpGenSwOut]	6	1			T174	1		T201	1		T372	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	14	1			T373	1		T287	1		T369	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T374	1		T294	2		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T73	1		T327	1		T375	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T212	1		T142	1		T293	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T79	1		T9	1		T376	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T296	1		T377	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T378	1		T342	1		T379	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T218	1		T71	1		T9	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T48	1		T316	1		T350	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T89	1		T285	1		-	-
auto[6]	auto[StOwnerKey]	auto[OpGenId]	6	1			T55	1		T202	1		T380	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T381	1		T130	1		T382	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T335	1		T383	1		T384	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	15	1			T77	1		T69	1		T105	2
auto[6]	auto[StDisabled]	auto[OpGenId]	32	1			T2	1		T103	1		T69	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T19	1		T23	1		T77	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	66	1			T101	1		T75	1		T103	1
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T100	1		T135	1		T356	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	5	1			T120	1		T49	1		T309	1
auto[6]	auto[StInvalid]	auto[OpGenId]	10	1			T70	1		T196	1		T50	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T385	1		T386	1		T387	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T51	1		T290	1		T263	1
auto[7]	auto[StReset]	auto[OpGenId]	10	1			T120	1		T51	1		T9	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	9	1			T8	1		T174	1		T388	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T15	1		T211	1		T90	1
auto[7]	auto[StInit]	auto[OpAdvance]	2	1			T389	1		T390	1		-	-
auto[7]	auto[StInit]	auto[OpGenId]	2	1			T391	1		T59	1		-	-
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T217	1		T293	1		T230	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	12	1			T38	1		T42	1		T383	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T234	1		T371	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T269	1		T227	1		T392	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T69	1		T134	1		T137	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	14	1			T39	1		T215	1		T393	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T394	1		T380	1		T395	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T135	1		T108	1		T300	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T202	1		T396	1		T315	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T335	1		T383	1		T397	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T341	1		T296	1		T254	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	6	1			T71	1		T398	1		T245	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T9	1		T308	1		T137	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T145	1		T208	1		T268	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	8	1			T333	1		T127	1		T270	1
auto[7]	auto[StDisabled]	auto[OpGenId]	22	1			T31	1		T71	1		T118	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	33	1			T38	1		T19	1		T83	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	68	1			T1	1		T4	2		T101	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T95	1		T382	1		T371	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T399	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	7	1			T117	1		T53	1		T387	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T291	1		T400	1		T401	2
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T50	1		T362	1		T386	1