Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1359

1

T1

1

T2

1

T4

4

clear_one[1]

auto[0]

auto[0]

auto[0]

436

1

T15

1

T6

1

T48

2

clear_one[1]

auto[0]

auto[0]

auto[1]

142

1

T4

1

T17

1

T47

1

clear_one[1]

auto[0]

auto[1]

auto[0]

108

1

T17

1

T20

1

T76

1

clear_one[1]

auto[0]

auto[1]

auto[1]

42

1

T100

1

T96

1

T194

2

clear_one[2]

auto[0]

auto[0]

auto[0]

418

1

T1

2

T2

1

T15

1

clear_one[2]

auto[0]

auto[0]

auto[1]

115

1

T4

2

T17

1

T101

3

clear_one[2]

auto[1]

auto[0]

auto[0]

115

1

T15

1

T48

1

T217

2

clear_one[2]

auto[1]

auto[0]

auto[1]

29

1

T69

1

T108

1

T402

2

clear_one[3]

auto[0]

auto[0]

auto[0]

392

1

T2

1

T16

1

T38

1

clear_one[3]

auto[0]

auto[1]

auto[0]

114

1

T1

2

T39

1

T23

1

clear_one[3]

auto[1]

auto[0]

auto[0]

120

1

T48

2

T208

1

T8

3

clear_one[3]

auto[1]

auto[1]

auto[0]

39

1

T218

1

T207

1

T258

2

clear_none

auto[0]

auto[0]

auto[0]

1304

1

T1

1

T2

2

T4

2

clear_none

auto[0]

auto[0]

auto[1]

147

1

T4

2

T17

1

T101

1

clear_none

auto[0]

auto[1]

auto[0]

120

1

T1

2

T39

3

T22

1

clear_none

auto[0]

auto[1]

auto[1]

25

1

T19

1

T8

1

T118

1

clear_none

auto[1]

auto[0]

auto[0]

156

1

T15

4

T48

1

T95

1

clear_none

auto[1]

auto[0]

auto[1]

44

1

T47

1

T83

10

T220

1

clear_none

auto[1]

auto[1]

auto[0]

36

1

T23

1

T104

1

T69

2

clear_none

auto[1]

auto[1]

auto[1]

26

1

T96

1

T83

1

T71

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1292	1			T1	1		T2	1		T4	4
clear_all	auto[1]	67	1			T77	1		T103	1		T105	1
clear_one[1]	auto[0]	685	1			T4	1		T15	1		T6	1
clear_one[1]	auto[1]	43	1			T105	3		T281	2		T285	1
clear_one[2]	auto[0]	641	1			T1	2		T2	1		T4	2
clear_one[2]	auto[1]	36	1			T103	1		T106	3		T281	2
clear_one[3]	auto[0]	623	1			T1	2		T2	1		T16	1
clear_one[3]	auto[1]	42	1			T105	4		T106	2		T319	1
clear_none	auto[0]	1759	1			T1	3		T2	2		T4	4
clear_none	auto[1]	99	1			T83	11		T104	4		T105	3