Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

10707

1

T1

5

T4

12

T15

16

auto[Attestation]

7292

1

T1

3

T2

8

T4

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2520	1			T2	2		T16	1		T5	1
auto[Aes]	3248	1			T15	18		T17	1		T38	4
auto[Kmac]	3273	1			T1	8		T2	2		T5	1
auto[Otbn]	3290	1			T4	16		T16	2		T5	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7596	1			T1	8		T2	8		T4	8
auto[OpGenId]	5668	1			T2	4		T16	1		T5	4
auto[OpGenSwOut]	5647	1			T2	2		T16	2		T5	4
auto[OpGenHwOut]	6684	1			T1	8		T2	2		T4	16
auto[OpDisable]	123	1			T100	1		T76	1		T95	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10538

1

T1

8

T2

8

T4

8

auto[OpDoneFail]

15180

1

T1

8

T2

8

T4

16

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	5980	1			T1	1		T2	1		T4	9
auto[StInit]	3677	1			T1	2		T2	2		T4	2
auto[StCreatorRootKey]	3161	1			T1	2		T2	2		T4	2
auto[StOwnerIntKey]	2779	1			T1	2		T2	2		T4	2
auto[StOwnerKey]	2391	1			T1	2		T2	2		T4	2
auto[StDisabled]	7730	1			T1	7		T2	7		T4	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	278	1			T16	1		T17	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	105	1			T22	1		T100	1		T20	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	77	1			T77	1		T31	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	66	1			T22	1		T217	1		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	68	1			T217	2		T42	1		T8	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	224	1			T5	1		T17	1		T38	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	289	1			T19	1		T100	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	106	1			T24	1		T69	1		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	94	1			T38	1		T19	1		T215	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	68	1			T22	1		T77	1		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	51	1			T17	1		T31	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	223	1			T47	2		T100	1		T102	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	302	1			T17	2		T38	1		T21	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	111	1			T6	1		T21	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	85	1			T65	1		T121	2		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	60	1			T21	1		T116	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	57	1			T83	1		T213	1		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	250	1			T68	1		T74	1		T96	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	303	1			T16	1		T17	1		T21	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	108	1			T5	1		T21	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	96	1			T31	1		T95	1		T219	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	73	1			T77	1		T116	1		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	51	1			T38	1		T7	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	246	1			T38	1		T19	1		T100	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	42	1			T69	3		T71	1		T8	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	91	1			T6	1		T23	1		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	83	1			T65	1		T215	1		T218	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	77	1			T74	1		T31	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	55	1			T19	1		T7	1		T69	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	198	1			T19	1		T23	1		T102	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	74	1			T69	4		T71	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	97	1			T68	2		T20	1		T217	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	81	1			T25	1		T71	1		T97	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	66	1			T22	1		T20	1		T77	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	55	1			T146	1		T218	1		T69	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	195	1			T31	1		T83	1		T142	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	70	1			T69	3		T71	1		T79	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	96	1			T29	1		T220	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	77	1			T2	1		T77	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T21	1		T20	1		T31	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	57	1			T5	1		T68	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	199	1			T2	1		T17	2		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T69	4		T90	1		T221	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	89	1			T22	1		T95	1		T143	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T21	1		T47	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	68	1			T38	1		T19	2		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	64	1			T95	1		T96	2		T69	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	200	1			T5	1		T19	1		T96	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	254	1			T17	2		T21	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	89	1			T73	1		T20	1		T31	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	76	1			T22	1		T143	1		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	63	1			T95	1		T143	1		T69	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	45	1			T47	2		T96	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	159	1			T47	2		T76	1		T103	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	440	1			T15	10		T38	1		T48	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	109	1			T15	1		T83	1		T122	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	123	1			T15	1		T47	1		T219	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	97	1			T15	1		T48	1		T73	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	90	1			T83	1		T65	1		T143	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	265	1			T15	3		T38	1		T48	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	424	1			T38	3		T21	2		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	123	1			T95	1		T24	1		T45	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	116	1			T21	1		T76	1		T145	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T1	1		T39	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	73	1			T217	1		T143	1		T145	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	259	1			T1	4		T39	3		T77	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	432	1			T4	8		T16	1		T38	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	116	1			T22	1		T101	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T4	1		T47	1		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	110	1			T101	1		T220	1		T69	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	80	1			T101	1		T96	1		T217	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	247	1			T4	3		T101	1		T75	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	39	1			T69	1		T71	1		T8	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	86	1			T6	1		T20	2		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	68	1			T17	1		T100	1		T31	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	76	1			T2	1		T71	1		T9	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	53	1			T83	1		T65	1		T222	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	148	1			T2	1		T76	1		T95	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	50	1			T69	1		T71	1		T8	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	130	1			T38	1		T21	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	97	1			T48	1		T41	1		T219	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	90	1			T73	1		T45	1		T25	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	85	1			T15	1		T48	1		T83	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	273	1			T15	1		T47	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	50	1			T69	1		T71	1		T8	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	123	1			T1	1		T39	1		T20	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	104	1			T1	1		T17	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	108	1			T22	1		T65	1		T122	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	88	1			T1	1		T39	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	275	1			T39	1		T100	1		T23	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	37	1			T71	1		T8	1		T9	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	128	1			T4	1		T6	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	90	1			T100	1		T211	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	98	1			T4	1		T75	1		T77	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	97	1			T4	1		T17	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	296	1			T4	1		T17	1		T19	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	191	1			T22	1		T77	1		T217	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	627	1			T16	1		T5	1		T17	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	201	1			T17	1		T38	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	630	1			T19	1		T47	2		T100	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	184	1			T21	1		T83	1		T116	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	681	1			T6	1		T17	2		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	208	1			T38	1		T77	1		T31	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	669	1			T16	1		T5	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	197	1			T19	1		T74	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	349	1			T6	1		T19	1		T23	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	185	1			T22	1		T77	1		T116	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	383	1			T68	2		T20	2		T31	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	196	1			T2	1		T5	1		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	377	1			T2	1		T17	2		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	205	1			T38	1		T21	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	364	1			T5	1		T19	2		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	171	1			T47	2		T22	1		T95	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	515	1			T17	2		T21	1		T19	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	292	1			T15	2		T47	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	832	1			T15	14		T38	2		T48	7
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	265	1			T1	1		T21	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	822	1			T1	4		T38	3		T21	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	294	1			T4	1		T47	1		T101	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	804	1			T4	11		T16	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	174	1			T2	1		T17	1		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	296	1			T2	1		T6	1		T20	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	269	1			T15	1		T48	2		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	456	1			T15	1		T38	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	285	1			T1	2		T17	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	463	1			T1	1		T39	2		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	273	1			T4	2		T17	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	473	1			T4	2		T6	1		T17	1