Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31781

1

T1

20

T2

21

T4

29

auto[1]

253

1

T77

4

T83

12

T103

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31791	1			T1	20		T2	21		T4	29
auto[134217728:268435455]	11	1			T336	2		T428	1		T429	1
auto[268435456:402653183]	7	1			T83	1		T105	1		T411	1
auto[402653184:536870911]	7	1			T106	1		T261	1		T336	1
auto[536870912:671088639]	8	1			T77	1		T83	1		T311	1
auto[671088640:805306367]	11	1			T83	1		T285	1		T300	1
auto[805306368:939524095]	10	1			T104	1		T281	1		T310	1
auto[939524096:1073741823]	6	1			T105	1		T285	1		T336	1
auto[1073741824:1207959551]	8	1			T77	1		T103	1		T336	1
auto[1207959552:1342177279]	5	1			T83	1		T336	1		T300	1
auto[1342177280:1476395007]	7	1			T104	1		T105	1		T281	1
auto[1476395008:1610612735]	10	1			T83	1		T104	1		T107	1
auto[1610612736:1744830463]	7	1			T107	1		T278	1		T280	1
auto[1744830464:1879048191]	11	1			T83	1		T103	1		T104	1
auto[1879048192:2013265919]	8	1			T83	1		T105	1		T107	1
auto[2013265920:2147483647]	8	1			T77	1		T270	1		T430	1
auto[2147483648:2281701375]	10	1			T83	1		T107	1		T270	1
auto[2281701376:2415919103]	8	1			T336	1		T278	1		T431	2
auto[2415919104:2550136831]	8	1			T336	1		T255	1		T432	1
auto[2550136832:2684354559]	7	1			T104	1		T281	1		T430	1
auto[2684354560:2818572287]	6	1			T255	1		T297	1		T431	1
auto[2818572288:2952790015]	7	1			T105	1		T285	1		T429	1
auto[2952790016:3087007743]	8	1			T106	1		T107	1		T430	1
auto[3087007744:3221225471]	12	1			T83	2		T285	1		T255	1
auto[3221225472:3355443199]	8	1			T83	2		T281	1		T319	1
auto[3355443200:3489660927]	6	1			T104	1		T285	1		T256	1
auto[3489660928:3623878655]	11	1			T281	1		T261	1		T278	1
auto[3623878656:3758096383]	6	1			T300	1		T278	1		T311	1
auto[3758096384:3892314111]	6	1			T77	1		T310	1		T431	1
auto[3892314112:4026531839]	3	1			T285	1		T255	1		T412	1
auto[4026531840:4160749567]	5	1			T294	1		T433	1		T434	1
auto[4160749568:4294967295]	8	1			T285	1		T300	1		T430	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31781	1			T1	20		T2	21		T4	29
auto[0:134217727]	auto[1]	10	1			T105	1		T106	1		T336	1
auto[134217728:268435455]	auto[1]	11	1			T336	2		T428	1		T429	1
auto[268435456:402653183]	auto[1]	7	1			T83	1		T105	1		T411	1
auto[402653184:536870911]	auto[1]	7	1			T106	1		T261	1		T336	1
auto[536870912:671088639]	auto[1]	8	1			T77	1		T83	1		T311	1
auto[671088640:805306367]	auto[1]	11	1			T83	1		T285	1		T300	1
auto[805306368:939524095]	auto[1]	10	1			T104	1		T281	1		T310	1
auto[939524096:1073741823]	auto[1]	6	1			T105	1		T285	1		T336	1
auto[1073741824:1207959551]	auto[1]	8	1			T77	1		T103	1		T336	1
auto[1207959552:1342177279]	auto[1]	5	1			T83	1		T336	1		T300	1
auto[1342177280:1476395007]	auto[1]	7	1			T104	1		T105	1		T281	1
auto[1476395008:1610612735]	auto[1]	10	1			T83	1		T104	1		T107	1
auto[1610612736:1744830463]	auto[1]	7	1			T107	1		T278	1		T280	1
auto[1744830464:1879048191]	auto[1]	11	1			T83	1		T103	1		T104	1
auto[1879048192:2013265919]	auto[1]	8	1			T83	1		T105	1		T107	1
auto[2013265920:2147483647]	auto[1]	8	1			T77	1		T270	1		T430	1
auto[2147483648:2281701375]	auto[1]	10	1			T83	1		T107	1		T270	1
auto[2281701376:2415919103]	auto[1]	8	1			T336	1		T278	1		T431	2
auto[2415919104:2550136831]	auto[1]	8	1			T336	1		T255	1		T432	1
auto[2550136832:2684354559]	auto[1]	7	1			T104	1		T281	1		T430	1
auto[2684354560:2818572287]	auto[1]	6	1			T255	1		T297	1		T431	1
auto[2818572288:2952790015]	auto[1]	7	1			T105	1		T285	1		T429	1
auto[2952790016:3087007743]	auto[1]	8	1			T106	1		T107	1		T430	1
auto[3087007744:3221225471]	auto[1]	12	1			T83	2		T285	1		T255	1
auto[3221225472:3355443199]	auto[1]	8	1			T83	2		T281	1		T319	1
auto[3355443200:3489660927]	auto[1]	6	1			T104	1		T285	1		T256	1
auto[3489660928:3623878655]	auto[1]	11	1			T281	1		T261	1		T278	1
auto[3623878656:3758096383]	auto[1]	6	1			T300	1		T278	1		T311	1
auto[3758096384:3892314111]	auto[1]	6	1			T77	1		T310	1		T431	1
auto[3892314112:4026531839]	auto[1]	3	1			T285	1		T255	1		T412	1
auto[4026531840:4160749567]	auto[1]	5	1			T294	1		T433	1		T434	1
auto[4160749568:4294967295]	auto[1]	8	1			T285	1		T300	1		T430	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1644

1

T16

7

T6

5

T17

1

auto[1]

1738

1

T16

1

T6

1

T17

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	115	1			T6	1		T47	1		T68	1
auto[134217728:268435455]	117	1			T16	1		T6	1		T23	1
auto[268435456:402653183]	100	1			T47	1		T96	1		T104	1
auto[402653184:536870911]	114	1			T100	1		T20	1		T95	1
auto[536870912:671088639]	118	1			T96	1		T103	1		T29	1
auto[671088640:805306367]	122	1			T16	1		T19	1		T100	1
auto[805306368:939524095]	89	1			T17	1		T22	1		T95	1
auto[939524096:1073741823]	93	1			T23	1		T83	1		T142	1
auto[1073741824:1207959551]	114	1			T16	1		T6	1		T64	1
auto[1207959552:1342177279]	96	1			T6	1		T77	1		T103	1
auto[1342177280:1476395007]	115	1			T17	1		T68	1		T95	1
auto[1476395008:1610612735]	113	1			T17	1		T47	1		T23	1
auto[1610612736:1744830463]	108	1			T31	1		T70	1		T7	2
auto[1744830464:1879048191]	100	1			T76	1		T7	1		T142	1
auto[1879048192:2013265919]	115	1			T64	1		T31	1		T83	1
auto[2013265920:2147483647]	105	1			T19	1		T22	1		T103	1
auto[2147483648:2281701375]	92	1			T104	1		T69	7		T71	1
auto[2281701376:2415919103]	89	1			T17	1		T218	1		T8	1
auto[2415919104:2550136831]	104	1			T117	1		T69	3		T71	1
auto[2550136832:2684354559]	96	1			T64	1		T29	1		T123	1
auto[2684354560:2818572287]	119	1			T18	2		T20	1		T96	1
auto[2818572288:2952790015]	89	1			T16	1		T19	1		T47	1
auto[2952790016:3087007743]	115	1			T40	1		T76	1		T103	1
auto[3087007744:3221225471]	110	1			T64	1		T96	1		T116	1
auto[3221225472:3355443199]	102	1			T17	1		T47	1		T40	1
auto[3355443200:3489660927]	103	1			T23	1		T7	1		T142	1
auto[3489660928:3623878655]	93	1			T6	1		T23	1		T215	1
auto[3623878656:3758096383]	109	1			T16	1		T22	1		T73	1
auto[3758096384:3892314111]	99	1			T16	1		T83	1		T70	1
auto[3892314112:4026531839]	117	1			T16	1		T6	1		T7	1
auto[4026531840:4160749567]	97	1			T23	1		T40	1		T68	1
auto[4160749568:4294967295]	114	1			T16	1		T17	1		T18	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	59	1			T47	1		T68	1		T20	1
auto[0:134217727]	auto[1]	56	1			T6	1		T197	1		T309	1
auto[134217728:268435455]	auto[0]	60	1			T16	1		T6	1		T23	1
auto[134217728:268435455]	auto[1]	57	1			T69	1		T71	2		T8	2
auto[268435456:402653183]	auto[0]	42	1			T47	1		T104	1		T71	1
auto[268435456:402653183]	auto[1]	58	1			T96	1		T69	1		T195	1
auto[402653184:536870911]	auto[0]	65	1			T100	1		T20	1		T95	1
auto[402653184:536870911]	auto[1]	49	1			T142	1		T69	3		T71	1
auto[536870912:671088639]	auto[0]	62	1			T96	1		T103	1		T29	1
auto[536870912:671088639]	auto[1]	56	1			T71	1		T192	1		T107	1
auto[671088640:805306367]	auto[0]	54	1			T16	1		T19	1		T100	1
auto[671088640:805306367]	auto[1]	68	1			T219	1		T25	1		T121	1
auto[805306368:939524095]	auto[0]	44	1			T8	1		T105	1		T258	1
auto[805306368:939524095]	auto[1]	45	1			T17	1		T22	1		T95	1
auto[939524096:1073741823]	auto[0]	41	1			T23	1		T83	1		T142	1
auto[939524096:1073741823]	auto[1]	52	1			T104	1		T8	1		T378	1
auto[1073741824:1207959551]	auto[0]	50	1			T16	1		T6	1		T29	1
auto[1073741824:1207959551]	auto[1]	64	1			T64	1		T218	1		T69	1
auto[1207959552:1342177279]	auto[0]	48	1			T6	1		T103	1		T71	1
auto[1207959552:1342177279]	auto[1]	48	1			T77	1		T104	1		T69	1
auto[1342177280:1476395007]	auto[0]	58	1			T68	1		T24	1		T116	1
auto[1342177280:1476395007]	auto[1]	57	1			T17	1		T95	1		T218	1
auto[1476395008:1610612735]	auto[0]	55	1			T217	1		T117	1		T42	1
auto[1476395008:1610612735]	auto[1]	58	1			T17	1		T47	1		T23	1
auto[1610612736:1744830463]	auto[0]	51	1			T70	1		T7	1		T196	1
auto[1610612736:1744830463]	auto[1]	57	1			T31	1		T7	1		T30	1
auto[1744830464:1879048191]	auto[0]	54	1			T7	1		T142	1		T29	1
auto[1744830464:1879048191]	auto[1]	46	1			T76	1		T104	1		T209	1
auto[1879048192:2013265919]	auto[0]	59	1			T217	1		T116	1		T25	1
auto[1879048192:2013265919]	auto[1]	56	1			T64	1		T31	1		T83	1
auto[2013265920:2147483647]	auto[0]	47	1			T22	1		T8	2		T196	1
auto[2013265920:2147483647]	auto[1]	58	1			T19	1		T103	1		T122	1
auto[2147483648:2281701375]	auto[0]	41	1			T104	1		T192	1		T125	1
auto[2147483648:2281701375]	auto[1]	51	1			T69	7		T71	1		T120	1
auto[2281701376:2415919103]	auto[0]	39	1			T8	1		T264	1		T306	1
auto[2281701376:2415919103]	auto[1]	50	1			T17	1		T218	1		T129	1
auto[2415919104:2550136831]	auto[0]	46	1			T69	1		T286	1		T108	3
auto[2415919104:2550136831]	auto[1]	58	1			T117	1		T69	2		T71	1
auto[2550136832:2684354559]	auto[0]	47	1			T29	1		T69	1		T52	1
auto[2550136832:2684354559]	auto[1]	49	1			T64	1		T123	1		T69	1
auto[2684354560:2818572287]	auto[0]	57	1			T18	2		T96	1		T70	1
auto[2684354560:2818572287]	auto[1]	62	1			T20	1		T217	1		T7	1
auto[2818572288:2952790015]	auto[0]	44	1			T16	1		T23	1		T215	1
auto[2818572288:2952790015]	auto[1]	45	1			T19	1		T47	1		T69	1
auto[2952790016:3087007743]	auto[0]	47	1			T40	1		T103	1		T69	1
auto[2952790016:3087007743]	auto[1]	68	1			T76	1		T69	2		T8	2
auto[3087007744:3221225471]	auto[0]	62	1			T64	1		T96	1		T215	1
auto[3087007744:3221225471]	auto[1]	48	1			T116	1		T219	1		T69	2
auto[3221225472:3355443199]	auto[0]	48	1			T20	1		T217	1		T29	2
auto[3221225472:3355443199]	auto[1]	54	1			T17	1		T47	1		T40	1
auto[3355443200:3489660927]	auto[0]	46	1			T23	1		T142	1		T71	1
auto[3355443200:3489660927]	auto[1]	57	1			T7	1		T143	1		T69	1
auto[3489660928:3623878655]	auto[0]	51	1			T6	1		T215	1		T71	1
auto[3489660928:3623878655]	auto[1]	42	1			T23	1		T143	1		T121	1
auto[3623878656:3758096383]	auto[0]	58	1			T16	1		T116	1		T117	1
auto[3623878656:3758096383]	auto[1]	51	1			T22	1		T73	1		T68	1
auto[3758096384:3892314111]	auto[0]	44	1			T83	1		T30	1		T8	1
auto[3758096384:3892314111]	auto[1]	55	1			T16	1		T70	1		T116	1
auto[3892314112:4026531839]	auto[0]	64	1			T16	1		T6	1		T215	2
auto[3892314112:4026531839]	auto[1]	53	1			T7	1		T215	1		T192	1
auto[4026531840:4160749567]	auto[0]	45	1			T23	1		T40	1		T42	1
auto[4026531840:4160749567]	auto[1]	52	1			T68	1		T77	1		T96	1
auto[4160749568:4294967295]	auto[0]	56	1			T16	1		T17	1		T18	1
auto[4160749568:4294967295]	auto[1]	58	1			T64	1		T116	2		T69	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1640

1

T16

7

T6

5

T18

2

auto[1]

1742

1

T16

1

T6

1

T17

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	119	1			T16	1		T116	1		T219	1
auto[134217728:268435455]	113	1			T18	1		T96	1		T29	1
auto[268435456:402653183]	106	1			T18	1		T64	1		T70	1
auto[402653184:536870911]	108	1			T16	1		T95	1		T83	1
auto[536870912:671088639]	108	1			T7	1		T143	1		T218	1
auto[671088640:805306367]	104	1			T16	1		T100	1		T23	1
auto[805306368:939524095]	106	1			T6	1		T77	1		T7	1
auto[939524096:1073741823]	96	1			T40	1		T64	1		T68	1
auto[1073741824:1207959551]	92	1			T20	1		T95	2		T42	1
auto[1207959552:1342177279]	108	1			T17	2		T77	1		T217	1
auto[1342177280:1476395007]	100	1			T47	1		T215	2		T69	1
auto[1476395008:1610612735]	114	1			T47	1		T217	1		T7	1
auto[1610612736:1744830463]	119	1			T20	1		T123	1		T69	3
auto[1744830464:1879048191]	108	1			T6	1		T23	1		T24	1
auto[1879048192:2013265919]	111	1			T6	1		T96	1		T24	1
auto[2013265920:2147483647]	83	1			T22	1		T218	1		T71	2
auto[2147483648:2281701375]	94	1			T96	1		T83	1		T218	1
auto[2281701376:2415919103]	109	1			T16	1		T17	1		T100	1
auto[2415919104:2550136831]	96	1			T6	1		T23	1		T103	1
auto[2550136832:2684354559]	121	1			T23	1		T64	1		T68	1
auto[2684354560:2818572287]	120	1			T70	1		T116	1		T7	1
auto[2818572288:2952790015]	100	1			T16	1		T17	1		T96	1
auto[2952790016:3087007743]	107	1			T6	1		T47	1		T103	2
auto[3087007744:3221225471]	106	1			T16	1		T17	1		T23	1
auto[3221225472:3355443199]	105	1			T17	1		T217	1		T116	2
auto[3355443200:3489660927]	108	1			T18	1		T23	1		T64	1
auto[3489660928:3623878655]	96	1			T31	1		T70	1		T29	1
auto[3623878656:3758096383]	100	1			T16	1		T6	1		T47	1
auto[3758096384:3892314111]	109	1			T19	2		T68	1		T76	1
auto[3892314112:4026531839]	100	1			T19	1		T40	1		T20	1
auto[4026531840:4160749567]	107	1			T47	1		T22	1		T40	1
auto[4160749568:4294967295]	109	1			T16	1		T68	1		T31	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	64	1			T116	1		T42	1		T196	1
auto[0:134217727]	auto[1]	55	1			T16	1		T219	1		T215	1
auto[134217728:268435455]	auto[0]	55	1			T18	1		T96	1		T49	1
auto[134217728:268435455]	auto[1]	58	1			T29	1		T123	1		T8	2
auto[268435456:402653183]	auto[0]	49	1			T64	1		T215	2		T69	1
auto[268435456:402653183]	auto[1]	57	1			T18	1		T70	1		T71	2
auto[402653184:536870911]	auto[0]	58	1			T16	1		T95	1		T116	1
auto[402653184:536870911]	auto[1]	50	1			T83	1		T215	1		T104	1
auto[536870912:671088639]	auto[0]	55	1			T143	1		T69	1		T30	1
auto[536870912:671088639]	auto[1]	53	1			T7	1		T218	1		T69	2
auto[671088640:805306367]	auto[0]	48	1			T16	1		T23	1		T143	1
auto[671088640:805306367]	auto[1]	56	1			T100	1		T64	1		T69	1
auto[805306368:939524095]	auto[0]	55	1			T6	1		T108	1		T435	1
auto[805306368:939524095]	auto[1]	51	1			T77	1		T7	1		T122	1
auto[939524096:1073741823]	auto[0]	48	1			T40	1		T64	1		T68	1
auto[939524096:1073741823]	auto[1]	48	1			T207	1		T269	1		T9	1
auto[1073741824:1207959551]	auto[0]	49	1			T95	1		T42	1		T120	1
auto[1073741824:1207959551]	auto[1]	43	1			T20	1		T95	1		T71	1
auto[1207959552:1342177279]	auto[0]	49	1			T217	1		T69	1		T71	1
auto[1207959552:1342177279]	auto[1]	59	1			T17	2		T77	1		T69	4
auto[1342177280:1476395007]	auto[0]	51	1			T215	2		T69	1		T42	1
auto[1342177280:1476395007]	auto[1]	49	1			T47	1		T209	1		T284	1
auto[1476395008:1610612735]	auto[0]	63	1			T47	1		T25	1		T29	1
auto[1476395008:1610612735]	auto[1]	51	1			T217	1		T7	1		T218	1
auto[1610612736:1744830463]	auto[0]	54	1			T20	1		T123	1		T30	1
auto[1610612736:1744830463]	auto[1]	65	1			T69	3		T71	1		T194	1
auto[1744830464:1879048191]	auto[0]	48	1			T23	1		T103	1		T143	1
auto[1744830464:1879048191]	auto[1]	60	1			T6	1		T24	1		T69	1
auto[1879048192:2013265919]	auto[0]	51	1			T6	1		T29	1		T123	1
auto[1879048192:2013265919]	auto[1]	60	1			T96	1		T24	1		T116	1
auto[2013265920:2147483647]	auto[0]	37	1			T71	1		T194	1		T35	1
auto[2013265920:2147483647]	auto[1]	46	1			T22	1		T218	1		T71	1
auto[2147483648:2281701375]	auto[0]	44	1			T96	1		T83	1		T120	1
auto[2147483648:2281701375]	auto[1]	50	1			T218	1		T69	2		T8	1
auto[2281701376:2415919103]	auto[0]	50	1			T16	1		T100	1		T116	1
auto[2281701376:2415919103]	auto[1]	59	1			T17	1		T64	1		T69	1
auto[2415919104:2550136831]	auto[0]	45	1			T6	1		T23	1		T103	1
auto[2415919104:2550136831]	auto[1]	51	1			T125	1		T33	1		T341	1
auto[2550136832:2684354559]	auto[0]	59	1			T68	1		T29	1		T69	1
auto[2550136832:2684354559]	auto[1]	62	1			T23	1		T64	1		T76	1
auto[2684354560:2818572287]	auto[0]	61	1			T70	1		T7	1		T103	1
auto[2684354560:2818572287]	auto[1]	59	1			T116	1		T69	1		T8	2
auto[2818572288:2952790015]	auto[0]	46	1			T16	1		T217	1		T142	1
auto[2818572288:2952790015]	auto[1]	54	1			T17	1		T96	1		T219	1
auto[2952790016:3087007743]	auto[0]	51	1			T6	1		T47	1		T103	2
auto[2952790016:3087007743]	auto[1]	56	1			T142	1		T51	1		T9	1
auto[3087007744:3221225471]	auto[0]	53	1			T16	1		T23	1		T69	1
auto[3087007744:3221225471]	auto[1]	53	1			T17	1		T73	1		T8	1
auto[3221225472:3355443199]	auto[0]	51	1			T116	1		T117	1		T49	1
auto[3221225472:3355443199]	auto[1]	54	1			T17	1		T217	1		T116	1
auto[3355443200:3489660927]	auto[0]	50	1			T18	1		T29	1		T69	1
auto[3355443200:3489660927]	auto[1]	58	1			T23	1		T64	1		T121	1
auto[3489660928:3623878655]	auto[0]	41	1			T70	1		T29	1		T286	2
auto[3489660928:3623878655]	auto[1]	55	1			T31	1		T71	1		T207	1
auto[3623878656:3758096383]	auto[0]	61	1			T16	1		T6	1		T23	1
auto[3623878656:3758096383]	auto[1]	39	1			T47	1		T22	1		T68	1
auto[3758096384:3892314111]	auto[0]	52	1			T68	1		T83	1		T217	1
auto[3758096384:3892314111]	auto[1]	57	1			T19	2		T76	1		T25	1
auto[3892314112:4026531839]	auto[0]	42	1			T19	1		T20	1		T8	2
auto[3892314112:4026531839]	auto[1]	58	1			T40	1		T104	1		T207	1
auto[4026531840:4160749567]	auto[0]	46	1			T47	1		T22	1		T40	1
auto[4026531840:4160749567]	auto[1]	61	1			T96	1		T7	1		T143	1
auto[4160749568:4294967295]	auto[0]	54	1			T16	1		T68	1		T7	1
auto[4160749568:4294967295]	auto[1]	55	1			T31	1		T116	1		T8	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1645

1

T16

6

T6

4

T17

1

auto[1]

1737

1

T16

2

T6

2

T17

5