Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4610

1

T16

12

T6

10

T17

10

auto[1]

2154

1

T16

4

T6

2

T17

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	240	1			T16	2		T23	2		T83	2
auto[134217728:268435455]	236	1			T47	2		T22	2		T23	2
auto[268435456:402653183]	240	1			T16	4		T64	4		T116	2
auto[402653184:536870911]	220	1			T47	2		T40	2		T217	4
auto[536870912:671088639]	210	1			T18	2		T103	2		T215	2
auto[671088640:805306367]	198	1			T217	2		T104	2		T69	2
auto[805306368:939524095]	202	1			T23	2		T116	2		T7	2
auto[939524096:1073741823]	216	1			T19	2		T23	2		T68	2
auto[1073741824:1207959551]	228	1			T6	2		T18	2		T64	2
auto[1207959552:1342177279]	256	1			T17	2		T64	2		T20	2
auto[1342177280:1476395007]	216	1			T40	2		T25	2		T142	2
auto[1476395008:1610612735]	180	1			T17	2		T47	2		T23	2
auto[1610612736:1744830463]	218	1			T83	2		T103	2		T143	2
auto[1744830464:1879048191]	192	1			T215	4		T121	2		T104	2
auto[1879048192:2013265919]	200	1			T18	2		T40	2		T96	2
auto[2013265920:2147483647]	190	1			T17	4		T19	2		T68	2
auto[2147483648:2281701375]	210	1			T6	2		T23	2		T116	2
auto[2281701376:2415919103]	214	1			T31	2		T25	2		T129	2
auto[2415919104:2550136831]	200	1			T64	2		T7	2		T123	2
auto[2550136832:2684354559]	206	1			T68	2		T103	2		T30	2
auto[2684354560:2818572287]	202	1			T64	2		T31	2		T69	2
auto[2818572288:2952790015]	256	1			T6	2		T22	2		T68	2
auto[2952790016:3087007743]	198	1			T22	2		T100	2		T7	2
auto[3087007744:3221225471]	202	1			T17	2		T96	2		T116	2
auto[3221225472:3355443199]	238	1			T96	2		T116	2		T69	2
auto[3355443200:3489660927]	190	1			T16	2		T123	2		T71	4
auto[3489660928:3623878655]	218	1			T16	4		T6	2		T17	2
auto[3623878656:3758096383]	182	1			T6	2		T77	2		T96	2
auto[3758096384:3892314111]	172	1			T19	2		T20	2		T70	4
auto[3892314112:4026531839]	242	1			T23	2		T68	2		T20	4
auto[4026531840:4160749567]	194	1			T16	4		T96	2		T117	4
auto[4160749568:4294967295]	198	1			T6	2		T47	2		T100	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	146	1			T218	2		T69	2		T30	2
auto[0:134217727]	auto[1]	94	1			T16	2		T23	2		T83	2
auto[134217728:268435455]	auto[0]	148	1			T47	2		T31	2		T116	2
auto[134217728:268435455]	auto[1]	88	1			T22	2		T23	2		T73	2
auto[268435456:402653183]	auto[0]	168	1			T16	2		T64	4		T116	2
auto[268435456:402653183]	auto[1]	72	1			T16	2		T219	2		T69	4
auto[402653184:536870911]	auto[0]	128	1			T47	2		T40	2		T217	4
auto[402653184:536870911]	auto[1]	92	1			T71	2		T8	2		T306	2
auto[536870912:671088639]	auto[0]	164	1			T18	2		T215	2		T121	2
auto[536870912:671088639]	auto[1]	46	1			T103	2		T135	2		T118	2
auto[671088640:805306367]	auto[0]	132	1			T217	2		T104	2		T69	2
auto[671088640:805306367]	auto[1]	66	1			T71	2		T107	2		T108	2
auto[805306368:939524095]	auto[0]	148	1			T116	2		T7	2		T143	4
auto[805306368:939524095]	auto[1]	54	1			T23	2		T8	2		T126	2
auto[939524096:1073741823]	auto[0]	148	1			T23	2		T142	2		T143	2
auto[939524096:1073741823]	auto[1]	68	1			T19	2		T68	2		T24	2
auto[1073741824:1207959551]	auto[0]	164	1			T6	2		T18	2		T64	2
auto[1073741824:1207959551]	auto[1]	64	1			T123	2		T69	2		T8	2
auto[1207959552:1342177279]	auto[0]	168	1			T17	2		T64	2		T24	2
auto[1207959552:1342177279]	auto[1]	88	1			T20	2		T105	2		T107	2
auto[1342177280:1476395007]	auto[0]	158	1			T142	2		T69	4		T71	2
auto[1342177280:1476395007]	auto[1]	58	1			T40	2		T25	2		T69	2
auto[1476395008:1610612735]	auto[0]	138	1			T17	2		T47	2		T23	2
auto[1476395008:1610612735]	auto[1]	42	1			T95	2		T264	2		T309	2
auto[1610612736:1744830463]	auto[0]	146	1			T143	2		T29	2		T8	2
auto[1610612736:1744830463]	auto[1]	72	1			T83	2		T103	2		T69	2
auto[1744830464:1879048191]	auto[0]	120	1			T215	4		T104	2		T69	2
auto[1744830464:1879048191]	auto[1]	72	1			T121	2		T42	2		T287	2
auto[1879048192:2013265919]	auto[0]	146	1			T18	2		T40	2		T96	2
auto[1879048192:2013265919]	auto[1]	54	1			T8	2		T402	2		T221	2
auto[2013265920:2147483647]	auto[0]	118	1			T17	4		T68	2		T76	2
auto[2013265920:2147483647]	auto[1]	72	1			T19	2		T120	2		T437	2
auto[2147483648:2281701375]	auto[0]	168	1			T6	2		T23	2		T116	2
auto[2147483648:2281701375]	auto[1]	42	1			T207	2		T108	2		T237	2
auto[2281701376:2415919103]	auto[0]	138	1			T129	2		T341	2		T284	2
auto[2281701376:2415919103]	auto[1]	76	1			T31	2		T25	2		T126	2
auto[2415919104:2550136831]	auto[0]	148	1			T64	2		T7	2		T123	2
auto[2415919104:2550136831]	auto[1]	52	1			T106	2		T108	2		T440	2
auto[2550136832:2684354559]	auto[0]	146	1			T68	2		T30	2		T194	2
auto[2550136832:2684354559]	auto[1]	60	1			T103	2		T49	2		T126	2
auto[2684354560:2818572287]	auto[0]	128	1			T64	2		T31	2		T71	2
auto[2684354560:2818572287]	auto[1]	74	1			T69	2		T120	2		T8	4
auto[2818572288:2952790015]	auto[0]	172	1			T6	2		T76	2		T218	2
auto[2818572288:2952790015]	auto[1]	84	1			T22	2		T68	2		T143	2
auto[2952790016:3087007743]	auto[0]	118	1			T123	2		T120	2		T49	2
auto[2952790016:3087007743]	auto[1]	80	1			T22	2		T100	2		T7	2
auto[3087007744:3221225471]	auto[0]	130	1			T142	2		T42	2		T194	2
auto[3087007744:3221225471]	auto[1]	72	1			T17	2		T96	2		T116	2
auto[3221225472:3355443199]	auto[0]	176	1			T96	2		T116	2		T69	2
auto[3221225472:3355443199]	auto[1]	62	1			T52	2		T197	2		T9	2
auto[3355443200:3489660927]	auto[0]	108	1			T16	2		T123	2		T71	4
auto[3355443200:3489660927]	auto[1]	82	1			T105	2		T91	2		T381	2
auto[3489660928:3623878655]	auto[0]	156	1			T16	4		T6	2		T17	2
auto[3489660928:3623878655]	auto[1]	62	1			T29	2		T221	2		T400	2
auto[3623878656:3758096383]	auto[0]	124	1			T6	2		T96	2		T116	2
auto[3623878656:3758096383]	auto[1]	58	1			T77	2		T8	2		T341	2
auto[3758096384:3892314111]	auto[0]	114	1			T20	2		T70	4		T217	2
auto[3758096384:3892314111]	auto[1]	58	1			T19	2		T69	2		T107	2
auto[3892314112:4026531839]	auto[0]	170	1			T23	2		T20	4		T95	2
auto[3892314112:4026531839]	auto[1]	72	1			T68	2		T91	2		T441	2
auto[4026531840:4160749567]	auto[0]	142	1			T16	4		T96	2		T117	2
auto[4026531840:4160749567]	auto[1]	52	1			T117	2		T8	2		T194	2
auto[4160749568:4294967295]	auto[0]	132	1			T100	2		T116	2		T69	6
auto[4160749568:4294967295]	auto[1]	66	1			T6	2		T47	2		T77	2