Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2947

1

T16

8

T6

6

T17

6

auto[1]

258

1

T77

2

T83

9

T103

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T17	1		T47	1		T69	1
auto[134217728:268435455]	90	1			T6	1		T100	2		T23	1
auto[268435456:402653183]	102	1			T7	1		T104	1		T69	2
auto[402653184:536870911]	120	1			T47	1		T96	1		T83	1
auto[536870912:671088639]	93	1			T6	1		T47	1		T23	1
auto[671088640:805306367]	100	1			T17	1		T68	1		T96	1
auto[805306368:939524095]	96	1			T16	1		T47	1		T77	1
auto[939524096:1073741823]	92	1			T22	1		T217	1		T104	1
auto[1073741824:1207959551]	105	1			T22	1		T103	1		T215	1
auto[1207959552:1342177279]	108	1			T19	1		T215	1		T104	1
auto[1342177280:1476395007]	101	1			T16	2		T20	1		T69	2
auto[1476395008:1610612735]	106	1			T16	1		T6	1		T103	1
auto[1610612736:1744830463]	117	1			T23	1		T68	1		T77	1
auto[1744830464:1879048191]	93	1			T95	1		T96	1		T116	2
auto[1879048192:2013265919]	104	1			T18	1		T47	1		T23	1
auto[2013265920:2147483647]	94	1			T31	1		T217	1		T103	1
auto[2147483648:2281701375]	105	1			T23	1		T77	1		T95	1
auto[2281701376:2415919103]	100	1			T17	1		T22	1		T40	1
auto[2415919104:2550136831]	101	1			T70	1		T117	1		T29	1
auto[2550136832:2684354559]	88	1			T23	1		T20	1		T96	1
auto[2684354560:2818572287]	101	1			T6	1		T20	2		T142	1
auto[2818572288:2952790015]	68	1			T6	1		T103	1		T71	1
auto[2952790016:3087007743]	101	1			T19	1		T83	1		T7	1
auto[3087007744:3221225471]	116	1			T68	1		T83	1		T29	1
auto[3221225472:3355443199]	103	1			T40	1		T76	1		T83	2
auto[3355443200:3489660927]	108	1			T6	1		T31	1		T7	1
auto[3489660928:3623878655]	98	1			T16	1		T17	1		T116	1
auto[3623878656:3758096383]	116	1			T19	1		T40	1		T68	1
auto[3758096384:3892314111]	99	1			T16	1		T17	1		T23	1
auto[3892314112:4026531839]	95	1			T16	2		T83	1		T70	1
auto[4026531840:4160749567]	90	1			T17	1		T76	1		T83	1
auto[4160749568:4294967295]	95	1			T77	1		T95	1		T25	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	95	1			T17	1		T47	1		T69	1
auto[0:134217727]	auto[1]	5	1			T319	1		T270	1		T428	1
auto[134217728:268435455]	auto[0]	86	1			T6	1		T100	2		T23	1
auto[134217728:268435455]	auto[1]	4	1			T319	1		T311	1		T379	1
auto[268435456:402653183]	auto[0]	95	1			T7	1		T104	1		T69	2
auto[268435456:402653183]	auto[1]	7	1			T105	1		T106	1		T107	1
auto[402653184:536870911]	auto[0]	111	1			T47	1		T96	1		T116	1
auto[402653184:536870911]	auto[1]	9	1			T83	1		T336	1		T431	1
auto[536870912:671088639]	auto[0]	83	1			T6	1		T47	1		T23	1
auto[536870912:671088639]	auto[1]	10	1			T104	1		T336	1		T428	1
auto[671088640:805306367]	auto[0]	90	1			T17	1		T68	1		T96	1
auto[671088640:805306367]	auto[1]	10	1			T83	2		T106	1		T285	1
auto[805306368:939524095]	auto[0]	90	1			T16	1		T47	1		T31	1
auto[805306368:939524095]	auto[1]	6	1			T77	1		T432	1		T429	1
auto[939524096:1073741823]	auto[0]	81	1			T22	1		T217	1		T104	1
auto[939524096:1073741823]	auto[1]	11	1			T270	1		T430	1		T432	1
auto[1073741824:1207959551]	auto[0]	93	1			T22	1		T103	1		T215	1
auto[1073741824:1207959551]	auto[1]	12	1			T107	2		T336	1		T300	1
auto[1207959552:1342177279]	auto[0]	97	1			T19	1		T215	1		T69	1
auto[1207959552:1342177279]	auto[1]	11	1			T104	1		T105	1		T107	2
auto[1342177280:1476395007]	auto[0]	97	1			T16	2		T20	1		T69	2
auto[1342177280:1476395007]	auto[1]	4	1			T255	1		T278	1		T280	1
auto[1476395008:1610612735]	auto[0]	101	1			T16	1		T6	1		T103	1
auto[1476395008:1610612735]	auto[1]	5	1			T107	1		T336	1		T429	2
auto[1610612736:1744830463]	auto[0]	105	1			T23	1		T68	1		T77	1
auto[1610612736:1744830463]	auto[1]	12	1			T83	1		T281	1		T285	1
auto[1744830464:1879048191]	auto[0]	87	1			T95	1		T96	1		T116	2
auto[1744830464:1879048191]	auto[1]	6	1			T103	1		T311	1		T428	1
auto[1879048192:2013265919]	auto[0]	94	1			T18	1		T47	1		T23	1
auto[1879048192:2013265919]	auto[1]	10	1			T103	1		T281	1		T411	1
auto[2013265920:2147483647]	auto[0]	91	1			T31	1		T217	1		T103	1
auto[2013265920:2147483647]	auto[1]	3	1			T105	1		T275	1		T442	1
auto[2147483648:2281701375]	auto[0]	99	1			T23	1		T95	1		T116	1
auto[2147483648:2281701375]	auto[1]	6	1			T77	1		T103	1		T429	1
auto[2281701376:2415919103]	auto[0]	91	1			T17	1		T22	1		T40	1
auto[2281701376:2415919103]	auto[1]	9	1			T336	1		T311	1		T412	1
auto[2415919104:2550136831]	auto[0]	93	1			T70	1		T117	1		T29	1
auto[2415919104:2550136831]	auto[1]	8	1			T107	1		T285	1		T270	1
auto[2550136832:2684354559]	auto[0]	84	1			T23	1		T20	1		T96	1
auto[2550136832:2684354559]	auto[1]	4	1			T281	1		T311	1		T429	1
auto[2684354560:2818572287]	auto[0]	97	1			T6	1		T20	2		T142	1
auto[2684354560:2818572287]	auto[1]	4	1			T255	1		T412	1		T443	1
auto[2818572288:2952790015]	auto[0]	62	1			T6	1		T71	1		T196	1
auto[2818572288:2952790015]	auto[1]	6	1			T103	1		T434	1		T444	1
auto[2952790016:3087007743]	auto[0]	90	1			T19	1		T83	1		T7	1
auto[2952790016:3087007743]	auto[1]	11	1			T104	1		T105	1		T336	1
auto[3087007744:3221225471]	auto[0]	99	1			T68	1		T29	1		T121	1
auto[3087007744:3221225471]	auto[1]	17	1			T83	1		T106	1		T319	1
auto[3221225472:3355443199]	auto[0]	94	1			T40	1		T76	1		T24	1
auto[3221225472:3355443199]	auto[1]	9	1			T83	2		T105	1		T310	1
auto[3355443200:3489660927]	auto[0]	103	1			T6	1		T31	1		T7	1
auto[3355443200:3489660927]	auto[1]	5	1			T285	1		T280	1		T429	1
auto[3489660928:3623878655]	auto[0]	90	1			T16	1		T17	1		T116	1
auto[3489660928:3623878655]	auto[1]	8	1			T107	1		T278	1		T428	1
auto[3623878656:3758096383]	auto[0]	104	1			T19	1		T40	1		T68	1
auto[3623878656:3758096383]	auto[1]	12	1			T105	1		T285	1		T300	1
auto[3758096384:3892314111]	auto[0]	95	1			T16	1		T17	1		T23	1
auto[3758096384:3892314111]	auto[1]	4	1			T278	1		T257	1		T274	1
auto[3892314112:4026531839]	auto[0]	88	1			T16	2		T70	1		T218	1
auto[3892314112:4026531839]	auto[1]	7	1			T83	1		T107	1		T255	1
auto[4026531840:4160749567]	auto[0]	75	1			T17	1		T76	1		T215	1
auto[4026531840:4160749567]	auto[1]	15	1			T83	1		T105	3		T107	1
auto[4160749568:4294967295]	auto[0]	87	1			T77	1		T95	1		T25	1
auto[4160749568:4294967295]	auto[1]	8	1			T104	1		T319	1		T261	1