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Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 108 1 T16 1 T47 2 T68 2
auto[134217728:268435455] 87 1 T16 1 T64 1 T103 1
auto[268435456:402653183] 98 1 T17 1 T18 1 T142 1
auto[402653184:536870911] 105 1 T64 1 T77 1 T215 1
auto[536870912:671088639] 114 1 T47 1 T40 1 T20 1
auto[671088640:805306367] 100 1 T6 1 T47 1 T23 1
auto[805306368:939524095] 108 1 T47 1 T69 2 T120 1
auto[939524096:1073741823] 108 1 T19 1 T96 1 T7 1
auto[1073741824:1207959551] 79 1 T16 2 T6 1 T23 1
auto[1207959552:1342177279] 111 1 T215 1 T29 1 T121 1
auto[1342177280:1476395007] 104 1 T22 1 T68 1 T96 1
auto[1476395008:1610612735] 106 1 T16 1 T17 1 T19 1
auto[1610612736:1744830463] 105 1 T217 1 T42 1 T8 1
auto[1744830464:1879048191] 109 1 T23 1 T64 1 T7 1
auto[1879048192:2013265919] 100 1 T217 1 T29 1 T123 1
auto[2013265920:2147483647] 106 1 T64 1 T95 1 T70 2
auto[2147483648:2281701375] 104 1 T64 1 T96 1 T83 1
auto[2281701376:2415919103] 115 1 T16 1 T40 1 T77 1
auto[2415919104:2550136831] 109 1 T217 1 T116 2 T219 1
auto[2550136832:2684354559] 105 1 T83 1 T207 1 T8 2
auto[2684354560:2818572287] 89 1 T68 1 T76 1 T121 1
auto[2818572288:2952790015] 109 1 T23 1 T20 1 T95 1
auto[2952790016:3087007743] 105 1 T6 1 T17 1 T40 1
auto[3087007744:3221225471] 121 1 T16 1 T6 1 T17 1
auto[3221225472:3355443199] 123 1 T16 1 T20 1 T31 1
auto[3355443200:3489660927] 111 1 T6 1 T100 1 T103 1
auto[3489660928:3623878655] 111 1 T19 1 T31 1 T116 1
auto[3623878656:3758096383] 98 1 T18 1 T29 1 T69 3
auto[3758096384:3892314111] 123 1 T17 2 T20 1 T24 1
auto[3892314112:4026531839] 102 1 T6 1 T22 1 T23 1
auto[4026531840:4160749567] 109 1 T100 1 T215 1 T143 1
auto[4160749568:4294967295] 100 1 T68 1 T215 1 T69 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 52 1 T16 1 T68 2 T103 1
auto[0:134217727] auto[1] 56 1 T47 2 T31 1 T143 1
auto[134217728:268435455] auto[0] 44 1 T16 1 T30 1 T9 1
auto[134217728:268435455] auto[1] 43 1 T64 1 T103 1 T25 1
auto[268435456:402653183] auto[0] 52 1 T18 1 T142 1 T29 1
auto[268435456:402653183] auto[1] 46 1 T17 1 T69 1 T207 1
auto[402653184:536870911] auto[0] 51 1 T64 1 T215 1 T117 1
auto[402653184:536870911] auto[1] 54 1 T77 1 T69 1 T125 1
auto[536870912:671088639] auto[0] 54 1 T47 1 T7 1 T30 1
auto[536870912:671088639] auto[1] 60 1 T40 1 T20 1 T217 1
auto[671088640:805306367] auto[0] 40 1 T47 1 T30 1 T71 1
auto[671088640:805306367] auto[1] 60 1 T6 1 T23 1 T76 1
auto[805306368:939524095] auto[0] 48 1 T120 1 T135 1 T9 1
auto[805306368:939524095] auto[1] 60 1 T47 1 T69 2 T192 1
auto[939524096:1073741823] auto[0] 56 1 T19 1 T96 1 T7 1
auto[939524096:1073741823] auto[1] 52 1 T69 2 T8 1 T194 1
auto[1073741824:1207959551] auto[0] 43 1 T16 1 T6 1 T103 1
auto[1073741824:1207959551] auto[1] 36 1 T16 1 T23 1 T64 1
auto[1207959552:1342177279] auto[0] 50 1 T215 1 T29 1 T71 1
auto[1207959552:1342177279] auto[1] 61 1 T121 1 T69 1 T71 1
auto[1342177280:1476395007] auto[0] 56 1 T22 1 T68 1 T69 2
auto[1342177280:1476395007] auto[1] 48 1 T96 1 T116 1 T8 1
auto[1476395008:1610612735] auto[0] 46 1 T17 1 T95 1 T116 1
auto[1476395008:1610612735] auto[1] 60 1 T16 1 T19 1 T22 1
auto[1610612736:1744830463] auto[0] 55 1 T217 1 T35 1 T269 1
auto[1610612736:1744830463] auto[1] 50 1 T42 1 T8 1 T9 1
auto[1744830464:1879048191] auto[0] 53 1 T215 1 T104 1 T69 1
auto[1744830464:1879048191] auto[1] 56 1 T23 1 T64 1 T7 1
auto[1879048192:2013265919] auto[0] 46 1 T123 1 T71 1 T51 1
auto[1879048192:2013265919] auto[1] 54 1 T217 1 T29 1 T71 1
auto[2013265920:2147483647] auto[0] 52 1 T64 1 T70 2 T69 1
auto[2013265920:2147483647] auto[1] 54 1 T95 1 T30 1 T8 3
auto[2147483648:2281701375] auto[0] 56 1 T215 1 T25 1 T117 1
auto[2147483648:2281701375] auto[1] 48 1 T64 1 T96 1 T83 1
auto[2281701376:2415919103] auto[0] 55 1 T16 1 T40 1 T217 1
auto[2281701376:2415919103] auto[1] 60 1 T77 1 T70 1 T69 2
auto[2415919104:2550136831] auto[0] 57 1 T217 1 T116 1 T7 1
auto[2415919104:2550136831] auto[1] 52 1 T116 1 T219 1 T7 1
auto[2550136832:2684354559] auto[0] 51 1 T8 1 T196 1 T49 1
auto[2550136832:2684354559] auto[1] 54 1 T83 1 T207 1 T8 1
auto[2684354560:2818572287] auto[0] 43 1 T68 1 T105 1 T264 1
auto[2684354560:2818572287] auto[1] 46 1 T76 1 T121 1 T69 1
auto[2818572288:2952790015] auto[0] 51 1 T23 1 T20 1 T95 1
auto[2818572288:2952790015] auto[1] 58 1 T24 1 T69 1 T71 1
auto[2952790016:3087007743] auto[0] 48 1 T6 1 T40 1 T194 1
auto[2952790016:3087007743] auto[1] 57 1 T17 1 T116 1 T218 1
auto[3087007744:3221225471] auto[0] 61 1 T16 1 T6 1 T23 2
auto[3087007744:3221225471] auto[1] 60 1 T17 1 T18 1 T8 2
auto[3221225472:3355443199] auto[0] 61 1 T16 1 T20 1 T83 1
auto[3221225472:3355443199] auto[1] 62 1 T31 1 T116 1 T218 1
auto[3355443200:3489660927] auto[0] 55 1 T69 2 T129 1 T333 1
auto[3355443200:3489660927] auto[1] 56 1 T6 1 T100 1 T103 1
auto[3489660928:3623878655] auto[0] 48 1 T31 1 T116 1 T143 1
auto[3489660928:3623878655] auto[1] 63 1 T19 1 T123 1 T69 2
auto[3623878656:3758096383] auto[0] 49 1 T18 1 T29 1 T42 1
auto[3623878656:3758096383] auto[1] 49 1 T69 3 T120 1 T129 1
auto[3758096384:3892314111] auto[0] 60 1 T20 1 T116 1 T69 1
auto[3758096384:3892314111] auto[1] 63 1 T17 2 T24 1 T104 1
auto[3892314112:4026531839] auto[0] 50 1 T6 1 T22 1 T23 1
auto[3892314112:4026531839] auto[1] 52 1 T69 2 T209 1 T436 1
auto[4026531840:4160749567] auto[0] 56 1 T100 1 T143 1 T117 1
auto[4026531840:4160749567] auto[1] 53 1 T215 1 T71 2 T333 1
auto[4160749568:4294967295] auto[0] 46 1 T120 1 T8 1 T9 1
auto[4160749568:4294967295] auto[1] 54 1 T68 1 T215 1 T69 1

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