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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 1625 1 T16 7 T6 4 T18 2
auto[1] 1757 1 T16 1 T6 2 T17 6



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 113 1 T18 1 T64 1 T83 1
auto[134217728:268435455] 97 1 T23 1 T217 1 T7 1
auto[268435456:402653183] 102 1 T6 2 T23 1 T20 1
auto[402653184:536870911] 111 1 T17 1 T64 1 T31 1
auto[536870912:671088639] 110 1 T64 1 T116 1 T215 1
auto[671088640:805306367] 123 1 T47 1 T23 1 T77 1
auto[805306368:939524095] 110 1 T23 1 T103 1 T142 1
auto[939524096:1073741823] 104 1 T16 1 T68 1 T96 2
auto[1073741824:1207959551] 105 1 T40 1 T25 1 T29 1
auto[1207959552:1342177279] 107 1 T6 1 T77 1 T69 2
auto[1342177280:1476395007] 85 1 T64 1 T31 1 T116 1
auto[1476395008:1610612735] 104 1 T23 1 T20 1 T219 1
auto[1610612736:1744830463] 106 1 T17 1 T95 1 T142 1
auto[1744830464:1879048191] 88 1 T22 1 T116 1 T215 1
auto[1879048192:2013265919] 105 1 T69 3 T71 1 T8 3
auto[2013265920:2147483647] 102 1 T40 1 T68 2 T24 1
auto[2147483648:2281701375] 97 1 T22 1 T68 1 T104 1
auto[2281701376:2415919103] 124 1 T16 2 T18 1 T19 1
auto[2415919104:2550136831] 89 1 T16 1 T47 1 T70 2
auto[2550136832:2684354559] 105 1 T100 1 T96 1 T103 1
auto[2684354560:2818572287] 101 1 T16 1 T18 1 T19 1
auto[2818572288:2952790015] 95 1 T16 1 T6 3 T17 1
auto[2952790016:3087007743] 118 1 T16 1 T22 1 T73 1
auto[3087007744:3221225471] 116 1 T17 1 T19 1 T68 1
auto[3221225472:3355443199] 118 1 T7 1 T29 1 T218 1
auto[3355443200:3489660927] 94 1 T16 1 T17 1 T47 1
auto[3489660928:3623878655] 105 1 T40 1 T20 1 T116 1
auto[3623878656:3758096383] 123 1 T23 1 T64 2 T95 1
auto[3758096384:3892314111] 106 1 T17 1 T7 1 T29 1
auto[3892314112:4026531839] 96 1 T47 1 T31 1 T83 1
auto[4026531840:4160749567] 118 1 T47 1 T100 1 T76 1
auto[4160749568:4294967295] 105 1 T116 1 T104 1 T69 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 57 1 T18 1 T83 1 T143 1
auto[0:134217727] auto[1] 56 1 T64 1 T116 1 T143 1
auto[134217728:268435455] auto[0] 44 1 T23 1 T217 1 T7 1
auto[134217728:268435455] auto[1] 53 1 T69 2 T71 1 T8 3
auto[268435456:402653183] auto[0] 46 1 T6 1 T20 1 T96 1
auto[268435456:402653183] auto[1] 56 1 T6 1 T23 1 T76 1
auto[402653184:536870911] auto[0] 59 1 T217 1 T123 1 T71 1
auto[402653184:536870911] auto[1] 52 1 T17 1 T64 1 T31 1
auto[536870912:671088639] auto[0] 50 1 T116 1 T215 1 T69 1
auto[536870912:671088639] auto[1] 60 1 T64 1 T69 2 T207 1
auto[671088640:805306367] auto[0] 58 1 T215 1 T29 1 T69 1
auto[671088640:805306367] auto[1] 65 1 T47 1 T23 1 T77 1
auto[805306368:939524095] auto[0] 57 1 T23 1 T103 1 T142 1
auto[805306368:939524095] auto[1] 53 1 T121 1 T105 1 T129 1
auto[939524096:1073741823] auto[0] 55 1 T16 1 T68 1 T96 1
auto[939524096:1073741823] auto[1] 49 1 T96 1 T116 1 T143 1
auto[1073741824:1207959551] auto[0] 55 1 T29 1 T207 1 T8 1
auto[1073741824:1207959551] auto[1] 50 1 T40 1 T25 1 T69 2
auto[1207959552:1342177279] auto[0] 50 1 T6 1 T8 1 T51 1
auto[1207959552:1342177279] auto[1] 57 1 T77 1 T69 2 T30 1
auto[1342177280:1476395007] auto[0] 45 1 T64 1 T31 1 T29 1
auto[1342177280:1476395007] auto[1] 40 1 T116 1 T69 1 T9 1
auto[1476395008:1610612735] auto[0] 51 1 T20 1 T71 1 T51 1
auto[1476395008:1610612735] auto[1] 53 1 T23 1 T219 1 T218 1
auto[1610612736:1744830463] auto[0] 46 1 T117 1 T69 1 T42 1
auto[1610612736:1744830463] auto[1] 60 1 T17 1 T95 1 T142 1
auto[1744830464:1879048191] auto[0] 43 1 T22 1 T123 1 T207 1
auto[1744830464:1879048191] auto[1] 45 1 T116 1 T215 1 T71 1
auto[1879048192:2013265919] auto[0] 48 1 T71 1 T8 1 T106 1
auto[1879048192:2013265919] auto[1] 57 1 T69 3 T8 2 T79 1
auto[2013265920:2147483647] auto[0] 55 1 T40 1 T68 1 T69 1
auto[2013265920:2147483647] auto[1] 47 1 T68 1 T24 1 T103 1
auto[2147483648:2281701375] auto[0] 49 1 T68 1 T30 1 T71 1
auto[2147483648:2281701375] auto[1] 48 1 T22 1 T104 1 T69 1
auto[2281701376:2415919103] auto[0] 52 1 T16 1 T70 1 T217 1
auto[2281701376:2415919103] auto[1] 72 1 T16 1 T18 1 T19 1
auto[2415919104:2550136831] auto[0] 46 1 T16 1 T70 2 T69 1
auto[2415919104:2550136831] auto[1] 43 1 T47 1 T71 1 T8 1
auto[2550136832:2684354559] auto[0] 48 1 T96 1 T8 1 T194 1
auto[2550136832:2684354559] auto[1] 57 1 T100 1 T103 1 T120 1
auto[2684354560:2818572287] auto[0] 46 1 T16 1 T18 1 T215 1
auto[2684354560:2818572287] auto[1] 55 1 T19 1 T258 1 T9 1
auto[2818572288:2952790015] auto[0] 42 1 T16 1 T6 2 T23 1
auto[2818572288:2952790015] auto[1] 53 1 T6 1 T17 1 T69 1
auto[2952790016:3087007743] auto[0] 53 1 T16 1 T22 1 T116 1
auto[2952790016:3087007743] auto[1] 65 1 T73 1 T215 1 T121 1
auto[3087007744:3221225471] auto[0] 46 1 T20 1 T103 1 T33 1
auto[3087007744:3221225471] auto[1] 70 1 T17 1 T19 1 T68 1
auto[3221225472:3355443199] auto[0] 65 1 T29 1 T104 1 T120 1
auto[3221225472:3355443199] auto[1] 53 1 T7 1 T218 1 T69 1
auto[3355443200:3489660927] auto[0] 44 1 T16 1 T47 1 T217 1
auto[3355443200:3489660927] auto[1] 50 1 T17 1 T207 1 T106 1
auto[3489660928:3623878655] auto[0] 54 1 T40 1 T116 1 T117 1
auto[3489660928:3623878655] auto[1] 51 1 T20 1 T215 1 T69 1
auto[3623878656:3758096383] auto[0] 59 1 T95 1 T29 2 T69 1
auto[3623878656:3758096383] auto[1] 64 1 T23 1 T64 2 T218 1
auto[3758096384:3892314111] auto[0] 45 1 T71 1 T194 1 T51 1
auto[3758096384:3892314111] auto[1] 61 1 T17 1 T7 1 T29 1
auto[3892314112:4026531839] auto[0] 46 1 T47 1 T83 1 T269 1
auto[3892314112:4026531839] auto[1] 50 1 T31 1 T123 1 T69 2
auto[4026531840:4160749567] auto[0] 59 1 T100 1 T95 1 T116 1
auto[4026531840:4160749567] auto[1] 59 1 T47 1 T76 1 T125 1
auto[4160749568:4294967295] auto[0] 52 1 T104 1 T69 1 T42 1
auto[4160749568:4294967295] auto[1] 53 1 T116 1 T69 1 T207 1

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