Unified Coverage Report :: Group Instance : max_creator_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4734

1

T16

12

T6

10

T17

12

auto[1]

2030

1

T16

4

T6

2

T19

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	204	1			T64	2		T7	2		T215	2
auto[134217728:268435455]	208	1			T47	2		T20	2		T116	2
auto[268435456:402653183]	194	1			T20	2		T76	2		T103	2
auto[402653184:536870911]	210	1			T47	2		T117	2		T104	2
auto[536870912:671088639]	218	1			T6	2		T47	2		T24	2
auto[671088640:805306367]	224	1			T64	2		T219	2		T7	2
auto[805306368:939524095]	204	1			T19	2		T22	2		T217	2
auto[939524096:1073741823]	204	1			T16	2		T6	2		T64	2
auto[1073741824:1207959551]	196	1			T68	4		T70	2		T116	2
auto[1207959552:1342177279]	220	1			T16	2		T17	2		T18	2
auto[1342177280:1476395007]	192	1			T83	2		T103	2		T29	2
auto[1476395008:1610612735]	232	1			T95	2		T96	2		T24	2
auto[1610612736:1744830463]	196	1			T16	2		T6	2		T17	2
auto[1744830464:1879048191]	230	1			T6	2		T18	2		T23	2
auto[1879048192:2013265919]	178	1			T20	2		T31	2		T95	2
auto[2013265920:2147483647]	206	1			T47	2		T64	2		T25	2
auto[2147483648:2281701375]	244	1			T47	2		T40	2		T64	2
auto[2281701376:2415919103]	202	1			T19	2		T23	2		T64	2
auto[2415919104:2550136831]	222	1			T19	2		T23	2		T76	2
auto[2550136832:2684354559]	216	1			T16	2		T143	2		T117	2
auto[2684354560:2818572287]	206	1			T17	2		T20	2		T215	2
auto[2818572288:2952790015]	234	1			T22	4		T23	2		T77	2
auto[2952790016:3087007743]	170	1			T16	2		T100	2		T123	2
auto[3087007744:3221225471]	220	1			T23	2		T217	2		T142	4
auto[3221225472:3355443199]	202	1			T23	2		T69	2		T207	4
auto[3355443200:3489660927]	192	1			T100	2		T40	2		T31	2
auto[3489660928:3623878655]	238	1			T68	2		T31	2		T122	2
auto[3623878656:3758096383]	250	1			T17	2		T95	2		T217	2
auto[3758096384:3892314111]	178	1			T16	2		T17	2		T68	2
auto[3892314112:4026531839]	190	1			T16	2		T6	2		T17	2
auto[4026531840:4160749567]	236	1			T16	2		T6	2		T83	2
auto[4160749568:4294967295]	248	1			T18	2		T40	2		T70	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	154	1			T64	2		T7	2		T215	2
auto[0:134217727]	auto[1]	50	1			T69	2		T269	2		T319	2
auto[134217728:268435455]	auto[0]	152	1			T47	2		T20	2		T116	2
auto[134217728:268435455]	auto[1]	56	1			T89	2		T290	2		T439	2
auto[268435456:402653183]	auto[0]	156	1			T20	2		T76	2		T215	2
auto[268435456:402653183]	auto[1]	38	1			T103	2		T69	2		T118	2
auto[402653184:536870911]	auto[0]	146	1			T47	2		T117	2		T104	2
auto[402653184:536870911]	auto[1]	64	1			T69	2		T402	2		T91	2
auto[536870912:671088639]	auto[0]	142	1			T6	2		T47	2		T24	2
auto[536870912:671088639]	auto[1]	76	1			T116	2		T42	2		T120	2
auto[671088640:805306367]	auto[0]	174	1			T64	2		T219	2		T103	2
auto[671088640:805306367]	auto[1]	50	1			T7	2		T89	2		T319	2
auto[805306368:939524095]	auto[0]	132	1			T19	2		T217	2		T104	2
auto[805306368:939524095]	auto[1]	72	1			T22	2		T7	2		T43	2
auto[939524096:1073741823]	auto[0]	162	1			T16	2		T6	2		T64	2
auto[939524096:1073741823]	auto[1]	42	1			T217	2		T207	2		T196	2
auto[1073741824:1207959551]	auto[0]	130	1			T116	2		T120	2		T8	2
auto[1073741824:1207959551]	auto[1]	66	1			T68	4		T70	2		T121	2
auto[1207959552:1342177279]	auto[0]	150	1			T16	2		T17	2		T18	2
auto[1207959552:1342177279]	auto[1]	70	1			T73	2		T68	2		T69	2
auto[1342177280:1476395007]	auto[0]	140	1			T29	2		T123	2		T105	2
auto[1342177280:1476395007]	auto[1]	52	1			T83	2		T103	2		T351	2
auto[1476395008:1610612735]	auto[0]	166	1			T24	2		T69	2		T120	2
auto[1476395008:1610612735]	auto[1]	66	1			T95	2		T96	2		T143	2
auto[1610612736:1744830463]	auto[0]	134	1			T6	2		T17	2		T123	2
auto[1610612736:1744830463]	auto[1]	62	1			T16	2		T83	2		T35	2
auto[1744830464:1879048191]	auto[0]	170	1			T6	2		T18	2		T23	2
auto[1744830464:1879048191]	auto[1]	60	1			T96	2		T333	2		T306	2
auto[1879048192:2013265919]	auto[0]	106	1			T31	2		T29	2		T30	2
auto[1879048192:2013265919]	auto[1]	72	1			T20	2		T95	2		T69	4
auto[2013265920:2147483647]	auto[0]	136	1			T47	2		T64	2		T25	2
auto[2013265920:2147483647]	auto[1]	70	1			T197	2		T118	2		T323	2
auto[2147483648:2281701375]	auto[0]	172	1			T47	2		T217	2		T69	4
auto[2147483648:2281701375]	auto[1]	72	1			T40	2		T64	2		T77	2
auto[2281701376:2415919103]	auto[0]	134	1			T23	2		T215	2		T69	2
auto[2281701376:2415919103]	auto[1]	68	1			T19	2		T64	2		T71	2
auto[2415919104:2550136831]	auto[0]	156	1			T23	2		T76	2		T116	2
auto[2415919104:2550136831]	auto[1]	66	1			T19	2		T96	2		T8	2
auto[2550136832:2684354559]	auto[0]	166	1			T16	2		T143	2		T69	2
auto[2550136832:2684354559]	auto[1]	50	1			T117	2		T127	2		T130	2
auto[2684354560:2818572287]	auto[0]	136	1			T17	2		T215	2		T69	2
auto[2684354560:2818572287]	auto[1]	70	1			T20	2		T218	2		T30	2
auto[2818572288:2952790015]	auto[0]	168	1			T23	2		T7	2		T215	2
auto[2818572288:2952790015]	auto[1]	66	1			T22	4		T77	2		T8	2
auto[2952790016:3087007743]	auto[0]	116	1			T16	2		T123	2		T30	2
auto[2952790016:3087007743]	auto[1]	54	1			T100	2		T8	2		T79	2
auto[3087007744:3221225471]	auto[0]	158	1			T23	2		T142	4		T104	2
auto[3087007744:3221225471]	auto[1]	62	1			T217	2		T104	2		T120	2
auto[3221225472:3355443199]	auto[0]	142	1			T69	2		T207	2		T52	2
auto[3221225472:3355443199]	auto[1]	60	1			T23	2		T207	2		T436	2
auto[3355443200:3489660927]	auto[0]	136	1			T40	2		T31	2		T96	4
auto[3355443200:3489660927]	auto[1]	56	1			T100	2		T69	2		T30	2
auto[3489660928:3623878655]	auto[0]	158	1			T68	2		T31	2		T122	2
auto[3489660928:3623878655]	auto[1]	80	1			T79	2		T174	2		T90	2
auto[3623878656:3758096383]	auto[0]	164	1			T17	2		T116	2		T7	2
auto[3623878656:3758096383]	auto[1]	86	1			T95	2		T217	2		T29	2
auto[3758096384:3892314111]	auto[0]	124	1			T17	2		T68	2		T8	2
auto[3758096384:3892314111]	auto[1]	54	1			T16	2		T9	2		T89	2
auto[3892314112:4026531839]	auto[0]	130	1			T16	2		T6	2		T17	2
auto[3892314112:4026531839]	auto[1]	60	1			T218	2		T8	2		T135	2
auto[4026531840:4160749567]	auto[0]	158	1			T16	2		T29	2		T69	2
auto[4026531840:4160749567]	auto[1]	78	1			T6	2		T83	2		T70	2
auto[4160749568:4294967295]	auto[0]	166	1			T18	2		T40	2		T116	2
auto[4160749568:4294967295]	auto[1]	82	1			T70	2		T218	2		T121	2