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 LINE       3159
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T41,T8,T79
1	1	1	Covered	T16,T6,T17

 LINE       3162
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T16
1	1	0	Covered	T79,T9,T89
1	1	1	Covered	T16,T6,T17

 LINE       3165
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T8,T79,T9
1	1	1	Covered	T16,T6,T17

 LINE       3168
 EXPRESSION (addr_hit[27] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T68,T79,T89
1	1	1	Covered	T16,T6,T17

 LINE       3171
 EXPRESSION (addr_hit[28] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T79,T9,T89
1	1	1	Covered	T16,T6,T17

 LINE       3174
 EXPRESSION (addr_hit[29] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T16
1	1	0	Covered	T68,T79,T9
1	1	1	Covered	T16,T6,T17

 LINE       3177
 EXPRESSION (addr_hit[30] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T16
1	1	0	Covered	T8,T79,T9
1	1	1	Covered	T16,T6,T17

 LINE       3180
 EXPRESSION (addr_hit[31] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T16
1	1	0	Covered	T68,T8,T79
1	1	1	Covered	T16,T6,T17

 LINE       3183
 EXPRESSION (addr_hit[32] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T79,T9,T91
1	1	1	Covered	T16,T6,T17

 LINE       3186
 EXPRESSION (addr_hit[33] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T68,T9,T94
1	1	1	Covered	T16,T6,T17

 LINE       3189
 EXPRESSION (addr_hit[34] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T68,T79,T9
1	1	1	Covered	T16,T6,T17

 LINE       3192
 EXPRESSION (addr_hit[35] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T68,T79,T9
1	1	1	Covered	T16,T6,T17

 LINE       3195
 EXPRESSION (addr_hit[36] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T68,T79,T9
1	1	1	Covered	T16,T6,T17

 LINE       3198
 EXPRESSION (addr_hit[37] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T16
1	1	0	Not Covered
1	1	1	Covered	T68,T8,T79

 LINE       3199
 EXPRESSION (addr_hit[37] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T3,T4,T16
1	1	0	Covered	T68,T8,T79
1	1	1	Covered	T16,T6,T17

 LINE       3202
 EXPRESSION (addr_hit[38] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T68,T8,T9
1	1	1	Covered	T16,T6,T17

 LINE       3205
 EXPRESSION (addr_hit[39] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Not Covered
1	1	1	Covered	T68,T8,T79

 LINE       3206
 EXPRESSION (addr_hit[39] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T8,T79,T9
1	1	1	Covered	T16,T6,T17

 LINE       3209
 EXPRESSION (addr_hit[40] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T68,T8,T79
1	1	1	Covered	T16,T6,T17

 LINE       3212
 EXPRESSION (addr_hit[41] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Not Covered
1	1	1	Covered	T68,T8,T79

 LINE       3213
 EXPRESSION (addr_hit[41] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T4,T16,T6
1	1	0	Covered	T68,T8,T9
1	1	1	Covered	T16,T6,T17

 LINE       3216
 EXPRESSION (addr_hit[42] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T155,T153,T156
1	1	1	Covered	T1,T2,T4

 LINE       3219
 EXPRESSION (addr_hit[43] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T157,T158
1	1	1	Covered	T1,T2,T4

 LINE       3222
 EXPRESSION (addr_hit[44] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T159,T160
1	1	1	Covered	T1,T2,T4

 LINE       3225
 EXPRESSION (addr_hit[45] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T161
1	1	1	Covered	T1,T2,T4

 LINE       3228
 EXPRESSION (addr_hit[46] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T45,T162
1	1	1	Covered	T1,T2,T4

 LINE       3231
 EXPRESSION (addr_hit[47] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       3234
 EXPRESSION (addr_hit[48] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T148,T163,T164
1	1	1	Covered	T1,T2,T4

 LINE       3237
 EXPRESSION (addr_hit[49] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T165,T160,T166
1	1	1	Covered	T1,T2,T4

 LINE       3240
 EXPRESSION (addr_hit[50] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T167,T153,T168
1	1	1	Covered	T1,T2,T4

 LINE       3243
 EXPRESSION (addr_hit[51] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T169
1	1	1	Covered	T1,T2,T4

 LINE       3246
 EXPRESSION (addr_hit[52] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T149,T170,T153
1	1	1	Covered	T1,T2,T4

 LINE       3249
 EXPRESSION (addr_hit[53] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T4

 LINE       3252
 EXPRESSION (addr_hit[54] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T153
1	1	1	Covered	T1,T2,T4

 LINE       3255
 EXPRESSION (addr_hit[55] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T171,T172,T164
1	1	1	Covered	T1,T2,T4

 LINE       3258
 EXPRESSION (addr_hit[56] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T173,T152,T153
1	1	1	Covered	T1,T2,T4

 LINE       3261
 EXPRESSION (addr_hit[57] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T164,T169
1	1	1	Covered	T1,T2,T4

 LINE       3264
 EXPRESSION (addr_hit[59] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T8,T9,T89
1	1	1	Covered	T147,T148,T149

 LINE       3267
 EXPRESSION (addr_hit[60] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T68,T79,T9
1	1	1	Covered	T1,T2,T4

 LINE       3274
 EXPRESSION (addr_hit[62] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T68,T79,T9
1	1	1	Covered	T19,T20,T31

 LINE       3665
 SUB-EXPRESSION (rst_done & shadow_rst_done)
                 ----1---   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T84,T80,T85
1	0	Covered	T80,T85,T81
1	1	Covered	T1,T2,T3