Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

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Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	46	1			T73	1		T62	1		T126	1
auto[OpGenId]	14	1			T39	1		T33	1		T211	2
auto[OpGenSwOut]	15	1			T56	1		T57	1		T122	1
auto[OpGenHwOut]	24	1			T4	1		T38	1		T128	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1772	1			T11	180		T62	1		T70	3
auto[StInit]	79	1			T73	1		T37	1		T38	1
auto[StCreatorRootKey]	51	1			T62	1		T21	1		T107	1
auto[StOwnerIntKey]	40	1			T4	1		T36	1		T35	1
auto[StOwnerKey]	34	1			T56	1		T126	1		T87	1
auto[StDisabled]	468	1			T62	3		T70	9		T63	4
auto[StInvalid]	50	1			T16	1		T47	1		T104	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3474

1

T1

1

T2

1

T3

1

auto[1]

99

1

T4

1

T73

1

T62

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1767	1			T11	180		T62	1		T70	3
auto[StReset]	auto[1]	5	1			T29	1		T129	1		T212	1
auto[StInit]	auto[0]	38	1			T37	1		T133	1		T87	1
auto[StInit]	auto[1]	41	1			T73	1		T38	1		T69	1
auto[StCreatorRootKey]	auto[0]	31	1			T21	1		T107	1		T40	1
auto[StCreatorRootKey]	auto[1]	20	1			T62	1		T122	1		T39	1
auto[StOwnerIntKey]	auto[0]	30	1			T36	1		T35	1		T28	1
auto[StOwnerIntKey]	auto[1]	10	1			T4	1		T57	1		T87	1
auto[StOwnerKey]	auto[0]	26	1			T56	1		T87	1		T89	1
auto[StOwnerKey]	auto[1]	8	1			T126	1		T134	1		T135	1
auto[StDisabled]	auto[0]	453	1			T62	3		T70	9		T63	4
auto[StDisabled]	auto[1]	15	1			T56	1		T6	1		T211	1
auto[StInvalid]	auto[0]	50	1			T16	1		T47	1		T104	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut]]	--	--	2
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	4	1			T29	1		T129	1		T130	1
auto[StReset]	auto[OpGenHwOut]	1	1			T212	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	11	1			T73	1		T213	1		T137	1
auto[StInit]	auto[OpGenId]	7	1			T33	1		T214	1		T196	1
auto[StInit]	auto[OpGenSwOut]	5	1			T69	1		T215	1		T216	1
auto[StInit]	auto[OpGenHwOut]	18	1			T38	1		T128	1		T5	1
auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T62	1		T138	1		T217	1
auto[StCreatorRootKey]	auto[OpGenId]	3	1			T39	1		T211	1		T218	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T122	1		T139	1		T197	1
auto[StCreatorRootKey]	auto[OpGenHwOut]	1	1			T219	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T87	1		T220	1		T197	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T184	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T57	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	1	1			T4	1		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	5	1			T126	1		T134	1		T135	1
auto[StOwnerKey]	auto[OpGenId]	1	1			T219	1		-	-		-	-
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T91	1		T221	1		-	-
auto[StDisabled]	auto[OpAdvance]	8	1			T6	1		T217	1		T222	1
auto[StDisabled]	auto[OpGenId]	2	1			T211	1		T223	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	4	1			T56	1		T224	1		T225	1
auto[StDisabled]	auto[OpGenHwOut]	1	1			T226	1		-	-		-	-