Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4834

1

T1

4

T2

12

T3

5

auto[1]

588

1

T14

4

T20

1

T64

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4834

1

T1

4

T2

12

T3

5

auto[1]

588

1

T14

4

T20

1

T64

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4864

1

T1

3

T2

12

T3

5

auto[1]

558

1

T1

1

T17

3

T18

3

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4864

1

T1

3

T2

12

T3

5

auto[1]

558

1

T1

1

T17

3

T18

3

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	423	1			T18	1		T19	3		T20	1
auto[OpGenId]	1197	1			T3	2		T15	2		T16	2
auto[OpGenSwOut]	1164	1			T1	1		T3	1		T4	1
auto[OpGenHwOut]	2551	1			T1	2		T2	12		T3	2
auto[OpDisable]	87	1			T1	1		T70	2		T68	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	423	1			T18	1		T19	3		T20	1
auto[OpGenId]	1197	1			T3	2		T15	2		T16	2
auto[OpGenSwOut]	1164	1			T1	1		T3	1		T4	1
auto[OpGenHwOut]	2551	1			T1	2		T2	12		T3	2
auto[OpDisable]	87	1			T1	1		T70	2		T68	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4879

1

T1

3

T2

9

T3

2

auto[1]

543

1

T1

1

T2

3

T3

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4879

1

T1

3

T2

9

T3

2

auto[1]

543

1

T1

1

T2

3

T3

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5146

1

T1

4

T2

12

T3

5

auto[1]

276

1

T19

5

T98

7

T100

11

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1844	1			T1	1		T2	5		T3	2
auto[1]	725	1			T1	1		T3	1		T16	1
auto[2]	682	1			T1	1		T3	1		T14	1
auto[3]	703	1			T1	1		T2	4		T14	3
auto[4]	335	1			T14	1		T18	1		T19	5
auto[5]	358	1			T2	2		T3	1		T14	2
auto[6]	386	1			T2	1		T15	1		T17	2
auto[7]	389	1			T16	1		T17	1		T19	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1468	1			T2	3		T3	1		T14	3
clear_one[1]	725	1			T1	1		T3	1		T16	1
clear_one[2]	682	1			T1	1		T3	1		T14	1
clear_one[3]	703	1			T1	1		T2	4		T14	3
clear_none	1844	1			T1	1		T2	5		T3	2

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1010	1			T2	4		T17	5		T43	1
auto[StInit]	648	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	575	1			T2	1		T3	1		T14	1
auto[StOwnerIntKey]	523	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	515	1			T2	1		T14	1		T17	1
auto[StDisabled]	1863	1			T1	2		T2	4		T3	2
auto[StInvalid]	288	1			T16	4		T47	6		T104	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1010	1			T2	4		T17	5		T43	1
auto[StInit]	648	1			T1	1		T2	1		T3	1
auto[StCreatorRootKey]	575	1			T2	1		T3	1		T14	1
auto[StOwnerIntKey]	523	1			T1	1		T2	1		T3	1
auto[StOwnerKey]	515	1			T2	1		T14	1		T17	1
auto[StDisabled]	1863	1			T1	2		T2	4		T3	2
auto[StInvalid]	288	1			T16	4		T47	6		T104	2

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	56	224	80.00	56

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	4
[auto[1] - auto[4]]	[auto[StReset]]	[auto[OpDisable]]	--	--	4
[auto[1] - auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	16
[auto[1] - auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[5]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	3
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T227	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	147	1			T24	1		T62	2		T47	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	162	1			T93	1		T74	1		T47	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	253	1			T2	2		T17	2		T43	1
auto[0]	auto[StInit]	auto[OpAdvance]	34	1			T20	1		T70	1		T48	1
auto[0]	auto[StInit]	auto[OpGenId]	89	1			T3	1		T73	1		T70	2
auto[0]	auto[StInit]	auto[OpGenSwOut]	93	1			T1	1		T4	1		T19	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	192	1			T14	1		T16	1		T61	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T70	1		T63	1		T149	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	46	1			T18	1		T63	1		T203	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	59	1			T42	1		T63	1		T108	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	73	1			T3	1		T64	1		T228	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	17	1			T108	1		T128	2		T229	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	29	1			T15	1		T70	1		T63	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	36	1			T62	1		T77	1		T108	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	58	1			T93	1		T228	1		T48	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T56	1		T149	1		T230	2
auto[0]	auto[StOwnerKey]	auto[OpGenId]	26	1			T106	1		T87	1		T128	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	31	1			T203	2		T108	1		T128	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	54	1			T2	1		T61	1		T95	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	24	1			T70	1		T98	1		T230	1
auto[0]	auto[StDisabled]	auto[OpGenId]	76	1			T15	1		T62	1		T70	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T43	1		T70	1		T128	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	153	1			T2	2		T17	1		T18	1
auto[0]	auto[StDisabled]	auto[OpDisable]	24	1			T77	1		T87	1		T128	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	14	1			T67	1		T231	1		T232	2
auto[0]	auto[StInvalid]	auto[OpGenId]	22	1			T47	1		T71	1		T231	2
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	18	1			T44	1		T233	1		T234	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	25	1			T47	1		T104	1		T46	1
auto[1]	auto[StReset]	auto[OpGenId]	25	1			T62	1		T235	1		T236	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	19	1			T128	1		T53	1		T237	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	49	1			T17	1		T95	1		T238	1
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T87	1		T239	1		T240	1
auto[1]	auto[StInit]	auto[OpGenId]	8	1			T108	1		T241	1		T143	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	9	1			T242	1		T243	1		T222	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	22	1			T95	1		T128	1		T244	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T109	1		T6	1		T245	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T70	1		T208	1		T87	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	20	1			T70	1		T204	1		T128	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T210	1		T246	1		T108	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T87	1		T109	1		T247	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T70	1		T63	1		T248	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	23	1			T208	1		T149	1		T128	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	33	1			T18	1		T95	1		T249	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T24	1		T217	1		T250	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	24	1			T74	1		T207	1		T89	2
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T109	1		T251	1		T211	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	46	1			T17	1		T92	1		T238	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	20	1			T18	1		T252	1		T229	1
auto[1]	auto[StDisabled]	auto[OpGenId]	59	1			T18	1		T70	2		T100	3
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	73	1			T3	1		T20	1		T64	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	130	1			T1	1		T61	1		T92	2
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T68	1		T69	1		T128	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	9	1			T46	2		T253	2		T254	1
auto[1]	auto[StInvalid]	auto[OpGenId]	10	1			T67	1		T255	1		T256	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T16	1		T235	1		T257	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T235	1		T131	1		T258	1
auto[2]	auto[StReset]	auto[OpGenId]	18	1			T74	1		T70	1		T208	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	22	1			T56	1		T128	1		T259	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	52	1			T62	1		T95	1		T107	1
auto[2]	auto[StInit]	auto[OpAdvance]	2	1			T128	1		T260	1		-	-
auto[2]	auto[StInit]	auto[OpGenId]	10	1			T128	1		T53	1		T261	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	9	1			T68	1		T148	1		T107	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	18	1			T262	1		T263	1		T264	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T24	1		T87	1		T265	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T98	1		T105	1		T266	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T69	1		T267	1		T250	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	44	1			T95	1		T199	1		T148	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T62	1		T56	1		T268	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T56	2		T207	1		T213	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T108	1		T110	1		T195	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T3	1		T17	1		T42	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T111	1		T269	1		T270	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	12	1			T128	1		T211	1		T222	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T105	1		T271	1		T222	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	35	1			T208	1		T98	1		T272	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	21	1			T56	1		T273	1		T236	1
auto[2]	auto[StDisabled]	auto[OpGenId]	56	1			T98	3		T194	1		T108	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T18	1		T20	1		T70	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	156	1			T14	1		T17	2		T20	1
auto[2]	auto[StDisabled]	auto[OpDisable]	18	1			T1	1		T242	1		T213	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	6	1			T274	1		T275	1		T276	1
auto[2]	auto[StInvalid]	auto[OpGenId]	12	1			T47	1		T67	1		T44	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T46	1		T277	1		T278	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T47	1		T71	1		T131	1
auto[3]	auto[StReset]	auto[OpGenId]	20	1			T47	2		T56	1		T202	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	15	1			T208	1		T136	1		T279	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	29	1			T2	2		T48	1		T280	1
auto[3]	auto[StInit]	auto[OpAdvance]	10	1			T128	1		T229	1		T49	1
auto[3]	auto[StInit]	auto[OpGenId]	15	1			T56	1		T281	1		T89	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	13	1			T26	1		T211	1		T271	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	15	1			T93	1		T282	1		T283	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	13	1			T284	1		T217	1		T285	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T140	1		T108	1		T286	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	8	1			T287	2		T288	1		T289	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	28	1			T14	1		T92	1		T290	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T229	1		T291	1		T197	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T70	1		T26	1		T69	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T195	1		T211	1		T217	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	47	1			T1	1		T2	1		T92	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T197	1		T292	1		T293	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	18	1			T70	1		T108	1		T281	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	17	1			T294	1		T295	1		T296	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	36	1			T14	1		T70	2		T228	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	20	1			T108	1		T87	1		T195	1
auto[3]	auto[StDisabled]	auto[OpGenId]	61	1			T20	1		T70	1		T56	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	46	1			T100	1		T106	3		T202	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	184	1			T2	1		T14	1		T17	1
auto[3]	auto[StDisabled]	auto[OpDisable]	10	1			T70	1		T213	1		T195	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	9	1			T71	1		T46	1		T257	1
auto[3]	auto[StInvalid]	auto[OpGenId]	12	1			T16	1		T67	1		T234	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T47	1		T235	1		T44	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T16	1		T131	1		T257	1
auto[4]	auto[StReset]	auto[OpGenId]	17	1			T236	1		T65	1		T297	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	10	1			T107	1		T298	1		T128	2
auto[4]	auto[StReset]	auto[OpGenHwOut]	20	1			T62	1		T207	1		T299	1
auto[4]	auto[StInit]	auto[OpAdvance]	3	1			T45	1		T300	1		T301	1
auto[4]	auto[StInit]	auto[OpGenId]	6	1			T241	1		T302	1		T303	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	4	1			T62	1		T25	1		T304	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	9	1			T305	1		T306	1		T143	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T56	1		T89	1		T307	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T257	1		T308	1		T302	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T309	1		T310	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T56	1		T87	1		T89	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T111	1		T112	1		T311	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T6	1		T197	1		T312	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T267	1		T250	1		T294	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	12	1			T14	1		T199	1		T282	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T313	1		T314	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	11	1			T18	1		T194	1		T195	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T128	1		T22	1		T91	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T19	1		T244	1		T6	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	19	1			T19	3		T62	1		T98	1
auto[4]	auto[StDisabled]	auto[OpGenId]	21	1			T209	1		T315	1		T213	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T70	1		T56	1		T106	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T19	1		T70	1		T210	1
auto[4]	auto[StDisabled]	auto[OpDisable]	7	1			T316	1		T224	1		T145	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T317	1		T318	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	5	1			T319	1		T320	1		T321	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T71	1		T322	1		T323	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T131	1		T279	1		T278	1
auto[5]	auto[StReset]	auto[OpGenId]	11	1			T74	1		T69	1		T231	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	9	1			T324	1		T266	1		T259	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	20	1			T238	1		T325	2		T264	1
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T207	1		T236	1		T326	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	6	1			T195	1		T45	1		T50	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	14	1			T2	1		T327	1		T328	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T26	1		T297	1		T91	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T110	1		T329	1		T144	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T128	1		T330	2		T331	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T17	1		T61	1		T57	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T192	1		T295	1		-	-
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T43	1		T70	1		T204	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T332	1		T333	1		T289	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T202	1		T305	1		T334	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T312	1		T147	1		-	-
auto[5]	auto[StOwnerKey]	auto[OpGenId]	11	1			T77	1		T108	1		T55	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T110	1		T143	1		T302	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T305	1		T335	1		T336	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	22	1			T74	1		T337	1		T109	1
auto[5]	auto[StDisabled]	auto[OpGenId]	29	1			T3	1		T19	2		T70	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	17	1			T70	2		T230	1		T291	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T2	1		T14	2		T228	1
auto[5]	auto[StDisabled]	auto[OpDisable]	8	1			T123	1		T108	1		T211	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	6	1			T338	1		T339	1		T322	1
auto[5]	auto[StInvalid]	auto[OpGenId]	8	1			T340	1		T338	1		T341	2
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T256	1		T342	1		T343	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T320	1		T344	1		T345	1
auto[6]	auto[StReset]	auto[OpGenId]	15	1			T128	1		T7	1		T281	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	15	1			T128	1		T229	1		T211	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	32	1			T17	1		T305	1		T244	1
auto[6]	auto[StInit]	auto[OpAdvance]	5	1			T62	1		T329	1		T91	1
auto[6]	auto[StInit]	auto[OpGenId]	6	1			T70	1		T91	1		T97	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	2	1			T69	1		T346	1		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	13	1			T17	1		T24	1		T280	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T74	1		T100	3		T347	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T43	1		T50	1		T220	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T62	1		T348	1		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T2	1		T77	1		T298	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T100	1		T221	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T56	1		T273	1		T128	2
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T87	1		T211	1		T243	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T210	1		T349	1		T280	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T62	1		T350	1		T351	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	10	1			T70	1		T352	1		T211	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T62	1		T267	1		T143	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T353	1		T128	1		T262	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	10	1			T48	1		T89	1		T354	1
auto[6]	auto[StDisabled]	auto[OpGenId]	35	1			T64	1		T56	1		T108	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	33	1			T15	1		T128	1		T229	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T210	1		T249	1		T280	1
auto[6]	auto[StDisabled]	auto[OpDisable]	3	1			T6	1		T91	1		T196	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	4	1			T257	1		T355	1		T344	1
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T277	1		T317	1		T356	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T234	1		T279	1		T357	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T66	1		T255	1		T358	1
auto[7]	auto[StReset]	auto[OpGenId]	16	1			T56	1		T38	1		T205	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	12	1			T70	2		T89	1		T359	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T17	1		T95	1		T305	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T28	1		T222	1		T270	1
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T6	1		T49	1		T360	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	7	1			T143	1		T45	1		T197	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	17	1			T105	1		T69	1		T213	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T269	1		T129	1		T361	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T69	1		T108	1		T128	2
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T108	1		T362	1		T363	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T364	1		T108	1		T280	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T108	1		T354	2		T222	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T19	1		T128	1		T217	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T19	1		T298	1		T128	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T365	1		T242	1		T262	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T284	1		T366	1		T367	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	5	1			T62	1		T267	1		T222	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T70	1		T121	1		T250	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T290	1		T249	1		T364	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	10	1			T113	1		T217	1		T354	1
auto[7]	auto[StDisabled]	auto[OpGenId]	30	1			T24	1		T108	2		T89	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T70	1		T48	1		T77	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	82	1			T61	1		T62	1		T95	2
auto[7]	auto[StDisabled]	auto[OpDisable]	7	1			T70	1		T141	1		T313	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	3	1			T255	1		T368	1		T369	1
auto[7]	auto[StInvalid]	auto[OpGenId]	6	1			T16	1		T47	1		T339	2
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T235	1		T338	1		T342	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T104	1		T253	1		T339	1