Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1468

1

T2

3

T3

1

T14

3

clear_one[1]

auto[0]

auto[0]

auto[0]

436

1

T16

1

T17

1

T18

2

clear_one[1]

auto[0]

auto[0]

auto[1]

133

1

T1

1

T3

1

T61

1

clear_one[1]

auto[0]

auto[1]

auto[0]

128

1

T17

1

T18

1

T70

4

clear_one[1]

auto[0]

auto[1]

auto[1]

28

1

T43

1

T70

1

T48

1

clear_one[2]

auto[0]

auto[0]

auto[0]

390

1

T1

1

T17

3

T42

1

clear_one[2]

auto[0]

auto[0]

auto[1]

122

1

T3

1

T18

1

T61

2

clear_one[2]

auto[1]

auto[0]

auto[0]

133

1

T14

1

T64

1

T92

1

clear_one[2]

auto[1]

auto[0]

auto[1]

37

1

T20

1

T56

1

T98

5

clear_one[3]

auto[0]

auto[0]

auto[0]

390

1

T2

4

T16

2

T61

1

clear_one[3]

auto[0]

auto[1]

auto[0]

117

1

T1

1

T17

1

T20

1

clear_one[3]

auto[1]

auto[0]

auto[0]

144

1

T14

3

T92

2

T100

1

clear_one[3]

auto[1]

auto[1]

auto[0]

52

1

T100

1

T106

3

T370

1

clear_none

auto[0]

auto[0]

auto[0]

1318

1

T1

1

T2

2

T3

1

clear_none

auto[0]

auto[0]

auto[1]

133

1

T2

3

T3

1

T61

1

clear_none

auto[0]

auto[1]

auto[0]

142

1

T17

1

T18

1

T64

1

clear_none

auto[0]

auto[1]

auto[1]

29

1

T18

1

T43

2

T87

2

clear_none

auto[1]

auto[0]

auto[0]

129

1

T92

1

T93

1

T70

1

clear_none

auto[1]

auto[0]

auto[1]

31

1

T98

1

T100

1

T121

1

clear_none

auto[1]

auto[1]

auto[0]

32

1

T63

1

T108

2

T236

1

clear_none

auto[1]

auto[1]

auto[1]

30

1

T70

1

T56

1

T371

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1398	1			T2	3		T3	1		T14	3
clear_all	auto[1]	70	1			T19	5		T98	1		T100	3
clear_one[1]	auto[0]	671	1			T1	1		T3	1		T16	1
clear_one[1]	auto[1]	54	1			T100	4		T121	4		T203	3
clear_one[2]	auto[0]	651	1			T1	1		T3	1		T14	1
clear_one[2]	auto[1]	31	1			T98	6		T111	3		T112	1
clear_one[3]	auto[0]	666	1			T1	1		T2	4		T14	3
clear_one[3]	auto[1]	37	1			T100	1		T106	2		T229	1
clear_none	auto[0]	1760	1			T1	1		T2	5		T3	2
clear_none	auto[1]	84	1			T100	3		T121	3		T203	3