Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11183

1

T1

4

T2

12

T3

4

auto[Attestation]

7878

1

T1

5

T2

4

T3

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2862	1			T1	1		T4	1		T15	2
auto[Aes]	3411	1			T3	2		T4	4		T14	8
auto[Kmac]	3405	1			T1	2		T16	1		T17	19
auto[Otbn]	3389	1			T1	5		T2	16		T3	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7650	1			T1	4		T2	8		T3	8
auto[OpGenId]	5994	1			T1	1		T3	5		T4	2
auto[OpGenSwOut]	6013	1			T1	4		T3	1		T4	3
auto[OpGenHwOut]	7054	1			T1	4		T2	16		T3	4
auto[OpDisable]	161	1			T1	1		T93	1		T70	3

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10774

1

T1

9

T2

8

T3

8

auto[OpDoneFail]

16098

1

T1

5

T2

16

T3

10

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6530	1			T1	1		T2	9		T3	3
auto[StInit]	3814	1			T1	3		T2	2		T3	2
auto[StCreatorRootKey]	3189	1			T1	5		T2	2		T3	2
auto[StOwnerIntKey]	2841	1			T1	2		T2	2		T3	2
auto[StOwnerKey]	2555	1			T2	2		T3	2		T14	2
auto[StDisabled]	7943	1			T1	3		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	336	1			T43	1		T93	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	113	1			T35	1		T25	1		T70	4
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	81	1			T18	1		T42	1		T21	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	83	1			T19	1		T20	2		T105	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	57	1			T18	1		T202	1		T203	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	214	1			T64	1		T43	3		T93	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	344	1			T93	3		T24	1		T62	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	114	1			T15	1		T19	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	89	1			T36	1		T63	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	81	1			T42	1		T24	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	50	1			T56	1		T204	1		T205	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	213	1			T18	3		T19	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	295	1			T43	1		T24	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	83	1			T24	1		T56	1		T204	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	96	1			T36	1		T62	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	80	1			T35	1		T43	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	63	1			T18	1		T70	1		T63	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	219	1			T1	1		T18	1		T20	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	335	1			T93	1		T62	1		T74	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	111	1			T1	1		T42	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	101	1			T70	1		T56	1		T101	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	69	1			T24	1		T62	2		T56	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	54	1			T70	1		T56	2		T77	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	214	1			T15	2		T20	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	79	1			T70	2		T108	2		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	103	1			T4	1		T24	1		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	99	1			T1	1		T19	1		T20	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	81	1			T98	1		T105	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T70	2		T105	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	229	1			T15	1		T19	1		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	87	1			T70	3		T63	1		T108	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	111	1			T4	1		T19	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	64	1			T4	1		T62	1		T70	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	84	1			T24	1		T70	1		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	65	1			T207	1		T108	1		T87	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	207	1			T43	1		T93	2		T70	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	85	1			T70	1		T108	4		T87	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	107	1			T25	2		T63	1		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	94	1			T16	1		T93	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T75	1		T56	1		T178	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	61	1			T62	1		T70	1		T56	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	214	1			T24	1		T70	1		T56	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	84	1			T63	1		T108	2		T128	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	109	1			T1	1		T25	3		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	75	1			T62	1		T76	1		T77	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	64	1			T93	1		T24	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	86	1			T19	1		T43	1		T70	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	199	1			T3	1		T18	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	269	1			T93	1		T62	3		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	118	1			T70	1		T63	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	65	1			T43	1		T70	1		T106	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	62	1			T56	1		T140	1		T78	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	71	1			T70	2		T56	1		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	187	1			T18	1		T19	2		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	423	1			T3	1		T93	1		T62	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	123	1			T14	1		T92	1		T25	5
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	102	1			T4	1		T14	1		T92	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	103	1			T42	1		T74	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	93	1			T92	1		T76	1		T210	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	275	1			T3	1		T14	2		T92	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	536	1			T17	11		T43	1		T24	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	103	1			T25	4		T95	1		T107	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	95	1			T18	1		T64	1		T70	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T1	1		T42	1		T70	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	89	1			T20	1		T76	2		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	290	1			T17	2		T19	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	422	1			T2	8		T43	1		T93	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	129	1			T36	1		T61	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	93	1			T1	1		T2	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	100	1			T4	1		T61	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	94	1			T61	1		T76	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	288	1			T2	3		T18	1		T20	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	71	1			T70	2		T68	1		T128	6
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	100	1			T16	1		T36	2		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T70	2		T63	1		T56	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	54	1			T63	1		T121	1		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	60	1			T15	1		T20	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	198	1			T20	1		T70	1		T63	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	75	1			T70	1		T108	3		T87	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	99	1			T4	1		T16	1		T93	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	116	1			T210	1		T56	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	111	1			T14	1		T18	1		T92	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	96	1			T14	1		T64	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	286	1			T14	2		T20	1		T64	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	62	1			T70	1		T68	1		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	128	1			T17	1		T103	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T17	1		T35	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T17	1		T42	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	79	1			T17	1		T43	1		T70	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	274	1			T17	2		T18	1		T20	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	85	1			T70	4		T63	2		T87	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	106	1			T2	1		T43	1		T62	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	108	1			T1	1		T3	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T2	1		T3	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	97	1			T2	1		T19	1		T76	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	273	1			T1	1		T2	1		T61	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	201	1			T18	2		T19	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	683	1			T20	2		T35	1		T64	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	200	1			T42	1		T36	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	691	1			T15	1		T18	3		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	223	1			T18	1		T36	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	613	1			T1	1		T18	1		T20	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	206	1			T24	1		T62	2		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	678	1			T1	1		T15	2		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	220	1			T1	1		T19	1		T20	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	430	1			T4	1		T15	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	205	1			T4	1		T24	1		T62	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	413	1			T4	1		T19	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	205	1			T93	1		T62	2		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	428	1			T16	1		T24	1		T25	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	211	1			T19	1		T43	1		T93	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	406	1			T1	1		T3	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	174	1			T43	1		T70	2		T56	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	598	1			T18	1		T19	2		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	289	1			T4	1		T14	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	830	1			T3	2		T14	3		T92	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	259	1			T1	1		T18	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	941	1			T17	13		T19	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	279	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	847	1			T2	11		T18	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	166	1			T15	1		T70	1		T63	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	390	1			T16	1		T36	2		T20	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	308	1			T14	2		T18	1		T64	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	475	1			T4	1		T14	2		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	252	1			T17	3		T42	1		T35	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	484	1			T17	3		T18	1		T20	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	280	1			T1	1		T2	2		T3	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	482	1			T1	1		T2	2		T61	2