Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32815

1

T1

17

T2

27

T3

22

auto[1]

289

1

T19

4

T98

7

T100

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32817	1			T1	17		T2	27		T3	22
auto[134217728:268435455]	17	1			T19	1		T229	1		T111	1
auto[268435456:402653183]	13	1			T229	1		T113	1		T287	2
auto[402653184:536870911]	5	1			T287	1		T402	1		T363	1
auto[536870912:671088639]	15	1			T229	1		T402	1		T330	1
auto[671088640:805306367]	8	1			T112	1		T287	1		T403	1
auto[805306368:939524095]	12	1			T111	1		T404	2		T403	1
auto[939524096:1073741823]	2	1			T405	1		T406	1		-	-
auto[1073741824:1207959551]	7	1			T121	1		T354	1		T407	2
auto[1207959552:1342177279]	10	1			T19	1		T230	1		T229	1
auto[1342177280:1476395007]	7	1			T113	1		T287	1		T408	1
auto[1476395008:1610612735]	16	1			T98	2		T100	2		T121	1
auto[1610612736:1744830463]	12	1			T100	1		T111	1		T287	1
auto[1744830464:1879048191]	1	1			T112	1		-	-		-	-
auto[1879048192:2013265919]	10	1			T100	1		T229	1		T354	1
auto[2013265920:2147483647]	7	1			T121	1		T203	1		T227	1
auto[2147483648:2281701375]	8	1			T98	1		T227	1		T409	1
auto[2281701376:2415919103]	14	1			T203	1		T230	1		T287	2
auto[2415919104:2550136831]	7	1			T19	1		T229	1		T354	1
auto[2550136832:2684354559]	9	1			T229	1		T112	1		T113	1
auto[2684354560:2818572287]	13	1			T98	1		T106	1		T203	1
auto[2818572288:2952790015]	8	1			T106	1		T112	1		T410	1
auto[2952790016:3087007743]	15	1			T98	1		T203	1		T112	1
auto[3087007744:3221225471]	9	1			T111	1		T113	1		T287	2
auto[3221225472:3355443199]	8	1			T100	1		T112	1		T404	1
auto[3355443200:3489660927]	11	1			T203	1		T109	1		T112	1
auto[3489660928:3623878655]	5	1			T270	1		T408	1		T411	1
auto[3623878656:3758096383]	9	1			T98	1		T383	1		T112	1
auto[3758096384:3892314111]	5	1			T19	1		T112	1		T227	1
auto[3892314112:4026531839]	9	1			T229	1		T112	1		T287	2
auto[4026531840:4160749567]	9	1			T106	1		T230	1		T354	1
auto[4160749568:4294967295]	6	1			T404	1		T330	1		T411	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32815	1			T1	17		T2	27		T3	22
auto[0:134217727]	auto[1]	2	1			T98	1		T412	1		-	-
auto[134217728:268435455]	auto[1]	17	1			T19	1		T229	1		T111	1
auto[268435456:402653183]	auto[1]	13	1			T229	1		T113	1		T287	2
auto[402653184:536870911]	auto[1]	5	1			T287	1		T402	1		T363	1
auto[536870912:671088639]	auto[1]	15	1			T229	1		T402	1		T330	1
auto[671088640:805306367]	auto[1]	8	1			T112	1		T287	1		T403	1
auto[805306368:939524095]	auto[1]	12	1			T111	1		T404	2		T403	1
auto[939524096:1073741823]	auto[1]	2	1			T405	1		T406	1		-	-
auto[1073741824:1207959551]	auto[1]	7	1			T121	1		T354	1		T407	2
auto[1207959552:1342177279]	auto[1]	10	1			T19	1		T230	1		T229	1
auto[1342177280:1476395007]	auto[1]	7	1			T113	1		T287	1		T408	1
auto[1476395008:1610612735]	auto[1]	16	1			T98	2		T100	2		T121	1
auto[1610612736:1744830463]	auto[1]	12	1			T100	1		T111	1		T287	1
auto[1744830464:1879048191]	auto[1]	1	1			T112	1		-	-		-	-
auto[1879048192:2013265919]	auto[1]	10	1			T100	1		T229	1		T354	1
auto[2013265920:2147483647]	auto[1]	7	1			T121	1		T203	1		T227	1
auto[2147483648:2281701375]	auto[1]	8	1			T98	1		T227	1		T409	1
auto[2281701376:2415919103]	auto[1]	14	1			T203	1		T230	1		T287	2
auto[2415919104:2550136831]	auto[1]	7	1			T19	1		T229	1		T354	1
auto[2550136832:2684354559]	auto[1]	9	1			T229	1		T112	1		T113	1
auto[2684354560:2818572287]	auto[1]	13	1			T98	1		T106	1		T203	1
auto[2818572288:2952790015]	auto[1]	8	1			T106	1		T112	1		T410	1
auto[2952790016:3087007743]	auto[1]	15	1			T98	1		T203	1		T112	1
auto[3087007744:3221225471]	auto[1]	9	1			T111	1		T113	1		T287	2
auto[3221225472:3355443199]	auto[1]	8	1			T100	1		T112	1		T404	1
auto[3355443200:3489660927]	auto[1]	11	1			T203	1		T109	1		T112	1
auto[3489660928:3623878655]	auto[1]	5	1			T270	1		T408	1		T411	1
auto[3623878656:3758096383]	auto[1]	9	1			T98	1		T383	1		T112	1
auto[3758096384:3892314111]	auto[1]	5	1			T19	1		T112	1		T227	1
auto[3892314112:4026531839]	auto[1]	9	1			T229	1		T112	1		T287	2
auto[4026531840:4160749567]	auto[1]	9	1			T106	1		T230	1		T354	1
auto[4160749568:4294967295]	auto[1]	6	1			T404	1		T330	1		T411	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1550

1

T4

2

T19

2

T42

1

auto[1]

1843

1

T1

1

T4

2

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T73	1		T74	2		T70	1
auto[134217728:268435455]	99	1			T16	1		T19	1		T62	1
auto[268435456:402653183]	116	1			T62	1		T70	1		T63	1
auto[402653184:536870911]	118	1			T20	1		T24	1		T74	1
auto[536870912:671088639]	112	1			T21	1		T105	1		T26	3
auto[671088640:805306367]	95	1			T24	1		T70	1		T63	1
auto[805306368:939524095]	109	1			T42	1		T47	1		T98	2
auto[939524096:1073741823]	107	1			T93	1		T25	1		T70	2
auto[1073741824:1207959551]	90	1			T47	1		T48	1		T38	1
auto[1207959552:1342177279]	96	1			T4	1		T93	1		T24	1
auto[1342177280:1476395007]	126	1			T70	1		T209	1		T140	1
auto[1476395008:1610612735]	110	1			T43	1		T62	1		T47	2
auto[1610612736:1744830463]	109	1			T25	1		T70	2		T56	1
auto[1744830464:1879048191]	101	1			T18	1		T25	1		T56	1
auto[1879048192:2013265919]	97	1			T4	1		T19	1		T36	1
auto[2013265920:2147483647]	112	1			T43	1		T70	2		T104	1
auto[2147483648:2281701375]	98	1			T43	1		T57	1		T100	1
auto[2281701376:2415919103]	119	1			T76	1		T70	2		T56	3
auto[2415919104:2550136831]	120	1			T4	1		T93	1		T62	1
auto[2550136832:2684354559]	94	1			T62	2		T47	1		T25	1
auto[2684354560:2818572287]	118	1			T1	1		T18	1		T74	2
auto[2818572288:2952790015]	99	1			T43	1		T73	1		T47	1
auto[2952790016:3087007743]	109	1			T4	1		T62	1		T74	1
auto[3087007744:3221225471]	108	1			T16	1		T73	1		T76	1
auto[3221225472:3355443199]	102	1			T43	1		T24	1		T47	1
auto[3355443200:3489660927]	119	1			T20	1		T43	2		T93	1
auto[3489660928:3623878655]	100	1			T93	1		T24	1		T70	1
auto[3623878656:3758096383]	105	1			T42	1		T47	1		T70	1
auto[3758096384:3892314111]	82	1			T98	2		T77	1		T71	1
auto[3892314112:4026531839]	102	1			T43	1		T73	1		T70	1
auto[4026531840:4160749567]	101	1			T93	1		T62	1		T74	1
auto[4160749568:4294967295]	121	1			T19	2		T62	1		T70	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	42	1			T73	1		T102	1		T104	1
auto[0:134217727]	auto[1]	57	1			T74	2		T70	1		T204	1
auto[134217728:268435455]	auto[0]	39	1			T19	1		T124	1		T231	1
auto[134217728:268435455]	auto[1]	60	1			T16	1		T62	1		T70	2
auto[268435456:402653183]	auto[0]	58	1			T62	1		T70	1		T63	1
auto[268435456:402653183]	auto[1]	58	1			T69	1		T203	1		T127	1
auto[402653184:536870911]	auto[0]	50	1			T24	1		T74	1		T70	1
auto[402653184:536870911]	auto[1]	68	1			T20	1		T70	1		T122	1
auto[536870912:671088639]	auto[0]	49	1			T203	1		T231	1		T133	2
auto[536870912:671088639]	auto[1]	63	1			T21	1		T105	1		T26	3
auto[671088640:805306367]	auto[0]	47	1			T24	1		T63	1		T98	1
auto[671088640:805306367]	auto[1]	48	1			T70	1		T57	1		T203	1
auto[805306368:939524095]	auto[0]	62	1			T47	1		T98	2		T204	1
auto[805306368:939524095]	auto[1]	47	1			T42	1		T104	1		T26	1
auto[939524096:1073741823]	auto[0]	47	1			T93	1		T25	1		T107	1
auto[939524096:1073741823]	auto[1]	60	1			T70	2		T104	1		T235	1
auto[1073741824:1207959551]	auto[0]	40	1			T47	1		T38	1		T128	1
auto[1073741824:1207959551]	auto[1]	50	1			T48	1		T108	1		T87	2
auto[1207959552:1342177279]	auto[0]	47	1			T4	1		T93	1		T24	1
auto[1207959552:1342177279]	auto[1]	49	1			T70	1		T57	1		T69	1
auto[1342177280:1476395007]	auto[0]	54	1			T70	1		T107	1		T69	1
auto[1342177280:1476395007]	auto[1]	72	1			T209	1		T140	1		T77	1
auto[1476395008:1610612735]	auto[0]	52	1			T62	1		T47	2		T70	1
auto[1476395008:1610612735]	auto[1]	58	1			T43	1		T70	1		T100	1
auto[1610612736:1744830463]	auto[0]	49	1			T25	1		T70	1		T56	1
auto[1610612736:1744830463]	auto[1]	60	1			T70	1		T48	1		T121	1
auto[1744830464:1879048191]	auto[0]	54	1			T25	1		T56	1		T122	1
auto[1744830464:1879048191]	auto[1]	47	1			T18	1		T209	1		T108	1
auto[1879048192:2013265919]	auto[0]	46	1			T36	1		T20	1		T62	1
auto[1879048192:2013265919]	auto[1]	51	1			T4	1		T19	1		T25	1
auto[2013265920:2147483647]	auto[0]	55	1			T43	1		T70	1		T104	1
auto[2013265920:2147483647]	auto[1]	57	1			T70	1		T106	1		T26	1
auto[2147483648:2281701375]	auto[0]	47	1			T43	1		T100	1		T324	1
auto[2147483648:2281701375]	auto[1]	51	1			T57	1		T209	1		T67	1
auto[2281701376:2415919103]	auto[0]	54	1			T70	1		T56	2		T48	1
auto[2281701376:2415919103]	auto[1]	65	1			T76	1		T70	1		T56	1
auto[2415919104:2550136831]	auto[0]	64	1			T4	1		T93	1		T62	1
auto[2415919104:2550136831]	auto[1]	56	1			T70	1		T231	1		T89	1
auto[2550136832:2684354559]	auto[0]	34	1			T25	1		T63	1		T337	1
auto[2550136832:2684354559]	auto[1]	60	1			T62	2		T47	1		T70	1
auto[2684354560:2818572287]	auto[0]	52	1			T74	1		T56	1		T105	1
auto[2684354560:2818572287]	auto[1]	66	1			T1	1		T18	1		T74	1
auto[2818572288:2952790015]	auto[0]	46	1			T43	1		T73	1		T47	1
auto[2818572288:2952790015]	auto[1]	53	1			T70	1		T56	1		T104	1
auto[2952790016:3087007743]	auto[0]	55	1			T62	1		T74	1		T63	1
auto[2952790016:3087007743]	auto[1]	54	1			T4	1		T70	2		T149	1
auto[3087007744:3221225471]	auto[0]	41	1			T69	1		T88	1		T136	1
auto[3087007744:3221225471]	auto[1]	67	1			T16	1		T73	1		T76	1
auto[3221225472:3355443199]	auto[0]	43	1			T47	1		T67	1		T46	1
auto[3221225472:3355443199]	auto[1]	59	1			T43	1		T24	1		T56	1
auto[3355443200:3489660927]	auto[0]	51	1			T20	1		T43	1		T93	1
auto[3355443200:3489660927]	auto[1]	68	1			T43	1		T70	2		T102	1
auto[3489660928:3623878655]	auto[0]	47	1			T149	1		T28	1		T122	1
auto[3489660928:3623878655]	auto[1]	53	1			T93	1		T24	1		T70	1
auto[3623878656:3758096383]	auto[0]	41	1			T42	1		T235	1		T238	1
auto[3623878656:3758096383]	auto[1]	64	1			T47	1		T70	1		T105	1
auto[3758096384:3892314111]	auto[0]	30	1			T98	2		T77	1		T71	1
auto[3758096384:3892314111]	auto[1]	52	1			T108	2		T128	1		T229	1
auto[3892314112:4026531839]	auto[0]	53	1			T43	1		T73	1		T70	1
auto[3892314112:4026531839]	auto[1]	49	1			T102	1		T122	1		T69	1
auto[4026531840:4160749567]	auto[0]	40	1			T93	1		T74	1		T235	1
auto[4026531840:4160749567]	auto[1]	61	1			T62	1		T70	2		T98	1
auto[4160749568:4294967295]	auto[0]	61	1			T19	1		T70	1		T149	1
auto[4160749568:4294967295]	auto[1]	60	1			T19	1		T62	1		T70	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1564

1

T4

3

T19

2

T42

1

auto[1]

1830

1

T1

1

T4

1

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T18	1		T47	1		T63	1
auto[134217728:268435455]	99	1			T4	1		T62	2		T70	1
auto[268435456:402653183]	101	1			T20	1		T47	1		T70	1
auto[402653184:536870911]	103	1			T20	1		T25	1		T70	2
auto[536870912:671088639]	120	1			T43	1		T70	1		T56	2
auto[671088640:805306367]	106	1			T4	1		T19	1		T24	1
auto[805306368:939524095]	95	1			T19	2		T62	1		T70	2
auto[939524096:1073741823]	108	1			T70	1		T38	1		T209	1
auto[1073741824:1207959551]	105	1			T74	1		T56	2		T106	1
auto[1207959552:1342177279]	91	1			T36	1		T73	1		T63	1
auto[1342177280:1476395007]	102	1			T62	1		T74	1		T70	1
auto[1476395008:1610612735]	123	1			T24	1		T70	3		T105	1
auto[1610612736:1744830463]	100	1			T24	1		T73	1		T62	1
auto[1744830464:1879048191]	92	1			T73	1		T47	1		T70	3
auto[1879048192:2013265919]	104	1			T62	1		T74	1		T47	1
auto[2013265920:2147483647]	122	1			T4	1		T43	1		T93	1
auto[2147483648:2281701375]	98	1			T43	1		T62	1		T70	1
auto[2281701376:2415919103]	110	1			T42	1		T43	1		T73	1
auto[2415919104:2550136831]	110	1			T1	1		T62	1		T74	1
auto[2550136832:2684354559]	99	1			T4	1		T70	1		T56	1
auto[2684354560:2818572287]	110	1			T20	1		T43	1		T62	1
auto[2818572288:2952790015]	118	1			T93	2		T73	1		T21	1
auto[2952790016:3087007743]	104	1			T74	1		T28	1		T67	1
auto[3087007744:3221225471]	113	1			T16	1		T93	1		T56	1
auto[3221225472:3355443199]	95	1			T43	1		T63	1		T56	1
auto[3355443200:3489660927]	107	1			T16	1		T19	1		T24	1
auto[3489660928:3623878655]	115	1			T56	1		T98	1		T102	1
auto[3623878656:3758096383]	110	1			T43	1		T70	2		T48	1
auto[3758096384:3892314111]	97	1			T18	1		T70	1		T105	1
auto[3892314112:4026531839]	128	1			T42	1		T43	1		T24	1
auto[4026531840:4160749567]	106	1			T93	1		T62	1		T74	1
auto[4160749568:4294967295]	110	1			T93	1		T25	1		T70	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	29	1			T47	1		T63	1		T202	1
auto[0:134217727]	auto[1]	64	1			T18	1		T124	1		T105	1
auto[134217728:268435455]	auto[0]	37	1			T4	1		T62	1		T127	1
auto[134217728:268435455]	auto[1]	62	1			T62	1		T70	1		T202	1
auto[268435456:402653183]	auto[0]	48	1			T47	1		T108	1		T128	1
auto[268435456:402653183]	auto[1]	53	1			T20	1		T70	1		T202	1
auto[402653184:536870911]	auto[0]	53	1			T20	1		T25	1		T63	2
auto[402653184:536870911]	auto[1]	50	1			T70	2		T69	1		T108	1
auto[536870912:671088639]	auto[0]	68	1			T70	1		T56	1		T107	1
auto[536870912:671088639]	auto[1]	52	1			T43	1		T56	1		T48	1
auto[671088640:805306367]	auto[0]	52	1			T4	1		T24	1		T74	1
auto[671088640:805306367]	auto[1]	54	1			T19	1		T70	1		T100	1
auto[805306368:939524095]	auto[0]	36	1			T19	1		T62	1		T104	1
auto[805306368:939524095]	auto[1]	59	1			T19	1		T70	2		T105	1
auto[939524096:1073741823]	auto[0]	48	1			T202	1		T231	1		T87	1
auto[939524096:1073741823]	auto[1]	60	1			T70	1		T38	1		T209	1
auto[1073741824:1207959551]	auto[0]	41	1			T56	1		T121	1		T46	1
auto[1073741824:1207959551]	auto[1]	64	1			T74	1		T56	1		T106	1
auto[1207959552:1342177279]	auto[0]	44	1			T73	1		T63	1		T124	1
auto[1207959552:1342177279]	auto[1]	47	1			T36	1		T69	1		T194	1
auto[1342177280:1476395007]	auto[0]	42	1			T62	1		T74	1		T104	1
auto[1342177280:1476395007]	auto[1]	60	1			T70	1		T209	1		T140	1
auto[1476395008:1610612735]	auto[0]	57	1			T70	1		T105	1		T127	1
auto[1476395008:1610612735]	auto[1]	66	1			T24	1		T70	2		T106	1
auto[1610612736:1744830463]	auto[0]	50	1			T73	1		T62	1		T70	1
auto[1610612736:1744830463]	auto[1]	50	1			T24	1		T70	1		T104	1
auto[1744830464:1879048191]	auto[0]	48	1			T73	1		T47	1		T149	2
auto[1744830464:1879048191]	auto[1]	44	1			T70	3		T102	1		T104	1
auto[1879048192:2013265919]	auto[0]	43	1			T62	1		T74	1		T47	1
auto[1879048192:2013265919]	auto[1]	61	1			T70	1		T57	1		T26	1
auto[2013265920:2147483647]	auto[0]	58	1			T4	1		T93	1		T48	1
auto[2013265920:2147483647]	auto[1]	64	1			T43	1		T47	1		T70	1
auto[2147483648:2281701375]	auto[0]	39	1			T62	1		T70	1		T56	1
auto[2147483648:2281701375]	auto[1]	59	1			T43	1		T63	1		T26	1
auto[2281701376:2415919103]	auto[0]	58	1			T43	1		T73	1		T47	1
auto[2281701376:2415919103]	auto[1]	52	1			T42	1		T70	1		T48	1
auto[2415919104:2550136831]	auto[0]	54	1			T62	1		T25	1		T70	1
auto[2415919104:2550136831]	auto[1]	56	1			T1	1		T74	1		T70	2
auto[2550136832:2684354559]	auto[0]	51	1			T70	1		T56	1		T98	1
auto[2550136832:2684354559]	auto[1]	48	1			T4	1		T71	1		T108	1
auto[2684354560:2818572287]	auto[0]	58	1			T20	1		T43	1		T62	1
auto[2684354560:2818572287]	auto[1]	52	1			T76	1		T56	1		T104	1
auto[2818572288:2952790015]	auto[0]	52	1			T93	2		T73	1		T47	1
auto[2818572288:2952790015]	auto[1]	66	1			T21	1		T70	3		T57	1
auto[2952790016:3087007743]	auto[0]	50	1			T74	1		T28	1		T69	1
auto[2952790016:3087007743]	auto[1]	54	1			T67	1		T194	1		T87	1
auto[3087007744:3221225471]	auto[0]	46	1			T93	1		T107	1		T238	2
auto[3087007744:3221225471]	auto[1]	67	1			T16	1		T56	1		T106	1
auto[3221225472:3355443199]	auto[0]	42	1			T122	1		T203	1		T324	1
auto[3221225472:3355443199]	auto[1]	53	1			T43	1		T63	1		T56	1
auto[3355443200:3489660927]	auto[0]	53	1			T19	1		T24	1		T56	1
auto[3355443200:3489660927]	auto[1]	54	1			T16	1		T26	1		T203	1
auto[3489660928:3623878655]	auto[0]	50	1			T98	1		T71	1		T69	1
auto[3489660928:3623878655]	auto[1]	65	1			T56	1		T102	1		T204	1
auto[3623878656:3758096383]	auto[0]	51	1			T43	1		T108	1		T46	2
auto[3623878656:3758096383]	auto[1]	59	1			T70	2		T48	1		T71	1
auto[3758096384:3892314111]	auto[0]	45	1			T67	1		T128	1		T7	1
auto[3758096384:3892314111]	auto[1]	52	1			T18	1		T70	1		T105	1
auto[3892314112:4026531839]	auto[0]	58	1			T42	1		T43	1		T24	1
auto[3892314112:4026531839]	auto[1]	70	1			T70	2		T56	1		T106	1
auto[4026531840:4160749567]	auto[0]	49	1			T93	1		T74	1		T47	1
auto[4026531840:4160749567]	auto[1]	57	1			T62	1		T25	2		T57	1
auto[4160749568:4294967295]	auto[0]	54	1			T25	1		T70	1		T38	1
auto[4160749568:4294967295]	auto[1]	56	1			T93	1		T70	1		T28	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1556

1

T4

2

T19

2

T20

2

auto[1]

1837

1

T1

1

T4

2

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T19	1		T24	1		T62	1
auto[134217728:268435455]	107	1			T24	1		T73	2		T235	1
auto[268435456:402653183]	104	1			T47	1		T76	1		T70	1
auto[402653184:536870911]	103	1			T93	1		T62	1		T21	1
auto[536870912:671088639]	87	1			T47	1		T70	2		T202	1
auto[671088640:805306367]	102	1			T20	1		T43	1		T74	1
auto[805306368:939524095]	84	1			T19	1		T70	1		T56	1
auto[939524096:1073741823]	127	1			T18	1		T42	1		T73	1
auto[1073741824:1207959551]	98	1			T20	1		T43	1		T74	1
auto[1207959552:1342177279]	111	1			T16	1		T43	2		T62	1
auto[1342177280:1476395007]	105	1			T25	1		T70	1		T63	1
auto[1476395008:1610612735]	102	1			T16	1		T20	1		T24	1
auto[1610612736:1744830463]	103	1			T93	1		T56	1		T48	1
auto[1744830464:1879048191]	112	1			T18	1		T70	1		T63	1
auto[1879048192:2013265919]	125	1			T62	1		T70	1		T56	1
auto[2013265920:2147483647]	122	1			T42	1		T74	1		T76	1
auto[2147483648:2281701375]	123	1			T4	1		T36	1		T74	1
auto[2281701376:2415919103]	89	1			T74	1		T26	1		T128	2
auto[2415919104:2550136831]	106	1			T93	1		T47	1		T70	3
auto[2550136832:2684354559]	110	1			T43	1		T73	1		T62	2
auto[2684354560:2818572287]	107	1			T70	3		T57	1		T38	1
auto[2818572288:2952790015]	94	1			T4	1		T19	1		T47	1
auto[2952790016:3087007743]	106	1			T1	1		T43	1		T93	1
auto[3087007744:3221225471]	111	1			T19	1		T62	1		T47	1
auto[3221225472:3355443199]	91	1			T43	1		T62	1		T25	1
auto[3355443200:3489660927]	128	1			T93	1		T73	1		T62	1
auto[3489660928:3623878655]	96	1			T4	1		T93	1		T25	1
auto[3623878656:3758096383]	95	1			T70	3		T56	2		T105	1
auto[3758096384:3892314111]	97	1			T70	1		T98	1		T209	1
auto[3892314112:4026531839]	117	1			T4	1		T43	1		T62	1
auto[4026531840:4160749567]	101	1			T70	1		T69	2		T231	1
auto[4160749568:4294967295]	124	1			T47	1		T100	1		T104	1