Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3008

1

T1

1

T4

2

T16

2

auto[1]

308

1

T19

9

T98

9

T100

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T16	1		T18	1		T20	1
auto[134217728:268435455]	112	1			T19	1		T43	1		T24	1
auto[268435456:402653183]	93	1			T62	1		T74	1		T70	2
auto[402653184:536870911]	106	1			T42	1		T204	1		T69	1
auto[536870912:671088639]	101	1			T24	1		T62	1		T70	2
auto[671088640:805306367]	96	1			T93	1		T63	1		T98	1
auto[805306368:939524095]	110	1			T24	1		T47	1		T76	1
auto[939524096:1073741823]	104	1			T20	1		T74	1		T100	1
auto[1073741824:1207959551]	103	1			T18	1		T19	3		T43	1
auto[1207959552:1342177279]	83	1			T19	1		T74	1		T70	3
auto[1342177280:1476395007]	105	1			T73	1		T62	1		T74	1
auto[1476395008:1610612735]	91	1			T93	1		T47	1		T70	2
auto[1610612736:1744830463]	103	1			T19	1		T70	2		T56	1
auto[1744830464:1879048191]	112	1			T19	1		T42	1		T47	1
auto[1879048192:2013265919]	105	1			T19	1		T93	1		T25	2
auto[2013265920:2147483647]	102	1			T93	1		T70	2		T102	1
auto[2147483648:2281701375]	109	1			T4	1		T24	1		T70	2
auto[2281701376:2415919103]	102	1			T1	1		T19	1		T43	1
auto[2415919104:2550136831]	92	1			T76	1		T100	2		T104	1
auto[2550136832:2684354559]	103	1			T19	1		T93	1		T25	1
auto[2684354560:2818572287]	102	1			T74	1		T56	1		T100	1
auto[2818572288:2952790015]	113	1			T43	1		T74	1		T25	1
auto[2952790016:3087007743]	118	1			T74	1		T57	1		T38	1
auto[3087007744:3221225471]	111	1			T24	1		T25	1		T70	3
auto[3221225472:3355443199]	98	1			T70	3		T56	2		T67	1
auto[3355443200:3489660927]	105	1			T36	1		T43	2		T62	1
auto[3489660928:3623878655]	115	1			T16	1		T62	1		T47	1
auto[3623878656:3758096383]	107	1			T19	1		T70	1		T56	2
auto[3758096384:3892314111]	109	1			T4	1		T21	1		T70	3
auto[3892314112:4026531839]	101	1			T70	2		T63	1		T98	2
auto[4026531840:4160749567]	91	1			T19	2		T20	1		T43	1
auto[4160749568:4294967295]	108	1			T43	1		T62	1		T98	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	97	1			T16	1		T18	1		T20	1
auto[0:134217727]	auto[1]	9	1			T203	1		T111	1		T402	1
auto[134217728:268435455]	auto[0]	103	1			T43	1		T24	1		T74	1
auto[134217728:268435455]	auto[1]	9	1			T19	1		T98	1		T229	1
auto[268435456:402653183]	auto[0]	86	1			T62	1		T74	1		T70	2
auto[268435456:402653183]	auto[1]	7	1			T113	1		T287	2		T407	2
auto[402653184:536870911]	auto[0]	93	1			T42	1		T204	1		T69	1
auto[402653184:536870911]	auto[1]	13	1			T203	1		T112	1		T287	2
auto[536870912:671088639]	auto[0]	93	1			T24	1		T62	1		T70	2
auto[536870912:671088639]	auto[1]	8	1			T121	1		T229	1		T287	1
auto[671088640:805306367]	auto[0]	85	1			T93	1		T63	1		T98	1
auto[671088640:805306367]	auto[1]	11	1			T230	1		T111	1		T113	1
auto[805306368:939524095]	auto[0]	101	1			T24	1		T47	1		T76	1
auto[805306368:939524095]	auto[1]	9	1			T229	1		T109	1		T287	1
auto[939524096:1073741823]	auto[0]	99	1			T20	1		T74	1		T104	1
auto[939524096:1073741823]	auto[1]	5	1			T100	1		T111	1		T330	1
auto[1073741824:1207959551]	auto[0]	92	1			T18	1		T19	1		T43	1
auto[1073741824:1207959551]	auto[1]	11	1			T19	2		T121	1		T111	1
auto[1207959552:1342177279]	auto[0]	73	1			T74	1		T70	3		T56	1
auto[1207959552:1342177279]	auto[1]	10	1			T19	1		T230	1		T229	1
auto[1342177280:1476395007]	auto[0]	94	1			T73	1		T62	1		T74	1
auto[1342177280:1476395007]	auto[1]	11	1			T98	2		T203	1		T230	1
auto[1476395008:1610612735]	auto[0]	84	1			T93	1		T47	1		T70	2
auto[1476395008:1610612735]	auto[1]	7	1			T230	1		T287	2		T427	1
auto[1610612736:1744830463]	auto[0]	95	1			T70	2		T56	1		T100	1
auto[1610612736:1744830463]	auto[1]	8	1			T19	1		T121	1		T287	1
auto[1744830464:1879048191]	auto[0]	102	1			T42	1		T47	1		T70	1
auto[1744830464:1879048191]	auto[1]	10	1			T19	1		T418	1		T285	3
auto[1879048192:2013265919]	auto[0]	95	1			T19	1		T93	1		T25	2
auto[1879048192:2013265919]	auto[1]	10	1			T98	1		T229	1		T354	2
auto[2013265920:2147483647]	auto[0]	94	1			T93	1		T70	2		T102	1
auto[2013265920:2147483647]	auto[1]	8	1			T112	1		T287	1		T404	1
auto[2147483648:2281701375]	auto[0]	103	1			T4	1		T24	1		T70	2
auto[2147483648:2281701375]	auto[1]	6	1			T404	1		T403	1		T424	1
auto[2281701376:2415919103]	auto[0]	93	1			T1	1		T19	1		T43	1
auto[2281701376:2415919103]	auto[1]	9	1			T203	1		T229	2		T330	1
auto[2415919104:2550136831]	auto[0]	83	1			T76	1		T104	1		T48	2
auto[2415919104:2550136831]	auto[1]	9	1			T100	2		T112	2		T285	1
auto[2550136832:2684354559]	auto[0]	90	1			T19	1		T93	1		T25	1
auto[2550136832:2684354559]	auto[1]	13	1			T229	1		T112	1		T404	1
auto[2684354560:2818572287]	auto[0]	95	1			T74	1		T56	1		T77	1
auto[2684354560:2818572287]	auto[1]	7	1			T100	1		T330	1		T408	1
auto[2818572288:2952790015]	auto[0]	99	1			T43	1		T74	1		T25	1
auto[2818572288:2952790015]	auto[1]	14	1			T98	1		T230	1		T237	1
auto[2952790016:3087007743]	auto[0]	105	1			T74	1		T57	1		T38	1
auto[2952790016:3087007743]	auto[1]	13	1			T121	1		T203	1		T229	1
auto[3087007744:3221225471]	auto[0]	102	1			T24	1		T25	1		T70	3
auto[3087007744:3221225471]	auto[1]	9	1			T98	1		T230	1		T383	1
auto[3221225472:3355443199]	auto[0]	88	1			T70	3		T56	2		T67	1
auto[3221225472:3355443199]	auto[1]	10	1			T287	2		T402	1		T403	1
auto[3355443200:3489660927]	auto[0]	92	1			T36	1		T43	2		T62	1
auto[3355443200:3489660927]	auto[1]	13	1			T98	2		T402	1		T404	1
auto[3489660928:3623878655]	auto[0]	104	1			T16	1		T62	1		T47	1
auto[3489660928:3623878655]	auto[1]	11	1			T106	1		T230	1		T383	1
auto[3623878656:3758096383]	auto[0]	96	1			T70	1		T56	2		T104	1
auto[3623878656:3758096383]	auto[1]	11	1			T19	1		T121	1		T111	1
auto[3758096384:3892314111]	auto[0]	101	1			T4	1		T21	1		T70	3
auto[3758096384:3892314111]	auto[1]	8	1			T229	1		T270	1		T409	1
auto[3892314112:4026531839]	auto[0]	91	1			T70	2		T63	1		T98	1
auto[3892314112:4026531839]	auto[1]	10	1			T98	1		T203	1		T230	1
auto[4026531840:4160749567]	auto[0]	82	1			T20	1		T43	1		T47	1
auto[4026531840:4160749567]	auto[1]	9	1			T19	2		T230	1		T287	1
auto[4160749568:4294967295]	auto[0]	98	1			T43	1		T62	1		T98	1
auto[4160749568:4294967295]	auto[1]	10	1			T229	1		T237	1		T287	1