Unified Coverage Report :: Group Instance : attest_sw_binding_6

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1557

1

T4

3

T19

2

T20

2

auto[1]

1836

1

T1

1

T4

1

T16

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T18	1		T106	1		T202	1
auto[134217728:268435455]	128	1			T43	1		T93	1		T62	1
auto[268435456:402653183]	108	1			T25	1		T70	3		T56	2
auto[402653184:536870911]	96	1			T4	1		T43	1		T24	1
auto[536870912:671088639]	97	1			T42	1		T56	1		T104	1
auto[671088640:805306367]	121	1			T62	2		T74	2		T70	3
auto[805306368:939524095]	100	1			T93	1		T76	1		T70	3
auto[939524096:1073741823]	99	1			T70	2		T107	1		T121	1
auto[1073741824:1207959551]	108	1			T4	1		T16	1		T62	1
auto[1207959552:1342177279]	96	1			T43	1		T93	1		T62	1
auto[1342177280:1476395007]	96	1			T19	1		T43	1		T125	1
auto[1476395008:1610612735]	117	1			T43	1		T47	1		T25	1
auto[1610612736:1744830463]	115	1			T24	1		T70	3		T63	1
auto[1744830464:1879048191]	105	1			T20	1		T62	1		T47	1
auto[1879048192:2013265919]	97	1			T20	1		T63	1		T104	1
auto[2013265920:2147483647]	111	1			T43	1		T93	1		T24	1
auto[2147483648:2281701375]	103	1			T62	2		T47	1		T70	1
auto[2281701376:2415919103]	114	1			T1	1		T73	1		T74	1
auto[2415919104:2550136831]	117	1			T42	1		T36	1		T21	1
auto[2550136832:2684354559]	116	1			T70	2		T57	1		T105	1
auto[2684354560:2818572287]	114	1			T4	1		T20	1		T47	1
auto[2818572288:2952790015]	97	1			T16	1		T43	1		T93	1
auto[2952790016:3087007743]	96	1			T24	1		T70	3		T209	1
auto[3087007744:3221225471]	116	1			T4	1		T18	1		T19	1
auto[3221225472:3355443199]	103	1			T73	1		T76	1		T70	1
auto[3355443200:3489660927]	89	1			T19	1		T98	1		T106	1
auto[3489660928:3623878655]	103	1			T47	1		T25	1		T70	1
auto[3623878656:3758096383]	96	1			T62	1		T74	1		T124	1
auto[3758096384:3892314111]	121	1			T93	1		T24	1		T73	1
auto[3892314112:4026531839]	117	1			T62	1		T47	1		T56	1
auto[4026531840:4160749567]	87	1			T43	1		T74	1		T47	1
auto[4160749568:4294967295]	108	1			T19	1		T73	1		T98	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	49	1			T202	1		T273	1		T88	1
auto[0:134217727]	auto[1]	53	1			T18	1		T106	1		T108	1
auto[134217728:268435455]	auto[0]	49	1			T62	1		T273	1		T128	1
auto[134217728:268435455]	auto[1]	79	1			T43	1		T93	1		T70	2
auto[268435456:402653183]	auto[0]	51	1			T25	1		T56	1		T98	1
auto[268435456:402653183]	auto[1]	57	1			T70	3		T56	1		T131	1
auto[402653184:536870911]	auto[0]	41	1			T43	1		T24	1		T70	1
auto[402653184:536870911]	auto[1]	55	1			T4	1		T70	1		T105	1
auto[536870912:671088639]	auto[0]	55	1			T56	1		T48	1		T149	1
auto[536870912:671088639]	auto[1]	42	1			T42	1		T104	1		T127	1
auto[671088640:805306367]	auto[0]	56	1			T74	1		T70	2		T69	2
auto[671088640:805306367]	auto[1]	65	1			T62	2		T74	1		T70	1
auto[805306368:939524095]	auto[0]	39	1			T93	1		T70	2		T127	1
auto[805306368:939524095]	auto[1]	61	1			T76	1		T70	1		T209	1
auto[939524096:1073741823]	auto[0]	46	1			T107	1		T231	1		T87	1
auto[939524096:1073741823]	auto[1]	53	1			T70	2		T121	1		T69	1
auto[1073741824:1207959551]	auto[0]	57	1			T4	1		T48	1		T235	1
auto[1073741824:1207959551]	auto[1]	51	1			T16	1		T62	1		T57	1
auto[1207959552:1342177279]	auto[0]	42	1			T43	1		T93	1		T62	1
auto[1207959552:1342177279]	auto[1]	54	1			T25	1		T100	1		T102	1
auto[1342177280:1476395007]	auto[0]	46	1			T122	1		T108	1		T236	1
auto[1342177280:1476395007]	auto[1]	50	1			T19	1		T43	1		T125	1
auto[1476395008:1610612735]	auto[0]	50	1			T43	1		T25	1		T104	1
auto[1476395008:1610612735]	auto[1]	67	1			T47	1		T102	1		T209	1
auto[1610612736:1744830463]	auto[0]	49	1			T24	1		T70	1		T56	1
auto[1610612736:1744830463]	auto[1]	66	1			T70	2		T63	1		T104	1
auto[1744830464:1879048191]	auto[0]	51	1			T20	1		T62	1		T47	1
auto[1744830464:1879048191]	auto[1]	54	1			T70	2		T102	1		T413	1
auto[1879048192:2013265919]	auto[0]	45	1			T104	1		T238	1		T231	1
auto[1879048192:2013265919]	auto[1]	52	1			T20	1		T63	1		T38	1
auto[2013265920:2147483647]	auto[0]	57	1			T43	1		T93	1		T24	1
auto[2013265920:2147483647]	auto[1]	54	1			T74	1		T47	1		T70	1
auto[2147483648:2281701375]	auto[0]	47	1			T62	2		T47	1		T70	1
auto[2147483648:2281701375]	auto[1]	56	1			T56	1		T104	1		T235	1
auto[2281701376:2415919103]	auto[0]	47	1			T73	1		T63	1		T105	1
auto[2281701376:2415919103]	auto[1]	67	1			T1	1		T74	1		T70	2
auto[2415919104:2550136831]	auto[0]	45	1			T205	1		T141	1		T414	1
auto[2415919104:2550136831]	auto[1]	72	1			T42	1		T36	1		T21	1
auto[2550136832:2684354559]	auto[0]	47	1			T70	2		T204	1		T87	1
auto[2550136832:2684354559]	auto[1]	69	1			T57	1		T105	1		T149	1
auto[2684354560:2818572287]	auto[0]	62	1			T4	1		T20	1		T47	1
auto[2684354560:2818572287]	auto[1]	52	1			T56	1		T100	1		T105	1
auto[2818572288:2952790015]	auto[0]	46	1			T43	1		T93	1		T73	1
auto[2818572288:2952790015]	auto[1]	51	1			T16	1		T70	1		T56	1
auto[2952790016:3087007743]	auto[0]	47	1			T24	1		T252	1		T131	1
auto[2952790016:3087007743]	auto[1]	49	1			T70	3		T209	1		T67	1
auto[3087007744:3221225471]	auto[0]	58	1			T4	1		T19	1		T74	2
auto[3087007744:3221225471]	auto[1]	58	1			T18	1		T70	2		T124	1
auto[3221225472:3355443199]	auto[0]	46	1			T73	1		T107	1		T127	1
auto[3221225472:3355443199]	auto[1]	57	1			T76	1		T70	1		T26	1
auto[3355443200:3489660927]	auto[0]	38	1			T19	1		T238	1		T46	1
auto[3355443200:3489660927]	auto[1]	51	1			T98	1		T106	1		T149	1
auto[3489660928:3623878655]	auto[0]	52	1			T47	1		T25	1		T63	1
auto[3489660928:3623878655]	auto[1]	51	1			T70	1		T56	1		T69	2
auto[3623878656:3758096383]	auto[0]	50	1			T62	1		T74	1		T124	1
auto[3623878656:3758096383]	auto[1]	46	1			T48	1		T67	1		T87	2
auto[3758096384:3892314111]	auto[0]	57	1			T73	1		T47	1		T25	1
auto[3758096384:3892314111]	auto[1]	64	1			T93	1		T24	1		T48	1
auto[3892314112:4026531839]	auto[0]	51	1			T62	1		T47	1		T98	1
auto[3892314112:4026531839]	auto[1]	66	1			T56	1		T106	1		T122	1
auto[4026531840:4160749567]	auto[0]	40	1			T74	1		T47	1		T63	1
auto[4026531840:4160749567]	auto[1]	47	1			T43	1		T70	2		T56	1
auto[4160749568:4294967295]	auto[0]	41	1			T73	1		T98	2		T202	1
auto[4160749568:4294967295]	auto[1]	67	1			T19	1		T28	1		T205	1