| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.88 | 99.04 | 98.11 | 99.20 | 100.00 | 99.02 | 98.63 | 91.19 |
| T169 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.1738303670 | Aug 23 05:51:58 PM UTC 24 | Aug 23 05:52:07 PM UTC 24 | 269982819 ps | ||
| T1008 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.313658772 | Aug 23 05:51:59 PM UTC 24 | Aug 23 05:52:07 PM UTC 24 | 358716060 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.1751208121 | Aug 23 05:52:06 PM UTC 24 | Aug 23 05:52:08 PM UTC 24 | 69477963 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.2435887318 | Aug 23 05:52:04 PM UTC 24 | Aug 23 05:52:08 PM UTC 24 | 159442353 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.376578972 | Aug 23 05:52:06 PM UTC 24 | Aug 23 05:52:08 PM UTC 24 | 40321243 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.905911235 | Aug 23 05:52:06 PM UTC 24 | Aug 23 05:52:09 PM UTC 24 | 57580340 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.989022477 | Aug 23 05:52:04 PM UTC 24 | Aug 23 05:52:09 PM UTC 24 | 173957599 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.524878532 | Aug 23 05:52:07 PM UTC 24 | Aug 23 05:52:09 PM UTC 24 | 15023913 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.1848199162 | Aug 23 05:52:07 PM UTC 24 | Aug 23 05:52:09 PM UTC 24 | 39838818 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2624847840 | Aug 23 05:52:07 PM UTC 24 | Aug 23 05:52:10 PM UTC 24 | 31260013 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.775807430 | Aug 23 05:52:04 PM UTC 24 | Aug 23 05:52:10 PM UTC 24 | 215054263 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.3256339004 | Aug 23 05:52:07 PM UTC 24 | Aug 23 05:52:10 PM UTC 24 | 91149639 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3181401382 | Aug 23 05:52:06 PM UTC 24 | Aug 23 05:52:11 PM UTC 24 | 539096363 ps | ||
| T170 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.1250798739 | Aug 23 05:52:05 PM UTC 24 | Aug 23 05:52:11 PM UTC 24 | 289870795 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.2292004992 | Aug 23 05:52:08 PM UTC 24 | Aug 23 05:52:11 PM UTC 24 | 29454369 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.1360926618 | Aug 23 05:52:09 PM UTC 24 | Aug 23 05:52:12 PM UTC 24 | 109587990 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2227252385 | Aug 23 05:52:07 PM UTC 24 | Aug 23 05:52:12 PM UTC 24 | 127385203 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1860122512 | Aug 23 05:52:08 PM UTC 24 | Aug 23 05:52:12 PM UTC 24 | 221145518 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3845629471 | Aug 23 05:52:09 PM UTC 24 | Aug 23 05:52:12 PM UTC 24 | 91696823 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.3981783395 | Aug 23 05:52:11 PM UTC 24 | Aug 23 05:52:13 PM UTC 24 | 9747178 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2847390525 | Aug 23 05:52:10 PM UTC 24 | Aug 23 05:52:13 PM UTC 24 | 326987217 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.481857934 | Aug 23 05:52:09 PM UTC 24 | Aug 23 05:52:14 PM UTC 24 | 131319409 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.593828569 | Aug 23 05:52:12 PM UTC 24 | Aug 23 05:52:14 PM UTC 24 | 29828501 ps | ||
| T155 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.124445952 | Aug 23 05:52:07 PM UTC 24 | Aug 23 05:52:14 PM UTC 24 | 292011870 ps | ||
| T161 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.1365037819 | Aug 23 05:52:08 PM UTC 24 | Aug 23 05:52:14 PM UTC 24 | 478555188 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.1943084416 | Aug 23 05:52:08 PM UTC 24 | Aug 23 05:52:15 PM UTC 24 | 164076696 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.3807787198 | Aug 23 05:52:11 PM UTC 24 | Aug 23 05:52:15 PM UTC 24 | 47309916 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3183475060 | Aug 23 05:52:12 PM UTC 24 | Aug 23 05:52:15 PM UTC 24 | 73979903 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.3083640070 | Aug 23 05:52:13 PM UTC 24 | Aug 23 05:52:15 PM UTC 24 | 37619543 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3413846521 | Aug 23 05:52:12 PM UTC 24 | Aug 23 05:52:16 PM UTC 24 | 102214031 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2496134127 | Aug 23 05:52:08 PM UTC 24 | Aug 23 05:52:16 PM UTC 24 | 216315777 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3871300031 | Aug 23 05:52:14 PM UTC 24 | Aug 23 05:52:17 PM UTC 24 | 134561658 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.2808057529 | Aug 23 05:52:14 PM UTC 24 | Aug 23 05:52:17 PM UTC 24 | 26001095 ps | ||
| T176 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.1154830494 | Aug 23 05:52:11 PM UTC 24 | Aug 23 05:52:17 PM UTC 24 | 150587747 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.563055047 | Aug 23 05:52:02 PM UTC 24 | Aug 23 05:52:17 PM UTC 24 | 467831976 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.1695321803 | Aug 23 05:52:15 PM UTC 24 | Aug 23 05:52:17 PM UTC 24 | 13067167 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.576717985 | Aug 23 05:52:13 PM UTC 24 | Aug 23 05:52:17 PM UTC 24 | 261988270 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.4154218018 | Aug 23 05:52:15 PM UTC 24 | Aug 23 05:52:17 PM UTC 24 | 48490807 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3784479177 | Aug 23 05:52:14 PM UTC 24 | Aug 23 05:52:17 PM UTC 24 | 54311929 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.1213926521 | Aug 23 05:52:16 PM UTC 24 | Aug 23 05:52:18 PM UTC 24 | 24061950 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1607678151 | Aug 23 05:52:15 PM UTC 24 | Aug 23 05:52:18 PM UTC 24 | 66579179 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4118334661 | Aug 23 05:52:13 PM UTC 24 | Aug 23 05:52:19 PM UTC 24 | 225649257 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.3111855268 | Aug 23 05:52:15 PM UTC 24 | Aug 23 05:52:19 PM UTC 24 | 44024760 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.2724125794 | Aug 23 05:52:17 PM UTC 24 | Aug 23 05:52:19 PM UTC 24 | 10194972 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.4043111254 | Aug 23 05:52:17 PM UTC 24 | Aug 23 05:52:19 PM UTC 24 | 14182875 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1273327900 | Aug 23 05:52:16 PM UTC 24 | Aug 23 05:52:19 PM UTC 24 | 89217118 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1276813852 | Aug 23 05:52:16 PM UTC 24 | Aug 23 05:52:19 PM UTC 24 | 476977433 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.4274231016 | Aug 23 05:52:18 PM UTC 24 | Aug 23 05:52:19 PM UTC 24 | 47861665 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.3660765467 | Aug 23 05:52:18 PM UTC 24 | Aug 23 05:52:19 PM UTC 24 | 30092232 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.162886092 | Aug 23 05:52:18 PM UTC 24 | Aug 23 05:52:19 PM UTC 24 | 20531017 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.4189824237 | Aug 23 05:52:18 PM UTC 24 | Aug 23 05:52:19 PM UTC 24 | 7664092 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2285959921 | Aug 23 05:52:11 PM UTC 24 | Aug 23 05:52:19 PM UTC 24 | 270452853 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.2668192813 | Aug 23 05:52:18 PM UTC 24 | Aug 23 05:52:19 PM UTC 24 | 23872689 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.3892396489 | Aug 23 05:52:19 PM UTC 24 | Aug 23 05:52:21 PM UTC 24 | 22855982 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.1687865367 | Aug 23 05:52:19 PM UTC 24 | Aug 23 05:52:21 PM UTC 24 | 12577352 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.2993898768 | Aug 23 05:52:19 PM UTC 24 | Aug 23 05:52:21 PM UTC 24 | 15036047 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1736312457 | Aug 23 05:52:07 PM UTC 24 | Aug 23 05:52:21 PM UTC 24 | 455364965 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.4271178208 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 45596713 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.920624767 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 35555795 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.187701073 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 30328103 ps | ||
| T173 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.2044980168 | Aug 23 05:52:13 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 252805342 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.4005580915 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 16547931 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.1918650429 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 47125436 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.3950676628 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 12636144 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.4115551821 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 46110342 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.3800641668 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 8072820 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.2681194863 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 59681739 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.287850896 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 129760148 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.4046342106 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 27625536 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.1322439391 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 21039799 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2031694908 | Aug 23 05:52:20 PM UTC 24 | Aug 23 05:52:22 PM UTC 24 | 11649732 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.627972741 | Aug 23 05:52:15 PM UTC 24 | Aug 23 05:52:23 PM UTC 24 | 283800105 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.1213064326 | Aug 23 05:52:21 PM UTC 24 | Aug 23 05:52:23 PM UTC 24 | 33654126 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.2845746545 | Aug 23 05:52:21 PM UTC 24 | Aug 23 05:52:23 PM UTC 24 | 12161232 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.27809165 | Aug 23 05:52:21 PM UTC 24 | Aug 23 05:52:23 PM UTC 24 | 15232328 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.293501821 | Aug 23 05:52:22 PM UTC 24 | Aug 23 05:52:24 PM UTC 24 | 11555911 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.2970484735 | Aug 23 05:52:22 PM UTC 24 | Aug 23 05:52:24 PM UTC 24 | 13635629 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.3754068665 | Aug 23 05:52:22 PM UTC 24 | Aug 23 05:52:24 PM UTC 24 | 41850138 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.917572005 | Aug 23 05:52:15 PM UTC 24 | Aug 23 05:52:27 PM UTC 24 | 381866371 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_cfg_regwen.744522052 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 1216749824 ps |
| CPU time | 7.11 seconds |
| Started | Aug 23 07:02:37 PM UTC 24 |
| Finished | Aug 23 07:02:46 PM UTC 24 |
| Peak memory | 225952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744522052 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.744522052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all.1185600530 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3972783606 ps |
| CPU time | 25.53 seconds |
| Started | Aug 23 07:02:45 PM UTC 24 |
| Finished | Aug 23 07:03:11 PM UTC 24 |
| Peak memory | 228184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185600530 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1185600530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_stress_all_with_rand_reset.2625613492 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 1515016523 ps |
| CPU time | 14.84 seconds |
| Started | Aug 23 07:02:46 PM UTC 24 |
| Finished | Aug 23 07:03:02 PM UTC 24 |
| Peak memory | 232304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2625613492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr _stress_all_with_rand_reset.2625613492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all.3251648103 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 1273758465 ps |
| CPU time | 39.02 seconds |
| Started | Aug 23 07:03:50 PM UTC 24 |
| Finished | Aug 23 07:04:31 PM UTC 24 |
| Peak memory | 228196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251648103 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3251648103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_sec_cm.2411128047 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 580974751 ps |
| CPU time | 8.71 seconds |
| Started | Aug 23 07:03:05 PM UTC 24 |
| Finished | Aug 23 07:03:15 PM UTC 24 |
| Peak memory | 256408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411128047 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2411128047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2482770181 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 216074402 ps |
| CPU time | 5.04 seconds |
| Started | Aug 23 05:51:28 PM UTC 24 |
| Finished | Aug 23 05:51:34 PM UTC 24 |
| Peak memory | 230780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482770181 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors.2482770181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all.3080379692 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 1570342431 ps |
| CPU time | 14.99 seconds |
| Started | Aug 23 07:03:04 PM UTC 24 |
| Finished | Aug 23 07:03:21 PM UTC 24 |
| Peak memory | 232200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080379692 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3080379692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_lc_disable.2358796086 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 311238220 ps |
| CPU time | 3.48 seconds |
| Started | Aug 23 07:02:37 PM UTC 24 |
| Finished | Aug 23 07:02:42 PM UTC 24 |
| Peak memory | 217968 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2358796086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2358796086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_kmac_rsp_err.1502168202 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 607767005 ps |
| CPU time | 3.19 seconds |
| Started | Aug 23 07:03:00 PM UTC 24 |
| Finished | Aug 23 07:03:05 PM UTC 24 |
| Peak memory | 226460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502168202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1502168202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_stress_all.1780497610 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 16058148180 ps |
| CPU time | 36.81 seconds |
| Started | Aug 23 07:05:10 PM UTC 24 |
| Finished | Aug 23 07:05:48 PM UTC 24 |
| Peak memory | 228184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780497610 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1780497610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_custom_cm.1898933666 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 116479962 ps |
| CPU time | 2.67 seconds |
| Started | Aug 23 07:04:36 PM UTC 24 |
| Finished | Aug 23 07:04:40 PM UTC 24 |
| Peak memory | 232736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898933666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1898933666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_stress_all.6026352 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 2349062343 ps |
| CPU time | 39.55 seconds |
| Started | Aug 23 07:03:36 PM UTC 24 |
| Finished | Aug 23 07:04:17 PM UTC 24 |
| Peak memory | 232320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6026352 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.6026352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_cfg_regwen.1516809605 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 268175791 ps |
| CPU time | 10.79 seconds |
| Started | Aug 23 07:05:36 PM UTC 24 |
| Finished | Aug 23 07:05:48 PM UTC 24 |
| Peak memory | 226112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516809605 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1516809605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.595985831 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 451072876 ps |
| CPU time | 3.55 seconds |
| Started | Aug 23 05:51:28 PM UTC 24 |
| Finished | Aug 23 05:51:33 PM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595985831 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow_reg_errors_with_csr_rw.595985831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_hwsw_invalid_input.761305013 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 1575643482 ps |
| CPU time | 18.25 seconds |
| Started | Aug 23 07:02:40 PM UTC 24 |
| Finished | Aug 23 07:03:00 PM UTC 24 |
| Peak memory | 230176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761305013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.761305013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_cfg_regwen.2204842043 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 232925443 ps |
| CPU time | 10.37 seconds |
| Started | Aug 23 07:06:55 PM UTC 24 |
| Finished | Aug 23 07:07:07 PM UTC 24 |
| Peak memory | 226168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204842043 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2204842043 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_custom_cm.3989129801 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 177150681 ps |
| CPU time | 2.43 seconds |
| Started | Aug 23 07:04:04 PM UTC 24 |
| Finished | Aug 23 07:04:09 PM UTC 24 |
| Peak memory | 226580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989129801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3989129801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_cfg_regwen.4261244727 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2618119554 ps |
| CPU time | 26.93 seconds |
| Started | Aug 23 07:02:53 PM UTC 24 |
| Finished | Aug 23 07:03:21 PM UTC 24 |
| Peak memory | 226252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261244727 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.4261244727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all_with_rand_reset.1507791562 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 1844608978 ps |
| CPU time | 14.26 seconds |
| Started | Aug 23 07:04:09 PM UTC 24 |
| Finished | Aug 23 07:04:25 PM UTC 24 |
| Peak memory | 232588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1507791562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr _stress_all_with_rand_reset.1507791562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_cfg_regwen.2835198595 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 179935026 ps |
| CPU time | 4.76 seconds |
| Started | Aug 23 07:09:02 PM UTC 24 |
| Finished | Aug 23 07:09:08 PM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835198595 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.2835198595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_sync_async_fault_cross.4292327146 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 241854552 ps |
| CPU time | 2.29 seconds |
| Started | Aug 23 07:02:45 PM UTC 24 |
| Finished | Aug 23 07:02:48 PM UTC 24 |
| Peak memory | 219936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292327146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.4292327146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_cfg_regwen.2639414138 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 1045937412 ps |
| CPU time | 12.04 seconds |
| Started | Aug 23 07:12:45 PM UTC 24 |
| Finished | Aug 23 07:12:58 PM UTC 24 |
| Peak memory | 226288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639414138 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2639414138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_stress_all_with_rand_reset.209597465 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 607441762 ps |
| CPU time | 7.79 seconds |
| Started | Aug 23 07:03:51 PM UTC 24 |
| Finished | Aug 23 07:04:00 PM UTC 24 |
| Peak memory | 231876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=209597465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_ stress_all_with_rand_reset.209597465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_custom_cm.3703635478 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 750736451 ps |
| CPU time | 4.39 seconds |
| Started | Aug 23 07:02:42 PM UTC 24 |
| Finished | Aug 23 07:02:47 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3703635478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3703635478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_custom_cm.3491277075 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 80731511 ps |
| CPU time | 1.38 seconds |
| Started | Aug 23 07:03:01 PM UTC 24 |
| Finished | Aug 23 07:03:04 PM UTC 24 |
| Peak memory | 228512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491277075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.3491277075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_kmac.3027521894 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 332164272 ps |
| CPU time | 7.09 seconds |
| Started | Aug 23 07:02:36 PM UTC 24 |
| Finished | Aug 23 07:02:45 PM UTC 24 |
| Peak memory | 218264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3027521894 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3027521894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all_with_rand_reset.3814628456 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2611203698 ps |
| CPU time | 22.77 seconds |
| Started | Aug 23 07:04:41 PM UTC 24 |
| Finished | Aug 23 07:05:06 PM UTC 24 |
| Peak memory | 232704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3814628456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr _stress_all_with_rand_reset.3814628456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_hwsw_invalid_input.3286922478 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 41509115 ps |
| CPU time | 2.2 seconds |
| Started | Aug 23 07:07:00 PM UTC 24 |
| Finished | Aug 23 07:07:04 PM UTC 24 |
| Peak memory | 218308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3286922478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3286922478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_hwsw_invalid_input.3155876688 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 73615794 ps |
| CPU time | 3.58 seconds |
| Started | Aug 23 07:07:12 PM UTC 24 |
| Finished | Aug 23 07:07:17 PM UTC 24 |
| Peak memory | 228116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155876688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3155876688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_custom_cm.2454946048 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 268819518 ps |
| CPU time | 3.1 seconds |
| Started | Aug 23 07:13:58 PM UTC 24 |
| Finished | Aug 23 07:14:02 PM UTC 24 |
| Peak memory | 228320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454946048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2454946048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_cfg_regwen.1467006533 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 433150595 ps |
| CPU time | 5.77 seconds |
| Started | Aug 23 07:11:55 PM UTC 24 |
| Finished | Aug 23 07:12:02 PM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1467006533 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1467006533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all.251197840 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 3681712211 ps |
| CPU time | 40.4 seconds |
| Started | Aug 23 07:08:06 PM UTC 24 |
| Finished | Aug 23 07:08:48 PM UTC 24 |
| Peak memory | 231984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251197840 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.251197840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_cfg_regwen.132045549 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 610870972 ps |
| CPU time | 6.88 seconds |
| Started | Aug 23 07:14:48 PM UTC 24 |
| Finished | Aug 23 07:14:56 PM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132045549 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.132045549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_stress_all.4236514029 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 12318103545 ps |
| CPU time | 61.11 seconds |
| Started | Aug 23 07:04:52 PM UTC 24 |
| Finished | Aug 23 07:05:55 PM UTC 24 |
| Peak memory | 232280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236514029 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.4236514029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3422137975 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 475823218 ps |
| CPU time | 9.1 seconds |
| Started | Aug 23 05:51:33 PM UTC 24 |
| Finished | Aug 23 05:51:43 PM UTC 24 |
| Peak memory | 226412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422137975 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors_with_csr_rw.3422137975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_hwsw_invalid_input.1274235861 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 1216663423 ps |
| CPU time | 7.42 seconds |
| Started | Aug 23 07:02:59 PM UTC 24 |
| Finished | Aug 23 07:03:08 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274235861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1274235861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_alert_test.356537517 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 69498325 ps |
| CPU time | 0.81 seconds |
| Started | Aug 23 07:02:47 PM UTC 24 |
| Finished | Aug 23 07:02:49 PM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356537517 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.356537517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_intg_err.3143672788 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 281527282 ps |
| CPU time | 5.78 seconds |
| Started | Aug 23 05:51:49 PM UTC 24 |
| Finished | Aug 23 05:51:56 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3143672788 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err.3143672788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_stress_all.3525399613 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 5554494680 ps |
| CPU time | 36.8 seconds |
| Started | Aug 23 07:09:29 PM UTC 24 |
| Finished | Aug 23 07:10:08 PM UTC 24 |
| Peak memory | 226176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525399613 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3525399613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_kmac_rsp_err.2282859641 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 142297054 ps |
| CPU time | 2.27 seconds |
| Started | Aug 23 07:05:58 PM UTC 24 |
| Finished | Aug 23 07:06:02 PM UTC 24 |
| Peak memory | 224140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282859641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2282859641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_cfg_regwen.3657626190 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 6895909971 ps |
| CPU time | 75.4 seconds |
| Started | Aug 23 07:16:04 PM UTC 24 |
| Finished | Aug 23 07:17:21 PM UTC 24 |
| Peak memory | 226212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657626190 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3657626190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_kmac_rsp_err.4074196221 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 564391193 ps |
| CPU time | 5.42 seconds |
| Started | Aug 23 07:05:27 PM UTC 24 |
| Finished | Aug 23 07:05:33 PM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074196221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.4074196221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_stress_all.207886502 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 6003086054 ps |
| CPU time | 66.13 seconds |
| Started | Aug 23 07:05:45 PM UTC 24 |
| Finished | Aug 23 07:06:53 PM UTC 24 |
| Peak memory | 231716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207886502 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.207886502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_cfg_regwen.1746579471 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 735640222 ps |
| CPU time | 4.05 seconds |
| Started | Aug 23 07:08:14 PM UTC 24 |
| Finished | Aug 23 07:08:20 PM UTC 24 |
| Peak memory | 226440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746579471 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1746579471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_cfg_regwen.2378787355 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 99403755 ps |
| CPU time | 4.68 seconds |
| Started | Aug 23 07:03:17 PM UTC 24 |
| Finished | Aug 23 07:03:23 PM UTC 24 |
| Peak memory | 224256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378787355 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2378787355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_hwsw_invalid_input.1212531326 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 197950711 ps |
| CPU time | 2.47 seconds |
| Started | Aug 23 07:08:04 PM UTC 24 |
| Finished | Aug 23 07:08:07 PM UTC 24 |
| Peak memory | 224032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212531326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1212531326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all_with_rand_reset.1661803487 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 519035923 ps |
| CPU time | 14.76 seconds |
| Started | Aug 23 07:12:03 PM UTC 24 |
| Finished | Aug 23 07:12:19 PM UTC 24 |
| Peak memory | 232384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1661803487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymg r_stress_all_with_rand_reset.1661803487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_aes.2214375503 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 497748244 ps |
| CPU time | 2.65 seconds |
| Started | Aug 23 07:03:56 PM UTC 24 |
| Finished | Aug 23 07:04:00 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2214375503 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2214375503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_intg_err.2120590769 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 967784030 ps |
| CPU time | 5.87 seconds |
| Started | Aug 23 05:51:59 PM UTC 24 |
| Finished | Aug 23 05:52:06 PM UTC 24 |
| Peak memory | 215920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120590769 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_err.2120590769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_intg_err.3899509288 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 412964804 ps |
| CPU time | 3.77 seconds |
| Started | Aug 23 05:51:43 PM UTC 24 |
| Finished | Aug 23 05:51:48 PM UTC 24 |
| Peak memory | 226324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899509288 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.3899509288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_custom_cm.7797068 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 1872435316 ps |
| CPU time | 9.65 seconds |
| Started | Aug 23 07:06:26 PM UTC 24 |
| Finished | Aug 23 07:06:37 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7797068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=k eymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.7797068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_kmac_rsp_err.4177442864 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 139004314 ps |
| CPU time | 1.98 seconds |
| Started | Aug 23 07:06:26 PM UTC 24 |
| Finished | Aug 23 07:06:29 PM UTC 24 |
| Peak memory | 231652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177442864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4177442864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_cfg_regwen.213842469 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 12770332638 ps |
| CPU time | 125.19 seconds |
| Started | Aug 23 07:07:40 PM UTC 24 |
| Finished | Aug 23 07:09:48 PM UTC 24 |
| Peak memory | 231988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213842469 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.213842469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_kmac_rsp_err.3433272733 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 131713001 ps |
| CPU time | 2.27 seconds |
| Started | Aug 23 07:13:57 PM UTC 24 |
| Finished | Aug 23 07:14:00 PM UTC 24 |
| Peak memory | 230852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433272733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3433272733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_intg_err.124445952 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 292011870 ps |
| CPU time | 5.66 seconds |
| Started | Aug 23 05:52:07 PM UTC 24 |
| Finished | Aug 23 05:52:14 PM UTC 24 |
| Peak memory | 226036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=124445952 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err.124445952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_intg_err.1365037819 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 478555188 ps |
| CPU time | 4.33 seconds |
| Started | Aug 23 05:52:08 PM UTC 24 |
| Finished | Aug 23 05:52:14 PM UTC 24 |
| Peak memory | 226416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365037819 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err.1365037819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_custom_cm.1172915127 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 100193266 ps |
| CPU time | 4.15 seconds |
| Started | Aug 23 07:14:56 PM UTC 24 |
| Finished | Aug 23 07:15:02 PM UTC 24 |
| Peak memory | 232428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172915127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1172915127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_random.1346906131 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 1222587012 ps |
| CPU time | 7.85 seconds |
| Started | Aug 23 07:02:36 PM UTC 24 |
| Finished | Aug 23 07:02:45 PM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346906131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.1346906131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_otbn.1593592300 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 118984769 ps |
| CPU time | 2.95 seconds |
| Started | Aug 23 07:05:51 PM UTC 24 |
| Finished | Aug 23 07:05:55 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593592300 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1593592300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_sync_async_fault_cross.3648310532 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 70154699 ps |
| CPU time | 1.67 seconds |
| Started | Aug 23 07:07:03 PM UTC 24 |
| Finished | Aug 23 07:07:05 PM UTC 24 |
| Peak memory | 219588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648310532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3648310532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all_with_rand_reset.4058327283 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 500239012 ps |
| CPU time | 17.07 seconds |
| Started | Aug 23 07:07:32 PM UTC 24 |
| Finished | Aug 23 07:07:50 PM UTC 24 |
| Peak memory | 232376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4058327283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymg r_stress_all_with_rand_reset.4058327283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_stress_all.2765404870 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 6187045144 ps |
| CPU time | 56.77 seconds |
| Started | Aug 23 07:07:51 PM UTC 24 |
| Finished | Aug 23 07:08:50 PM UTC 24 |
| Peak memory | 232568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765404870 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2765404870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_lc_disable.3081183754 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 218648356 ps |
| CPU time | 2.66 seconds |
| Started | Aug 23 07:03:18 PM UTC 24 |
| Finished | Aug 23 07:03:22 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081183754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3081183754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_hwsw_invalid_input.3608703727 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 159747381 ps |
| CPU time | 2.67 seconds |
| Started | Aug 23 07:08:52 PM UTC 24 |
| Finished | Aug 23 07:08:56 PM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608703727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3608703727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_cfg_regwen.843127250 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 249363576 ps |
| CPU time | 8.95 seconds |
| Started | Aug 23 07:04:17 PM UTC 24 |
| Finished | Aug 23 07:04:27 PM UTC 24 |
| Peak memory | 232304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843127250 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.843127250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_cfg_regwen.4233922902 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 310579690 ps |
| CPU time | 7.14 seconds |
| Started | Aug 23 07:04:32 PM UTC 24 |
| Finished | Aug 23 07:04:40 PM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233922902 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.4233922902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_custom_cm.545890998 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 381096574 ps |
| CPU time | 3.78 seconds |
| Started | Aug 23 07:09:25 PM UTC 24 |
| Finished | Aug 23 07:09:30 PM UTC 24 |
| Peak memory | 232436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545890998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.545890998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_custom_cm.555960924 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 470158843 ps |
| CPU time | 5 seconds |
| Started | Aug 23 07:15:29 PM UTC 24 |
| Finished | Aug 23 07:15:35 PM UTC 24 |
| Peak memory | 226424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555960924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.555960924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_custom_cm.3437386106 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 62368118 ps |
| CPU time | 2.26 seconds |
| Started | Aug 23 07:07:28 PM UTC 24 |
| Finished | Aug 23 07:07:32 PM UTC 24 |
| Peak memory | 226392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437386106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3437386106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_hwsw_invalid_input.4050772749 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 223201676 ps |
| CPU time | 3.8 seconds |
| Started | Aug 23 07:06:25 PM UTC 24 |
| Finished | Aug 23 07:06:31 PM UTC 24 |
| Peak memory | 230244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050772749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.4050772749 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_cfg_regwen.1285793411 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 37859278 ps |
| CPU time | 2.42 seconds |
| Started | Aug 23 07:07:24 PM UTC 24 |
| Finished | Aug 23 07:07:27 PM UTC 24 |
| Peak memory | 224420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285793411 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1285793411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_sync_async_fault_cross.3912295449 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 60424472 ps |
| CPU time | 1.33 seconds |
| Started | Aug 23 07:07:50 PM UTC 24 |
| Finished | Aug 23 07:07:53 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912295449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3912295449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_stress_all.1182751191 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 34156308869 ps |
| CPU time | 190.33 seconds |
| Started | Aug 23 07:08:25 PM UTC 24 |
| Finished | Aug 23 07:11:39 PM UTC 24 |
| Peak memory | 232316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182751191 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1182751191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_kmac_rsp_err.1266443375 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 104196095 ps |
| CPU time | 3.49 seconds |
| Started | Aug 23 07:08:54 PM UTC 24 |
| Finished | Aug 23 07:08:59 PM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266443375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1266443375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all_with_rand_reset.377347216 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 221010747 ps |
| CPU time | 7.59 seconds |
| Started | Aug 23 07:09:11 PM UTC 24 |
| Finished | Aug 23 07:09:19 PM UTC 24 |
| Peak memory | 232308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=377347216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr _stress_all_with_rand_reset.377347216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_intg_err.1024541509 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 2343433316 ps |
| CPU time | 8.83 seconds |
| Started | Aug 23 05:51:34 PM UTC 24 |
| Finished | Aug 23 05:51:44 PM UTC 24 |
| Peak memory | 226176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024541509 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.1024541509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_intg_err.296188828 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 102274593 ps |
| CPU time | 2.64 seconds |
| Started | Aug 23 05:52:00 PM UTC 24 |
| Finished | Aug 23 05:52:04 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296188828 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.296188828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_intg_err.2044980168 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 252805342 ps |
| CPU time | 7.46 seconds |
| Started | Aug 23 05:52:13 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 226092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044980168 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.2044980168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_intg_err.627972741 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 283800105 ps |
| CPU time | 6.46 seconds |
| Started | Aug 23 05:52:15 PM UTC 24 |
| Finished | Aug 23 05:52:23 PM UTC 24 |
| Peak memory | 226120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627972741 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err.627972741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_intg_err.2191461491 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 955578712 ps |
| CPU time | 5.93 seconds |
| Started | Aug 23 05:51:37 PM UTC 24 |
| Finished | Aug 23 05:51:44 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191461491 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.2191461491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_intg_err.4083857267 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3579788472 ps |
| CPU time | 6.31 seconds |
| Started | Aug 23 05:51:55 PM UTC 24 |
| Finished | Aug 23 05:52:03 PM UTC 24 |
| Peak memory | 228332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083857267 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.4083857267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_sec_cm.2279817314 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 1175466192 ps |
| CPU time | 11.02 seconds |
| Started | Aug 23 07:02:46 PM UTC 24 |
| Finished | Aug 23 07:02:58 PM UTC 24 |
| Peak memory | 260116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279817314 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2279817314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_sync_async_fault_cross.4184259481 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 197541659 ps |
| CPU time | 1.83 seconds |
| Started | Aug 23 07:06:01 PM UTC 24 |
| Finished | Aug 23 07:06:03 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184259481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.4184259481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_custom_cm.2054072303 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 52320195 ps |
| CPU time | 1.51 seconds |
| Started | Aug 23 07:12:50 PM UTC 24 |
| Finished | Aug 23 07:12:53 PM UTC 24 |
| Peak memory | 215648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054072303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2054072303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_sec_cm.2607451207 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 1802853270 ps |
| CPU time | 9.45 seconds |
| Started | Aug 23 07:03:51 PM UTC 24 |
| Finished | Aug 23 07:04:02 PM UTC 24 |
| Peak memory | 254032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607451207 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2607451207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_custom_cm.3613315712 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 141858786 ps |
| CPU time | 2.98 seconds |
| Started | Aug 23 07:11:22 PM UTC 24 |
| Finished | Aug 23 07:11:26 PM UTC 24 |
| Peak memory | 226432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613315712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3613315712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_custom_cm.1861631833 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 83883936 ps |
| CPU time | 2.74 seconds |
| Started | Aug 23 07:14:33 PM UTC 24 |
| Finished | Aug 23 07:14:37 PM UTC 24 |
| Peak memory | 224328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1861631833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1861631833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_sw_invalid_input.1683932703 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 287794120 ps |
| CPU time | 7.27 seconds |
| Started | Aug 23 07:02:39 PM UTC 24 |
| Finished | Aug 23 07:02:48 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683932703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1683932703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_hwsw_invalid_input.1858485739 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 158805846 ps |
| CPU time | 4.52 seconds |
| Started | Aug 23 07:05:27 PM UTC 24 |
| Finished | Aug 23 07:05:32 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858485739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1858485739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_kmac_rsp_err.2223392561 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 266477010 ps |
| CPU time | 2.38 seconds |
| Started | Aug 23 07:05:41 PM UTC 24 |
| Finished | Aug 23 07:05:44 PM UTC 24 |
| Peak memory | 232192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223392561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2223392561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_stress_all.1693692060 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 1114904628 ps |
| CPU time | 7.26 seconds |
| Started | Aug 23 07:06:01 PM UTC 24 |
| Finished | Aug 23 07:06:09 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693692060 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.1693692060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all.642545210 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 505741877 ps |
| CPU time | 11.69 seconds |
| Started | Aug 23 07:06:47 PM UTC 24 |
| Finished | Aug 23 07:07:00 PM UTC 24 |
| Peak memory | 232344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642545210 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.642545210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_sideload.996630 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 71143897 ps |
| CPU time | 2.48 seconds |
| Started | Aug 23 07:07:19 PM UTC 24 |
| Finished | Aug 23 07:07:23 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=ke ymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.996630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_cfg_regwen.2232453905 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 73861513 ps |
| CPU time | 3.65 seconds |
| Started | Aug 23 07:07:58 PM UTC 24 |
| Finished | Aug 23 07:08:03 PM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232453905 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2232453905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_cfg_regwen.621551770 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 72604426 ps |
| CPU time | 3.44 seconds |
| Started | Aug 23 07:08:34 PM UTC 24 |
| Finished | Aug 23 07:08:39 PM UTC 24 |
| Peak memory | 226404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621551770 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.621551770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_protect.2018232184 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 4067777924 ps |
| CPU time | 12.17 seconds |
| Started | Aug 23 07:09:26 PM UTC 24 |
| Finished | Aug 23 07:09:40 PM UTC 24 |
| Peak memory | 228584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018232184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2018232184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_cfg_regwen.1300769330 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 189603932 ps |
| CPU time | 8.82 seconds |
| Started | Aug 23 07:10:01 PM UTC 24 |
| Finished | Aug 23 07:10:11 PM UTC 24 |
| Peak memory | 224092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300769330 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1300769330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_hwsw_invalid_input.1479957887 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 387064926 ps |
| CPU time | 1.74 seconds |
| Started | Aug 23 07:10:28 PM UTC 24 |
| Finished | Aug 23 07:10:31 PM UTC 24 |
| Peak memory | 224536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479957887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1479957887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_kmac_rsp_err.439599851 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 333666876 ps |
| CPU time | 1.68 seconds |
| Started | Aug 23 07:10:28 PM UTC 24 |
| Finished | Aug 23 07:10:31 PM UTC 24 |
| Peak memory | 229596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439599851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.439599851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_kmac_rsp_err.913042503 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 32082333 ps |
| CPU time | 1.74 seconds |
| Started | Aug 23 07:11:10 PM UTC 24 |
| Finished | Aug 23 07:11:13 PM UTC 24 |
| Peak memory | 231308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913042503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.913042503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_stress_all.1405073536 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 1821476985 ps |
| CPU time | 21.17 seconds |
| Started | Aug 23 07:12:24 PM UTC 24 |
| Finished | Aug 23 07:12:46 PM UTC 24 |
| Peak memory | 228452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405073536 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1405073536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_cfg_regwen.27739429 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 87644810 ps |
| CPU time | 2.92 seconds |
| Started | Aug 23 07:13:01 PM UTC 24 |
| Finished | Aug 23 07:13:05 PM UTC 24 |
| Peak memory | 224356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27739429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.27739429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_custom_cm.630633106 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 74580828 ps |
| CPU time | 2.62 seconds |
| Started | Aug 23 07:13:07 PM UTC 24 |
| Finished | Aug 23 07:13:11 PM UTC 24 |
| Peak memory | 230324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630633106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.630633106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_stress_all.4165178988 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 16681205745 ps |
| CPU time | 42.26 seconds |
| Started | Aug 23 07:13:31 PM UTC 24 |
| Finished | Aug 23 07:14:15 PM UTC 24 |
| Peak memory | 226140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165178988 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.4165178988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_custom_cm.2230680745 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 65919260 ps |
| CPU time | 2.86 seconds |
| Started | Aug 23 07:06:44 PM UTC 24 |
| Finished | Aug 23 07:06:48 PM UTC 24 |
| Peak memory | 226392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230680745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2230680745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_custom_cm.615142842 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 215138102 ps |
| CPU time | 4.3 seconds |
| Started | Aug 23 07:10:30 PM UTC 24 |
| Finished | Aug 23 07:10:35 PM UTC 24 |
| Peak memory | 228484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615142842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.615142842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_aliasing.4124454124 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 136638043 ps |
| CPU time | 7.35 seconds |
| Started | Aug 23 05:51:30 PM UTC 24 |
| Finished | Aug 23 05:51:39 PM UTC 24 |
| Peak memory | 216108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124454124 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.4124454124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_bit_bash.4252192362 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 533059657 ps |
| CPU time | 5.63 seconds |
| Started | Aug 23 05:51:30 PM UTC 24 |
| Finished | Aug 23 05:51:37 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252192362 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.4252192362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_hw_reset.568051428 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 33247871 ps |
| CPU time | 1.17 seconds |
| Started | Aug 23 05:51:29 PM UTC 24 |
| Finished | Aug 23 05:51:32 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568051428 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.568051428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.68172340 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 76979027 ps |
| CPU time | 1.32 seconds |
| Started | Aug 23 05:51:32 PM UTC 24 |
| Finished | Aug 23 05:51:34 PM UTC 24 |
| Peak memory | 213652 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=68172340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_mem_rw_wit h_rand_reset.68172340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_csr_rw.1995397384 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 65417777 ps |
| CPU time | 0.89 seconds |
| Started | Aug 23 05:51:30 PM UTC 24 |
| Finished | Aug 23 05:51:32 PM UTC 24 |
| Peak memory | 213216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995397384 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1995397384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_intr_test.27806079 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 48911494 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:51:29 PM UTC 24 |
| Finished | Aug 23 05:51:31 PM UTC 24 |
| Peak memory | 213484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27806079 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.27806079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1681431684 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 72199331 ps |
| CPU time | 1.35 seconds |
| Started | Aug 23 05:51:31 PM UTC 24 |
| Finished | Aug 23 05:51:33 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1681431684 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_same_csr_outstanding.1681431684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_errors.4008727232 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 47418761 ps |
| CPU time | 1.61 seconds |
| Started | Aug 23 05:51:28 PM UTC 24 |
| Finished | Aug 23 05:51:31 PM UTC 24 |
| Peak memory | 231784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008727232 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.4008727232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/0.keymgr_tl_intg_err.3574944129 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 431361016 ps |
| CPU time | 3.14 seconds |
| Started | Aug 23 05:51:29 PM UTC 24 |
| Finished | Aug 23 05:51:34 PM UTC 24 |
| Peak memory | 226104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574944129 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.3574944129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_aliasing.1818368015 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 552382548 ps |
| CPU time | 14.04 seconds |
| Started | Aug 23 05:51:36 PM UTC 24 |
| Finished | Aug 23 05:51:51 PM UTC 24 |
| Peak memory | 216044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818368015 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1818368015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3021522613 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 7555394230 ps |
| CPU time | 17.76 seconds |
| Started | Aug 23 05:51:35 PM UTC 24 |
| Finished | Aug 23 05:51:54 PM UTC 24 |
| Peak memory | 216292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021522613 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3021522613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3250296140 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 37096789 ps |
| CPU time | 1.01 seconds |
| Started | Aug 23 05:51:35 PM UTC 24 |
| Finished | Aug 23 05:51:37 PM UTC 24 |
| Peak memory | 213716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250296140 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3250296140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.2097580658 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 30061191 ps |
| CPU time | 1.78 seconds |
| Started | Aug 23 05:51:36 PM UTC 24 |
| Finished | Aug 23 05:51:39 PM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2097580658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_mem_rw_w ith_rand_reset.2097580658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_csr_rw.2730320061 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 40333280 ps |
| CPU time | 0.86 seconds |
| Started | Aug 23 05:51:35 PM UTC 24 |
| Finished | Aug 23 05:51:37 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2730320061 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2730320061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_intr_test.1551481263 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 71315307 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 05:51:34 PM UTC 24 |
| Finished | Aug 23 05:51:36 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1551481263 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1551481263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1330897288 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 84632031 ps |
| CPU time | 2.06 seconds |
| Started | Aug 23 05:51:36 PM UTC 24 |
| Finished | Aug 23 05:51:39 PM UTC 24 |
| Peak memory | 216004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330897288 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_same_csr_outstanding.1330897288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.593481447 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 169210953 ps |
| CPU time | 2.77 seconds |
| Started | Aug 23 05:51:32 PM UTC 24 |
| Finished | Aug 23 05:51:36 PM UTC 24 |
| Peak memory | 226516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593481447 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow_reg_errors.593481447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/1.keymgr_tl_errors.1631799047 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 26876424 ps |
| CPU time | 1.39 seconds |
| Started | Aug 23 05:51:34 PM UTC 24 |
| Finished | Aug 23 05:51:36 PM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631799047 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1631799047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2428162582 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 21320576 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 05:51:59 PM UTC 24 |
| Finished | Aug 23 05:52:01 PM UTC 24 |
| Peak memory | 225872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2428162582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_mem_rw_ with_rand_reset.2428162582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_csr_rw.3651446762 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 16381824 ps |
| CPU time | 0.87 seconds |
| Started | Aug 23 05:51:58 PM UTC 24 |
| Finished | Aug 23 05:52:00 PM UTC 24 |
| Peak memory | 213564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651446762 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.3651446762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_intr_test.1098937630 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 37021825 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 05:51:58 PM UTC 24 |
| Finished | Aug 23 05:51:59 PM UTC 24 |
| Peak memory | 213544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098937630 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.1098937630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2106740912 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 821056329 ps |
| CPU time | 2.84 seconds |
| Started | Aug 23 05:51:59 PM UTC 24 |
| Finished | Aug 23 05:52:03 PM UTC 24 |
| Peak memory | 215208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106740912 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_same_csr_outstanding.2106740912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.4179172654 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 694635045 ps |
| CPU time | 1.5 seconds |
| Started | Aug 23 05:51:57 PM UTC 24 |
| Finished | Aug 23 05:51:59 PM UTC 24 |
| Peak memory | 223900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179172654 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors.4179172654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3861322692 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 80388190 ps |
| CPU time | 3.83 seconds |
| Started | Aug 23 05:51:57 PM UTC 24 |
| Finished | Aug 23 05:52:02 PM UTC 24 |
| Peak memory | 226532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861322692 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shadow_reg_errors_with_csr_rw.3861322692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_errors.2410406403 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 93300058 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 05:51:58 PM UTC 24 |
| Finished | Aug 23 05:52:00 PM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410406403 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2410406403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/10.keymgr_tl_intg_err.1738303670 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 269982819 ps |
| CPU time | 8.47 seconds |
| Started | Aug 23 05:51:58 PM UTC 24 |
| Finished | Aug 23 05:52:07 PM UTC 24 |
| Peak memory | 226104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738303670 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_err.1738303670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2404862386 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 127415881 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 05:52:00 PM UTC 24 |
| Finished | Aug 23 05:52:02 PM UTC 24 |
| Peak memory | 223808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2404862386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_mem_rw_ with_rand_reset.2404862386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_csr_rw.33242397 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 50345375 ps |
| CPU time | 0.79 seconds |
| Started | Aug 23 05:52:00 PM UTC 24 |
| Finished | Aug 23 05:52:02 PM UTC 24 |
| Peak memory | 213416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33242397 -assert nopostproc +UVM_TESTNAME=keymgr_ base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22 /keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.33242397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_intr_test.1560002317 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 58840272 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 05:52:00 PM UTC 24 |
| Finished | Aug 23 05:52:02 PM UTC 24 |
| Peak memory | 213452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560002317 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1560002317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3251003685 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 38014657 ps |
| CPU time | 1.77 seconds |
| Started | Aug 23 05:52:00 PM UTC 24 |
| Finished | Aug 23 05:52:03 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251003685 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_same_csr_outstanding.3251003685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.814648728 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 757209449 ps |
| CPU time | 2.51 seconds |
| Started | Aug 23 05:51:59 PM UTC 24 |
| Finished | Aug 23 05:52:02 PM UTC 24 |
| Peak memory | 225992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814648728 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors.814648728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.313658772 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 358716060 ps |
| CPU time | 7.39 seconds |
| Started | Aug 23 05:51:59 PM UTC 24 |
| Finished | Aug 23 05:52:07 PM UTC 24 |
| Peak memory | 226540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313658772 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shadow_reg_errors_with_csr_rw.313658772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/11.keymgr_tl_errors.904339346 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 201298650 ps |
| CPU time | 2.44 seconds |
| Started | Aug 23 05:51:59 PM UTC 24 |
| Finished | Aug 23 05:52:02 PM UTC 24 |
| Peak memory | 228296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904339346 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.904339346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.4145374466 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 169164511 ps |
| CPU time | 1.03 seconds |
| Started | Aug 23 05:52:02 PM UTC 24 |
| Finished | Aug 23 05:52:05 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4145374466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_mem_rw_ with_rand_reset.4145374466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_csr_rw.2765615221 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 32077188 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 05:52:01 PM UTC 24 |
| Finished | Aug 23 05:52:03 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2765615221 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2765615221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_intr_test.1623624276 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 54629212 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:52:00 PM UTC 24 |
| Finished | Aug 23 05:52:02 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623624276 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1623624276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3272825856 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 335246925 ps |
| CPU time | 1.96 seconds |
| Started | Aug 23 05:52:02 PM UTC 24 |
| Finished | Aug 23 05:52:05 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272825856 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_same_csr_outstanding.3272825856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.501059329 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 181518451 ps |
| CPU time | 3.09 seconds |
| Started | Aug 23 05:52:00 PM UTC 24 |
| Finished | Aug 23 05:52:04 PM UTC 24 |
| Peak memory | 226748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501059329 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors.501059329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1123437727 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 1855526192 ps |
| CPU time | 4.53 seconds |
| Started | Aug 23 05:52:00 PM UTC 24 |
| Finished | Aug 23 05:52:06 PM UTC 24 |
| Peak memory | 226460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123437727 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow_reg_errors_with_csr_rw.1123437727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/12.keymgr_tl_errors.1089393785 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 257088183 ps |
| CPU time | 4.11 seconds |
| Started | Aug 23 05:52:00 PM UTC 24 |
| Finished | Aug 23 05:52:06 PM UTC 24 |
| Peak memory | 226276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089393785 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.1089393785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2880803129 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 41990206 ps |
| CPU time | 1.63 seconds |
| Started | Aug 23 05:52:04 PM UTC 24 |
| Finished | Aug 23 05:52:06 PM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2880803129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_mem_rw_ with_rand_reset.2880803129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_csr_rw.2577167950 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 18856268 ps |
| CPU time | 0.96 seconds |
| Started | Aug 23 05:52:04 PM UTC 24 |
| Finished | Aug 23 05:52:06 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577167950 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2577167950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_intr_test.1057531609 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 26240400 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 05:52:04 PM UTC 24 |
| Finished | Aug 23 05:52:05 PM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057531609 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1057531609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1653422109 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 87665429 ps |
| CPU time | 2.03 seconds |
| Started | Aug 23 05:52:04 PM UTC 24 |
| Finished | Aug 23 05:52:07 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653422109 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_same_csr_outstanding.1653422109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3641538413 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 369389784 ps |
| CPU time | 2.77 seconds |
| Started | Aug 23 05:52:02 PM UTC 24 |
| Finished | Aug 23 05:52:06 PM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641538413 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors.3641538413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.563055047 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 467831976 ps |
| CPU time | 13.18 seconds |
| Started | Aug 23 05:52:02 PM UTC 24 |
| Finished | Aug 23 05:52:17 PM UTC 24 |
| Peak memory | 232628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563055047 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shadow_reg_errors_with_csr_rw.563055047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_errors.3825451563 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 305818930 ps |
| CPU time | 2.81 seconds |
| Started | Aug 23 05:52:02 PM UTC 24 |
| Finished | Aug 23 05:52:06 PM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825451563 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3825451563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/13.keymgr_tl_intg_err.2435887318 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 159442353 ps |
| CPU time | 3.19 seconds |
| Started | Aug 23 05:52:04 PM UTC 24 |
| Finished | Aug 23 05:52:08 PM UTC 24 |
| Peak memory | 226160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435887318 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err.2435887318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.376578972 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 40321243 ps |
| CPU time | 1.33 seconds |
| Started | Aug 23 05:52:06 PM UTC 24 |
| Finished | Aug 23 05:52:08 PM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=376578972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_mem_rw_w ith_rand_reset.376578972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_csr_rw.1751208121 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 69477963 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 05:52:06 PM UTC 24 |
| Finished | Aug 23 05:52:08 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1751208121 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1751208121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_intr_test.2988678034 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 29410344 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 05:52:05 PM UTC 24 |
| Finished | Aug 23 05:52:07 PM UTC 24 |
| Peak memory | 213188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988678034 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.2988678034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.905911235 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 57580340 ps |
| CPU time | 1.76 seconds |
| Started | Aug 23 05:52:06 PM UTC 24 |
| Finished | Aug 23 05:52:09 PM UTC 24 |
| Peak memory | 213132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905911235 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_same_csr_outstanding.905911235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.775807430 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 215054263 ps |
| CPU time | 5.03 seconds |
| Started | Aug 23 05:52:04 PM UTC 24 |
| Finished | Aug 23 05:52:10 PM UTC 24 |
| Peak memory | 226684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775807430 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors.775807430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.989022477 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 173957599 ps |
| CPU time | 3.81 seconds |
| Started | Aug 23 05:52:04 PM UTC 24 |
| Finished | Aug 23 05:52:09 PM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989022477 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow_reg_errors_with_csr_rw.989022477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_errors.1044790725 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 197464686 ps |
| CPU time | 1.75 seconds |
| Started | Aug 23 05:52:04 PM UTC 24 |
| Finished | Aug 23 05:52:07 PM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044790725 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1044790725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/14.keymgr_tl_intg_err.1250798739 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 289870795 ps |
| CPU time | 4.95 seconds |
| Started | Aug 23 05:52:05 PM UTC 24 |
| Finished | Aug 23 05:52:11 PM UTC 24 |
| Peak memory | 226128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250798739 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err.1250798739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2624847840 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 31260013 ps |
| CPU time | 1.27 seconds |
| Started | Aug 23 05:52:07 PM UTC 24 |
| Finished | Aug 23 05:52:10 PM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2624847840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_mem_rw_ with_rand_reset.2624847840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_csr_rw.1848199162 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 39838818 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 05:52:07 PM UTC 24 |
| Finished | Aug 23 05:52:09 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848199162 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1848199162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_intr_test.524878532 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 15023913 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 05:52:07 PM UTC 24 |
| Finished | Aug 23 05:52:09 PM UTC 24 |
| Peak memory | 213112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524878532 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.524878532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2227252385 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 127385203 ps |
| CPU time | 3.45 seconds |
| Started | Aug 23 05:52:07 PM UTC 24 |
| Finished | Aug 23 05:52:12 PM UTC 24 |
| Peak memory | 215936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227252385 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_same_csr_outstanding.2227252385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3181401382 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 539096363 ps |
| CPU time | 3.38 seconds |
| Started | Aug 23 05:52:06 PM UTC 24 |
| Finished | Aug 23 05:52:11 PM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181401382 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors.3181401382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1736312457 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 455364965 ps |
| CPU time | 12.43 seconds |
| Started | Aug 23 05:52:07 PM UTC 24 |
| Finished | Aug 23 05:52:21 PM UTC 24 |
| Peak memory | 226676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736312457 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shadow_reg_errors_with_csr_rw.1736312457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/15.keymgr_tl_errors.3256339004 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 91149639 ps |
| CPU time | 1.87 seconds |
| Started | Aug 23 05:52:07 PM UTC 24 |
| Finished | Aug 23 05:52:10 PM UTC 24 |
| Peak memory | 223668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3256339004 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3256339004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3845629471 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 91696823 ps |
| CPU time | 1.32 seconds |
| Started | Aug 23 05:52:09 PM UTC 24 |
| Finished | Aug 23 05:52:12 PM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3845629471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_mem_rw_ with_rand_reset.3845629471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_csr_rw.1360926618 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 109587990 ps |
| CPU time | 0.82 seconds |
| Started | Aug 23 05:52:09 PM UTC 24 |
| Finished | Aug 23 05:52:12 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360926618 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1360926618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_intr_test.2292004992 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 29454369 ps |
| CPU time | 0.89 seconds |
| Started | Aug 23 05:52:08 PM UTC 24 |
| Finished | Aug 23 05:52:11 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292004992 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2292004992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.481857934 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 131319409 ps |
| CPU time | 2.75 seconds |
| Started | Aug 23 05:52:09 PM UTC 24 |
| Finished | Aug 23 05:52:14 PM UTC 24 |
| Peak memory | 215920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481857934 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_same_csr_outstanding.481857934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1860122512 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 221145518 ps |
| CPU time | 2.26 seconds |
| Started | Aug 23 05:52:08 PM UTC 24 |
| Finished | Aug 23 05:52:12 PM UTC 24 |
| Peak memory | 226416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860122512 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors.1860122512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2496134127 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 216315777 ps |
| CPU time | 6.51 seconds |
| Started | Aug 23 05:52:08 PM UTC 24 |
| Finished | Aug 23 05:52:16 PM UTC 24 |
| Peak memory | 226408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496134127 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shadow_reg_errors_with_csr_rw.2496134127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/16.keymgr_tl_errors.1943084416 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 164076696 ps |
| CPU time | 4.62 seconds |
| Started | Aug 23 05:52:08 PM UTC 24 |
| Finished | Aug 23 05:52:15 PM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943084416 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.1943084416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3183475060 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 73979903 ps |
| CPU time | 1.55 seconds |
| Started | Aug 23 05:52:12 PM UTC 24 |
| Finished | Aug 23 05:52:15 PM UTC 24 |
| Peak memory | 225872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3183475060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_mem_rw_ with_rand_reset.3183475060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_csr_rw.593828569 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 29828501 ps |
| CPU time | 1.05 seconds |
| Started | Aug 23 05:52:12 PM UTC 24 |
| Finished | Aug 23 05:52:14 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593828569 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.593828569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_intr_test.3981783395 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 9747178 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 05:52:11 PM UTC 24 |
| Finished | Aug 23 05:52:13 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981783395 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3981783395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.886926317 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 52564728 ps |
| CPU time | 1.79 seconds |
| Started | Aug 23 05:52:12 PM UTC 24 |
| Finished | Aug 23 05:52:15 PM UTC 24 |
| Peak memory | 213592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886926317 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_same_csr_outstanding.886926317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2847390525 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 326987217 ps |
| CPU time | 2.47 seconds |
| Started | Aug 23 05:52:10 PM UTC 24 |
| Finished | Aug 23 05:52:13 PM UTC 24 |
| Peak memory | 226504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847390525 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors.2847390525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2285959921 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 270452853 ps |
| CPU time | 7.53 seconds |
| Started | Aug 23 05:52:11 PM UTC 24 |
| Finished | Aug 23 05:52:19 PM UTC 24 |
| Peak memory | 226532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285959921 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shadow_reg_errors_with_csr_rw.2285959921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_errors.3807787198 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 47309916 ps |
| CPU time | 2.79 seconds |
| Started | Aug 23 05:52:11 PM UTC 24 |
| Finished | Aug 23 05:52:15 PM UTC 24 |
| Peak memory | 226276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807787198 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3807787198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/17.keymgr_tl_intg_err.1154830494 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 150587747 ps |
| CPU time | 4.7 seconds |
| Started | Aug 23 05:52:11 PM UTC 24 |
| Finished | Aug 23 05:52:17 PM UTC 24 |
| Peak memory | 226352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154830494 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err.1154830494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3871300031 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 134561658 ps |
| CPU time | 1.12 seconds |
| Started | Aug 23 05:52:14 PM UTC 24 |
| Finished | Aug 23 05:52:17 PM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3871300031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_mem_rw_ with_rand_reset.3871300031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_csr_rw.2808057529 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 26001095 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 05:52:14 PM UTC 24 |
| Finished | Aug 23 05:52:17 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808057529 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2808057529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_intr_test.3083640070 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 37619543 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 05:52:13 PM UTC 24 |
| Finished | Aug 23 05:52:15 PM UTC 24 |
| Peak memory | 213188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083640070 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3083640070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3784479177 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 54311929 ps |
| CPU time | 2.11 seconds |
| Started | Aug 23 05:52:14 PM UTC 24 |
| Finished | Aug 23 05:52:17 PM UTC 24 |
| Peak memory | 216288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784479177 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_same_csr_outstanding.3784479177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.3413846521 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 102214031 ps |
| CPU time | 2.3 seconds |
| Started | Aug 23 05:52:12 PM UTC 24 |
| Finished | Aug 23 05:52:16 PM UTC 24 |
| Peak memory | 228468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413846521 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors.3413846521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4118334661 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 225649257 ps |
| CPU time | 4.56 seconds |
| Started | Aug 23 05:52:13 PM UTC 24 |
| Finished | Aug 23 05:52:19 PM UTC 24 |
| Peak memory | 226540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118334661 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shadow_reg_errors_with_csr_rw.4118334661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/18.keymgr_tl_errors.576717985 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 261988270 ps |
| CPU time | 2.92 seconds |
| Started | Aug 23 05:52:13 PM UTC 24 |
| Finished | Aug 23 05:52:17 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576717985 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.576717985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1273327900 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 89217118 ps |
| CPU time | 1.86 seconds |
| Started | Aug 23 05:52:16 PM UTC 24 |
| Finished | Aug 23 05:52:19 PM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1273327900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_mem_rw_ with_rand_reset.1273327900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_csr_rw.4154218018 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 48490807 ps |
| CPU time | 0.86 seconds |
| Started | Aug 23 05:52:15 PM UTC 24 |
| Finished | Aug 23 05:52:17 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154218018 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.4154218018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_intr_test.1695321803 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 13067167 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 05:52:15 PM UTC 24 |
| Finished | Aug 23 05:52:17 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695321803 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1695321803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1276813852 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 476977433 ps |
| CPU time | 1.85 seconds |
| Started | Aug 23 05:52:16 PM UTC 24 |
| Finished | Aug 23 05:52:19 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276813852 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_same_csr_outstanding.1276813852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1607678151 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 66579179 ps |
| CPU time | 2.18 seconds |
| Started | Aug 23 05:52:15 PM UTC 24 |
| Finished | Aug 23 05:52:18 PM UTC 24 |
| Peak memory | 226612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607678151 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors.1607678151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.917572005 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 381866371 ps |
| CPU time | 11.09 seconds |
| Started | Aug 23 05:52:15 PM UTC 24 |
| Finished | Aug 23 05:52:27 PM UTC 24 |
| Peak memory | 226540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917572005 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shadow_reg_errors_with_csr_rw.917572005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/19.keymgr_tl_errors.3111855268 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 44024760 ps |
| CPU time | 2.38 seconds |
| Started | Aug 23 05:52:15 PM UTC 24 |
| Finished | Aug 23 05:52:19 PM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111855268 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3111855268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_aliasing.4239680764 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 728352051 ps |
| CPU time | 7.03 seconds |
| Started | Aug 23 05:51:38 PM UTC 24 |
| Finished | Aug 23 05:51:46 PM UTC 24 |
| Peak memory | 215788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239680764 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.4239680764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_bit_bash.975668699 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 137177765 ps |
| CPU time | 5.26 seconds |
| Started | Aug 23 05:51:38 PM UTC 24 |
| Finished | Aug 23 05:51:45 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975668699 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.975668699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1465084736 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 172573182 ps |
| CPU time | 0.99 seconds |
| Started | Aug 23 05:51:38 PM UTC 24 |
| Finished | Aug 23 05:51:40 PM UTC 24 |
| Peak memory | 213716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465084736 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1465084736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1665040685 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 141402713 ps |
| CPU time | 2.04 seconds |
| Started | Aug 23 05:51:38 PM UTC 24 |
| Finished | Aug 23 05:51:42 PM UTC 24 |
| Peak memory | 232364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1665040685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_mem_rw_w ith_rand_reset.1665040685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_csr_rw.587331364 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 97467004 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 05:51:38 PM UTC 24 |
| Finished | Aug 23 05:51:41 PM UTC 24 |
| Peak memory | 213120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587331364 -assert nopostproc +UVM_TESTNAME=keymgr _base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 2/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.587331364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_intr_test.518530117 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 9319385 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 05:51:37 PM UTC 24 |
| Finished | Aug 23 05:51:39 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518530117 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.518530117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.1897168752 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 57042633 ps |
| CPU time | 2.12 seconds |
| Started | Aug 23 05:51:38 PM UTC 24 |
| Finished | Aug 23 05:51:42 PM UTC 24 |
| Peak memory | 215940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897168752 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_same_csr_outstanding.1897168752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1175676649 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 489348386 ps |
| CPU time | 3.67 seconds |
| Started | Aug 23 05:51:37 PM UTC 24 |
| Finished | Aug 23 05:51:42 PM UTC 24 |
| Peak memory | 230588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175676649 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors.1175676649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1958543787 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 650892298 ps |
| CPU time | 6.81 seconds |
| Started | Aug 23 05:51:37 PM UTC 24 |
| Finished | Aug 23 05:51:45 PM UTC 24 |
| Peak memory | 226736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958543787 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow_reg_errors_with_csr_rw.1958543787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/2.keymgr_tl_errors.605238570 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 69144250 ps |
| CPU time | 1.81 seconds |
| Started | Aug 23 05:51:37 PM UTC 24 |
| Finished | Aug 23 05:51:40 PM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605238570 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.605238570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/20.keymgr_intr_test.1213926521 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 24061950 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:52:16 PM UTC 24 |
| Finished | Aug 23 05:52:18 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213926521 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1213926521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/21.keymgr_intr_test.2724125794 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 10194972 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 05:52:17 PM UTC 24 |
| Finished | Aug 23 05:52:19 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724125794 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2724125794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/22.keymgr_intr_test.4043111254 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 14182875 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 05:52:17 PM UTC 24 |
| Finished | Aug 23 05:52:19 PM UTC 24 |
| Peak memory | 213564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4043111254 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.4043111254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/23.keymgr_intr_test.4274231016 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 47861665 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 05:52:18 PM UTC 24 |
| Finished | Aug 23 05:52:19 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274231016 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.4274231016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/24.keymgr_intr_test.2668192813 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 23872689 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 05:52:18 PM UTC 24 |
| Finished | Aug 23 05:52:19 PM UTC 24 |
| Peak memory | 213188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2668192813 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2668192813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/25.keymgr_intr_test.3660765467 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 30092232 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 05:52:18 PM UTC 24 |
| Finished | Aug 23 05:52:19 PM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660765467 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3660765467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/26.keymgr_intr_test.162886092 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 20531017 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 05:52:18 PM UTC 24 |
| Finished | Aug 23 05:52:19 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162886092 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.162886092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/27.keymgr_intr_test.4189824237 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 7664092 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 05:52:18 PM UTC 24 |
| Finished | Aug 23 05:52:19 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189824237 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.4189824237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/28.keymgr_intr_test.3892396489 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 22855982 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 05:52:19 PM UTC 24 |
| Finished | Aug 23 05:52:21 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892396489 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.3892396489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/29.keymgr_intr_test.1687865367 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 12577352 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 05:52:19 PM UTC 24 |
| Finished | Aug 23 05:52:21 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687865367 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1687865367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_aliasing.2449187401 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 1272571103 ps |
| CPU time | 6.77 seconds |
| Started | Aug 23 05:51:42 PM UTC 24 |
| Finished | Aug 23 05:51:50 PM UTC 24 |
| Peak memory | 215804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449187401 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2449187401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_bit_bash.168060551 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 3277693579 ps |
| CPU time | 12.64 seconds |
| Started | Aug 23 05:51:41 PM UTC 24 |
| Finished | Aug 23 05:51:55 PM UTC 24 |
| Peak memory | 216096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168060551 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.168060551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_hw_reset.3603403825 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 65916726 ps |
| CPU time | 0.98 seconds |
| Started | Aug 23 05:51:41 PM UTC 24 |
| Finished | Aug 23 05:51:43 PM UTC 24 |
| Peak memory | 213128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603403825 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.3603403825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2494387639 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 60193575 ps |
| CPU time | 1.54 seconds |
| Started | Aug 23 05:51:43 PM UTC 24 |
| Finished | Aug 23 05:51:46 PM UTC 24 |
| Peak memory | 223452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2494387639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_mem_rw_w ith_rand_reset.2494387639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_csr_rw.1668170573 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 23582528 ps |
| CPU time | 0.91 seconds |
| Started | Aug 23 05:51:41 PM UTC 24 |
| Finished | Aug 23 05:51:43 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668170573 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1668170573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_intr_test.578429523 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 36064561 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 05:51:40 PM UTC 24 |
| Finished | Aug 23 05:51:41 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578429523 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.578429523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2484709839 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 119832920 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 05:51:42 PM UTC 24 |
| Finished | Aug 23 05:51:44 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484709839 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_same_csr_outstanding.2484709839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2324134405 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 107401711 ps |
| CPU time | 2.02 seconds |
| Started | Aug 23 05:51:38 PM UTC 24 |
| Finished | Aug 23 05:51:42 PM UTC 24 |
| Peak memory | 226684 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324134405 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors.2324134405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1658540203 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 298698509 ps |
| CPU time | 6.86 seconds |
| Started | Aug 23 05:51:38 PM UTC 24 |
| Finished | Aug 23 05:51:46 PM UTC 24 |
| Peak memory | 226600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658540203 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shadow_reg_errors_with_csr_rw.1658540203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_errors.1849071177 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 30831607 ps |
| CPU time | 1.56 seconds |
| Started | Aug 23 05:51:39 PM UTC 24 |
| Finished | Aug 23 05:51:42 PM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849071177 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1849071177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/3.keymgr_tl_intg_err.3847984704 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 531497008 ps |
| CPU time | 3.95 seconds |
| Started | Aug 23 05:51:40 PM UTC 24 |
| Finished | Aug 23 05:51:45 PM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847984704 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.3847984704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/30.keymgr_intr_test.2993898768 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 15036047 ps |
| CPU time | 0.8 seconds |
| Started | Aug 23 05:52:19 PM UTC 24 |
| Finished | Aug 23 05:52:21 PM UTC 24 |
| Peak memory | 213188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993898768 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2993898768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/31.keymgr_intr_test.187701073 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 30328103 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187701073 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.187701073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/32.keymgr_intr_test.4271178208 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 45596713 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 213188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271178208 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.4271178208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/33.keymgr_intr_test.920624767 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 35555795 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920624767 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.920624767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/34.keymgr_intr_test.4005580915 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 16547931 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 213188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005580915 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.4005580915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/35.keymgr_intr_test.3950676628 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 12636144 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950676628 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3950676628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/36.keymgr_intr_test.1322439391 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 21039799 ps |
| CPU time | 0.81 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 213164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322439391 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1322439391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/37.keymgr_intr_test.1918650429 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 47125436 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918650429 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.1918650429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/38.keymgr_intr_test.287850896 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 129760148 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287850896 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.287850896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/39.keymgr_intr_test.2031694908 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 11649732 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031694908 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2031694908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_aliasing.2705370356 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 247945940 ps |
| CPU time | 7.01 seconds |
| Started | Aug 23 05:51:45 PM UTC 24 |
| Finished | Aug 23 05:51:53 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705370356 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2705370356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_bit_bash.4262776434 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 995981376 ps |
| CPU time | 12.03 seconds |
| Started | Aug 23 05:51:45 PM UTC 24 |
| Finished | Aug 23 05:51:58 PM UTC 24 |
| Peak memory | 215852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262776434 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.4262776434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3881440382 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 25420521 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 05:51:44 PM UTC 24 |
| Finished | Aug 23 05:51:46 PM UTC 24 |
| Peak memory | 212756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881440382 -assert nopostproc +UVM_TESTNAME =keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3881440382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.791016753 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 23928890 ps |
| CPU time | 0.95 seconds |
| Started | Aug 23 05:51:45 PM UTC 24 |
| Finished | Aug 23 05:51:47 PM UTC 24 |
| Peak memory | 223828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=791016753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_mem_rw_wi th_rand_reset.791016753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_csr_rw.1782443617 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 15243644 ps |
| CPU time | 0.95 seconds |
| Started | Aug 23 05:51:44 PM UTC 24 |
| Finished | Aug 23 05:51:46 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782443617 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1782443617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_intr_test.1210570604 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 50733662 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 05:51:44 PM UTC 24 |
| Finished | Aug 23 05:51:46 PM UTC 24 |
| Peak memory | 213352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210570604 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1210570604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.816757061 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 76713851 ps |
| CPU time | 1.33 seconds |
| Started | Aug 23 05:51:45 PM UTC 24 |
| Finished | Aug 23 05:51:48 PM UTC 24 |
| Peak memory | 213656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816757061 -assert nopostproc +U VM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_same_csr_outstanding.816757061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.770904506 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 550665184 ps |
| CPU time | 3.84 seconds |
| Started | Aug 23 05:51:43 PM UTC 24 |
| Finished | Aug 23 05:51:48 PM UTC 24 |
| Peak memory | 226800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770904506 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors.770904506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.4140922357 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 771816875 ps |
| CPU time | 5.73 seconds |
| Started | Aug 23 05:51:43 PM UTC 24 |
| Finished | Aug 23 05:51:50 PM UTC 24 |
| Peak memory | 226420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140922357 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow_reg_errors_with_csr_rw.4140922357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/4.keymgr_tl_errors.2980459113 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 345162357 ps |
| CPU time | 2.79 seconds |
| Started | Aug 23 05:51:43 PM UTC 24 |
| Finished | Aug 23 05:51:47 PM UTC 24 |
| Peak memory | 226136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980459113 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2980459113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/40.keymgr_intr_test.3800641668 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 8072820 ps |
| CPU time | 0.59 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 212496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800641668 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3800641668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/41.keymgr_intr_test.4115551821 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 46110342 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115551821 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.4115551821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/42.keymgr_intr_test.2681194863 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 59681739 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 213120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681194863 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2681194863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/43.keymgr_intr_test.4046342106 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 27625536 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 05:52:20 PM UTC 24 |
| Finished | Aug 23 05:52:22 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046342106 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4046342106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/44.keymgr_intr_test.27809165 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 15232328 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 05:52:21 PM UTC 24 |
| Finished | Aug 23 05:52:23 PM UTC 24 |
| Peak memory | 213580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27809165 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.27809165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/45.keymgr_intr_test.2845746545 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 12161232 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 05:52:21 PM UTC 24 |
| Finished | Aug 23 05:52:23 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845746545 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.2845746545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/46.keymgr_intr_test.1213064326 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 33654126 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 05:52:21 PM UTC 24 |
| Finished | Aug 23 05:52:23 PM UTC 24 |
| Peak memory | 213188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1213064326 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1213064326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/47.keymgr_intr_test.293501821 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 11555911 ps |
| CPU time | 0.65 seconds |
| Started | Aug 23 05:52:22 PM UTC 24 |
| Finished | Aug 23 05:52:24 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293501821 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.293501821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/48.keymgr_intr_test.2970484735 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 13635629 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 05:52:22 PM UTC 24 |
| Finished | Aug 23 05:52:24 PM UTC 24 |
| Peak memory | 213588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970484735 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2970484735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/49.keymgr_intr_test.3754068665 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 41850138 ps |
| CPU time | 0.79 seconds |
| Started | Aug 23 05:52:22 PM UTC 24 |
| Finished | Aug 23 05:52:24 PM UTC 24 |
| Peak memory | 213516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754068665 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3754068665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2224807355 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 23757663 ps |
| CPU time | 1.11 seconds |
| Started | Aug 23 05:51:47 PM UTC 24 |
| Finished | Aug 23 05:51:50 PM UTC 24 |
| Peak memory | 226176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2224807355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_mem_rw_w ith_rand_reset.2224807355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_csr_rw.1937104291 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 29814167 ps |
| CPU time | 0.86 seconds |
| Started | Aug 23 05:51:47 PM UTC 24 |
| Finished | Aug 23 05:51:50 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937104291 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1937104291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_intr_test.3309546956 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 45456721 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 05:51:46 PM UTC 24 |
| Finished | Aug 23 05:51:48 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309546956 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3309546956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2100306986 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 175295526 ps |
| CPU time | 1.73 seconds |
| Started | Aug 23 05:51:47 PM UTC 24 |
| Finished | Aug 23 05:51:51 PM UTC 24 |
| Peak memory | 213568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100306986 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_same_csr_outstanding.2100306986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1739448742 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 135008440 ps |
| CPU time | 1.64 seconds |
| Started | Aug 23 05:51:45 PM UTC 24 |
| Finished | Aug 23 05:51:48 PM UTC 24 |
| Peak memory | 226712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739448742 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors.1739448742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3638354521 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 278552571 ps |
| CPU time | 6.72 seconds |
| Started | Aug 23 05:51:46 PM UTC 24 |
| Finished | Aug 23 05:51:54 PM UTC 24 |
| Peak memory | 226856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638354521 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_reg_errors_with_csr_rw.3638354521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_errors.3948056214 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 43854870 ps |
| CPU time | 2.38 seconds |
| Started | Aug 23 05:51:46 PM UTC 24 |
| Finished | Aug 23 05:51:50 PM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948056214 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3948056214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/5.keymgr_tl_intg_err.313387020 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 408769301 ps |
| CPU time | 3.92 seconds |
| Started | Aug 23 05:51:46 PM UTC 24 |
| Finished | Aug 23 05:51:51 PM UTC 24 |
| Peak memory | 226464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313387020 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.313387020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2782135825 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 175113061 ps |
| CPU time | 1.88 seconds |
| Started | Aug 23 05:51:51 PM UTC 24 |
| Finished | Aug 23 05:51:54 PM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2782135825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_mem_rw_w ith_rand_reset.2782135825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_csr_rw.1127031449 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 23378596 ps |
| CPU time | 1.04 seconds |
| Started | Aug 23 05:51:50 PM UTC 24 |
| Finished | Aug 23 05:51:52 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127031449 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1127031449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_intr_test.451489885 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 11744814 ps |
| CPU time | 0.79 seconds |
| Started | Aug 23 05:51:50 PM UTC 24 |
| Finished | Aug 23 05:51:52 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451489885 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.451489885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.4135166573 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 94787062 ps |
| CPU time | 1.34 seconds |
| Started | Aug 23 05:51:50 PM UTC 24 |
| Finished | Aug 23 05:51:52 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135166573 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same_csr_outstanding.4135166573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3907597668 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 2002382500 ps |
| CPU time | 3.02 seconds |
| Started | Aug 23 05:51:48 PM UTC 24 |
| Finished | Aug 23 05:51:53 PM UTC 24 |
| Peak memory | 226584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907597668 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors.3907597668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.1257670864 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 842442032 ps |
| CPU time | 4.81 seconds |
| Started | Aug 23 05:51:48 PM UTC 24 |
| Finished | Aug 23 05:51:55 PM UTC 24 |
| Peak memory | 226432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257670864 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow_reg_errors_with_csr_rw.1257670864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/6.keymgr_tl_errors.2292412972 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 318270181 ps |
| CPU time | 2.2 seconds |
| Started | Aug 23 05:51:49 PM UTC 24 |
| Finished | Aug 23 05:51:53 PM UTC 24 |
| Peak memory | 226436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292412972 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2292412972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.60086154 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 51859553 ps |
| CPU time | 1.86 seconds |
| Started | Aug 23 05:51:53 PM UTC 24 |
| Finished | Aug 23 05:51:56 PM UTC 24 |
| Peak memory | 225500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=60086154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_mem_rw_wit h_rand_reset.60086154 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_csr_rw.2999302214 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 18947043 ps |
| CPU time | 1.07 seconds |
| Started | Aug 23 05:51:52 PM UTC 24 |
| Finished | Aug 23 05:51:54 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999302214 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2999302214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_intr_test.851422560 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 40452363 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 05:51:52 PM UTC 24 |
| Finished | Aug 23 05:51:54 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851422560 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/k eymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.851422560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1893304918 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 40745109 ps |
| CPU time | 1.33 seconds |
| Started | Aug 23 05:51:52 PM UTC 24 |
| Finished | Aug 23 05:51:55 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893304918 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_same_csr_outstanding.1893304918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.476569523 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 88606508 ps |
| CPU time | 1.99 seconds |
| Started | Aug 23 05:51:51 PM UTC 24 |
| Finished | Aug 23 05:51:54 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476569523 -assert nopostproc +UVM_ TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors.476569523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.788949553 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 3690138135 ps |
| CPU time | 6.03 seconds |
| Started | Aug 23 05:51:51 PM UTC 24 |
| Finished | Aug 23 05:51:58 PM UTC 24 |
| Peak memory | 226612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788949553 -assert nopo stproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow_reg_errors_with_csr_rw.788949553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_errors.2013855493 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 214249402 ps |
| CPU time | 2.96 seconds |
| Started | Aug 23 05:51:51 PM UTC 24 |
| Finished | Aug 23 05:51:55 PM UTC 24 |
| Peak memory | 226272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013855493 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2013855493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/7.keymgr_tl_intg_err.176451789 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 417609223 ps |
| CPU time | 3.01 seconds |
| Started | Aug 23 05:51:52 PM UTC 24 |
| Finished | Aug 23 05:51:56 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=176451789 -assert nopostproc +UVM_TESTNA ME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.176451789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1702045776 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 60572812 ps |
| CPU time | 1.26 seconds |
| Started | Aug 23 05:51:55 PM UTC 24 |
| Finished | Aug 23 05:51:58 PM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1702045776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_mem_rw_w ith_rand_reset.1702045776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_csr_rw.2866829925 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 93818544 ps |
| CPU time | 1.02 seconds |
| Started | Aug 23 05:51:54 PM UTC 24 |
| Finished | Aug 23 05:51:56 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866829925 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2866829925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_intr_test.1969216662 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 13322125 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 05:51:54 PM UTC 24 |
| Finished | Aug 23 05:51:56 PM UTC 24 |
| Peak memory | 213584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969216662 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1969216662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1788189805 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 116455586 ps |
| CPU time | 1.85 seconds |
| Started | Aug 23 05:51:55 PM UTC 24 |
| Finished | Aug 23 05:51:58 PM UTC 24 |
| Peak memory | 213124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788189805 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same_csr_outstanding.1788189805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2755411250 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 148705151 ps |
| CPU time | 2.57 seconds |
| Started | Aug 23 05:51:53 PM UTC 24 |
| Finished | Aug 23 05:51:57 PM UTC 24 |
| Peak memory | 225856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755411250 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors.2755411250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2341761397 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 307623977 ps |
| CPU time | 4.04 seconds |
| Started | Aug 23 05:51:53 PM UTC 24 |
| Finished | Aug 23 05:51:58 PM UTC 24 |
| Peak memory | 226796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341761397 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow_reg_errors_with_csr_rw.2341761397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_errors.2700975039 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 42009443 ps |
| CPU time | 2.63 seconds |
| Started | Aug 23 05:51:53 PM UTC 24 |
| Finished | Aug 23 05:51:57 PM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700975039 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2700975039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/8.keymgr_tl_intg_err.3691428010 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 427140900 ps |
| CPU time | 3.91 seconds |
| Started | Aug 23 05:51:54 PM UTC 24 |
| Finished | Aug 23 05:51:59 PM UTC 24 |
| Peak memory | 215868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3691428010 -assert nopostproc +UVM_TESTN AME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.3691428010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1791941664 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 22159579 ps |
| CPU time | 1.1 seconds |
| Started | Aug 23 05:51:57 PM UTC 24 |
| Finished | Aug 23 05:51:59 PM UTC 24 |
| Peak memory | 223824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1791941664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_mem_rw_w ith_rand_reset.1791941664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_csr_rw.3544786311 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 18915576 ps |
| CPU time | 0.86 seconds |
| Started | Aug 23 05:51:56 PM UTC 24 |
| Finished | Aug 23 05:51:59 PM UTC 24 |
| Peak memory | 212748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544786311 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3544786311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_intr_test.1506293827 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 13126389 ps |
| CPU time | 0.6 seconds |
| Started | Aug 23 05:51:55 PM UTC 24 |
| Finished | Aug 23 05:51:57 PM UTC 24 |
| Peak memory | 212944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506293827 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1506293827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2724142704 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 170364341 ps |
| CPU time | 1.35 seconds |
| Started | Aug 23 05:51:57 PM UTC 24 |
| Finished | Aug 23 05:51:59 PM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724142704 -assert nopostproc + UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same_csr_outstanding.2724142704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1761845248 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 207346287 ps |
| CPU time | 2.95 seconds |
| Started | Aug 23 05:51:55 PM UTC 24 |
| Finished | Aug 23 05:52:00 PM UTC 24 |
| Peak memory | 226492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761845248 -assert nopostproc +UVM _TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors.1761845248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_shadow_reg_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2900557032 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 968897029 ps |
| CPU time | 4.74 seconds |
| Started | Aug 23 05:51:55 PM UTC 24 |
| Finished | Aug 23 05:52:02 PM UTC 24 |
| Peak memory | 232172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900557032 -assert nop ostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow_reg_errors_with_csr_rw.2900557032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_shadow_reg_errors_with_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/cover_reg_top/9.keymgr_tl_errors.1546316060 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 311546738 ps |
| CPU time | 2.12 seconds |
| Started | Aug 23 05:51:55 PM UTC 24 |
| Finished | Aug 23 05:51:59 PM UTC 24 |
| Peak memory | 232692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546316060 -assert nopostproc +UVM_TESTNAME=keymgr_b ase_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ keymgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1546316060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_direct_to_disabled.1218365210 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 17712361 ps |
| CPU time | 1.31 seconds |
| Started | Aug 23 07:02:37 PM UTC 24 |
| Finished | Aug 23 07:02:40 PM UTC 24 |
| Peak memory | 214900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218365210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1218365210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_kmac_rsp_err.3515912496 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 149160475 ps |
| CPU time | 2.7 seconds |
| Started | Aug 23 07:02:40 PM UTC 24 |
| Finished | Aug 23 07:02:44 PM UTC 24 |
| Peak memory | 219948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515912496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3515912496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_sideload.1130230598 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 95143336 ps |
| CPU time | 3.4 seconds |
| Started | Aug 23 07:02:36 PM UTC 24 |
| Finished | Aug 23 07:02:41 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130230598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1130230598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_aes.3386310160 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 675685679 ps |
| CPU time | 6.29 seconds |
| Started | Aug 23 07:02:36 PM UTC 24 |
| Finished | Aug 23 07:02:44 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386310160 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3386310160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_otbn.1643078143 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 143341485 ps |
| CPU time | 2.65 seconds |
| Started | Aug 23 07:02:36 PM UTC 24 |
| Finished | Aug 23 07:02:40 PM UTC 24 |
| Peak memory | 217924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643078143 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.1643078143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_sideload_protect.2379086031 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 62571467 ps |
| CPU time | 2.42 seconds |
| Started | Aug 23 07:02:43 PM UTC 24 |
| Finished | Aug 23 07:02:46 PM UTC 24 |
| Peak memory | 218312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379086031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2379086031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/0.keymgr_smoke.971242965 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3089889615 ps |
| CPU time | 26.5 seconds |
| Started | Aug 23 07:02:36 PM UTC 24 |
| Finished | Aug 23 07:03:04 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=971242965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.971242965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/0.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_alert_test.3795364253 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 18336488 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 07:03:07 PM UTC 24 |
| Finished | Aug 23 07:03:08 PM UTC 24 |
| Peak memory | 213548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795364253 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3795364253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_direct_to_disabled.423410894 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 80677382 ps |
| CPU time | 3.04 seconds |
| Started | Aug 23 07:02:53 PM UTC 24 |
| Finished | Aug 23 07:02:57 PM UTC 24 |
| Peak memory | 228468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423410894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.423410894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_lc_disable.3752989814 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 630781099 ps |
| CPU time | 2.89 seconds |
| Started | Aug 23 07:02:57 PM UTC 24 |
| Finished | Aug 23 07:03:01 PM UTC 24 |
| Peak memory | 226084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752989814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3752989814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_random.3800081958 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 66491985 ps |
| CPU time | 3.44 seconds |
| Started | Aug 23 07:02:52 PM UTC 24 |
| Finished | Aug 23 07:02:57 PM UTC 24 |
| Peak memory | 220040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800081958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3800081958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_sideload.2467529021 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 127531474 ps |
| CPU time | 2.3 seconds |
| Started | Aug 23 07:02:48 PM UTC 24 |
| Finished | Aug 23 07:02:51 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467529021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2467529021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_aes.3981303222 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 142730722 ps |
| CPU time | 2.59 seconds |
| Started | Aug 23 07:02:49 PM UTC 24 |
| Finished | Aug 23 07:02:53 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981303222 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3981303222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_kmac.3204239847 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2215053329 ps |
| CPU time | 35.51 seconds |
| Started | Aug 23 07:02:49 PM UTC 24 |
| Finished | Aug 23 07:03:26 PM UTC 24 |
| Peak memory | 215900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3204239847 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3204239847 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_otbn.2910464063 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 108103887 ps |
| CPU time | 2.05 seconds |
| Started | Aug 23 07:02:49 PM UTC 24 |
| Finished | Aug 23 07:02:52 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2910464063 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2910464063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_sideload_protect.2766458185 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1179781234 ps |
| CPU time | 2.2 seconds |
| Started | Aug 23 07:03:02 PM UTC 24 |
| Finished | Aug 23 07:03:06 PM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766458185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2766458185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_smoke.905871148 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2867718993 ps |
| CPU time | 34.05 seconds |
| Started | Aug 23 07:02:47 PM UTC 24 |
| Finished | Aug 23 07:03:22 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905871148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.905871148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_stress_all_with_rand_reset.267543341 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 1227740680 ps |
| CPU time | 11.84 seconds |
| Started | Aug 23 07:03:04 PM UTC 24 |
| Finished | Aug 23 07:03:17 PM UTC 24 |
| Peak memory | 230308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=267543341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_ stress_all_with_rand_reset.267543341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/1.keymgr_sw_invalid_input.2849123530 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 709070557 ps |
| CPU time | 4.08 seconds |
| Started | Aug 23 07:02:58 PM UTC 24 |
| Finished | Aug 23 07:03:03 PM UTC 24 |
| Peak memory | 230252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849123530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2849123530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/1.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_alert_test.3555351551 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 50726050 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 07:05:33 PM UTC 24 |
| Finished | Aug 23 07:05:35 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555351551 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3555351551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_cfg_regwen.2005307271 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 707796437 ps |
| CPU time | 7.66 seconds |
| Started | Aug 23 07:05:21 PM UTC 24 |
| Finished | Aug 23 07:05:30 PM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005307271 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2005307271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_custom_cm.104595824 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 57833750 ps |
| CPU time | 1.77 seconds |
| Started | Aug 23 07:05:27 PM UTC 24 |
| Finished | Aug 23 07:05:29 PM UTC 24 |
| Peak memory | 217580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104595824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.104595824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_direct_to_disabled.1082237833 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 239210831 ps |
| CPU time | 2.35 seconds |
| Started | Aug 23 07:05:22 PM UTC 24 |
| Finished | Aug 23 07:05:26 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082237833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1082237833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_lc_disable.3600248425 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 64884954 ps |
| CPU time | 2.08 seconds |
| Started | Aug 23 07:05:24 PM UTC 24 |
| Finished | Aug 23 07:05:27 PM UTC 24 |
| Peak memory | 224040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600248425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3600248425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_random.1709944381 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 391390850 ps |
| CPU time | 3.94 seconds |
| Started | Aug 23 07:05:19 PM UTC 24 |
| Finished | Aug 23 07:05:24 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709944381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1709944381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_sideload.2781170170 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 133002865 ps |
| CPU time | 4.56 seconds |
| Started | Aug 23 07:05:15 PM UTC 24 |
| Finished | Aug 23 07:05:20 PM UTC 24 |
| Peak memory | 217932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781170170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2781170170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_aes.2965904779 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 136146465 ps |
| CPU time | 2.98 seconds |
| Started | Aug 23 07:05:19 PM UTC 24 |
| Finished | Aug 23 07:05:23 PM UTC 24 |
| Peak memory | 217984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965904779 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2965904779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_kmac.3120482825 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 40468929 ps |
| CPU time | 2.3 seconds |
| Started | Aug 23 07:05:15 PM UTC 24 |
| Finished | Aug 23 07:05:18 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3120482825 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3120482825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_otbn.867991074 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 766600001 ps |
| CPU time | 14.1 seconds |
| Started | Aug 23 07:05:19 PM UTC 24 |
| Finished | Aug 23 07:05:34 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=867991074 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.867991074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_sideload_protect.1434866137 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 211162928 ps |
| CPU time | 2.56 seconds |
| Started | Aug 23 07:05:29 PM UTC 24 |
| Finished | Aug 23 07:05:32 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434866137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1434866137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_smoke.3713301368 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 54389324 ps |
| CPU time | 2.29 seconds |
| Started | Aug 23 07:05:15 PM UTC 24 |
| Finished | Aug 23 07:05:18 PM UTC 24 |
| Peak memory | 215512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713301368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3713301368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_stress_all.682952978 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 440162813 ps |
| CPU time | 8.54 seconds |
| Started | Aug 23 07:05:31 PM UTC 24 |
| Finished | Aug 23 07:05:41 PM UTC 24 |
| Peak memory | 227996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682952978 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.682952978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_sw_invalid_input.3902246334 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 140421977 ps |
| CPU time | 3.89 seconds |
| Started | Aug 23 07:05:25 PM UTC 24 |
| Finished | Aug 23 07:05:30 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902246334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3902246334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/10.keymgr_sync_async_fault_cross.1479372180 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 30664327 ps |
| CPU time | 1.75 seconds |
| Started | Aug 23 07:05:30 PM UTC 24 |
| Finished | Aug 23 07:05:33 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479372180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1479372180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/10.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_alert_test.105806302 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 34339189 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 07:05:48 PM UTC 24 |
| Finished | Aug 23 07:05:50 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105806302 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.105806302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_custom_cm.1048270220 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 1019337974 ps |
| CPU time | 5.57 seconds |
| Started | Aug 23 07:05:42 PM UTC 24 |
| Finished | Aug 23 07:05:49 PM UTC 24 |
| Peak memory | 230508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048270220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1048270220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_direct_to_disabled.1565767791 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 39393388 ps |
| CPU time | 1.56 seconds |
| Started | Aug 23 07:05:38 PM UTC 24 |
| Finished | Aug 23 07:05:40 PM UTC 24 |
| Peak memory | 214296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565767791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1565767791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_hwsw_invalid_input.1791789316 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 5538959438 ps |
| CPU time | 40.69 seconds |
| Started | Aug 23 07:05:40 PM UTC 24 |
| Finished | Aug 23 07:06:22 PM UTC 24 |
| Peak memory | 218272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791789316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1791789316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_lc_disable.3572253702 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 246468294 ps |
| CPU time | 2.77 seconds |
| Started | Aug 23 07:05:39 PM UTC 24 |
| Finished | Aug 23 07:05:42 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572253702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3572253702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_random.2292449949 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 109752656 ps |
| CPU time | 1.98 seconds |
| Started | Aug 23 07:05:36 PM UTC 24 |
| Finished | Aug 23 07:05:39 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292449949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2292449949 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_sideload.2003024442 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 177108772 ps |
| CPU time | 1.5 seconds |
| Started | Aug 23 07:05:33 PM UTC 24 |
| Finished | Aug 23 07:05:36 PM UTC 24 |
| Peak memory | 215648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003024442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2003024442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_aes.4033060310 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 245571301 ps |
| CPU time | 2.49 seconds |
| Started | Aug 23 07:05:35 PM UTC 24 |
| Finished | Aug 23 07:05:39 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033060310 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.4033060310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_kmac.161585461 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 1699535783 ps |
| CPU time | 38.89 seconds |
| Started | Aug 23 07:05:34 PM UTC 24 |
| Finished | Aug 23 07:06:15 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161585461 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.161585461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_otbn.365669295 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 24693933 ps |
| CPU time | 1.8 seconds |
| Started | Aug 23 07:05:35 PM UTC 24 |
| Finished | Aug 23 07:05:38 PM UTC 24 |
| Peak memory | 217688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365669295 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.365669295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_sideload_protect.4226644328 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 151394437 ps |
| CPU time | 4 seconds |
| Started | Aug 23 07:05:43 PM UTC 24 |
| Finished | Aug 23 07:05:48 PM UTC 24 |
| Peak memory | 228292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226644328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.4226644328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_smoke.1671423219 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 32627468 ps |
| CPU time | 1.83 seconds |
| Started | Aug 23 07:05:33 PM UTC 24 |
| Finished | Aug 23 07:05:36 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671423219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1671423219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_sw_invalid_input.2340121542 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 90097429 ps |
| CPU time | 3.76 seconds |
| Started | Aug 23 07:05:40 PM UTC 24 |
| Finished | Aug 23 07:05:45 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340121542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2340121542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/11.keymgr_sync_async_fault_cross.3614691142 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 72902319 ps |
| CPU time | 1.55 seconds |
| Started | Aug 23 07:05:45 PM UTC 24 |
| Finished | Aug 23 07:05:48 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3614691142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3614691142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/11.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_alert_test.4262172637 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 13294980 ps |
| CPU time | 0.62 seconds |
| Started | Aug 23 07:06:04 PM UTC 24 |
| Finished | Aug 23 07:06:05 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262172637 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.4262172637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_cfg_regwen.3041962240 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 222586795 ps |
| CPU time | 2.77 seconds |
| Started | Aug 23 07:05:54 PM UTC 24 |
| Finished | Aug 23 07:05:58 PM UTC 24 |
| Peak memory | 224356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041962240 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.3041962240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_custom_cm.2176179411 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 450371807 ps |
| CPU time | 3.22 seconds |
| Started | Aug 23 07:05:58 PM UTC 24 |
| Finished | Aug 23 07:06:03 PM UTC 24 |
| Peak memory | 231280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176179411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2176179411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_direct_to_disabled.2756335326 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 158727874 ps |
| CPU time | 1.78 seconds |
| Started | Aug 23 07:05:55 PM UTC 24 |
| Finished | Aug 23 07:05:58 PM UTC 24 |
| Peak memory | 227788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756335326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2756335326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_hwsw_invalid_input.1495027472 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 238010498 ps |
| CPU time | 2.71 seconds |
| Started | Aug 23 07:05:56 PM UTC 24 |
| Finished | Aug 23 07:06:00 PM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495027472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1495027472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_lc_disable.699921320 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 194936922 ps |
| CPU time | 2.41 seconds |
| Started | Aug 23 07:05:55 PM UTC 24 |
| Finished | Aug 23 07:05:58 PM UTC 24 |
| Peak memory | 232616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699921320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.699921320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_random.1368322323 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 5050106048 ps |
| CPU time | 28.32 seconds |
| Started | Aug 23 07:05:54 PM UTC 24 |
| Finished | Aug 23 07:06:23 PM UTC 24 |
| Peak memory | 228296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368322323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1368322323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_sideload.3980603605 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 1029371390 ps |
| CPU time | 22.29 seconds |
| Started | Aug 23 07:05:49 PM UTC 24 |
| Finished | Aug 23 07:06:13 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980603605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3980603605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_aes.1734853300 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 41329541 ps |
| CPU time | 2.12 seconds |
| Started | Aug 23 07:05:51 PM UTC 24 |
| Finished | Aug 23 07:05:54 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734853300 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1734853300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_kmac.4220543752 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 370704912 ps |
| CPU time | 3.66 seconds |
| Started | Aug 23 07:05:50 PM UTC 24 |
| Finished | Aug 23 07:05:54 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220543752 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.4220543752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_sideload_protect.835860661 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 148223949 ps |
| CPU time | 1.97 seconds |
| Started | Aug 23 07:05:59 PM UTC 24 |
| Finished | Aug 23 07:06:02 PM UTC 24 |
| Peak memory | 217628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835860661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.835860661 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_smoke.3244705282 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 221530293 ps |
| CPU time | 2.44 seconds |
| Started | Aug 23 07:05:49 PM UTC 24 |
| Finished | Aug 23 07:05:53 PM UTC 24 |
| Peak memory | 217824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244705282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3244705282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/12.keymgr_sw_invalid_input.451388768 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 72360283 ps |
| CPU time | 3.06 seconds |
| Started | Aug 23 07:05:55 PM UTC 24 |
| Finished | Aug 23 07:05:59 PM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=451388768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.451388768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/12.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_alert_test.2577163644 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 7936032 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 07:06:18 PM UTC 24 |
| Finished | Aug 23 07:06:20 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577163644 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2577163644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_cfg_regwen.429839643 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 48880831 ps |
| CPU time | 2.16 seconds |
| Started | Aug 23 07:06:09 PM UTC 24 |
| Finished | Aug 23 07:06:13 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429839643 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.429839643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_custom_cm.3019217876 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 52905203 ps |
| CPU time | 1.4 seconds |
| Started | Aug 23 07:06:15 PM UTC 24 |
| Finished | Aug 23 07:06:17 PM UTC 24 |
| Peak memory | 225760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019217876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3019217876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_direct_to_disabled.3160405339 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 296686802 ps |
| CPU time | 2.09 seconds |
| Started | Aug 23 07:06:10 PM UTC 24 |
| Finished | Aug 23 07:06:13 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3160405339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3160405339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_hwsw_invalid_input.1394558033 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 102129766 ps |
| CPU time | 1.66 seconds |
| Started | Aug 23 07:06:14 PM UTC 24 |
| Finished | Aug 23 07:06:17 PM UTC 24 |
| Peak memory | 223704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1394558033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1394558033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_kmac_rsp_err.3981828091 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 52936904 ps |
| CPU time | 2 seconds |
| Started | Aug 23 07:06:14 PM UTC 24 |
| Finished | Aug 23 07:06:17 PM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981828091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.3981828091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_lc_disable.2763254829 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 400822675 ps |
| CPU time | 3.18 seconds |
| Started | Aug 23 07:06:14 PM UTC 24 |
| Finished | Aug 23 07:06:18 PM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763254829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2763254829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_random.2881580941 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 47921969 ps |
| CPU time | 1.95 seconds |
| Started | Aug 23 07:06:09 PM UTC 24 |
| Finished | Aug 23 07:06:12 PM UTC 24 |
| Peak memory | 217756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881580941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2881580941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_sideload.206052411 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 352622394 ps |
| CPU time | 2.85 seconds |
| Started | Aug 23 07:06:04 PM UTC 24 |
| Finished | Aug 23 07:06:08 PM UTC 24 |
| Peak memory | 218120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206052411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.206052411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_aes.362654617 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 465972889 ps |
| CPU time | 3 seconds |
| Started | Aug 23 07:06:08 PM UTC 24 |
| Finished | Aug 23 07:06:12 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362654617 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.362654617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_kmac.978517064 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 47865800 ps |
| CPU time | 1.75 seconds |
| Started | Aug 23 07:06:06 PM UTC 24 |
| Finished | Aug 23 07:06:09 PM UTC 24 |
| Peak memory | 217688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978517064 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.978517064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_otbn.2596398851 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 885002767 ps |
| CPU time | 5.61 seconds |
| Started | Aug 23 07:06:08 PM UTC 24 |
| Finished | Aug 23 07:06:15 PM UTC 24 |
| Peak memory | 217992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596398851 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2596398851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_sideload_protect.241665325 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 221332114 ps |
| CPU time | 2.37 seconds |
| Started | Aug 23 07:06:16 PM UTC 24 |
| Finished | Aug 23 07:06:19 PM UTC 24 |
| Peak memory | 230424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241665325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.241665325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_smoke.2449305578 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 609943368 ps |
| CPU time | 3.08 seconds |
| Started | Aug 23 07:06:04 PM UTC 24 |
| Finished | Aug 23 07:06:08 PM UTC 24 |
| Peak memory | 217936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449305578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2449305578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_stress_all.3524290713 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 1454357808 ps |
| CPU time | 42.04 seconds |
| Started | Aug 23 07:06:17 PM UTC 24 |
| Finished | Aug 23 07:07:01 PM UTC 24 |
| Peak memory | 226404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524290713 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3524290713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_sw_invalid_input.1476541586 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 817362144 ps |
| CPU time | 6.23 seconds |
| Started | Aug 23 07:06:14 PM UTC 24 |
| Finished | Aug 23 07:06:21 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1476541586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1476541586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/13.keymgr_sync_async_fault_cross.214543607 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 123000634 ps |
| CPU time | 2.23 seconds |
| Started | Aug 23 07:06:16 PM UTC 24 |
| Finished | Aug 23 07:06:19 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214543607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.214543607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/13.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_alert_test.4124921088 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 17638919 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 07:06:30 PM UTC 24 |
| Finished | Aug 23 07:06:32 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124921088 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4124921088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_cfg_regwen.2988345507 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 120100177 ps |
| CPU time | 3 seconds |
| Started | Aug 23 07:06:23 PM UTC 24 |
| Finished | Aug 23 07:06:27 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988345507 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2988345507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_direct_to_disabled.102607714 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 67819093 ps |
| CPU time | 2.71 seconds |
| Started | Aug 23 07:06:24 PM UTC 24 |
| Finished | Aug 23 07:06:28 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102607714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.102607714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_lc_disable.3744392774 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 57733595 ps |
| CPU time | 2.72 seconds |
| Started | Aug 23 07:06:24 PM UTC 24 |
| Finished | Aug 23 07:06:28 PM UTC 24 |
| Peak memory | 230336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3744392774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3744392774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_random.3678935835 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1140479435 ps |
| CPU time | 25.33 seconds |
| Started | Aug 23 07:06:23 PM UTC 24 |
| Finished | Aug 23 07:06:50 PM UTC 24 |
| Peak memory | 215516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678935835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3678935835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_sideload.3591505163 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 33782367 ps |
| CPU time | 2.04 seconds |
| Started | Aug 23 07:06:21 PM UTC 24 |
| Finished | Aug 23 07:06:24 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591505163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3591505163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_aes.1813640321 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 453721899 ps |
| CPU time | 3.94 seconds |
| Started | Aug 23 07:06:21 PM UTC 24 |
| Finished | Aug 23 07:06:26 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813640321 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1813640321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_kmac.545910497 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 241204092 ps |
| CPU time | 2.49 seconds |
| Started | Aug 23 07:06:21 PM UTC 24 |
| Finished | Aug 23 07:06:24 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545910497 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.545910497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_otbn.4027923536 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 234721303 ps |
| CPU time | 2.82 seconds |
| Started | Aug 23 07:06:22 PM UTC 24 |
| Finished | Aug 23 07:06:26 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4027923536 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4027923536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_sideload_protect.4026690426 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 71489624 ps |
| CPU time | 1.73 seconds |
| Started | Aug 23 07:06:27 PM UTC 24 |
| Finished | Aug 23 07:06:30 PM UTC 24 |
| Peak memory | 217628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026690426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.4026690426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_smoke.1342062615 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 27938013 ps |
| CPU time | 1.71 seconds |
| Started | Aug 23 07:06:19 PM UTC 24 |
| Finished | Aug 23 07:06:22 PM UTC 24 |
| Peak memory | 217712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342062615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1342062615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_stress_all.361240109 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 1434385124 ps |
| CPU time | 27.65 seconds |
| Started | Aug 23 07:06:29 PM UTC 24 |
| Finished | Aug 23 07:06:58 PM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361240109 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.361240109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_sw_invalid_input.580335218 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 129871179 ps |
| CPU time | 2.23 seconds |
| Started | Aug 23 07:06:24 PM UTC 24 |
| Finished | Aug 23 07:06:27 PM UTC 24 |
| Peak memory | 220260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580335218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.580335218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/14.keymgr_sync_async_fault_cross.4014380860 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 351833173 ps |
| CPU time | 2.34 seconds |
| Started | Aug 23 07:06:29 PM UTC 24 |
| Finished | Aug 23 07:06:32 PM UTC 24 |
| Peak memory | 220012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014380860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.4014380860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/14.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_alert_test.1242103403 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 27422365 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 07:06:48 PM UTC 24 |
| Finished | Aug 23 07:06:50 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242103403 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1242103403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_cfg_regwen.1197358319 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 34150529 ps |
| CPU time | 2.22 seconds |
| Started | Aug 23 07:06:37 PM UTC 24 |
| Finished | Aug 23 07:06:41 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197358319 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1197358319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_direct_to_disabled.1927344537 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 301911105 ps |
| CPU time | 2.76 seconds |
| Started | Aug 23 07:06:38 PM UTC 24 |
| Finished | Aug 23 07:06:43 PM UTC 24 |
| Peak memory | 223976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927344537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1927344537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_hwsw_invalid_input.444918109 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 380007764 ps |
| CPU time | 4.05 seconds |
| Started | Aug 23 07:06:42 PM UTC 24 |
| Finished | Aug 23 07:06:47 PM UTC 24 |
| Peak memory | 218272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444918109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.444918109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_kmac_rsp_err.3760002582 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 40111627 ps |
| CPU time | 1.88 seconds |
| Started | Aug 23 07:06:42 PM UTC 24 |
| Finished | Aug 23 07:06:45 PM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760002582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3760002582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_lc_disable.264044196 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 356033237 ps |
| CPU time | 3.71 seconds |
| Started | Aug 23 07:06:39 PM UTC 24 |
| Finished | Aug 23 07:06:44 PM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264044196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.264044196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_random.4048856015 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 80457466 ps |
| CPU time | 2.56 seconds |
| Started | Aug 23 07:06:37 PM UTC 24 |
| Finished | Aug 23 07:06:41 PM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048856015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.4048856015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_sideload.2059944534 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 406703742 ps |
| CPU time | 3.24 seconds |
| Started | Aug 23 07:06:32 PM UTC 24 |
| Finished | Aug 23 07:06:37 PM UTC 24 |
| Peak memory | 218168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059944534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2059944534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_aes.1819359359 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1302859750 ps |
| CPU time | 28.33 seconds |
| Started | Aug 23 07:06:33 PM UTC 24 |
| Finished | Aug 23 07:07:03 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819359359 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1819359359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_kmac.2349796168 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 131322154 ps |
| CPU time | 4.01 seconds |
| Started | Aug 23 07:06:32 PM UTC 24 |
| Finished | Aug 23 07:06:38 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349796168 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2349796168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_otbn.647685758 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 36587276 ps |
| CPU time | 1.53 seconds |
| Started | Aug 23 07:06:36 PM UTC 24 |
| Finished | Aug 23 07:06:39 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647685758 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.647685758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_sideload_protect.1044639977 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 20847434 ps |
| CPU time | 1.67 seconds |
| Started | Aug 23 07:06:44 PM UTC 24 |
| Finished | Aug 23 07:06:47 PM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044639977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1044639977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_smoke.3397804634 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 216927298 ps |
| CPU time | 2.36 seconds |
| Started | Aug 23 07:06:31 PM UTC 24 |
| Finished | Aug 23 07:06:35 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397804634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3397804634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_stress_all_with_rand_reset.1060436355 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 1343576505 ps |
| CPU time | 17.37 seconds |
| Started | Aug 23 07:06:48 PM UTC 24 |
| Finished | Aug 23 07:07:07 PM UTC 24 |
| Peak memory | 232736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1060436355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymg r_stress_all_with_rand_reset.1060436355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_sw_invalid_input.3807295858 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 263464607 ps |
| CPU time | 7.98 seconds |
| Started | Aug 23 07:06:40 PM UTC 24 |
| Finished | Aug 23 07:06:49 PM UTC 24 |
| Peak memory | 218080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807295858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3807295858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/15.keymgr_sync_async_fault_cross.1477923485 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 90010323 ps |
| CPU time | 1.83 seconds |
| Started | Aug 23 07:06:46 PM UTC 24 |
| Finished | Aug 23 07:06:49 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477923485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1477923485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/15.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_alert_test.2627702603 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 12643834 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 07:07:05 PM UTC 24 |
| Finished | Aug 23 07:07:07 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627702603 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2627702603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_custom_cm.1339919579 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 741755654 ps |
| CPU time | 7.81 seconds |
| Started | Aug 23 07:07:02 PM UTC 24 |
| Finished | Aug 23 07:07:11 PM UTC 24 |
| Peak memory | 218296 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339919579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1339919579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_direct_to_disabled.1095314282 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 119355850 ps |
| CPU time | 3.11 seconds |
| Started | Aug 23 07:06:55 PM UTC 24 |
| Finished | Aug 23 07:06:59 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095314282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1095314282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_kmac_rsp_err.4116461997 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 74497003 ps |
| CPU time | 2.07 seconds |
| Started | Aug 23 07:07:00 PM UTC 24 |
| Finished | Aug 23 07:07:04 PM UTC 24 |
| Peak memory | 224060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116461997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.4116461997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_lc_disable.51489227 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 227350149 ps |
| CPU time | 2.91 seconds |
| Started | Aug 23 07:06:58 PM UTC 24 |
| Finished | Aug 23 07:07:02 PM UTC 24 |
| Peak memory | 224132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51489227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.51489227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_random.3964773279 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 88395222 ps |
| CPU time | 2.95 seconds |
| Started | Aug 23 07:06:54 PM UTC 24 |
| Finished | Aug 23 07:06:58 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964773279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3964773279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_sideload.2284472566 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 958753886 ps |
| CPU time | 17.52 seconds |
| Started | Aug 23 07:06:49 PM UTC 24 |
| Finished | Aug 23 07:07:09 PM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284472566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2284472566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_aes.1544679984 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 44665904 ps |
| CPU time | 2.09 seconds |
| Started | Aug 23 07:06:51 PM UTC 24 |
| Finished | Aug 23 07:06:54 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544679984 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1544679984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_kmac.988107859 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 129145699 ps |
| CPU time | 2.03 seconds |
| Started | Aug 23 07:06:51 PM UTC 24 |
| Finished | Aug 23 07:06:54 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988107859 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.988107859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_otbn.1144794571 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 140464099 ps |
| CPU time | 4.75 seconds |
| Started | Aug 23 07:06:54 PM UTC 24 |
| Finished | Aug 23 07:07:00 PM UTC 24 |
| Peak memory | 218144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144794571 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1144794571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_sideload_protect.1080351548 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 42260426 ps |
| CPU time | 2.4 seconds |
| Started | Aug 23 07:07:02 PM UTC 24 |
| Finished | Aug 23 07:07:06 PM UTC 24 |
| Peak memory | 220324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080351548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1080351548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_smoke.676097546 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 409986027 ps |
| CPU time | 2.42 seconds |
| Started | Aug 23 07:06:49 PM UTC 24 |
| Finished | Aug 23 07:06:53 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676097546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.676097546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_stress_all.384519971 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5621014227 ps |
| CPU time | 59 seconds |
| Started | Aug 23 07:07:04 PM UTC 24 |
| Finished | Aug 23 07:08:05 PM UTC 24 |
| Peak memory | 228188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384519971 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.384519971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/16.keymgr_sw_invalid_input.1729032529 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 5568080331 ps |
| CPU time | 50.36 seconds |
| Started | Aug 23 07:06:59 PM UTC 24 |
| Finished | Aug 23 07:07:52 PM UTC 24 |
| Peak memory | 226528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729032529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1729032529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/16.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_alert_test.2102742545 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 30470342 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 07:07:18 PM UTC 24 |
| Finished | Aug 23 07:07:20 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102742545 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2102742545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_cfg_regwen.2397291282 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 406841196 ps |
| CPU time | 8.81 seconds |
| Started | Aug 23 07:07:10 PM UTC 24 |
| Finished | Aug 23 07:07:20 PM UTC 24 |
| Peak memory | 226064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397291282 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2397291282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_custom_cm.17087650 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 78909532 ps |
| CPU time | 1.66 seconds |
| Started | Aug 23 07:07:13 PM UTC 24 |
| Finished | Aug 23 07:07:16 PM UTC 24 |
| Peak memory | 217700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17087650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.17087650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_direct_to_disabled.2170728937 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 287275775 ps |
| CPU time | 2.28 seconds |
| Started | Aug 23 07:07:10 PM UTC 24 |
| Finished | Aug 23 07:07:13 PM UTC 24 |
| Peak memory | 228212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170728937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2170728937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_kmac_rsp_err.1967534904 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 592717854 ps |
| CPU time | 3.46 seconds |
| Started | Aug 23 07:07:12 PM UTC 24 |
| Finished | Aug 23 07:07:17 PM UTC 24 |
| Peak memory | 224168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967534904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1967534904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_lc_disable.3152071731 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 284491950 ps |
| CPU time | 3.51 seconds |
| Started | Aug 23 07:07:10 PM UTC 24 |
| Finished | Aug 23 07:07:15 PM UTC 24 |
| Peak memory | 224476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152071731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3152071731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_random.1066814119 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 438786297 ps |
| CPU time | 9.83 seconds |
| Started | Aug 23 07:07:10 PM UTC 24 |
| Finished | Aug 23 07:07:21 PM UTC 24 |
| Peak memory | 217988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066814119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1066814119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_sideload.3129960402 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 58905271 ps |
| CPU time | 2.12 seconds |
| Started | Aug 23 07:07:06 PM UTC 24 |
| Finished | Aug 23 07:07:09 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129960402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3129960402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_aes.2725171825 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 21938518 ps |
| CPU time | 1.49 seconds |
| Started | Aug 23 07:07:08 PM UTC 24 |
| Finished | Aug 23 07:07:10 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725171825 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.2725171825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_kmac.941449698 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 1509244253 ps |
| CPU time | 4.13 seconds |
| Started | Aug 23 07:07:08 PM UTC 24 |
| Finished | Aug 23 07:07:13 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941449698 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.941449698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_otbn.3339889931 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 133659810 ps |
| CPU time | 2.66 seconds |
| Started | Aug 23 07:07:08 PM UTC 24 |
| Finished | Aug 23 07:07:11 PM UTC 24 |
| Peak memory | 218320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339889931 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3339889931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_sideload_protect.3394422703 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 366222654 ps |
| CPU time | 2.62 seconds |
| Started | Aug 23 07:07:14 PM UTC 24 |
| Finished | Aug 23 07:07:18 PM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394422703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3394422703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_smoke.3326595141 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 182184775 ps |
| CPU time | 2.04 seconds |
| Started | Aug 23 07:07:06 PM UTC 24 |
| Finished | Aug 23 07:07:09 PM UTC 24 |
| Peak memory | 215736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326595141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3326595141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_stress_all.3674222582 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 964027475 ps |
| CPU time | 31.16 seconds |
| Started | Aug 23 07:07:17 PM UTC 24 |
| Finished | Aug 23 07:07:49 PM UTC 24 |
| Peak memory | 228628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3674222582 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3674222582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_sw_invalid_input.2083492080 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 3197895351 ps |
| CPU time | 6.24 seconds |
| Started | Aug 23 07:07:11 PM UTC 24 |
| Finished | Aug 23 07:07:18 PM UTC 24 |
| Peak memory | 215896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083492080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2083492080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/17.keymgr_sync_async_fault_cross.594286537 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 322520800 ps |
| CPU time | 2.81 seconds |
| Started | Aug 23 07:07:16 PM UTC 24 |
| Finished | Aug 23 07:07:20 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594286537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.594286537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/17.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_alert_test.698723869 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 18052985 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 07:07:32 PM UTC 24 |
| Finished | Aug 23 07:07:33 PM UTC 24 |
| Peak memory | 213540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698723869 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.698723869 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_direct_to_disabled.2937491469 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 741424415 ps |
| CPU time | 5.28 seconds |
| Started | Aug 23 07:07:24 PM UTC 24 |
| Finished | Aug 23 07:07:30 PM UTC 24 |
| Peak memory | 217876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937491469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2937491469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_hwsw_invalid_input.263496114 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 1515041481 ps |
| CPU time | 3.76 seconds |
| Started | Aug 23 07:07:26 PM UTC 24 |
| Finished | Aug 23 07:07:31 PM UTC 24 |
| Peak memory | 226068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263496114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.263496114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_kmac_rsp_err.2234632206 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 92184557 ps |
| CPU time | 3.48 seconds |
| Started | Aug 23 07:07:28 PM UTC 24 |
| Finished | Aug 23 07:07:33 PM UTC 24 |
| Peak memory | 230760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234632206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2234632206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_lc_disable.4067983680 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 1116471652 ps |
| CPU time | 3.2 seconds |
| Started | Aug 23 07:07:24 PM UTC 24 |
| Finished | Aug 23 07:07:28 PM UTC 24 |
| Peak memory | 230508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067983680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.4067983680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_random.3214264342 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 147799725 ps |
| CPU time | 5.14 seconds |
| Started | Aug 23 07:07:21 PM UTC 24 |
| Finished | Aug 23 07:07:28 PM UTC 24 |
| Peak memory | 230248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3214264342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3214264342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_aes.1616712854 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 23549964 ps |
| CPU time | 1.64 seconds |
| Started | Aug 23 07:07:20 PM UTC 24 |
| Finished | Aug 23 07:07:23 PM UTC 24 |
| Peak memory | 217688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616712854 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1616712854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_kmac.336380198 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 636802972 ps |
| CPU time | 2.61 seconds |
| Started | Aug 23 07:07:20 PM UTC 24 |
| Finished | Aug 23 07:07:24 PM UTC 24 |
| Peak memory | 218120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336380198 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.336380198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_otbn.1903196756 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 93799797 ps |
| CPU time | 2.34 seconds |
| Started | Aug 23 07:07:21 PM UTC 24 |
| Finished | Aug 23 07:07:25 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903196756 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1903196756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_sideload_protect.297963263 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 1310738563 ps |
| CPU time | 12.73 seconds |
| Started | Aug 23 07:07:28 PM UTC 24 |
| Finished | Aug 23 07:07:42 PM UTC 24 |
| Peak memory | 224168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297963263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.297963263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_smoke.1934316617 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 51290330 ps |
| CPU time | 2.19 seconds |
| Started | Aug 23 07:07:19 PM UTC 24 |
| Finished | Aug 23 07:07:22 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1934316617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1934316617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_stress_all.749498814 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 507059079 ps |
| CPU time | 15.19 seconds |
| Started | Aug 23 07:07:30 PM UTC 24 |
| Finished | Aug 23 07:07:47 PM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749498814 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.749498814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_sw_invalid_input.12475319 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 321219212 ps |
| CPU time | 4.93 seconds |
| Started | Aug 23 07:07:25 PM UTC 24 |
| Finished | Aug 23 07:07:31 PM UTC 24 |
| Peak memory | 230248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12475319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.12475319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/18.keymgr_sync_async_fault_cross.3909225312 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 112123614 ps |
| CPU time | 2.34 seconds |
| Started | Aug 23 07:07:29 PM UTC 24 |
| Finished | Aug 23 07:07:33 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909225312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3909225312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/18.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_alert_test.3080538835 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 9905124 ps |
| CPU time | 0.63 seconds |
| Started | Aug 23 07:07:54 PM UTC 24 |
| Finished | Aug 23 07:07:55 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3080538835 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3080538835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_custom_cm.843685845 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 56832910 ps |
| CPU time | 2.76 seconds |
| Started | Aug 23 07:07:49 PM UTC 24 |
| Finished | Aug 23 07:07:53 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843685845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.843685845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_direct_to_disabled.3955794853 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 308555102 ps |
| CPU time | 6.75 seconds |
| Started | Aug 23 07:07:41 PM UTC 24 |
| Finished | Aug 23 07:07:49 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955794853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3955794853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_hwsw_invalid_input.4059063411 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 4109550294 ps |
| CPU time | 18.02 seconds |
| Started | Aug 23 07:07:46 PM UTC 24 |
| Finished | Aug 23 07:08:05 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059063411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.4059063411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_kmac_rsp_err.2043439468 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 712323046 ps |
| CPU time | 4.86 seconds |
| Started | Aug 23 07:07:48 PM UTC 24 |
| Finished | Aug 23 07:07:54 PM UTC 24 |
| Peak memory | 232052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043439468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2043439468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_lc_disable.2539215297 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 78935569 ps |
| CPU time | 1.79 seconds |
| Started | Aug 23 07:07:43 PM UTC 24 |
| Finished | Aug 23 07:07:45 PM UTC 24 |
| Peak memory | 225632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2539215297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2539215297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_random.3083488380 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 106873228 ps |
| CPU time | 3.03 seconds |
| Started | Aug 23 07:07:38 PM UTC 24 |
| Finished | Aug 23 07:07:43 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083488380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3083488380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_sideload.3116633842 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 39804701 ps |
| CPU time | 2.25 seconds |
| Started | Aug 23 07:07:34 PM UTC 24 |
| Finished | Aug 23 07:07:37 PM UTC 24 |
| Peak memory | 218364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116633842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3116633842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_aes.1497815801 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 798674610 ps |
| CPU time | 17.61 seconds |
| Started | Aug 23 07:07:34 PM UTC 24 |
| Finished | Aug 23 07:07:53 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497815801 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1497815801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_kmac.1227630687 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 361089831 ps |
| CPU time | 4.77 seconds |
| Started | Aug 23 07:07:34 PM UTC 24 |
| Finished | Aug 23 07:07:40 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227630687 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1227630687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_otbn.2704837734 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 76612162 ps |
| CPU time | 2.52 seconds |
| Started | Aug 23 07:07:37 PM UTC 24 |
| Finished | Aug 23 07:07:41 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704837734 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2704837734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_sideload_protect.770378559 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 78109767 ps |
| CPU time | 1.22 seconds |
| Started | Aug 23 07:07:50 PM UTC 24 |
| Finished | Aug 23 07:07:53 PM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770378559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.770378559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_smoke.568975156 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 95451315 ps |
| CPU time | 2.73 seconds |
| Started | Aug 23 07:07:33 PM UTC 24 |
| Finished | Aug 23 07:07:37 PM UTC 24 |
| Peak memory | 215808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568975156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.568975156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/19.keymgr_sw_invalid_input.3468073868 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 1179346319 ps |
| CPU time | 3.48 seconds |
| Started | Aug 23 07:07:44 PM UTC 24 |
| Finished | Aug 23 07:07:48 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468073868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3468073868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/19.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_alert_test.2734156786 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 44631252 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 07:03:26 PM UTC 24 |
| Finished | Aug 23 07:03:28 PM UTC 24 |
| Peak memory | 213548 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734156786 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2734156786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_custom_cm.1603141519 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 248207999 ps |
| CPU time | 4.99 seconds |
| Started | Aug 23 07:03:22 PM UTC 24 |
| Finished | Aug 23 07:03:28 PM UTC 24 |
| Peak memory | 230712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603141519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.1603141519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_direct_to_disabled.1773237340 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 194447048 ps |
| CPU time | 1.87 seconds |
| Started | Aug 23 07:03:17 PM UTC 24 |
| Finished | Aug 23 07:03:20 PM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773237340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1773237340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_hwsw_invalid_input.4292090952 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 141205506 ps |
| CPU time | 5.01 seconds |
| Started | Aug 23 07:03:21 PM UTC 24 |
| Finished | Aug 23 07:03:27 PM UTC 24 |
| Peak memory | 224324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292090952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4292090952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_kmac_rsp_err.113573354 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 159901499 ps |
| CPU time | 3.8 seconds |
| Started | Aug 23 07:03:21 PM UTC 24 |
| Finished | Aug 23 07:03:26 PM UTC 24 |
| Peak memory | 226092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113573354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.113573354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_random.2981785277 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 1419017091 ps |
| CPU time | 9.28 seconds |
| Started | Aug 23 07:03:16 PM UTC 24 |
| Finished | Aug 23 07:03:26 PM UTC 24 |
| Peak memory | 230172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981785277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2981785277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_sec_cm.1891248086 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 1924581001 ps |
| CPU time | 7.35 seconds |
| Started | Aug 23 07:03:26 PM UTC 24 |
| Finished | Aug 23 07:03:35 PM UTC 24 |
| Peak memory | 252092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891248086 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1891248086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_sideload.3626789477 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 853341571 ps |
| CPU time | 8.43 seconds |
| Started | Aug 23 07:03:09 PM UTC 24 |
| Finished | Aug 23 07:03:18 PM UTC 24 |
| Peak memory | 217984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626789477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3626789477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_aes.2084960479 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 126384216 ps |
| CPU time | 3.24 seconds |
| Started | Aug 23 07:03:12 PM UTC 24 |
| Finished | Aug 23 07:03:16 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084960479 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2084960479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_kmac.3420752040 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 55588475 ps |
| CPU time | 2.56 seconds |
| Started | Aug 23 07:03:09 PM UTC 24 |
| Finished | Aug 23 07:03:12 PM UTC 24 |
| Peak memory | 217920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420752040 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3420752040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_otbn.3673501839 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 145795394 ps |
| CPU time | 2.56 seconds |
| Started | Aug 23 07:03:13 PM UTC 24 |
| Finished | Aug 23 07:03:16 PM UTC 24 |
| Peak memory | 215872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673501839 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3673501839 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_sideload_protect.3676079403 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 48998327 ps |
| CPU time | 2.19 seconds |
| Started | Aug 23 07:03:22 PM UTC 24 |
| Finished | Aug 23 07:03:25 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676079403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3676079403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_smoke.966640767 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 875479505 ps |
| CPU time | 14.19 seconds |
| Started | Aug 23 07:03:08 PM UTC 24 |
| Finished | Aug 23 07:03:23 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966640767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.966640767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all.189615551 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 295862885 ps |
| CPU time | 5.06 seconds |
| Started | Aug 23 07:03:23 PM UTC 24 |
| Finished | Aug 23 07:03:29 PM UTC 24 |
| Peak memory | 216168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189615551 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.189615551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_stress_all_with_rand_reset.2270864425 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 336943867 ps |
| CPU time | 7.37 seconds |
| Started | Aug 23 07:03:24 PM UTC 24 |
| Finished | Aug 23 07:03:33 PM UTC 24 |
| Peak memory | 228328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2270864425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr _stress_all_with_rand_reset.2270864425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_sw_invalid_input.241962472 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 287649153 ps |
| CPU time | 8.11 seconds |
| Started | Aug 23 07:03:19 PM UTC 24 |
| Finished | Aug 23 07:03:28 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241962472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.241962472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/2.keymgr_sync_async_fault_cross.340157878 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 50704380 ps |
| CPU time | 1.65 seconds |
| Started | Aug 23 07:03:23 PM UTC 24 |
| Finished | Aug 23 07:03:26 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340157878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.340157878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/2.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_alert_test.3678257095 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 36555461 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 07:08:09 PM UTC 24 |
| Finished | Aug 23 07:08:11 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678257095 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3678257095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_custom_cm.1990561598 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 143580612 ps |
| CPU time | 1.74 seconds |
| Started | Aug 23 07:08:05 PM UTC 24 |
| Finished | Aug 23 07:08:08 PM UTC 24 |
| Peak memory | 218336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990561598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.1990561598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_direct_to_disabled.2684461069 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 38100004 ps |
| CPU time | 1.96 seconds |
| Started | Aug 23 07:08:01 PM UTC 24 |
| Finished | Aug 23 07:08:04 PM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684461069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2684461069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_kmac_rsp_err.585382879 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 38092809 ps |
| CPU time | 2.24 seconds |
| Started | Aug 23 07:08:05 PM UTC 24 |
| Finished | Aug 23 07:08:08 PM UTC 24 |
| Peak memory | 230284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585382879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.585382879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_lc_disable.2144934293 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 335263104 ps |
| CPU time | 2.83 seconds |
| Started | Aug 23 07:08:01 PM UTC 24 |
| Finished | Aug 23 07:08:04 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144934293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2144934293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_random.3962422934 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 3239697969 ps |
| CPU time | 30.26 seconds |
| Started | Aug 23 07:07:57 PM UTC 24 |
| Finished | Aug 23 07:08:29 PM UTC 24 |
| Peak memory | 228264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3962422934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3962422934 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_sideload.1159143009 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 97262089 ps |
| CPU time | 1.53 seconds |
| Started | Aug 23 07:07:54 PM UTC 24 |
| Finished | Aug 23 07:07:56 PM UTC 24 |
| Peak memory | 214116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159143009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1159143009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_aes.4096232880 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 124930420 ps |
| CPU time | 3.81 seconds |
| Started | Aug 23 07:07:55 PM UTC 24 |
| Finished | Aug 23 07:08:00 PM UTC 24 |
| Peak memory | 216264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096232880 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.4096232880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_kmac.1290717786 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 524747698 ps |
| CPU time | 13.4 seconds |
| Started | Aug 23 07:07:54 PM UTC 24 |
| Finished | Aug 23 07:08:09 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290717786 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1290717786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_otbn.2327927785 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 283067043 ps |
| CPU time | 2.8 seconds |
| Started | Aug 23 07:07:56 PM UTC 24 |
| Finished | Aug 23 07:08:00 PM UTC 24 |
| Peak memory | 218180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327927785 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2327927785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_sideload_protect.3058076232 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 141428724 ps |
| CPU time | 1.73 seconds |
| Started | Aug 23 07:08:05 PM UTC 24 |
| Finished | Aug 23 07:08:08 PM UTC 24 |
| Peak memory | 217648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058076232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3058076232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_smoke.329666791 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 117805567 ps |
| CPU time | 2.64 seconds |
| Started | Aug 23 07:07:54 PM UTC 24 |
| Finished | Aug 23 07:07:58 PM UTC 24 |
| Peak memory | 215768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329666791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.329666791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_stress_all_with_rand_reset.3548882383 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 320744760 ps |
| CPU time | 11.08 seconds |
| Started | Aug 23 07:08:09 PM UTC 24 |
| Finished | Aug 23 07:08:21 PM UTC 24 |
| Peak memory | 232308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3548882383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymg r_stress_all_with_rand_reset.3548882383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_sw_invalid_input.2462445420 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 75915716 ps |
| CPU time | 3.45 seconds |
| Started | Aug 23 07:08:01 PM UTC 24 |
| Finished | Aug 23 07:08:05 PM UTC 24 |
| Peak memory | 228448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462445420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2462445420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/20.keymgr_sync_async_fault_cross.952404306 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 293868128 ps |
| CPU time | 2.86 seconds |
| Started | Aug 23 07:08:06 PM UTC 24 |
| Finished | Aug 23 07:08:10 PM UTC 24 |
| Peak memory | 219728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952404306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.952404306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/20.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_alert_test.2757735388 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 22782555 ps |
| CPU time | 0.91 seconds |
| Started | Aug 23 07:08:28 PM UTC 24 |
| Finished | Aug 23 07:08:30 PM UTC 24 |
| Peak memory | 213724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757735388 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2757735388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_custom_cm.272198780 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 77617709 ps |
| CPU time | 1.95 seconds |
| Started | Aug 23 07:08:22 PM UTC 24 |
| Finished | Aug 23 07:08:25 PM UTC 24 |
| Peak memory | 224360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272198780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.272198780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_direct_to_disabled.70023113 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 1905510057 ps |
| CPU time | 12.46 seconds |
| Started | Aug 23 07:08:16 PM UTC 24 |
| Finished | Aug 23 07:08:29 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70023113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.70023113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_hwsw_invalid_input.2694472348 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 108704195 ps |
| CPU time | 4.37 seconds |
| Started | Aug 23 07:08:21 PM UTC 24 |
| Finished | Aug 23 07:08:26 PM UTC 24 |
| Peak memory | 224352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694472348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2694472348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_kmac_rsp_err.1566087279 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 114081253 ps |
| CPU time | 4.12 seconds |
| Started | Aug 23 07:08:22 PM UTC 24 |
| Finished | Aug 23 07:08:27 PM UTC 24 |
| Peak memory | 223976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566087279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1566087279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_lc_disable.1333004927 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 133289711 ps |
| CPU time | 1.89 seconds |
| Started | Aug 23 07:08:16 PM UTC 24 |
| Finished | Aug 23 07:08:19 PM UTC 24 |
| Peak memory | 229752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333004927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1333004927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_random.3590373652 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 951353245 ps |
| CPU time | 6.35 seconds |
| Started | Aug 23 07:08:13 PM UTC 24 |
| Finished | Aug 23 07:08:21 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590373652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3590373652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_sideload.3284840350 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 407734169 ps |
| CPU time | 1.71 seconds |
| Started | Aug 23 07:08:10 PM UTC 24 |
| Finished | Aug 23 07:08:13 PM UTC 24 |
| Peak memory | 215648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3284840350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3284840350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_aes.553298999 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 28660231 ps |
| CPU time | 2 seconds |
| Started | Aug 23 07:08:11 PM UTC 24 |
| Finished | Aug 23 07:08:14 PM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553298999 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.553298999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_kmac.2966806398 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 1203819255 ps |
| CPU time | 3.58 seconds |
| Started | Aug 23 07:08:10 PM UTC 24 |
| Finished | Aug 23 07:08:14 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966806398 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2966806398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_otbn.605299315 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 78171547 ps |
| CPU time | 1.54 seconds |
| Started | Aug 23 07:08:11 PM UTC 24 |
| Finished | Aug 23 07:08:14 PM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605299315 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.605299315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_sideload_protect.772879241 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 261033859 ps |
| CPU time | 3.36 seconds |
| Started | Aug 23 07:08:24 PM UTC 24 |
| Finished | Aug 23 07:08:29 PM UTC 24 |
| Peak memory | 218088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772879241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.772879241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_smoke.2355993703 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1941248500 ps |
| CPU time | 13.67 seconds |
| Started | Aug 23 07:08:09 PM UTC 24 |
| Finished | Aug 23 07:08:24 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355993703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2355993703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/21.keymgr_sw_invalid_input.2793433111 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 62624697 ps |
| CPU time | 3.44 seconds |
| Started | Aug 23 07:08:20 PM UTC 24 |
| Finished | Aug 23 07:08:24 PM UTC 24 |
| Peak memory | 226180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2793433111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2793433111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/21.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_alert_test.2097085177 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 20164426 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 07:08:44 PM UTC 24 |
| Finished | Aug 23 07:08:45 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097085177 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2097085177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_custom_cm.2052428502 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 70296822 ps |
| CPU time | 2.81 seconds |
| Started | Aug 23 07:08:39 PM UTC 24 |
| Finished | Aug 23 07:08:43 PM UTC 24 |
| Peak memory | 230944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052428502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2052428502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_direct_to_disabled.2348453921 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 71354770 ps |
| CPU time | 2.06 seconds |
| Started | Aug 23 07:08:34 PM UTC 24 |
| Finished | Aug 23 07:08:38 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348453921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2348453921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_hwsw_invalid_input.2169643959 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 374624595 ps |
| CPU time | 4.72 seconds |
| Started | Aug 23 07:08:37 PM UTC 24 |
| Finished | Aug 23 07:08:42 PM UTC 24 |
| Peak memory | 224448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169643959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2169643959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_kmac_rsp_err.2309799070 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 170575043 ps |
| CPU time | 4.38 seconds |
| Started | Aug 23 07:08:39 PM UTC 24 |
| Finished | Aug 23 07:08:44 PM UTC 24 |
| Peak memory | 232268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309799070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2309799070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_lc_disable.2266435911 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 86023667 ps |
| CPU time | 2.55 seconds |
| Started | Aug 23 07:08:36 PM UTC 24 |
| Finished | Aug 23 07:08:39 PM UTC 24 |
| Peak memory | 230544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266435911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2266435911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_random.1733886276 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 123705613 ps |
| CPU time | 4.61 seconds |
| Started | Aug 23 07:08:32 PM UTC 24 |
| Finished | Aug 23 07:08:38 PM UTC 24 |
| Peak memory | 228200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1733886276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1733886276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_sideload.2790825620 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 188933624 ps |
| CPU time | 3.78 seconds |
| Started | Aug 23 07:08:30 PM UTC 24 |
| Finished | Aug 23 07:08:35 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2790825620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2790825620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_aes.1501765968 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 241840985 ps |
| CPU time | 3.64 seconds |
| Started | Aug 23 07:08:30 PM UTC 24 |
| Finished | Aug 23 07:08:35 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501765968 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1501765968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_kmac.1587842621 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 135562965 ps |
| CPU time | 4.64 seconds |
| Started | Aug 23 07:08:30 PM UTC 24 |
| Finished | Aug 23 07:08:36 PM UTC 24 |
| Peak memory | 218160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587842621 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1587842621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_otbn.261288952 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 35816510 ps |
| CPU time | 2.01 seconds |
| Started | Aug 23 07:08:30 PM UTC 24 |
| Finished | Aug 23 07:08:33 PM UTC 24 |
| Peak memory | 216128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261288952 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.261288952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_sideload_protect.61229832 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 88751997 ps |
| CPU time | 1.57 seconds |
| Started | Aug 23 07:08:39 PM UTC 24 |
| Finished | Aug 23 07:08:42 PM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61229832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.61229832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_smoke.118633734 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 402784763 ps |
| CPU time | 2.75 seconds |
| Started | Aug 23 07:08:28 PM UTC 24 |
| Finished | Aug 23 07:08:32 PM UTC 24 |
| Peak memory | 217900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118633734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.118633734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_stress_all.2759828907 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 1782290523 ps |
| CPU time | 19.09 seconds |
| Started | Aug 23 07:08:40 PM UTC 24 |
| Finished | Aug 23 07:09:01 PM UTC 24 |
| Peak memory | 225896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759828907 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2759828907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_sw_invalid_input.1462675637 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 33299375 ps |
| CPU time | 1.98 seconds |
| Started | Aug 23 07:08:36 PM UTC 24 |
| Finished | Aug 23 07:08:39 PM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462675637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1462675637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/22.keymgr_sync_async_fault_cross.3303532326 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 571299374 ps |
| CPU time | 2.82 seconds |
| Started | Aug 23 07:08:40 PM UTC 24 |
| Finished | Aug 23 07:08:44 PM UTC 24 |
| Peak memory | 219884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303532326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3303532326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/22.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_alert_test.1736921419 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 41208473 ps |
| CPU time | 0.66 seconds |
| Started | Aug 23 07:08:59 PM UTC 24 |
| Finished | Aug 23 07:09:01 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736921419 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1736921419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_cfg_regwen.2073587165 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 74405415 ps |
| CPU time | 2.6 seconds |
| Started | Aug 23 07:08:50 PM UTC 24 |
| Finished | Aug 23 07:08:53 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073587165 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2073587165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_custom_cm.1411950636 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 187232632 ps |
| CPU time | 5.78 seconds |
| Started | Aug 23 07:08:54 PM UTC 24 |
| Finished | Aug 23 07:09:01 PM UTC 24 |
| Peak memory | 232516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411950636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1411950636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_direct_to_disabled.1675300121 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 66406183 ps |
| CPU time | 2.6 seconds |
| Started | Aug 23 07:08:50 PM UTC 24 |
| Finished | Aug 23 07:08:53 PM UTC 24 |
| Peak memory | 230352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675300121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1675300121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_lc_disable.542133192 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 284370828 ps |
| CPU time | 3.29 seconds |
| Started | Aug 23 07:08:50 PM UTC 24 |
| Finished | Aug 23 07:08:54 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542133192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.542133192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_random.1032775746 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 104892785 ps |
| CPU time | 4.59 seconds |
| Started | Aug 23 07:08:47 PM UTC 24 |
| Finished | Aug 23 07:08:53 PM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032775746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1032775746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_sideload.747982243 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 60370008 ps |
| CPU time | 2.3 seconds |
| Started | Aug 23 07:08:45 PM UTC 24 |
| Finished | Aug 23 07:08:48 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747982243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.747982243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_aes.2192444325 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 351896280 ps |
| CPU time | 4.24 seconds |
| Started | Aug 23 07:08:46 PM UTC 24 |
| Finished | Aug 23 07:08:51 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192444325 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2192444325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_kmac.1519995440 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 91239537 ps |
| CPU time | 2.79 seconds |
| Started | Aug 23 07:08:45 PM UTC 24 |
| Finished | Aug 23 07:08:49 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519995440 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1519995440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_otbn.2871649210 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 385349708 ps |
| CPU time | 5.24 seconds |
| Started | Aug 23 07:08:47 PM UTC 24 |
| Finished | Aug 23 07:08:54 PM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871649210 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2871649210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_sideload_protect.842406124 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 348169452 ps |
| CPU time | 2.45 seconds |
| Started | Aug 23 07:08:54 PM UTC 24 |
| Finished | Aug 23 07:08:58 PM UTC 24 |
| Peak memory | 224264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=842406124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.842406124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_smoke.1305538239 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 121007954 ps |
| CPU time | 1.87 seconds |
| Started | Aug 23 07:08:44 PM UTC 24 |
| Finished | Aug 23 07:08:47 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305538239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1305538239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all.314407567 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 255819144 ps |
| CPU time | 5.9 seconds |
| Started | Aug 23 07:08:54 PM UTC 24 |
| Finished | Aug 23 07:09:01 PM UTC 24 |
| Peak memory | 230176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314407567 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.314407567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_stress_all_with_rand_reset.4248350438 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 293600277 ps |
| CPU time | 15.08 seconds |
| Started | Aug 23 07:08:57 PM UTC 24 |
| Finished | Aug 23 07:09:13 PM UTC 24 |
| Peak memory | 232308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4248350438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymg r_stress_all_with_rand_reset.4248350438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_sw_invalid_input.2813128648 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 2092448765 ps |
| CPU time | 7.66 seconds |
| Started | Aug 23 07:08:51 PM UTC 24 |
| Finished | Aug 23 07:09:00 PM UTC 24 |
| Peak memory | 228124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813128648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2813128648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/23.keymgr_sync_async_fault_cross.3220027652 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 112528408 ps |
| CPU time | 2 seconds |
| Started | Aug 23 07:08:54 PM UTC 24 |
| Finished | Aug 23 07:08:58 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220027652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3220027652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/23.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_alert_test.2315685559 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 26044707 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 07:09:12 PM UTC 24 |
| Finished | Aug 23 07:09:14 PM UTC 24 |
| Peak memory | 213724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315685559 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2315685559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_custom_cm.283597858 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 146530289 ps |
| CPU time | 5.2 seconds |
| Started | Aug 23 07:09:08 PM UTC 24 |
| Finished | Aug 23 07:09:14 PM UTC 24 |
| Peak memory | 220084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283597858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.283597858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_direct_to_disabled.4279726124 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 211992651 ps |
| CPU time | 1.73 seconds |
| Started | Aug 23 07:09:04 PM UTC 24 |
| Finished | Aug 23 07:09:07 PM UTC 24 |
| Peak memory | 217812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279726124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.4279726124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_hwsw_invalid_input.1524708682 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 168649353 ps |
| CPU time | 3.76 seconds |
| Started | Aug 23 07:09:07 PM UTC 24 |
| Finished | Aug 23 07:09:12 PM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524708682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1524708682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_kmac_rsp_err.1425935807 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 31948509 ps |
| CPU time | 1.65 seconds |
| Started | Aug 23 07:09:08 PM UTC 24 |
| Finished | Aug 23 07:09:11 PM UTC 24 |
| Peak memory | 223584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425935807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1425935807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_random.3968208818 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 167395498 ps |
| CPU time | 2.75 seconds |
| Started | Aug 23 07:09:02 PM UTC 24 |
| Finished | Aug 23 07:09:06 PM UTC 24 |
| Peak memory | 215856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968208818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3968208818 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_sideload.2252710358 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 163991816 ps |
| CPU time | 1.92 seconds |
| Started | Aug 23 07:09:00 PM UTC 24 |
| Finished | Aug 23 07:09:03 PM UTC 24 |
| Peak memory | 214116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252710358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2252710358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_aes.572033197 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 125622384 ps |
| CPU time | 2 seconds |
| Started | Aug 23 07:09:01 PM UTC 24 |
| Finished | Aug 23 07:09:04 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572033197 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.572033197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_kmac.1788140598 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 1591261981 ps |
| CPU time | 6.48 seconds |
| Started | Aug 23 07:09:01 PM UTC 24 |
| Finished | Aug 23 07:09:09 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788140598 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1788140598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_otbn.1657706002 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 209109490 ps |
| CPU time | 4.16 seconds |
| Started | Aug 23 07:09:01 PM UTC 24 |
| Finished | Aug 23 07:09:07 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657706002 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1657706002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_sideload_protect.3362020940 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 251132872 ps |
| CPU time | 2.61 seconds |
| Started | Aug 23 07:09:09 PM UTC 24 |
| Finished | Aug 23 07:09:13 PM UTC 24 |
| Peak memory | 230236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362020940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3362020940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_smoke.3882182016 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 963404146 ps |
| CPU time | 5.05 seconds |
| Started | Aug 23 07:08:59 PM UTC 24 |
| Finished | Aug 23 07:09:05 PM UTC 24 |
| Peak memory | 218148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882182016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3882182016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_stress_all.1356685253 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 126181051547 ps |
| CPU time | 121.93 seconds |
| Started | Aug 23 07:09:11 PM UTC 24 |
| Finished | Aug 23 07:11:15 PM UTC 24 |
| Peak memory | 228260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356685253 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1356685253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_sw_invalid_input.2140646087 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 217228462 ps |
| CPU time | 3.16 seconds |
| Started | Aug 23 07:09:06 PM UTC 24 |
| Finished | Aug 23 07:09:10 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140646087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2140646087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/24.keymgr_sync_async_fault_cross.2617407234 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 134884634 ps |
| CPU time | 1.83 seconds |
| Started | Aug 23 07:09:09 PM UTC 24 |
| Finished | Aug 23 07:09:12 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617407234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.2617407234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/24.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_alert_test.1055843916 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 15445061 ps |
| CPU time | 0.72 seconds |
| Started | Aug 23 07:09:31 PM UTC 24 |
| Finished | Aug 23 07:09:32 PM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055843916 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.1055843916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_cfg_regwen.2999930049 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 108700554 ps |
| CPU time | 3.57 seconds |
| Started | Aug 23 07:09:18 PM UTC 24 |
| Finished | Aug 23 07:09:24 PM UTC 24 |
| Peak memory | 232560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999930049 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2999930049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_direct_to_disabled.1552375668 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 153586861 ps |
| CPU time | 3.71 seconds |
| Started | Aug 23 07:09:20 PM UTC 24 |
| Finished | Aug 23 07:09:25 PM UTC 24 |
| Peak memory | 230176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552375668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1552375668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_hwsw_invalid_input.1828378003 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 125400601 ps |
| CPU time | 3.84 seconds |
| Started | Aug 23 07:09:24 PM UTC 24 |
| Finished | Aug 23 07:09:29 PM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828378003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1828378003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_kmac_rsp_err.537840300 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 126940579 ps |
| CPU time | 4.79 seconds |
| Started | Aug 23 07:09:25 PM UTC 24 |
| Finished | Aug 23 07:09:31 PM UTC 24 |
| Peak memory | 224084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537840300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.537840300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_lc_disable.2490400885 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 720524660 ps |
| CPU time | 3.5 seconds |
| Started | Aug 23 07:09:21 PM UTC 24 |
| Finished | Aug 23 07:09:25 PM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490400885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2490400885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_random.1115632804 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 841866130 ps |
| CPU time | 20.73 seconds |
| Started | Aug 23 07:09:15 PM UTC 24 |
| Finished | Aug 23 07:09:38 PM UTC 24 |
| Peak memory | 226152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115632804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1115632804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_sideload.532484554 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 1491988249 ps |
| CPU time | 25.12 seconds |
| Started | Aug 23 07:09:13 PM UTC 24 |
| Finished | Aug 23 07:09:39 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532484554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.532484554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_aes.2218264122 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1039855726 ps |
| CPU time | 6.02 seconds |
| Started | Aug 23 07:09:14 PM UTC 24 |
| Finished | Aug 23 07:09:21 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218264122 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2218264122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_kmac.1156123979 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 262539969 ps |
| CPU time | 2.85 seconds |
| Started | Aug 23 07:09:14 PM UTC 24 |
| Finished | Aug 23 07:09:18 PM UTC 24 |
| Peak memory | 217736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156123979 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1156123979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_sideload_otbn.2583815171 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 166629876 ps |
| CPU time | 2.24 seconds |
| Started | Aug 23 07:09:14 PM UTC 24 |
| Finished | Aug 23 07:09:18 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583815171 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2583815171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_smoke.1056945364 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1875881610 ps |
| CPU time | 10.62 seconds |
| Started | Aug 23 07:09:13 PM UTC 24 |
| Finished | Aug 23 07:09:25 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056945364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1056945364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_sw_invalid_input.88133271 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 139070729 ps |
| CPU time | 3.85 seconds |
| Started | Aug 23 07:09:22 PM UTC 24 |
| Finished | Aug 23 07:09:27 PM UTC 24 |
| Peak memory | 224096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88133271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vc s/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.88133271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/25.keymgr_sync_async_fault_cross.3244805311 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 132143148 ps |
| CPU time | 1.19 seconds |
| Started | Aug 23 07:09:27 PM UTC 24 |
| Finished | Aug 23 07:09:30 PM UTC 24 |
| Peak memory | 216224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244805311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3244805311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/25.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_alert_test.1017239267 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 14267188 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 07:09:52 PM UTC 24 |
| Finished | Aug 23 07:09:54 PM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017239267 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1017239267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_cfg_regwen.3310476403 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 141822589 ps |
| CPU time | 3.43 seconds |
| Started | Aug 23 07:09:41 PM UTC 24 |
| Finished | Aug 23 07:09:45 PM UTC 24 |
| Peak memory | 226396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310476403 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3310476403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_custom_cm.2486187378 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1367179551 ps |
| CPU time | 4.16 seconds |
| Started | Aug 23 07:09:46 PM UTC 24 |
| Finished | Aug 23 07:09:51 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486187378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2486187378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_direct_to_disabled.1725214030 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 69661310 ps |
| CPU time | 2.23 seconds |
| Started | Aug 23 07:09:41 PM UTC 24 |
| Finished | Aug 23 07:09:44 PM UTC 24 |
| Peak memory | 217996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1725214030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1725214030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_hwsw_invalid_input.3682670774 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 344177489 ps |
| CPU time | 2.47 seconds |
| Started | Aug 23 07:09:45 PM UTC 24 |
| Finished | Aug 23 07:09:48 PM UTC 24 |
| Peak memory | 224360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682670774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3682670774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_kmac_rsp_err.3769090290 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 129206748 ps |
| CPU time | 3.06 seconds |
| Started | Aug 23 07:09:46 PM UTC 24 |
| Finished | Aug 23 07:09:50 PM UTC 24 |
| Peak memory | 230580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769090290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3769090290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_lc_disable.1686155629 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 83729293 ps |
| CPU time | 1.64 seconds |
| Started | Aug 23 07:09:43 PM UTC 24 |
| Finished | Aug 23 07:09:45 PM UTC 24 |
| Peak memory | 215588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686155629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1686155629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_random.299143449 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 34427605 ps |
| CPU time | 2.14 seconds |
| Started | Aug 23 07:09:39 PM UTC 24 |
| Finished | Aug 23 07:09:42 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299143449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.299143449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_sideload.63579815 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 542682833 ps |
| CPU time | 4.47 seconds |
| Started | Aug 23 07:09:33 PM UTC 24 |
| Finished | Aug 23 07:09:39 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63579815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.63579815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_aes.1694272968 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 447830748 ps |
| CPU time | 6.75 seconds |
| Started | Aug 23 07:09:37 PM UTC 24 |
| Finished | Aug 23 07:09:45 PM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694272968 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1694272968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_kmac.918409180 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 3152087321 ps |
| CPU time | 26.62 seconds |
| Started | Aug 23 07:09:36 PM UTC 24 |
| Finished | Aug 23 07:10:04 PM UTC 24 |
| Peak memory | 215896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918409180 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.918409180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_otbn.4194146029 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 122665390 ps |
| CPU time | 2.76 seconds |
| Started | Aug 23 07:09:38 PM UTC 24 |
| Finished | Aug 23 07:09:42 PM UTC 24 |
| Peak memory | 217988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194146029 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.4194146029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_sideload_protect.1341838431 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 719764747 ps |
| CPU time | 5.14 seconds |
| Started | Aug 23 07:09:46 PM UTC 24 |
| Finished | Aug 23 07:09:53 PM UTC 24 |
| Peak memory | 230384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341838431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1341838431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_smoke.3667174325 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 265498083 ps |
| CPU time | 2.37 seconds |
| Started | Aug 23 07:09:32 PM UTC 24 |
| Finished | Aug 23 07:09:35 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667174325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.3667174325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_stress_all.297242135 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 1183212923 ps |
| CPU time | 38.19 seconds |
| Started | Aug 23 07:09:49 PM UTC 24 |
| Finished | Aug 23 07:10:29 PM UTC 24 |
| Peak memory | 232180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297242135 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.297242135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_sw_invalid_input.1062740927 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 270584441 ps |
| CPU time | 5.54 seconds |
| Started | Aug 23 07:09:44 PM UTC 24 |
| Finished | Aug 23 07:09:50 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062740927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1062740927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/26.keymgr_sync_async_fault_cross.2246312148 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 45556024 ps |
| CPU time | 1.86 seconds |
| Started | Aug 23 07:09:48 PM UTC 24 |
| Finished | Aug 23 07:09:51 PM UTC 24 |
| Peak memory | 219736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246312148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2246312148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/26.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_alert_test.1473298253 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 21783300 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 07:10:14 PM UTC 24 |
| Finished | Aug 23 07:10:16 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473298253 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1473298253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_custom_cm.2492906765 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 380090251 ps |
| CPU time | 5.75 seconds |
| Started | Aug 23 07:10:06 PM UTC 24 |
| Finished | Aug 23 07:10:13 PM UTC 24 |
| Peak memory | 230648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492906765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2492906765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_direct_to_disabled.697788771 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 374476744 ps |
| CPU time | 2.77 seconds |
| Started | Aug 23 07:10:01 PM UTC 24 |
| Finished | Aug 23 07:10:04 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=697788771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.697788771 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_hwsw_invalid_input.3115718953 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1597227476 ps |
| CPU time | 18.37 seconds |
| Started | Aug 23 07:10:05 PM UTC 24 |
| Finished | Aug 23 07:10:25 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115718953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3115718953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_kmac_rsp_err.2223620147 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 122390757 ps |
| CPU time | 3.61 seconds |
| Started | Aug 23 07:10:05 PM UTC 24 |
| Finished | Aug 23 07:10:10 PM UTC 24 |
| Peak memory | 226060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223620147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2223620147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_lc_disable.1792268013 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 1792048198 ps |
| CPU time | 2.67 seconds |
| Started | Aug 23 07:10:02 PM UTC 24 |
| Finished | Aug 23 07:10:06 PM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792268013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1792268013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_random.3104265550 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 174102140 ps |
| CPU time | 4.04 seconds |
| Started | Aug 23 07:09:58 PM UTC 24 |
| Finished | Aug 23 07:10:04 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104265550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3104265550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_sideload.1095544395 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 872980734 ps |
| CPU time | 26.58 seconds |
| Started | Aug 23 07:09:52 PM UTC 24 |
| Finished | Aug 23 07:10:20 PM UTC 24 |
| Peak memory | 218328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095544395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1095544395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_aes.1546474610 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 240593589 ps |
| CPU time | 6.09 seconds |
| Started | Aug 23 07:09:54 PM UTC 24 |
| Finished | Aug 23 07:10:01 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546474610 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1546474610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_kmac.1434299157 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 169763975 ps |
| CPU time | 5.38 seconds |
| Started | Aug 23 07:09:53 PM UTC 24 |
| Finished | Aug 23 07:10:00 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434299157 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1434299157 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_otbn.4166190819 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 22805248 ps |
| CPU time | 1.62 seconds |
| Started | Aug 23 07:09:57 PM UTC 24 |
| Finished | Aug 23 07:10:00 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166190819 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4166190819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_sideload_protect.3335708560 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2798612562 ps |
| CPU time | 9.98 seconds |
| Started | Aug 23 07:10:08 PM UTC 24 |
| Finished | Aug 23 07:10:20 PM UTC 24 |
| Peak memory | 228256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335708560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3335708560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_smoke.148567735 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 370405346 ps |
| CPU time | 4.59 seconds |
| Started | Aug 23 07:09:52 PM UTC 24 |
| Finished | Aug 23 07:09:58 PM UTC 24 |
| Peak memory | 217836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148567735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.148567735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_stress_all.1846429408 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 12186093644 ps |
| CPU time | 31.2 seconds |
| Started | Aug 23 07:10:11 PM UTC 24 |
| Finished | Aug 23 07:10:43 PM UTC 24 |
| Peak memory | 232240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846429408 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1846429408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_sw_invalid_input.4210034446 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 182718422 ps |
| CPU time | 5.13 seconds |
| Started | Aug 23 07:10:04 PM UTC 24 |
| Finished | Aug 23 07:10:10 PM UTC 24 |
| Peak memory | 228232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210034446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.4210034446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/27.keymgr_sync_async_fault_cross.952907979 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 815997245 ps |
| CPU time | 6.33 seconds |
| Started | Aug 23 07:10:11 PM UTC 24 |
| Finished | Aug 23 07:10:18 PM UTC 24 |
| Peak memory | 220016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952907979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.952907979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/27.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_alert_test.1034792162 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 12522349 ps |
| CPU time | 0.82 seconds |
| Started | Aug 23 07:10:34 PM UTC 24 |
| Finished | Aug 23 07:10:36 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034792162 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1034792162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_cfg_regwen.4235576029 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 36036978 ps |
| CPU time | 2.52 seconds |
| Started | Aug 23 07:10:24 PM UTC 24 |
| Finished | Aug 23 07:10:27 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235576029 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.4235576029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_direct_to_disabled.580985432 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 178345394 ps |
| CPU time | 3.21 seconds |
| Started | Aug 23 07:10:25 PM UTC 24 |
| Finished | Aug 23 07:10:29 PM UTC 24 |
| Peak memory | 228292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580985432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.580985432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_lc_disable.2147245423 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 153324777 ps |
| CPU time | 3.2 seconds |
| Started | Aug 23 07:10:26 PM UTC 24 |
| Finished | Aug 23 07:10:30 PM UTC 24 |
| Peak memory | 223544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147245423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2147245423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_random.3497044179 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 117994210 ps |
| CPU time | 3.66 seconds |
| Started | Aug 23 07:10:23 PM UTC 24 |
| Finished | Aug 23 07:10:27 PM UTC 24 |
| Peak memory | 218304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497044179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3497044179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_sideload.2990262933 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 411346389 ps |
| CPU time | 3.11 seconds |
| Started | Aug 23 07:10:17 PM UTC 24 |
| Finished | Aug 23 07:10:21 PM UTC 24 |
| Peak memory | 216172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990262933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2990262933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_aes.3730936648 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 128225740 ps |
| CPU time | 2.91 seconds |
| Started | Aug 23 07:10:21 PM UTC 24 |
| Finished | Aug 23 07:10:25 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730936648 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3730936648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_kmac.2272292631 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 57827460 ps |
| CPU time | 2.58 seconds |
| Started | Aug 23 07:10:19 PM UTC 24 |
| Finished | Aug 23 07:10:23 PM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272292631 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2272292631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_otbn.2058470933 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 435105795 ps |
| CPU time | 3.2 seconds |
| Started | Aug 23 07:10:21 PM UTC 24 |
| Finished | Aug 23 07:10:25 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058470933 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2058470933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_sideload_protect.3278168625 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 68775341 ps |
| CPU time | 2.16 seconds |
| Started | Aug 23 07:10:30 PM UTC 24 |
| Finished | Aug 23 07:10:33 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278168625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3278168625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_smoke.2198743672 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 6815177740 ps |
| CPU time | 21.19 seconds |
| Started | Aug 23 07:10:17 PM UTC 24 |
| Finished | Aug 23 07:10:40 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198743672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2198743672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all.3819326478 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 682943361 ps |
| CPU time | 6.05 seconds |
| Started | Aug 23 07:10:32 PM UTC 24 |
| Finished | Aug 23 07:10:39 PM UTC 24 |
| Peak memory | 228452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819326478 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3819326478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_stress_all_with_rand_reset.2498774006 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 399675160 ps |
| CPU time | 5.06 seconds |
| Started | Aug 23 07:10:32 PM UTC 24 |
| Finished | Aug 23 07:10:39 PM UTC 24 |
| Peak memory | 232384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2498774006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymg r_stress_all_with_rand_reset.2498774006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_sw_invalid_input.706811053 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 3215032830 ps |
| CPU time | 11.29 seconds |
| Started | Aug 23 07:10:26 PM UTC 24 |
| Finished | Aug 23 07:10:39 PM UTC 24 |
| Peak memory | 225792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706811053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.706811053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/28.keymgr_sync_async_fault_cross.569341148 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 114577640 ps |
| CPU time | 1.53 seconds |
| Started | Aug 23 07:10:31 PM UTC 24 |
| Finished | Aug 23 07:10:34 PM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569341148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.569341148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/28.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_alert_test.1313536964 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 14934886 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 07:10:53 PM UTC 24 |
| Finished | Aug 23 07:10:55 PM UTC 24 |
| Peak memory | 213724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313536964 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1313536964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_cfg_regwen.1970259886 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 518903385 ps |
| CPU time | 22.43 seconds |
| Started | Aug 23 07:10:41 PM UTC 24 |
| Finished | Aug 23 07:11:06 PM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1970259886 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.1970259886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_custom_cm.2201221999 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 38917735 ps |
| CPU time | 1.76 seconds |
| Started | Aug 23 07:10:47 PM UTC 24 |
| Finished | Aug 23 07:10:50 PM UTC 24 |
| Peak memory | 230692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201221999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2201221999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_direct_to_disabled.2187143442 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 71616314 ps |
| CPU time | 2.72 seconds |
| Started | Aug 23 07:10:41 PM UTC 24 |
| Finished | Aug 23 07:10:46 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187143442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2187143442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_hwsw_invalid_input.1658518867 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 5907962563 ps |
| CPU time | 32.93 seconds |
| Started | Aug 23 07:10:47 PM UTC 24 |
| Finished | Aug 23 07:11:21 PM UTC 24 |
| Peak memory | 224160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658518867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1658518867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_kmac_rsp_err.753433434 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 39503025 ps |
| CPU time | 2.44 seconds |
| Started | Aug 23 07:10:47 PM UTC 24 |
| Finished | Aug 23 07:10:50 PM UTC 24 |
| Peak memory | 228396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753433434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.753433434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_lc_disable.3740872084 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 103949483 ps |
| CPU time | 4.49 seconds |
| Started | Aug 23 07:10:44 PM UTC 24 |
| Finished | Aug 23 07:10:51 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740872084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3740872084 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_random.1744843437 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 520151442 ps |
| CPU time | 3.1 seconds |
| Started | Aug 23 07:10:41 PM UTC 24 |
| Finished | Aug 23 07:10:46 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744843437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1744843437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_sideload.458224885 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 210641843 ps |
| CPU time | 2.1 seconds |
| Started | Aug 23 07:10:36 PM UTC 24 |
| Finished | Aug 23 07:10:40 PM UTC 24 |
| Peak memory | 218052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458224885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.458224885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_aes.2861739821 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 3188914200 ps |
| CPU time | 28.35 seconds |
| Started | Aug 23 07:10:40 PM UTC 24 |
| Finished | Aug 23 07:11:09 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861739821 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2861739821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_kmac.886016309 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 205926405 ps |
| CPU time | 6.35 seconds |
| Started | Aug 23 07:10:38 PM UTC 24 |
| Finished | Aug 23 07:10:45 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886016309 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.886016309 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_otbn.1758081290 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 97515953 ps |
| CPU time | 3.1 seconds |
| Started | Aug 23 07:10:40 PM UTC 24 |
| Finished | Aug 23 07:10:44 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758081290 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1758081290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_sideload_protect.3322567684 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 74515428 ps |
| CPU time | 1.56 seconds |
| Started | Aug 23 07:10:50 PM UTC 24 |
| Finished | Aug 23 07:10:53 PM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322567684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3322567684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_smoke.677593425 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 1788473486 ps |
| CPU time | 35.17 seconds |
| Started | Aug 23 07:10:34 PM UTC 24 |
| Finished | Aug 23 07:11:11 PM UTC 24 |
| Peak memory | 218148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677593425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.677593425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all.3423865820 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 752216589 ps |
| CPU time | 2.75 seconds |
| Started | Aug 23 07:10:51 PM UTC 24 |
| Finished | Aug 23 07:10:55 PM UTC 24 |
| Peak memory | 215748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423865820 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3423865820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_stress_all_with_rand_reset.164241234 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1281085927 ps |
| CPU time | 13.23 seconds |
| Started | Aug 23 07:10:52 PM UTC 24 |
| Finished | Aug 23 07:11:07 PM UTC 24 |
| Peak memory | 230400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=164241234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr _stress_all_with_rand_reset.164241234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_sw_invalid_input.2243302655 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 191969213 ps |
| CPU time | 2.67 seconds |
| Started | Aug 23 07:10:44 PM UTC 24 |
| Finished | Aug 23 07:10:49 PM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243302655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2243302655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/29.keymgr_sync_async_fault_cross.3383415249 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 108651124 ps |
| CPU time | 3.4 seconds |
| Started | Aug 23 07:10:51 PM UTC 24 |
| Finished | Aug 23 07:10:56 PM UTC 24 |
| Peak memory | 217996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383415249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3383415249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/29.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_alert_test.3923674700 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 12216561 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 07:03:38 PM UTC 24 |
| Finished | Aug 23 07:03:40 PM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923674700 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.3923674700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_cfg_regwen.4278545979 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 40886216 ps |
| CPU time | 2.62 seconds |
| Started | Aug 23 07:03:29 PM UTC 24 |
| Finished | Aug 23 07:03:32 PM UTC 24 |
| Peak memory | 224212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278545979 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.4278545979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_custom_cm.1876558724 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 86432152 ps |
| CPU time | 2.64 seconds |
| Started | Aug 23 07:03:34 PM UTC 24 |
| Finished | Aug 23 07:03:38 PM UTC 24 |
| Peak memory | 218260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876558724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1876558724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_direct_to_disabled.3954923893 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 21001061 ps |
| CPU time | 1.56 seconds |
| Started | Aug 23 07:03:30 PM UTC 24 |
| Finished | Aug 23 07:03:32 PM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954923893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3954923893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_hwsw_invalid_input.60868611 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 722830514 ps |
| CPU time | 3.03 seconds |
| Started | Aug 23 07:03:33 PM UTC 24 |
| Finished | Aug 23 07:03:37 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60868611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.60868611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_kmac_rsp_err.949359135 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 74404136 ps |
| CPU time | 1.76 seconds |
| Started | Aug 23 07:03:34 PM UTC 24 |
| Finished | Aug 23 07:03:37 PM UTC 24 |
| Peak memory | 224396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949359135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.949359135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_lc_disable.4200510124 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 154431853 ps |
| CPU time | 2.95 seconds |
| Started | Aug 23 07:03:33 PM UTC 24 |
| Finished | Aug 23 07:03:37 PM UTC 24 |
| Peak memory | 230516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200510124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.4200510124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_random.1912440536 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 79277792 ps |
| CPU time | 3.5 seconds |
| Started | Aug 23 07:03:29 PM UTC 24 |
| Finished | Aug 23 07:03:33 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912440536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1912440536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_sec_cm.3171378762 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 1068999247 ps |
| CPU time | 5.54 seconds |
| Started | Aug 23 07:03:38 PM UTC 24 |
| Finished | Aug 23 07:03:45 PM UTC 24 |
| Peak memory | 254312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171378762 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3171378762 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_sideload.1624015123 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 155231468 ps |
| CPU time | 5.35 seconds |
| Started | Aug 23 07:03:26 PM UTC 24 |
| Finished | Aug 23 07:03:33 PM UTC 24 |
| Peak memory | 218000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624015123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1624015123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_aes.2130200521 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 5994925726 ps |
| CPU time | 16.14 seconds |
| Started | Aug 23 07:03:28 PM UTC 24 |
| Finished | Aug 23 07:03:45 PM UTC 24 |
| Peak memory | 218340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130200521 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2130200521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_kmac.3307000297 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 1519125552 ps |
| CPU time | 31.05 seconds |
| Started | Aug 23 07:03:28 PM UTC 24 |
| Finished | Aug 23 07:04:00 PM UTC 24 |
| Peak memory | 218084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3307000297 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3307000297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_otbn.1116923094 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 64290684 ps |
| CPU time | 1.96 seconds |
| Started | Aug 23 07:03:29 PM UTC 24 |
| Finished | Aug 23 07:03:32 PM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116923094 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1116923094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_sideload_protect.2516803553 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 123074512 ps |
| CPU time | 3.14 seconds |
| Started | Aug 23 07:03:34 PM UTC 24 |
| Finished | Aug 23 07:03:38 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516803553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2516803553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_smoke.1033838480 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 1527383971 ps |
| CPU time | 8.24 seconds |
| Started | Aug 23 07:03:26 PM UTC 24 |
| Finished | Aug 23 07:03:36 PM UTC 24 |
| Peak memory | 217844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033838480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.1033838480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_sw_invalid_input.2725413437 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 1581955477 ps |
| CPU time | 11.62 seconds |
| Started | Aug 23 07:03:33 PM UTC 24 |
| Finished | Aug 23 07:03:46 PM UTC 24 |
| Peak memory | 220224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725413437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2725413437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/3.keymgr_sync_async_fault_cross.207148616 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 121983226 ps |
| CPU time | 2.34 seconds |
| Started | Aug 23 07:03:36 PM UTC 24 |
| Finished | Aug 23 07:03:40 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207148616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.207148616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/3.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_alert_test.3939258025 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 44809700 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 07:11:15 PM UTC 24 |
| Finished | Aug 23 07:11:17 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939258025 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3939258025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_cfg_regwen.4141492196 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 295375520 ps |
| CPU time | 10.89 seconds |
| Started | Aug 23 07:11:06 PM UTC 24 |
| Finished | Aug 23 07:11:18 PM UTC 24 |
| Peak memory | 226244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141492196 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.4141492196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_custom_cm.1655812868 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 147317362 ps |
| CPU time | 3.15 seconds |
| Started | Aug 23 07:11:11 PM UTC 24 |
| Finished | Aug 23 07:11:15 PM UTC 24 |
| Peak memory | 224364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655812868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1655812868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_direct_to_disabled.2132248955 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 38277097 ps |
| CPU time | 1.65 seconds |
| Started | Aug 23 07:11:06 PM UTC 24 |
| Finished | Aug 23 07:11:09 PM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132248955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2132248955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_hwsw_invalid_input.3254929159 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 570001396 ps |
| CPU time | 4.89 seconds |
| Started | Aug 23 07:11:08 PM UTC 24 |
| Finished | Aug 23 07:11:14 PM UTC 24 |
| Peak memory | 225884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254929159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3254929159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_lc_disable.379707438 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 187745291 ps |
| CPU time | 2.98 seconds |
| Started | Aug 23 07:11:06 PM UTC 24 |
| Finished | Aug 23 07:11:11 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379707438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.379707438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_random.412020795 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2375393808 ps |
| CPU time | 3.84 seconds |
| Started | Aug 23 07:11:02 PM UTC 24 |
| Finished | Aug 23 07:11:07 PM UTC 24 |
| Peak memory | 215900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412020795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.412020795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_sideload.4055216292 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 210672655 ps |
| CPU time | 3.64 seconds |
| Started | Aug 23 07:10:57 PM UTC 24 |
| Finished | Aug 23 07:11:02 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055216292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.4055216292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_aes.1042606484 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 123126117 ps |
| CPU time | 3.99 seconds |
| Started | Aug 23 07:11:00 PM UTC 24 |
| Finished | Aug 23 07:11:05 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1042606484 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1042606484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_kmac.392836180 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 124644079 ps |
| CPU time | 2.92 seconds |
| Started | Aug 23 07:10:57 PM UTC 24 |
| Finished | Aug 23 07:11:01 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392836180 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.392836180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_otbn.1991462259 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 43234890 ps |
| CPU time | 1.95 seconds |
| Started | Aug 23 07:11:02 PM UTC 24 |
| Finished | Aug 23 07:11:05 PM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991462259 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1991462259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_sideload_protect.875057443 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 184875869 ps |
| CPU time | 2.12 seconds |
| Started | Aug 23 07:11:11 PM UTC 24 |
| Finished | Aug 23 07:11:14 PM UTC 24 |
| Peak memory | 218284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875057443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.875057443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_smoke.3114575715 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 149718759 ps |
| CPU time | 2.83 seconds |
| Started | Aug 23 07:10:56 PM UTC 24 |
| Finished | Aug 23 07:10:59 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114575715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3114575715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_stress_all.645255711 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 1725361718 ps |
| CPU time | 26.26 seconds |
| Started | Aug 23 07:11:12 PM UTC 24 |
| Finished | Aug 23 07:11:40 PM UTC 24 |
| Peak memory | 226080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645255711 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.645255711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_sw_invalid_input.3172676304 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 135780729 ps |
| CPU time | 2.48 seconds |
| Started | Aug 23 07:11:08 PM UTC 24 |
| Finished | Aug 23 07:11:12 PM UTC 24 |
| Peak memory | 223876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172676304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3172676304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/30.keymgr_sync_async_fault_cross.3019761426 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 48843516 ps |
| CPU time | 2.03 seconds |
| Started | Aug 23 07:11:12 PM UTC 24 |
| Finished | Aug 23 07:11:15 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019761426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3019761426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/30.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_alert_test.3348429596 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 15731978 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 07:11:27 PM UTC 24 |
| Finished | Aug 23 07:11:29 PM UTC 24 |
| Peak memory | 213724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348429596 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3348429596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_cfg_regwen.3713413053 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 227446834 ps |
| CPU time | 4.63 seconds |
| Started | Aug 23 07:11:20 PM UTC 24 |
| Finished | Aug 23 07:11:25 PM UTC 24 |
| Peak memory | 226224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713413053 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3713413053 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_direct_to_disabled.1962898497 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 372979536 ps |
| CPU time | 7.96 seconds |
| Started | Aug 23 07:11:20 PM UTC 24 |
| Finished | Aug 23 07:11:29 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1962898497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1962898497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_hwsw_invalid_input.3266795080 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 104939846 ps |
| CPU time | 3.07 seconds |
| Started | Aug 23 07:11:21 PM UTC 24 |
| Finished | Aug 23 07:11:25 PM UTC 24 |
| Peak memory | 224172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266795080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3266795080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_kmac_rsp_err.385081680 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 437155813 ps |
| CPU time | 2.97 seconds |
| Started | Aug 23 07:11:21 PM UTC 24 |
| Finished | Aug 23 07:11:25 PM UTC 24 |
| Peak memory | 230984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385081680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.385081680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_lc_disable.1765891134 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 70243025 ps |
| CPU time | 3.88 seconds |
| Started | Aug 23 07:11:20 PM UTC 24 |
| Finished | Aug 23 07:11:25 PM UTC 24 |
| Peak memory | 219940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765891134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1765891134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_random.836586744 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 48207140 ps |
| CPU time | 2.92 seconds |
| Started | Aug 23 07:11:20 PM UTC 24 |
| Finished | Aug 23 07:11:24 PM UTC 24 |
| Peak memory | 217984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836586744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.836586744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_sideload.2543004570 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 21419600 ps |
| CPU time | 1.4 seconds |
| Started | Aug 23 07:11:16 PM UTC 24 |
| Finished | Aug 23 07:11:18 PM UTC 24 |
| Peak memory | 215648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543004570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2543004570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_aes.1754303535 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 116309973 ps |
| CPU time | 2.48 seconds |
| Started | Aug 23 07:11:16 PM UTC 24 |
| Finished | Aug 23 07:11:20 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754303535 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1754303535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_kmac.3091554732 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 71436847 ps |
| CPU time | 3.1 seconds |
| Started | Aug 23 07:11:16 PM UTC 24 |
| Finished | Aug 23 07:11:20 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091554732 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3091554732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_otbn.4224708049 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 42846678 ps |
| CPU time | 2.05 seconds |
| Started | Aug 23 07:11:17 PM UTC 24 |
| Finished | Aug 23 07:11:20 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224708049 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4224708049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_sideload_protect.4235429299 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 29130600 ps |
| CPU time | 1.39 seconds |
| Started | Aug 23 07:11:24 PM UTC 24 |
| Finished | Aug 23 07:11:27 PM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4235429299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.4235429299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_smoke.3087220026 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 72514245 ps |
| CPU time | 2.66 seconds |
| Started | Aug 23 07:11:15 PM UTC 24 |
| Finished | Aug 23 07:11:18 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087220026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3087220026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_stress_all.2195036720 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 393344319 ps |
| CPU time | 11.63 seconds |
| Started | Aug 23 07:11:26 PM UTC 24 |
| Finished | Aug 23 07:11:38 PM UTC 24 |
| Peak memory | 228196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195036720 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2195036720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_sw_invalid_input.2725177200 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 159353104 ps |
| CPU time | 3.36 seconds |
| Started | Aug 23 07:11:21 PM UTC 24 |
| Finished | Aug 23 07:11:25 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725177200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2725177200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/31.keymgr_sync_async_fault_cross.2998150546 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 81440889 ps |
| CPU time | 1.91 seconds |
| Started | Aug 23 07:11:26 PM UTC 24 |
| Finished | Aug 23 07:11:29 PM UTC 24 |
| Peak memory | 219616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998150546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2998150546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/31.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_alert_test.2592021719 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 21152223 ps |
| CPU time | 0.78 seconds |
| Started | Aug 23 07:11:40 PM UTC 24 |
| Finished | Aug 23 07:11:42 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592021719 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2592021719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_cfg_regwen.3306020766 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 63973942 ps |
| CPU time | 2.26 seconds |
| Started | Aug 23 07:11:31 PM UTC 24 |
| Finished | Aug 23 07:11:34 PM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306020766 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3306020766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_custom_cm.4015580328 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 110006791 ps |
| CPU time | 1.84 seconds |
| Started | Aug 23 07:11:35 PM UTC 24 |
| Finished | Aug 23 07:11:38 PM UTC 24 |
| Peak memory | 227744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015580328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4015580328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_direct_to_disabled.2584074252 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 185738832 ps |
| CPU time | 2.19 seconds |
| Started | Aug 23 07:11:32 PM UTC 24 |
| Finished | Aug 23 07:11:35 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584074252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2584074252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_hwsw_invalid_input.3727305327 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 12067715763 ps |
| CPU time | 51.95 seconds |
| Started | Aug 23 07:11:34 PM UTC 24 |
| Finished | Aug 23 07:12:28 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727305327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3727305327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_kmac_rsp_err.121304211 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 356577610 ps |
| CPU time | 4.77 seconds |
| Started | Aug 23 07:11:35 PM UTC 24 |
| Finished | Aug 23 07:11:41 PM UTC 24 |
| Peak memory | 226016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121304211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.121304211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_lc_disable.3046705667 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 28318827 ps |
| CPU time | 1.81 seconds |
| Started | Aug 23 07:11:34 PM UTC 24 |
| Finished | Aug 23 07:11:37 PM UTC 24 |
| Peak memory | 231404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046705667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.3046705667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_random.2884795297 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 99771368 ps |
| CPU time | 3.69 seconds |
| Started | Aug 23 07:11:29 PM UTC 24 |
| Finished | Aug 23 07:11:34 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884795297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2884795297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_sideload.4106628257 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 48415819 ps |
| CPU time | 1.82 seconds |
| Started | Aug 23 07:11:27 PM UTC 24 |
| Finished | Aug 23 07:11:30 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106628257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.4106628257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_aes.3533785961 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 243245719 ps |
| CPU time | 2.19 seconds |
| Started | Aug 23 07:11:29 PM UTC 24 |
| Finished | Aug 23 07:11:33 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533785961 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3533785961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_kmac.628030047 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 277353251 ps |
| CPU time | 3.02 seconds |
| Started | Aug 23 07:11:27 PM UTC 24 |
| Finished | Aug 23 07:11:31 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628030047 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.628030047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_otbn.2575639804 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 244023396 ps |
| CPU time | 2.65 seconds |
| Started | Aug 23 07:11:29 PM UTC 24 |
| Finished | Aug 23 07:11:33 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575639804 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2575639804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_sideload_protect.804841775 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 150755912 ps |
| CPU time | 2.42 seconds |
| Started | Aug 23 07:11:35 PM UTC 24 |
| Finished | Aug 23 07:11:39 PM UTC 24 |
| Peak memory | 226220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804841775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.804841775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_smoke.1112707755 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 471537247 ps |
| CPU time | 4.42 seconds |
| Started | Aug 23 07:11:27 PM UTC 24 |
| Finished | Aug 23 07:11:33 PM UTC 24 |
| Peak memory | 217840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112707755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1112707755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_stress_all.1285661537 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 221575457 ps |
| CPU time | 7.33 seconds |
| Started | Aug 23 07:11:39 PM UTC 24 |
| Finished | Aug 23 07:11:47 PM UTC 24 |
| Peak memory | 228196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285661537 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1285661537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_sw_invalid_input.1003211697 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 96516093 ps |
| CPU time | 3.98 seconds |
| Started | Aug 23 07:11:34 PM UTC 24 |
| Finished | Aug 23 07:11:39 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003211697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1003211697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/32.keymgr_sync_async_fault_cross.2992097927 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 26735012 ps |
| CPU time | 1.38 seconds |
| Started | Aug 23 07:11:38 PM UTC 24 |
| Finished | Aug 23 07:11:40 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992097927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2992097927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/32.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_alert_test.912668441 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 50221381 ps |
| CPU time | 0.76 seconds |
| Started | Aug 23 07:11:51 PM UTC 24 |
| Finished | Aug 23 07:11:53 PM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912668441 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.912668441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_cfg_regwen.449409999 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 228018995 ps |
| CPU time | 5.28 seconds |
| Started | Aug 23 07:11:44 PM UTC 24 |
| Finished | Aug 23 07:11:51 PM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449409999 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.449409999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_custom_cm.578852210 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 46869151 ps |
| CPU time | 2.06 seconds |
| Started | Aug 23 07:11:47 PM UTC 24 |
| Finished | Aug 23 07:11:50 PM UTC 24 |
| Peak memory | 232720 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578852210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.578852210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_direct_to_disabled.708345093 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 59164729 ps |
| CPU time | 2.4 seconds |
| Started | Aug 23 07:11:44 PM UTC 24 |
| Finished | Aug 23 07:11:48 PM UTC 24 |
| Peak memory | 228268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708345093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.708345093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_hwsw_invalid_input.3973160227 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 168743106 ps |
| CPU time | 3.32 seconds |
| Started | Aug 23 07:11:46 PM UTC 24 |
| Finished | Aug 23 07:11:50 PM UTC 24 |
| Peak memory | 226340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973160227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3973160227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_kmac_rsp_err.2521726343 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 107503308 ps |
| CPU time | 1.91 seconds |
| Started | Aug 23 07:11:46 PM UTC 24 |
| Finished | Aug 23 07:11:49 PM UTC 24 |
| Peak memory | 230604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521726343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2521726343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_lc_disable.390941589 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 180534031 ps |
| CPU time | 3.69 seconds |
| Started | Aug 23 07:11:44 PM UTC 24 |
| Finished | Aug 23 07:11:49 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=390941589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.390941589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_random.2705634856 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 1621132963 ps |
| CPU time | 6.5 seconds |
| Started | Aug 23 07:11:43 PM UTC 24 |
| Finished | Aug 23 07:11:50 PM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705634856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2705634856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_sideload.3167959181 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 163641509 ps |
| CPU time | 2.05 seconds |
| Started | Aug 23 07:11:40 PM UTC 24 |
| Finished | Aug 23 07:11:43 PM UTC 24 |
| Peak memory | 216172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167959181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.3167959181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_aes.4166927773 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 335744872 ps |
| CPU time | 1.9 seconds |
| Started | Aug 23 07:11:42 PM UTC 24 |
| Finished | Aug 23 07:11:45 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166927773 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4166927773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_kmac.1465003076 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 89726990 ps |
| CPU time | 1.67 seconds |
| Started | Aug 23 07:11:42 PM UTC 24 |
| Finished | Aug 23 07:11:44 PM UTC 24 |
| Peak memory | 217688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465003076 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1465003076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_otbn.1064257577 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 20125365 ps |
| CPU time | 1.49 seconds |
| Started | Aug 23 07:11:43 PM UTC 24 |
| Finished | Aug 23 07:11:46 PM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064257577 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1064257577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_sideload_protect.458109497 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 45121027 ps |
| CPU time | 2.27 seconds |
| Started | Aug 23 07:11:48 PM UTC 24 |
| Finished | Aug 23 07:11:52 PM UTC 24 |
| Peak memory | 226476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=458109497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.458109497 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_smoke.628017390 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 121689954 ps |
| CPU time | 2.34 seconds |
| Started | Aug 23 07:11:40 PM UTC 24 |
| Finished | Aug 23 07:11:44 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628017390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.628017390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all.3350493748 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 289316435 ps |
| CPU time | 9.81 seconds |
| Started | Aug 23 07:11:49 PM UTC 24 |
| Finished | Aug 23 07:12:00 PM UTC 24 |
| Peak memory | 226404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350493748 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3350493748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_stress_all_with_rand_reset.4200582600 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 1722336893 ps |
| CPU time | 15.09 seconds |
| Started | Aug 23 07:11:51 PM UTC 24 |
| Finished | Aug 23 07:12:07 PM UTC 24 |
| Peak memory | 232636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4200582600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymg r_stress_all_with_rand_reset.4200582600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_sw_invalid_input.674677681 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 87257896 ps |
| CPU time | 2.99 seconds |
| Started | Aug 23 07:11:46 PM UTC 24 |
| Finished | Aug 23 07:11:50 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674677681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.674677681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/33.keymgr_sync_async_fault_cross.750464394 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 819599171 ps |
| CPU time | 4.62 seconds |
| Started | Aug 23 07:11:48 PM UTC 24 |
| Finished | Aug 23 07:11:54 PM UTC 24 |
| Peak memory | 219936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750464394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.750464394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/33.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_alert_test.837134704 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 57339029 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 07:12:05 PM UTC 24 |
| Finished | Aug 23 07:12:06 PM UTC 24 |
| Peak memory | 213596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837134704 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.837134704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_custom_cm.3590070178 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 76914052 ps |
| CPU time | 2.56 seconds |
| Started | Aug 23 07:12:00 PM UTC 24 |
| Finished | Aug 23 07:12:03 PM UTC 24 |
| Peak memory | 215816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590070178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3590070178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_direct_to_disabled.1058094568 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 320533663 ps |
| CPU time | 2.85 seconds |
| Started | Aug 23 07:11:55 PM UTC 24 |
| Finished | Aug 23 07:11:59 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058094568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1058094568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_hwsw_invalid_input.4026279892 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 502444089 ps |
| CPU time | 2.38 seconds |
| Started | Aug 23 07:11:57 PM UTC 24 |
| Finished | Aug 23 07:12:01 PM UTC 24 |
| Peak memory | 224356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4026279892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.4026279892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_kmac_rsp_err.94712071 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 1898989843 ps |
| CPU time | 3.56 seconds |
| Started | Aug 23 07:11:58 PM UTC 24 |
| Finished | Aug 23 07:12:03 PM UTC 24 |
| Peak memory | 224308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94712071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.94712071 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_lc_disable.1646111908 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 75649026 ps |
| CPU time | 2.91 seconds |
| Started | Aug 23 07:11:56 PM UTC 24 |
| Finished | Aug 23 07:12:00 PM UTC 24 |
| Peak memory | 226156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646111908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1646111908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_random.1778398825 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 82939373 ps |
| CPU time | 2.58 seconds |
| Started | Aug 23 07:11:54 PM UTC 24 |
| Finished | Aug 23 07:11:57 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778398825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1778398825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_sideload.2407129495 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 95143440 ps |
| CPU time | 2.77 seconds |
| Started | Aug 23 07:11:51 PM UTC 24 |
| Finished | Aug 23 07:11:55 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407129495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2407129495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_aes.2962285380 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 231301721 ps |
| CPU time | 2.65 seconds |
| Started | Aug 23 07:11:52 PM UTC 24 |
| Finished | Aug 23 07:11:56 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962285380 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2962285380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_kmac.4170782936 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 1559809458 ps |
| CPU time | 29.45 seconds |
| Started | Aug 23 07:11:52 PM UTC 24 |
| Finished | Aug 23 07:12:23 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170782936 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4170782936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_otbn.2498947379 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 31514156 ps |
| CPU time | 1.95 seconds |
| Started | Aug 23 07:11:52 PM UTC 24 |
| Finished | Aug 23 07:11:55 PM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498947379 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2498947379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_sideload_protect.1099262606 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 92419308 ps |
| CPU time | 1.49 seconds |
| Started | Aug 23 07:12:01 PM UTC 24 |
| Finished | Aug 23 07:12:03 PM UTC 24 |
| Peak memory | 217600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099262606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1099262606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_smoke.843186399 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 220224372 ps |
| CPU time | 2.32 seconds |
| Started | Aug 23 07:11:51 PM UTC 24 |
| Finished | Aug 23 07:11:54 PM UTC 24 |
| Peak memory | 218144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843186399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.843186399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_stress_all.907679252 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 1119183291 ps |
| CPU time | 33.16 seconds |
| Started | Aug 23 07:12:02 PM UTC 24 |
| Finished | Aug 23 07:12:37 PM UTC 24 |
| Peak memory | 232248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907679252 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.907679252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_sw_invalid_input.3396465472 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 6196249050 ps |
| CPU time | 17.56 seconds |
| Started | Aug 23 07:11:56 PM UTC 24 |
| Finished | Aug 23 07:12:15 PM UTC 24 |
| Peak memory | 218016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396465472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3396465472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/34.keymgr_sync_async_fault_cross.1885055433 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 2204456166 ps |
| CPU time | 13.46 seconds |
| Started | Aug 23 07:12:02 PM UTC 24 |
| Finished | Aug 23 07:12:17 PM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885055433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1885055433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/34.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_alert_test.1889110741 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 52476755 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 07:12:25 PM UTC 24 |
| Finished | Aug 23 07:12:27 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1889110741 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1889110741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_cfg_regwen.2326442018 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 125199981 ps |
| CPU time | 5.87 seconds |
| Started | Aug 23 07:12:12 PM UTC 24 |
| Finished | Aug 23 07:12:19 PM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326442018 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2326442018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_custom_cm.2156925544 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 382798483 ps |
| CPU time | 2.58 seconds |
| Started | Aug 23 07:12:20 PM UTC 24 |
| Finished | Aug 23 07:12:24 PM UTC 24 |
| Peak memory | 226488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156925544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2156925544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_direct_to_disabled.312180588 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 288710020 ps |
| CPU time | 2.8 seconds |
| Started | Aug 23 07:12:14 PM UTC 24 |
| Finished | Aug 23 07:12:18 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312180588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.312180588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_hwsw_invalid_input.3888018111 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 5283356225 ps |
| CPU time | 76.07 seconds |
| Started | Aug 23 07:12:18 PM UTC 24 |
| Finished | Aug 23 07:13:36 PM UTC 24 |
| Peak memory | 224180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888018111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3888018111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_kmac_rsp_err.3540552029 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 1549848475 ps |
| CPU time | 12.24 seconds |
| Started | Aug 23 07:12:18 PM UTC 24 |
| Finished | Aug 23 07:12:32 PM UTC 24 |
| Peak memory | 226348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540552029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.3540552029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_lc_disable.1279838526 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 512444029 ps |
| CPU time | 3.63 seconds |
| Started | Aug 23 07:12:16 PM UTC 24 |
| Finished | Aug 23 07:12:20 PM UTC 24 |
| Peak memory | 218316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279838526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1279838526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_random.3925828857 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 636242762 ps |
| CPU time | 6.06 seconds |
| Started | Aug 23 07:12:10 PM UTC 24 |
| Finished | Aug 23 07:12:17 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925828857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3925828857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_sideload.3344091971 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 90401164 ps |
| CPU time | 3.43 seconds |
| Started | Aug 23 07:12:05 PM UTC 24 |
| Finished | Aug 23 07:12:09 PM UTC 24 |
| Peak memory | 217964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3344091971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3344091971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_aes.442392627 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 102906037 ps |
| CPU time | 2.44 seconds |
| Started | Aug 23 07:12:08 PM UTC 24 |
| Finished | Aug 23 07:12:11 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442392627 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.442392627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_kmac.2849766811 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 2401514160 ps |
| CPU time | 22.24 seconds |
| Started | Aug 23 07:12:07 PM UTC 24 |
| Finished | Aug 23 07:12:30 PM UTC 24 |
| Peak memory | 217944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849766811 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2849766811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_otbn.1995107217 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 196194860 ps |
| CPU time | 2.25 seconds |
| Started | Aug 23 07:12:09 PM UTC 24 |
| Finished | Aug 23 07:12:13 PM UTC 24 |
| Peak memory | 216196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1995107217 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1995107217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_sideload_protect.804080398 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 108343192 ps |
| CPU time | 3.47 seconds |
| Started | Aug 23 07:12:20 PM UTC 24 |
| Finished | Aug 23 07:12:25 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804080398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.804080398 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_smoke.2859986293 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 64221545 ps |
| CPU time | 2.32 seconds |
| Started | Aug 23 07:12:05 PM UTC 24 |
| Finished | Aug 23 07:12:08 PM UTC 24 |
| Peak memory | 217936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859986293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2859986293 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_sw_invalid_input.3197385987 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 95034221 ps |
| CPU time | 3.48 seconds |
| Started | Aug 23 07:12:18 PM UTC 24 |
| Finished | Aug 23 07:12:23 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197385987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3197385987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/35.keymgr_sync_async_fault_cross.2831834649 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 166297498 ps |
| CPU time | 2.9 seconds |
| Started | Aug 23 07:12:22 PM UTC 24 |
| Finished | Aug 23 07:12:26 PM UTC 24 |
| Peak memory | 220268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831834649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2831834649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/35.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_alert_test.2512908050 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 13713358 ps |
| CPU time | 0.67 seconds |
| Started | Aug 23 07:12:41 PM UTC 24 |
| Finished | Aug 23 07:12:43 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512908050 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2512908050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_cfg_regwen.3508200354 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 58470243 ps |
| CPU time | 2.19 seconds |
| Started | Aug 23 07:12:32 PM UTC 24 |
| Finished | Aug 23 07:12:36 PM UTC 24 |
| Peak memory | 226076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508200354 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3508200354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_custom_cm.3052761256 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 117274191 ps |
| CPU time | 1.75 seconds |
| Started | Aug 23 07:12:38 PM UTC 24 |
| Finished | Aug 23 07:12:41 PM UTC 24 |
| Peak memory | 231692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052761256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3052761256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_direct_to_disabled.2294504140 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 2537246589 ps |
| CPU time | 6.09 seconds |
| Started | Aug 23 07:12:33 PM UTC 24 |
| Finished | Aug 23 07:12:41 PM UTC 24 |
| Peak memory | 217940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2294504140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2294504140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_hwsw_invalid_input.3490628962 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 52004832 ps |
| CPU time | 1.61 seconds |
| Started | Aug 23 07:12:37 PM UTC 24 |
| Finished | Aug 23 07:12:40 PM UTC 24 |
| Peak memory | 225688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490628962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.3490628962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_kmac_rsp_err.3799575984 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 63062176 ps |
| CPU time | 2.23 seconds |
| Started | Aug 23 07:12:37 PM UTC 24 |
| Finished | Aug 23 07:12:40 PM UTC 24 |
| Peak memory | 223972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799575984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3799575984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_lc_disable.3016806816 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 231537920 ps |
| CPU time | 3 seconds |
| Started | Aug 23 07:12:35 PM UTC 24 |
| Finished | Aug 23 07:12:39 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016806816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3016806816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_random.3770430229 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 395893091 ps |
| CPU time | 4.06 seconds |
| Started | Aug 23 07:12:31 PM UTC 24 |
| Finished | Aug 23 07:12:36 PM UTC 24 |
| Peak memory | 216324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770430229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3770430229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_sideload.1234557772 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 221303451 ps |
| CPU time | 5.63 seconds |
| Started | Aug 23 07:12:26 PM UTC 24 |
| Finished | Aug 23 07:12:33 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234557772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1234557772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_aes.1308237562 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 277649156 ps |
| CPU time | 3.01 seconds |
| Started | Aug 23 07:12:29 PM UTC 24 |
| Finished | Aug 23 07:12:33 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308237562 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.1308237562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_kmac.2769291121 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 394865705 ps |
| CPU time | 8.67 seconds |
| Started | Aug 23 07:12:27 PM UTC 24 |
| Finished | Aug 23 07:12:37 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2769291121 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2769291121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_otbn.426627842 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 249173757 ps |
| CPU time | 2.67 seconds |
| Started | Aug 23 07:12:30 PM UTC 24 |
| Finished | Aug 23 07:12:34 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426627842 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.426627842 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_sideload_protect.923125265 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1055176007 ps |
| CPU time | 3.31 seconds |
| Started | Aug 23 07:12:38 PM UTC 24 |
| Finished | Aug 23 07:12:43 PM UTC 24 |
| Peak memory | 218028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923125265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.923125265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_smoke.3557274906 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 559959487 ps |
| CPU time | 11.23 seconds |
| Started | Aug 23 07:12:26 PM UTC 24 |
| Finished | Aug 23 07:12:39 PM UTC 24 |
| Peak memory | 217860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557274906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3557274906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all.204632859 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 2388681775 ps |
| CPU time | 12.46 seconds |
| Started | Aug 23 07:12:40 PM UTC 24 |
| Finished | Aug 23 07:12:53 PM UTC 24 |
| Peak memory | 228192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204632859 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.204632859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_stress_all_with_rand_reset.3515057036 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 3442648723 ps |
| CPU time | 22.11 seconds |
| Started | Aug 23 07:12:41 PM UTC 24 |
| Finished | Aug 23 07:13:04 PM UTC 24 |
| Peak memory | 232448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3515057036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymg r_stress_all_with_rand_reset.3515057036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_sw_invalid_input.375655024 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 334041711 ps |
| CPU time | 3.72 seconds |
| Started | Aug 23 07:12:35 PM UTC 24 |
| Finished | Aug 23 07:12:40 PM UTC 24 |
| Peak memory | 228128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=375655024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.375655024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/36.keymgr_sync_async_fault_cross.743286132 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 51598717 ps |
| CPU time | 1.69 seconds |
| Started | Aug 23 07:12:40 PM UTC 24 |
| Finished | Aug 23 07:12:42 PM UTC 24 |
| Peak memory | 217600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743286132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.743286132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/36.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_alert_test.2609188166 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 56625173 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 07:12:57 PM UTC 24 |
| Finished | Aug 23 07:12:59 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609188166 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2609188166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_direct_to_disabled.1825066188 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 314130990 ps |
| CPU time | 3.2 seconds |
| Started | Aug 23 07:12:47 PM UTC 24 |
| Finished | Aug 23 07:12:52 PM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825066188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1825066188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_hwsw_invalid_input.2125871101 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 49121765 ps |
| CPU time | 2.18 seconds |
| Started | Aug 23 07:12:49 PM UTC 24 |
| Finished | Aug 23 07:12:52 PM UTC 24 |
| Peak memory | 226484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125871101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2125871101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_kmac_rsp_err.3152537698 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 154109620 ps |
| CPU time | 5.14 seconds |
| Started | Aug 23 07:12:50 PM UTC 24 |
| Finished | Aug 23 07:12:56 PM UTC 24 |
| Peak memory | 232236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152537698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3152537698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_lc_disable.1520323592 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 283924278 ps |
| CPU time | 6.96 seconds |
| Started | Aug 23 07:12:47 PM UTC 24 |
| Finished | Aug 23 07:12:56 PM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520323592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1520323592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_random.83092250 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 154825839 ps |
| CPU time | 3.69 seconds |
| Started | Aug 23 07:12:44 PM UTC 24 |
| Finished | Aug 23 07:12:49 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83092250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.83092250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_sideload.2092993967 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 315397109 ps |
| CPU time | 5.71 seconds |
| Started | Aug 23 07:12:42 PM UTC 24 |
| Finished | Aug 23 07:12:49 PM UTC 24 |
| Peak memory | 215844 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092993967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2092993967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_aes.54339408 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 334838904 ps |
| CPU time | 2.36 seconds |
| Started | Aug 23 07:12:44 PM UTC 24 |
| Finished | Aug 23 07:12:47 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54339408 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.54339408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_kmac.3170429714 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 115901039 ps |
| CPU time | 2.5 seconds |
| Started | Aug 23 07:12:42 PM UTC 24 |
| Finished | Aug 23 07:12:46 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170429714 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3170429714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_otbn.721374455 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 51852112 ps |
| CPU time | 2.47 seconds |
| Started | Aug 23 07:12:44 PM UTC 24 |
| Finished | Aug 23 07:12:47 PM UTC 24 |
| Peak memory | 215928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721374455 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.721374455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_sideload_protect.3769154403 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 91574497 ps |
| CPU time | 3.64 seconds |
| Started | Aug 23 07:12:52 PM UTC 24 |
| Finished | Aug 23 07:12:57 PM UTC 24 |
| Peak memory | 224184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769154403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3769154403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_smoke.2445174931 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 228088081 ps |
| CPU time | 2.35 seconds |
| Started | Aug 23 07:12:41 PM UTC 24 |
| Finished | Aug 23 07:12:44 PM UTC 24 |
| Peak memory | 215848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445174931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2445174931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_stress_all.4106505803 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 185219303 ps |
| CPU time | 7.75 seconds |
| Started | Aug 23 07:12:53 PM UTC 24 |
| Finished | Aug 23 07:13:03 PM UTC 24 |
| Peak memory | 232336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106505803 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.4106505803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_sw_invalid_input.2970032888 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 1130479669 ps |
| CPU time | 24.59 seconds |
| Started | Aug 23 07:12:49 PM UTC 24 |
| Finished | Aug 23 07:13:15 PM UTC 24 |
| Peak memory | 224352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970032888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2970032888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/37.keymgr_sync_async_fault_cross.2908104831 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 59165194 ps |
| CPU time | 2.1 seconds |
| Started | Aug 23 07:12:53 PM UTC 24 |
| Finished | Aug 23 07:12:57 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908104831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2908104831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/37.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_alert_test.1965841609 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 9568413 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 07:13:14 PM UTC 24 |
| Finished | Aug 23 07:13:16 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965841609 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1965841609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_direct_to_disabled.2489436073 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 2912482001 ps |
| CPU time | 4.64 seconds |
| Started | Aug 23 07:13:04 PM UTC 24 |
| Finished | Aug 23 07:13:10 PM UTC 24 |
| Peak memory | 218028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489436073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2489436073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_hwsw_invalid_input.2290035437 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 70568467 ps |
| CPU time | 2.83 seconds |
| Started | Aug 23 07:13:06 PM UTC 24 |
| Finished | Aug 23 07:13:10 PM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290035437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2290035437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_kmac_rsp_err.656368007 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 1712342350 ps |
| CPU time | 5.11 seconds |
| Started | Aug 23 07:13:07 PM UTC 24 |
| Finished | Aug 23 07:13:13 PM UTC 24 |
| Peak memory | 224300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656368007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.656368007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_lc_disable.1049849250 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 59139206 ps |
| CPU time | 2.52 seconds |
| Started | Aug 23 07:13:04 PM UTC 24 |
| Finished | Aug 23 07:13:08 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049849250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.1049849250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_random.1195461566 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 656180985 ps |
| CPU time | 3.53 seconds |
| Started | Aug 23 07:13:01 PM UTC 24 |
| Finished | Aug 23 07:13:06 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195461566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1195461566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_sideload.2927169112 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 110202619 ps |
| CPU time | 3.87 seconds |
| Started | Aug 23 07:12:58 PM UTC 24 |
| Finished | Aug 23 07:13:04 PM UTC 24 |
| Peak memory | 218040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927169112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2927169112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_aes.2010709990 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 751881158 ps |
| CPU time | 16.68 seconds |
| Started | Aug 23 07:13:00 PM UTC 24 |
| Finished | Aug 23 07:13:18 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010709990 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2010709990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_kmac.1880770382 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 534442835 ps |
| CPU time | 2.85 seconds |
| Started | Aug 23 07:12:58 PM UTC 24 |
| Finished | Aug 23 07:13:03 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880770382 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1880770382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_otbn.4157993583 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 6498206249 ps |
| CPU time | 54.07 seconds |
| Started | Aug 23 07:13:00 PM UTC 24 |
| Finished | Aug 23 07:13:56 PM UTC 24 |
| Peak memory | 217944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4157993583 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.4157993583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_sideload_protect.3187158483 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 458207874 ps |
| CPU time | 2.74 seconds |
| Started | Aug 23 07:13:09 PM UTC 24 |
| Finished | Aug 23 07:13:13 PM UTC 24 |
| Peak memory | 226212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187158483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3187158483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_smoke.966897068 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 25519440 ps |
| CPU time | 1.54 seconds |
| Started | Aug 23 07:12:57 PM UTC 24 |
| Finished | Aug 23 07:13:00 PM UTC 24 |
| Peak memory | 216344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966897068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.966897068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all.3801944652 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 643254262 ps |
| CPU time | 20.48 seconds |
| Started | Aug 23 07:13:12 PM UTC 24 |
| Finished | Aug 23 07:13:33 PM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801944652 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3801944652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_stress_all_with_rand_reset.2095832608 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 588265555 ps |
| CPU time | 17.9 seconds |
| Started | Aug 23 07:13:12 PM UTC 24 |
| Finished | Aug 23 07:13:31 PM UTC 24 |
| Peak memory | 232508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2095832608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymg r_stress_all_with_rand_reset.2095832608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_sw_invalid_input.3961772117 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1911296579 ps |
| CPU time | 9.37 seconds |
| Started | Aug 23 07:13:04 PM UTC 24 |
| Finished | Aug 23 07:13:15 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961772117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3961772117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/38.keymgr_sync_async_fault_cross.2403264370 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 121138852 ps |
| CPU time | 3.62 seconds |
| Started | Aug 23 07:13:10 PM UTC 24 |
| Finished | Aug 23 07:13:15 PM UTC 24 |
| Peak memory | 219944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403264370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2403264370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/38.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_alert_test.2829711214 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 14504591 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 07:13:34 PM UTC 24 |
| Finished | Aug 23 07:13:36 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829711214 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2829711214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_cfg_regwen.3698072844 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 285167710 ps |
| CPU time | 12.49 seconds |
| Started | Aug 23 07:13:21 PM UTC 24 |
| Finished | Aug 23 07:13:35 PM UTC 24 |
| Peak memory | 226052 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698072844 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3698072844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_custom_cm.2226753158 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 396449630 ps |
| CPU time | 3.9 seconds |
| Started | Aug 23 07:13:28 PM UTC 24 |
| Finished | Aug 23 07:13:33 PM UTC 24 |
| Peak memory | 220332 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226753158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2226753158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_direct_to_disabled.1228925760 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 1426302590 ps |
| CPU time | 12.49 seconds |
| Started | Aug 23 07:13:21 PM UTC 24 |
| Finished | Aug 23 07:13:35 PM UTC 24 |
| Peak memory | 230600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228925760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1228925760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_hwsw_invalid_input.3690809504 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 592671670 ps |
| CPU time | 2.38 seconds |
| Started | Aug 23 07:13:27 PM UTC 24 |
| Finished | Aug 23 07:13:30 PM UTC 24 |
| Peak memory | 224356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690809504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3690809504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_kmac_rsp_err.2062516329 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 163469860 ps |
| CPU time | 2.94 seconds |
| Started | Aug 23 07:13:28 PM UTC 24 |
| Finished | Aug 23 07:13:32 PM UTC 24 |
| Peak memory | 224128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062516329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2062516329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_lc_disable.3686422451 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 489646392 ps |
| CPU time | 2.61 seconds |
| Started | Aug 23 07:13:22 PM UTC 24 |
| Finished | Aug 23 07:13:26 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686422451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3686422451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_random.667438151 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 405842066 ps |
| CPU time | 7.1 seconds |
| Started | Aug 23 07:13:19 PM UTC 24 |
| Finished | Aug 23 07:13:27 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667438151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.667438151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_sideload.4068473789 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 198770163 ps |
| CPU time | 2.24 seconds |
| Started | Aug 23 07:13:16 PM UTC 24 |
| Finished | Aug 23 07:13:20 PM UTC 24 |
| Peak memory | 218064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068473789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4068473789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_aes.307221070 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 119283921 ps |
| CPU time | 4.02 seconds |
| Started | Aug 23 07:13:17 PM UTC 24 |
| Finished | Aug 23 07:13:22 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307221070 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.307221070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_kmac.2252153809 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 125243985 ps |
| CPU time | 2.69 seconds |
| Started | Aug 23 07:13:17 PM UTC 24 |
| Finished | Aug 23 07:13:21 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252153809 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2252153809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_otbn.1345071700 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 73854133 ps |
| CPU time | 1.96 seconds |
| Started | Aug 23 07:13:17 PM UTC 24 |
| Finished | Aug 23 07:13:20 PM UTC 24 |
| Peak memory | 215704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345071700 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1345071700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_sideload_protect.1605111097 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 671432690 ps |
| CPU time | 6.37 seconds |
| Started | Aug 23 07:13:31 PM UTC 24 |
| Finished | Aug 23 07:13:39 PM UTC 24 |
| Peak memory | 218024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605111097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1605111097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_smoke.1793829831 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 2081276366 ps |
| CPU time | 12.07 seconds |
| Started | Aug 23 07:13:14 PM UTC 24 |
| Finished | Aug 23 07:13:27 PM UTC 24 |
| Peak memory | 216104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793829831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1793829831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/39.keymgr_sw_invalid_input.3742846211 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 234738985 ps |
| CPU time | 6.15 seconds |
| Started | Aug 23 07:13:23 PM UTC 24 |
| Finished | Aug 23 07:13:31 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3742846211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3742846211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/39.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_alert_test.1515070860 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 52340664 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 07:03:53 PM UTC 24 |
| Finished | Aug 23 07:03:55 PM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515070860 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1515070860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_cfg_regwen.3472612693 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 248822474 ps |
| CPU time | 3.56 seconds |
| Started | Aug 23 07:03:45 PM UTC 24 |
| Finished | Aug 23 07:03:49 PM UTC 24 |
| Peak memory | 224352 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472612693 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3472612693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_custom_cm.1752591152 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 201710055 ps |
| CPU time | 2.37 seconds |
| Started | Aug 23 07:03:49 PM UTC 24 |
| Finished | Aug 23 07:03:52 PM UTC 24 |
| Peak memory | 217972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752591152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1752591152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_direct_to_disabled.2085051061 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 263571672 ps |
| CPU time | 2.07 seconds |
| Started | Aug 23 07:03:45 PM UTC 24 |
| Finished | Aug 23 07:03:48 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2085051061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2085051061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_hwsw_invalid_input.1202187551 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 32664659 ps |
| CPU time | 2.08 seconds |
| Started | Aug 23 07:03:47 PM UTC 24 |
| Finished | Aug 23 07:03:50 PM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1202187551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1202187551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_kmac_rsp_err.3091275090 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 106869630 ps |
| CPU time | 3.04 seconds |
| Started | Aug 23 07:03:49 PM UTC 24 |
| Finished | Aug 23 07:03:53 PM UTC 24 |
| Peak memory | 213932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091275090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3091275090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_lc_disable.230784385 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 887646926 ps |
| CPU time | 3.09 seconds |
| Started | Aug 23 07:03:46 PM UTC 24 |
| Finished | Aug 23 07:03:50 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230784385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.230784385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_random.78267781 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 226299506 ps |
| CPU time | 4.54 seconds |
| Started | Aug 23 07:03:44 PM UTC 24 |
| Finished | Aug 23 07:03:49 PM UTC 24 |
| Peak memory | 228516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78267781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.78267781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_sideload.1746422435 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 114793151 ps |
| CPU time | 2.48 seconds |
| Started | Aug 23 07:03:39 PM UTC 24 |
| Finished | Aug 23 07:03:43 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746422435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1746422435 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_aes.404429149 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 548642097 ps |
| CPU time | 2.37 seconds |
| Started | Aug 23 07:03:41 PM UTC 24 |
| Finished | Aug 23 07:03:44 PM UTC 24 |
| Peak memory | 217540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404429149 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.404429149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_kmac.189504540 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 578307294 ps |
| CPU time | 7.62 seconds |
| Started | Aug 23 07:03:40 PM UTC 24 |
| Finished | Aug 23 07:03:49 PM UTC 24 |
| Peak memory | 215528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189504540 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.189504540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_otbn.3615082616 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 143232116 ps |
| CPU time | 3.23 seconds |
| Started | Aug 23 07:03:44 PM UTC 24 |
| Finished | Aug 23 07:03:48 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615082616 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3615082616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_sideload_protect.3305071503 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 847618920 ps |
| CPU time | 4.57 seconds |
| Started | Aug 23 07:03:50 PM UTC 24 |
| Finished | Aug 23 07:03:56 PM UTC 24 |
| Peak memory | 228188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305071503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3305071503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_smoke.2967187905 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 73587304 ps |
| CPU time | 2.95 seconds |
| Started | Aug 23 07:03:38 PM UTC 24 |
| Finished | Aug 23 07:03:42 PM UTC 24 |
| Peak memory | 217996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967187905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2967187905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_sw_invalid_input.3434184688 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 1054086027 ps |
| CPU time | 30.39 seconds |
| Started | Aug 23 07:03:46 PM UTC 24 |
| Finished | Aug 23 07:04:18 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434184688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3434184688 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/4.keymgr_sync_async_fault_cross.445166121 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 45140650 ps |
| CPU time | 2.09 seconds |
| Started | Aug 23 07:03:50 PM UTC 24 |
| Finished | Aug 23 07:03:53 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445166121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.445166121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/4.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_alert_test.3439028637 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 27416508 ps |
| CPU time | 0.74 seconds |
| Started | Aug 23 07:13:48 PM UTC 24 |
| Finished | Aug 23 07:13:49 PM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439028637 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3439028637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_cfg_regwen.1179011789 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 35363540 ps |
| CPU time | 2.48 seconds |
| Started | Aug 23 07:13:39 PM UTC 24 |
| Finished | Aug 23 07:13:43 PM UTC 24 |
| Peak memory | 224164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179011789 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1179011789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_custom_cm.523807728 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 281806248 ps |
| CPU time | 3.67 seconds |
| Started | Aug 23 07:13:43 PM UTC 24 |
| Finished | Aug 23 07:13:48 PM UTC 24 |
| Peak memory | 230520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523807728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.523807728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_direct_to_disabled.2426632875 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 540623489 ps |
| CPU time | 12 seconds |
| Started | Aug 23 07:13:39 PM UTC 24 |
| Finished | Aug 23 07:13:52 PM UTC 24 |
| Peak memory | 232168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426632875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2426632875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_hwsw_invalid_input.4230456353 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 397944162 ps |
| CPU time | 4.18 seconds |
| Started | Aug 23 07:13:42 PM UTC 24 |
| Finished | Aug 23 07:13:47 PM UTC 24 |
| Peak memory | 231708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230456353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.4230456353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_kmac_rsp_err.1197398854 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 373631013 ps |
| CPU time | 2.38 seconds |
| Started | Aug 23 07:13:42 PM UTC 24 |
| Finished | Aug 23 07:13:45 PM UTC 24 |
| Peak memory | 225576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197398854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1197398854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_lc_disable.2577705830 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 342183456 ps |
| CPU time | 2.53 seconds |
| Started | Aug 23 07:13:40 PM UTC 24 |
| Finished | Aug 23 07:13:44 PM UTC 24 |
| Peak memory | 224036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577705830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2577705830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_random.756571555 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 162632860 ps |
| CPU time | 2.9 seconds |
| Started | Aug 23 07:13:38 PM UTC 24 |
| Finished | Aug 23 07:13:42 PM UTC 24 |
| Peak memory | 224360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756571555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.756571555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_sideload.676506255 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 47558851 ps |
| CPU time | 1.68 seconds |
| Started | Aug 23 07:13:35 PM UTC 24 |
| Finished | Aug 23 07:13:38 PM UTC 24 |
| Peak memory | 217748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676506255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.676506255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_aes.1673659031 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 127597550 ps |
| CPU time | 2.87 seconds |
| Started | Aug 23 07:13:37 PM UTC 24 |
| Finished | Aug 23 07:13:41 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673659031 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1673659031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_kmac.3723640319 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 79216731 ps |
| CPU time | 2.93 seconds |
| Started | Aug 23 07:13:36 PM UTC 24 |
| Finished | Aug 23 07:13:41 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723640319 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3723640319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_otbn.2556536451 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 201069409 ps |
| CPU time | 6.61 seconds |
| Started | Aug 23 07:13:37 PM UTC 24 |
| Finished | Aug 23 07:13:45 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556536451 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2556536451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_sideload_protect.1365778964 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 189337908 ps |
| CPU time | 4.86 seconds |
| Started | Aug 23 07:13:44 PM UTC 24 |
| Finished | Aug 23 07:13:50 PM UTC 24 |
| Peak memory | 217948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365778964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1365778964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_smoke.3570644752 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 166988057 ps |
| CPU time | 4.49 seconds |
| Started | Aug 23 07:13:34 PM UTC 24 |
| Finished | Aug 23 07:13:40 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570644752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3570644752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all.1284216150 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 6352972651 ps |
| CPU time | 38.33 seconds |
| Started | Aug 23 07:13:45 PM UTC 24 |
| Finished | Aug 23 07:14:25 PM UTC 24 |
| Peak memory | 228260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284216150 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1284216150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_stress_all_with_rand_reset.1328246769 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 270142804 ps |
| CPU time | 9.37 seconds |
| Started | Aug 23 07:13:46 PM UTC 24 |
| Finished | Aug 23 07:13:57 PM UTC 24 |
| Peak memory | 232308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1328246769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymg r_stress_all_with_rand_reset.1328246769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_sw_invalid_input.2033555845 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 1051741235 ps |
| CPU time | 6.27 seconds |
| Started | Aug 23 07:13:40 PM UTC 24 |
| Finished | Aug 23 07:13:48 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033555845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2033555845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/40.keymgr_sync_async_fault_cross.2587938992 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 415383029 ps |
| CPU time | 2.34 seconds |
| Started | Aug 23 07:13:45 PM UTC 24 |
| Finished | Aug 23 07:13:49 PM UTC 24 |
| Peak memory | 217892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587938992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2587938992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/40.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_alert_test.3278874845 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 13049061 ps |
| CPU time | 0.83 seconds |
| Started | Aug 23 07:14:02 PM UTC 24 |
| Finished | Aug 23 07:14:04 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278874845 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3278874845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_cfg_regwen.2611829929 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1609486518 ps |
| CPU time | 55 seconds |
| Started | Aug 23 07:13:54 PM UTC 24 |
| Finished | Aug 23 07:14:50 PM UTC 24 |
| Peak memory | 226260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611829929 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2611829929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_direct_to_disabled.1425781923 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 124997009 ps |
| CPU time | 1.64 seconds |
| Started | Aug 23 07:13:55 PM UTC 24 |
| Finished | Aug 23 07:13:58 PM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425781923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1425781923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_hwsw_invalid_input.2487447999 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 392847230 ps |
| CPU time | 5.29 seconds |
| Started | Aug 23 07:13:57 PM UTC 24 |
| Finished | Aug 23 07:14:03 PM UTC 24 |
| Peak memory | 231972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487447999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2487447999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_lc_disable.3908106820 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 82786090 ps |
| CPU time | 2.01 seconds |
| Started | Aug 23 07:13:55 PM UTC 24 |
| Finished | Aug 23 07:13:58 PM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908106820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3908106820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_random.555500181 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 776909887 ps |
| CPU time | 5.75 seconds |
| Started | Aug 23 07:13:53 PM UTC 24 |
| Finished | Aug 23 07:14:00 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555500181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.555500181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_sideload.640140909 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 240822577 ps |
| CPU time | 5.74 seconds |
| Started | Aug 23 07:13:49 PM UTC 24 |
| Finished | Aug 23 07:13:56 PM UTC 24 |
| Peak memory | 217848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640140909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.640140909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_aes.2675224872 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 39537203 ps |
| CPU time | 2.26 seconds |
| Started | Aug 23 07:13:50 PM UTC 24 |
| Finished | Aug 23 07:13:54 PM UTC 24 |
| Peak memory | 217992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675224872 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2675224872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_kmac.533640269 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 423085883 ps |
| CPU time | 4.81 seconds |
| Started | Aug 23 07:13:50 PM UTC 24 |
| Finished | Aug 23 07:13:56 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533640269 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.533640269 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_otbn.172798287 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 40296081 ps |
| CPU time | 2.07 seconds |
| Started | Aug 23 07:13:51 PM UTC 24 |
| Finished | Aug 23 07:13:55 PM UTC 24 |
| Peak memory | 216160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172798287 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.172798287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_sideload_protect.2508234918 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 6807833870 ps |
| CPU time | 21.67 seconds |
| Started | Aug 23 07:13:59 PM UTC 24 |
| Finished | Aug 23 07:14:22 PM UTC 24 |
| Peak memory | 218360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508234918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2508234918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_smoke.554735343 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 159418010 ps |
| CPU time | 1.85 seconds |
| Started | Aug 23 07:13:49 PM UTC 24 |
| Finished | Aug 23 07:13:52 PM UTC 24 |
| Peak memory | 213520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554735343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.554735343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all.888170707 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2866349631 ps |
| CPU time | 32.92 seconds |
| Started | Aug 23 07:14:00 PM UTC 24 |
| Finished | Aug 23 07:14:35 PM UTC 24 |
| Peak memory | 226144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888170707 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.888170707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_stress_all_with_rand_reset.3155590131 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 184731863 ps |
| CPU time | 4.69 seconds |
| Started | Aug 23 07:14:00 PM UTC 24 |
| Finished | Aug 23 07:14:06 PM UTC 24 |
| Peak memory | 232388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3155590131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymg r_stress_all_with_rand_reset.3155590131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_sw_invalid_input.483559953 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 417242014 ps |
| CPU time | 3.46 seconds |
| Started | Aug 23 07:13:57 PM UTC 24 |
| Finished | Aug 23 07:14:01 PM UTC 24 |
| Peak memory | 228136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483559953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.483559953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/41.keymgr_sync_async_fault_cross.245901463 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 268854081 ps |
| CPU time | 1.72 seconds |
| Started | Aug 23 07:13:59 PM UTC 24 |
| Finished | Aug 23 07:14:02 PM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245901463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.245901463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/41.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_alert_test.1032542273 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 39103300 ps |
| CPU time | 0.78 seconds |
| Started | Aug 23 07:14:21 PM UTC 24 |
| Finished | Aug 23 07:14:23 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1032542273 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1032542273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_cfg_regwen.3961753361 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 164212274 ps |
| CPU time | 5.76 seconds |
| Started | Aug 23 07:14:08 PM UTC 24 |
| Finished | Aug 23 07:14:15 PM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961753361 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3961753361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_custom_cm.2862661397 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 361583179 ps |
| CPU time | 2.51 seconds |
| Started | Aug 23 07:14:16 PM UTC 24 |
| Finished | Aug 23 07:14:20 PM UTC 24 |
| Peak memory | 224384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862661397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2862661397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_direct_to_disabled.3330038133 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 153353740 ps |
| CPU time | 2 seconds |
| Started | Aug 23 07:14:10 PM UTC 24 |
| Finished | Aug 23 07:14:13 PM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330038133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3330038133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_hwsw_invalid_input.287111628 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 872365550 ps |
| CPU time | 7.84 seconds |
| Started | Aug 23 07:14:16 PM UTC 24 |
| Finished | Aug 23 07:14:25 PM UTC 24 |
| Peak memory | 218228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287111628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.287111628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_kmac_rsp_err.4257461430 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 49099643 ps |
| CPU time | 1.81 seconds |
| Started | Aug 23 07:14:16 PM UTC 24 |
| Finished | Aug 23 07:14:19 PM UTC 24 |
| Peak memory | 224016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257461430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.4257461430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_lc_disable.2176263200 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 33212269 ps |
| CPU time | 2.25 seconds |
| Started | Aug 23 07:14:11 PM UTC 24 |
| Finished | Aug 23 07:14:15 PM UTC 24 |
| Peak memory | 218028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2176263200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.2176263200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_random.1558463719 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 300913543 ps |
| CPU time | 7.4 seconds |
| Started | Aug 23 07:14:08 PM UTC 24 |
| Finished | Aug 23 07:14:16 PM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558463719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1558463719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_sideload.1145531324 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 256528219 ps |
| CPU time | 2.61 seconds |
| Started | Aug 23 07:14:03 PM UTC 24 |
| Finished | Aug 23 07:14:07 PM UTC 24 |
| Peak memory | 217980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145531324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1145531324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_aes.160571879 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 126518004 ps |
| CPU time | 4.1 seconds |
| Started | Aug 23 07:14:04 PM UTC 24 |
| Finished | Aug 23 07:14:10 PM UTC 24 |
| Peak memory | 217148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160571879 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.160571879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_kmac.1506826080 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 289957003 ps |
| CPU time | 4.26 seconds |
| Started | Aug 23 07:14:04 PM UTC 24 |
| Finished | Aug 23 07:14:10 PM UTC 24 |
| Peak memory | 217396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506826080 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1506826080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_otbn.899882279 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 217866537 ps |
| CPU time | 6.41 seconds |
| Started | Aug 23 07:14:08 PM UTC 24 |
| Finished | Aug 23 07:14:15 PM UTC 24 |
| Peak memory | 217904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899882279 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.899882279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_sideload_protect.1748328287 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 217607096 ps |
| CPU time | 2.93 seconds |
| Started | Aug 23 07:14:17 PM UTC 24 |
| Finished | Aug 23 07:14:21 PM UTC 24 |
| Peak memory | 215972 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748328287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1748328287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_smoke.2825397990 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 54010153 ps |
| CPU time | 2.26 seconds |
| Started | Aug 23 07:14:03 PM UTC 24 |
| Finished | Aug 23 07:14:06 PM UTC 24 |
| Peak memory | 218152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825397990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2825397990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_stress_all.334755191 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 4117758635 ps |
| CPU time | 72.62 seconds |
| Started | Aug 23 07:14:20 PM UTC 24 |
| Finished | Aug 23 07:15:34 PM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334755191 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.334755191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_sw_invalid_input.669495655 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 97417841 ps |
| CPU time | 4.03 seconds |
| Started | Aug 23 07:14:14 PM UTC 24 |
| Finished | Aug 23 07:14:20 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669495655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.669495655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/42.keymgr_sync_async_fault_cross.1030541709 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 210524115 ps |
| CPU time | 2.79 seconds |
| Started | Aug 23 07:14:17 PM UTC 24 |
| Finished | Aug 23 07:14:21 PM UTC 24 |
| Peak memory | 220008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030541709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1030541709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/42.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_alert_test.758563853 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 221993740 ps |
| CPU time | 0.7 seconds |
| Started | Aug 23 07:14:37 PM UTC 24 |
| Finished | Aug 23 07:14:39 PM UTC 24 |
| Peak memory | 213596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758563853 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.758563853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_cfg_regwen.4074137132 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 59538679 ps |
| CPU time | 3.71 seconds |
| Started | Aug 23 07:14:27 PM UTC 24 |
| Finished | Aug 23 07:14:32 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074137132 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.4074137132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_direct_to_disabled.728256061 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 209037613 ps |
| CPU time | 1.56 seconds |
| Started | Aug 23 07:14:27 PM UTC 24 |
| Finished | Aug 23 07:14:30 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728256061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.728256061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_hwsw_invalid_input.466538359 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 366933651 ps |
| CPU time | 2.78 seconds |
| Started | Aug 23 07:14:31 PM UTC 24 |
| Finished | Aug 23 07:14:35 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466538359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.466538359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_kmac_rsp_err.1036250725 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 46527789 ps |
| CPU time | 2.02 seconds |
| Started | Aug 23 07:14:33 PM UTC 24 |
| Finished | Aug 23 07:14:36 PM UTC 24 |
| Peak memory | 230444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036250725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1036250725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_lc_disable.3705752995 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 110082807 ps |
| CPU time | 2.53 seconds |
| Started | Aug 23 07:14:28 PM UTC 24 |
| Finished | Aug 23 07:14:32 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705752995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3705752995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_random.262579355 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 5646776514 ps |
| CPU time | 22.4 seconds |
| Started | Aug 23 07:14:26 PM UTC 24 |
| Finished | Aug 23 07:14:50 PM UTC 24 |
| Peak memory | 220000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262579355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.262579355 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_sideload.552477312 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 58115736 ps |
| CPU time | 2.6 seconds |
| Started | Aug 23 07:14:22 PM UTC 24 |
| Finished | Aug 23 07:14:26 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552477312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.552477312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_aes.1788117038 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 424919923 ps |
| CPU time | 3.74 seconds |
| Started | Aug 23 07:14:24 PM UTC 24 |
| Finished | Aug 23 07:14:28 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788117038 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1788117038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_kmac.1144819303 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 96391736 ps |
| CPU time | 2.7 seconds |
| Started | Aug 23 07:14:24 PM UTC 24 |
| Finished | Aug 23 07:14:27 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144819303 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1144819303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_otbn.3403400714 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 179890698 ps |
| CPU time | 5.02 seconds |
| Started | Aug 23 07:14:26 PM UTC 24 |
| Finished | Aug 23 07:14:32 PM UTC 24 |
| Peak memory | 218192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403400714 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.3403400714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_sideload_protect.735919122 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 6564708498 ps |
| CPU time | 23.48 seconds |
| Started | Aug 23 07:14:33 PM UTC 24 |
| Finished | Aug 23 07:14:58 PM UTC 24 |
| Peak memory | 230308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735919122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.735919122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_smoke.304974015 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 9441229992 ps |
| CPU time | 20.06 seconds |
| Started | Aug 23 07:14:22 PM UTC 24 |
| Finished | Aug 23 07:14:43 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304974015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.304974015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all.2896482667 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 602467254 ps |
| CPU time | 18.26 seconds |
| Started | Aug 23 07:14:36 PM UTC 24 |
| Finished | Aug 23 07:14:55 PM UTC 24 |
| Peak memory | 228196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896482667 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2896482667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_stress_all_with_rand_reset.1146631525 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 557874317 ps |
| CPU time | 10.45 seconds |
| Started | Aug 23 07:14:36 PM UTC 24 |
| Finished | Aug 23 07:14:47 PM UTC 24 |
| Peak memory | 232376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1146631525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymg r_stress_all_with_rand_reset.1146631525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_sw_invalid_input.213185353 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 550626194 ps |
| CPU time | 4.53 seconds |
| Started | Aug 23 07:14:30 PM UTC 24 |
| Finished | Aug 23 07:14:35 PM UTC 24 |
| Peak memory | 218060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213185353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.213185353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/43.keymgr_sync_async_fault_cross.4146725630 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 58552749 ps |
| CPU time | 1.54 seconds |
| Started | Aug 23 07:14:36 PM UTC 24 |
| Finished | Aug 23 07:14:38 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146725630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.4146725630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/43.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_alert_test.3475439334 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 9179378 ps |
| CPU time | 0.75 seconds |
| Started | Aug 23 07:14:59 PM UTC 24 |
| Finished | Aug 23 07:15:01 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475439334 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.3475439334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_direct_to_disabled.2279803801 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 909716482 ps |
| CPU time | 2.73 seconds |
| Started | Aug 23 07:14:49 PM UTC 24 |
| Finished | Aug 23 07:14:54 PM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279803801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2279803801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_hwsw_invalid_input.1648793853 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 82799093 ps |
| CPU time | 3.26 seconds |
| Started | Aug 23 07:14:55 PM UTC 24 |
| Finished | Aug 23 07:15:00 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648793853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1648793853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_kmac_rsp_err.3997933214 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 274136163 ps |
| CPU time | 1.75 seconds |
| Started | Aug 23 07:14:55 PM UTC 24 |
| Finished | Aug 23 07:14:58 PM UTC 24 |
| Peak memory | 217572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997933214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3997933214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_lc_disable.3456781338 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 358069494 ps |
| CPU time | 4.83 seconds |
| Started | Aug 23 07:14:51 PM UTC 24 |
| Finished | Aug 23 07:14:57 PM UTC 24 |
| Peak memory | 218220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456781338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3456781338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_random.1997577087 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 247272105 ps |
| CPU time | 4.91 seconds |
| Started | Aug 23 07:14:48 PM UTC 24 |
| Finished | Aug 23 07:14:54 PM UTC 24 |
| Peak memory | 226488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997577087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1997577087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_sideload.2065980549 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 99492358 ps |
| CPU time | 2.49 seconds |
| Started | Aug 23 07:14:40 PM UTC 24 |
| Finished | Aug 23 07:14:43 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065980549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2065980549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_aes.60404044 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 34146761 ps |
| CPU time | 2.08 seconds |
| Started | Aug 23 07:14:44 PM UTC 24 |
| Finished | Aug 23 07:14:47 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60404044 -assert nopostproc +UVM_TESTNAME=keymgr_base_ test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.60404044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_kmac.579643722 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 1240956691 ps |
| CPU time | 20.05 seconds |
| Started | Aug 23 07:14:40 PM UTC 24 |
| Finished | Aug 23 07:15:01 PM UTC 24 |
| Peak memory | 218212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579643722 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.579643722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_otbn.3766120532 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 48499454 ps |
| CPU time | 2.38 seconds |
| Started | Aug 23 07:14:45 PM UTC 24 |
| Finished | Aug 23 07:14:48 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766120532 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3766120532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_sideload_protect.1236738254 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 86872183 ps |
| CPU time | 1.72 seconds |
| Started | Aug 23 07:14:58 PM UTC 24 |
| Finished | Aug 23 07:15:01 PM UTC 24 |
| Peak memory | 224412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1236738254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1236738254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_smoke.309765495 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 1403731826 ps |
| CPU time | 28.36 seconds |
| Started | Aug 23 07:14:38 PM UTC 24 |
| Finished | Aug 23 07:15:08 PM UTC 24 |
| Peak memory | 215780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=309765495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.309765495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_stress_all.3888953261 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 1473199478 ps |
| CPU time | 18.48 seconds |
| Started | Aug 23 07:14:59 PM UTC 24 |
| Finished | Aug 23 07:15:19 PM UTC 24 |
| Peak memory | 226148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888953261 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3888953261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_sw_invalid_input.1879792152 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 123953422 ps |
| CPU time | 4.93 seconds |
| Started | Aug 23 07:14:52 PM UTC 24 |
| Finished | Aug 23 07:14:58 PM UTC 24 |
| Peak memory | 228156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1879792152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.1879792152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/44.keymgr_sync_async_fault_cross.512551608 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 65168728 ps |
| CPU time | 1.78 seconds |
| Started | Aug 23 07:14:58 PM UTC 24 |
| Finished | Aug 23 07:15:01 PM UTC 24 |
| Peak memory | 219676 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512551608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.512551608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/44.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_alert_test.1883604089 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 33388781 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 07:15:13 PM UTC 24 |
| Finished | Aug 23 07:15:15 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883604089 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.1883604089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_cfg_regwen.4107079611 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 682847727 ps |
| CPU time | 29.46 seconds |
| Started | Aug 23 07:15:05 PM UTC 24 |
| Finished | Aug 23 07:15:36 PM UTC 24 |
| Peak memory | 226404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107079611 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.4107079611 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_custom_cm.528459046 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 6421584899 ps |
| CPU time | 14.83 seconds |
| Started | Aug 23 07:15:08 PM UTC 24 |
| Finished | Aug 23 07:15:24 PM UTC 24 |
| Peak memory | 228268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528459046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.528459046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_direct_to_disabled.499178233 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 94844421 ps |
| CPU time | 2.13 seconds |
| Started | Aug 23 07:15:05 PM UTC 24 |
| Finished | Aug 23 07:15:08 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499178233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.499178233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_hwsw_invalid_input.2785362280 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 556154281 ps |
| CPU time | 2.61 seconds |
| Started | Aug 23 07:15:08 PM UTC 24 |
| Finished | Aug 23 07:15:11 PM UTC 24 |
| Peak memory | 230592 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785362280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2785362280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_kmac_rsp_err.2858898363 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 193993982 ps |
| CPU time | 1.77 seconds |
| Started | Aug 23 07:15:08 PM UTC 24 |
| Finished | Aug 23 07:15:11 PM UTC 24 |
| Peak memory | 223588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858898363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2858898363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_lc_disable.1984275683 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 396909318 ps |
| CPU time | 3.76 seconds |
| Started | Aug 23 07:15:06 PM UTC 24 |
| Finished | Aug 23 07:15:11 PM UTC 24 |
| Peak memory | 230204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984275683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1984275683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_random.2163872770 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 116409053 ps |
| CPU time | 2.09 seconds |
| Started | Aug 23 07:15:03 PM UTC 24 |
| Finished | Aug 23 07:15:07 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163872770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2163872770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_sideload.1826359187 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 751873846 ps |
| CPU time | 2.99 seconds |
| Started | Aug 23 07:15:02 PM UTC 24 |
| Finished | Aug 23 07:15:06 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826359187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1826359187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_aes.3607403349 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 47214194 ps |
| CPU time | 2.1 seconds |
| Started | Aug 23 07:15:02 PM UTC 24 |
| Finished | Aug 23 07:15:05 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607403349 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3607403349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_kmac.1685922105 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 78391438 ps |
| CPU time | 3.12 seconds |
| Started | Aug 23 07:15:02 PM UTC 24 |
| Finished | Aug 23 07:15:06 PM UTC 24 |
| Peak memory | 217992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685922105 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1685922105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_otbn.210143518 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 94234401 ps |
| CPU time | 2.82 seconds |
| Started | Aug 23 07:15:02 PM UTC 24 |
| Finished | Aug 23 07:15:06 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210143518 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.210143518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_sideload_protect.1590188500 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 197486091 ps |
| CPU time | 2.2 seconds |
| Started | Aug 23 07:15:09 PM UTC 24 |
| Finished | Aug 23 07:15:12 PM UTC 24 |
| Peak memory | 215900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590188500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1590188500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_smoke.295456618 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 83755482 ps |
| CPU time | 2.23 seconds |
| Started | Aug 23 07:15:00 PM UTC 24 |
| Finished | Aug 23 07:15:04 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295456618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.295456618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all.509551644 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 860487168 ps |
| CPU time | 24.91 seconds |
| Started | Aug 23 07:15:11 PM UTC 24 |
| Finished | Aug 23 07:15:37 PM UTC 24 |
| Peak memory | 228200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509551644 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.509551644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_stress_all_with_rand_reset.3286448448 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 512585318 ps |
| CPU time | 16.85 seconds |
| Started | Aug 23 07:15:13 PM UTC 24 |
| Finished | Aug 23 07:15:31 PM UTC 24 |
| Peak memory | 232612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3286448448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymg r_stress_all_with_rand_reset.3286448448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_sw_invalid_input.1315146622 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 88689383 ps |
| CPU time | 2.57 seconds |
| Started | Aug 23 07:15:08 PM UTC 24 |
| Finished | Aug 23 07:15:11 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315146622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.1315146622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/45.keymgr_sync_async_fault_cross.486735814 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 2374828837 ps |
| CPU time | 3.64 seconds |
| Started | Aug 23 07:15:09 PM UTC 24 |
| Finished | Aug 23 07:15:14 PM UTC 24 |
| Peak memory | 220328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=486735814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr -sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.486735814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/45.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_alert_test.1277006568 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 16225438 ps |
| CPU time | 0.84 seconds |
| Started | Aug 23 07:15:34 PM UTC 24 |
| Finished | Aug 23 07:15:36 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277006568 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.1277006568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_cfg_regwen.642056530 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 499686471 ps |
| CPU time | 11.86 seconds |
| Started | Aug 23 07:15:20 PM UTC 24 |
| Finished | Aug 23 07:15:33 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642056530 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.642056530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_direct_to_disabled.1115767628 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 137058043 ps |
| CPU time | 2.07 seconds |
| Started | Aug 23 07:15:21 PM UTC 24 |
| Finished | Aug 23 07:15:24 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115767628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1115767628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_hwsw_invalid_input.1340725393 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 76326920 ps |
| CPU time | 2.32 seconds |
| Started | Aug 23 07:15:26 PM UTC 24 |
| Finished | Aug 23 07:15:29 PM UTC 24 |
| Peak memory | 232196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340725393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1340725393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_kmac_rsp_err.1778180433 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 1375150951 ps |
| CPU time | 3.05 seconds |
| Started | Aug 23 07:15:26 PM UTC 24 |
| Finished | Aug 23 07:15:30 PM UTC 24 |
| Peak memory | 232244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778180433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1778180433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_lc_disable.4191022341 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 329023663 ps |
| CPU time | 4.17 seconds |
| Started | Aug 23 07:15:24 PM UTC 24 |
| Finished | Aug 23 07:15:30 PM UTC 24 |
| Peak memory | 224448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191022341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.4191022341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_random.2820522978 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 670386395 ps |
| CPU time | 15.84 seconds |
| Started | Aug 23 07:15:18 PM UTC 24 |
| Finished | Aug 23 07:15:35 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820522978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2820522978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_sideload.114177470 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 33521764 ps |
| CPU time | 1.89 seconds |
| Started | Aug 23 07:15:13 PM UTC 24 |
| Finished | Aug 23 07:15:16 PM UTC 24 |
| Peak memory | 215764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114177470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.114177470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_aes.3861166636 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 231648195 ps |
| CPU time | 2.82 seconds |
| Started | Aug 23 07:15:16 PM UTC 24 |
| Finished | Aug 23 07:15:20 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861166636 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3861166636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_kmac.76605993 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 423587459 ps |
| CPU time | 7 seconds |
| Started | Aug 23 07:15:15 PM UTC 24 |
| Finished | Aug 23 07:15:23 PM UTC 24 |
| Peak memory | 215832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76605993 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.76605993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_otbn.1466989616 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 2382976780 ps |
| CPU time | 4.53 seconds |
| Started | Aug 23 07:15:18 PM UTC 24 |
| Finished | Aug 23 07:15:24 PM UTC 24 |
| Peak memory | 215916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1466989616 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1466989616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_sideload_protect.3627107694 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 216838029 ps |
| CPU time | 2.08 seconds |
| Started | Aug 23 07:15:30 PM UTC 24 |
| Finished | Aug 23 07:15:34 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627107694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3627107694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_smoke.4118002044 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 236608721 ps |
| CPU time | 1.86 seconds |
| Started | Aug 23 07:15:13 PM UTC 24 |
| Finished | Aug 23 07:15:16 PM UTC 24 |
| Peak memory | 215772 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118002044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.4118002044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all.459519644 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 2606185494 ps |
| CPU time | 18.77 seconds |
| Started | Aug 23 07:15:30 PM UTC 24 |
| Finished | Aug 23 07:15:50 PM UTC 24 |
| Peak memory | 228264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459519644 -assert nopostproc +UVM_TESTNAME=k eymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.459519644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_stress_all_with_rand_reset.585123853 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 330829163 ps |
| CPU time | 12.43 seconds |
| Started | Aug 23 07:15:32 PM UTC 24 |
| Finished | Aug 23 07:15:45 PM UTC 24 |
| Peak memory | 230680 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=585123853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr _stress_all_with_rand_reset.585123853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_sw_invalid_input.588225270 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 181855858 ps |
| CPU time | 2.73 seconds |
| Started | Aug 23 07:15:24 PM UTC 24 |
| Finished | Aug 23 07:15:28 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588225270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.588225270 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/46.keymgr_sync_async_fault_cross.1335962800 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 169518888 ps |
| CPU time | 1.68 seconds |
| Started | Aug 23 07:15:30 PM UTC 24 |
| Finished | Aug 23 07:15:33 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335962800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1335962800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/46.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_alert_test.1832154650 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 11825711 ps |
| CPU time | 0.68 seconds |
| Started | Aug 23 07:15:48 PM UTC 24 |
| Finished | Aug 23 07:15:50 PM UTC 24 |
| Peak memory | 214176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832154650 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1832154650 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_cfg_regwen.4190897359 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 204015082 ps |
| CPU time | 3.62 seconds |
| Started | Aug 23 07:15:37 PM UTC 24 |
| Finished | Aug 23 07:15:42 PM UTC 24 |
| Peak memory | 226112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190897359 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.4190897359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_custom_cm.2026221565 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 1093261732 ps |
| CPU time | 2.77 seconds |
| Started | Aug 23 07:15:42 PM UTC 24 |
| Finished | Aug 23 07:15:46 PM UTC 24 |
| Peak memory | 226428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026221565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2026221565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_direct_to_disabled.561976694 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 1221345200 ps |
| CPU time | 6.97 seconds |
| Started | Aug 23 07:15:38 PM UTC 24 |
| Finished | Aug 23 07:15:47 PM UTC 24 |
| Peak memory | 217908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=561976694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.561976694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_hwsw_invalid_input.114584787 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 515172172 ps |
| CPU time | 3.38 seconds |
| Started | Aug 23 07:15:41 PM UTC 24 |
| Finished | Aug 23 07:15:45 PM UTC 24 |
| Peak memory | 226112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114584787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.114584787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_kmac_rsp_err.662241896 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 127640664 ps |
| CPU time | 3.16 seconds |
| Started | Aug 23 07:15:42 PM UTC 24 |
| Finished | Aug 23 07:15:46 PM UTC 24 |
| Peak memory | 230800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662241896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.662241896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_lc_disable.3736469063 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 616145882 ps |
| CPU time | 4.13 seconds |
| Started | Aug 23 07:15:38 PM UTC 24 |
| Finished | Aug 23 07:15:44 PM UTC 24 |
| Peak memory | 217976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736469063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3736469063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_random.1393655079 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 1107680185 ps |
| CPU time | 9.6 seconds |
| Started | Aug 23 07:15:37 PM UTC 24 |
| Finished | Aug 23 07:15:48 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393655079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1393655079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_sideload.3083191222 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 600391213 ps |
| CPU time | 13.55 seconds |
| Started | Aug 23 07:15:34 PM UTC 24 |
| Finished | Aug 23 07:15:49 PM UTC 24 |
| Peak memory | 217900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083191222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3083191222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_aes.2466040681 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 120727376 ps |
| CPU time | 4.13 seconds |
| Started | Aug 23 07:15:36 PM UTC 24 |
| Finished | Aug 23 07:15:41 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466040681 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2466040681 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_kmac.1130670421 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 76465972 ps |
| CPU time | 2.99 seconds |
| Started | Aug 23 07:15:36 PM UTC 24 |
| Finished | Aug 23 07:15:40 PM UTC 24 |
| Peak memory | 218164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130670421 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1130670421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_otbn.1100561577 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 73953113 ps |
| CPU time | 1.95 seconds |
| Started | Aug 23 07:15:36 PM UTC 24 |
| Finished | Aug 23 07:15:39 PM UTC 24 |
| Peak memory | 215612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100561577 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1100561577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_sideload_protect.4046934633 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 332178197 ps |
| CPU time | 2.69 seconds |
| Started | Aug 23 07:15:45 PM UTC 24 |
| Finished | Aug 23 07:15:48 PM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046934633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.4046934633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_smoke.3774402772 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 80906061 ps |
| CPU time | 2.17 seconds |
| Started | Aug 23 07:15:34 PM UTC 24 |
| Finished | Aug 23 07:15:38 PM UTC 24 |
| Peak memory | 217896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774402772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3774402772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_stress_all_with_rand_reset.3031338832 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 380218459 ps |
| CPU time | 10.56 seconds |
| Started | Aug 23 07:15:46 PM UTC 24 |
| Finished | Aug 23 07:15:58 PM UTC 24 |
| Peak memory | 230836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3031338832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymg r_stress_all_with_rand_reset.3031338832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_sw_invalid_input.1739375308 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 574937492 ps |
| CPU time | 3.33 seconds |
| Started | Aug 23 07:15:40 PM UTC 24 |
| Finished | Aug 23 07:15:44 PM UTC 24 |
| Peak memory | 228212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739375308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1739375308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/47.keymgr_sync_async_fault_cross.1119621333 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 272448708 ps |
| CPU time | 1.42 seconds |
| Started | Aug 23 07:15:45 PM UTC 24 |
| Finished | Aug 23 07:15:47 PM UTC 24 |
| Peak memory | 217604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119621333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1119621333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/47.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_alert_test.3857664590 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 27999264 ps |
| CPU time | 0.71 seconds |
| Started | Aug 23 07:15:59 PM UTC 24 |
| Finished | Aug 23 07:16:01 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857664590 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3857664590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_cfg_regwen.2727330178 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 105110913 ps |
| CPU time | 3.12 seconds |
| Started | Aug 23 07:15:51 PM UTC 24 |
| Finished | Aug 23 07:15:55 PM UTC 24 |
| Peak memory | 226096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727330178 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2727330178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_custom_cm.2510958434 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 126865017 ps |
| CPU time | 3.02 seconds |
| Started | Aug 23 07:15:56 PM UTC 24 |
| Finished | Aug 23 07:16:00 PM UTC 24 |
| Peak memory | 232792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510958434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2510958434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_direct_to_disabled.2184611976 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 82485522 ps |
| CPU time | 1.53 seconds |
| Started | Aug 23 07:15:52 PM UTC 24 |
| Finished | Aug 23 07:15:54 PM UTC 24 |
| Peak memory | 217812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184611976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2184611976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_hwsw_invalid_input.2692436334 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 18581199418 ps |
| CPU time | 54.8 seconds |
| Started | Aug 23 07:15:55 PM UTC 24 |
| Finished | Aug 23 07:16:51 PM UTC 24 |
| Peak memory | 224088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692436334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.2692436334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_kmac_rsp_err.3343196957 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 237664911 ps |
| CPU time | 4.15 seconds |
| Started | Aug 23 07:15:55 PM UTC 24 |
| Finished | Aug 23 07:16:00 PM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343196957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3343196957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_lc_disable.3359374128 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 37769797 ps |
| CPU time | 1.88 seconds |
| Started | Aug 23 07:15:53 PM UTC 24 |
| Finished | Aug 23 07:15:56 PM UTC 24 |
| Peak memory | 213604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359374128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3359374128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_random.738153632 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 1321029109 ps |
| CPU time | 4.88 seconds |
| Started | Aug 23 07:15:51 PM UTC 24 |
| Finished | Aug 23 07:15:57 PM UTC 24 |
| Peak memory | 217960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738153632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.738153632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_sideload.1353318503 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 615058329 ps |
| CPU time | 4.48 seconds |
| Started | Aug 23 07:15:48 PM UTC 24 |
| Finished | Aug 23 07:15:53 PM UTC 24 |
| Peak memory | 215840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1353318503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1353318503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_aes.859984479 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 584890948 ps |
| CPU time | 2.79 seconds |
| Started | Aug 23 07:15:49 PM UTC 24 |
| Finished | Aug 23 07:15:53 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859984479 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.859984479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_kmac.2736075534 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 2572262366 ps |
| CPU time | 4.63 seconds |
| Started | Aug 23 07:15:48 PM UTC 24 |
| Finished | Aug 23 07:15:54 PM UTC 24 |
| Peak memory | 218112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2736075534 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2736075534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_otbn.3737792303 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 693175001 ps |
| CPU time | 6.72 seconds |
| Started | Aug 23 07:15:49 PM UTC 24 |
| Finished | Aug 23 07:15:57 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737792303 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3737792303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_sideload_protect.2168604944 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 22656450 ps |
| CPU time | 1.5 seconds |
| Started | Aug 23 07:15:56 PM UTC 24 |
| Finished | Aug 23 07:15:59 PM UTC 24 |
| Peak memory | 215644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168604944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2168604944 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_smoke.1437792115 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 165641632 ps |
| CPU time | 3.43 seconds |
| Started | Aug 23 07:15:48 PM UTC 24 |
| Finished | Aug 23 07:15:52 PM UTC 24 |
| Peak memory | 215776 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437792115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.1437792115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_stress_all.1607754204 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 1890247263 ps |
| CPU time | 7.27 seconds |
| Started | Aug 23 07:15:57 PM UTC 24 |
| Finished | Aug 23 07:16:06 PM UTC 24 |
| Peak memory | 228488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607754204 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1607754204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_sw_invalid_input.2336758840 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 1803233354 ps |
| CPU time | 39 seconds |
| Started | Aug 23 07:15:55 PM UTC 24 |
| Finished | Aug 23 07:16:35 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336758840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2336758840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/48.keymgr_sync_async_fault_cross.1686223725 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 97211760 ps |
| CPU time | 2.37 seconds |
| Started | Aug 23 07:15:57 PM UTC 24 |
| Finished | Aug 23 07:16:01 PM UTC 24 |
| Peak memory | 217956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686223725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1686223725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/48.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_alert_test.1262461678 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 48049627 ps |
| CPU time | 0.85 seconds |
| Started | Aug 23 07:16:17 PM UTC 24 |
| Finished | Aug 23 07:16:19 PM UTC 24 |
| Peak memory | 213600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1262461678 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1262461678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_custom_cm.334999507 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 106394083 ps |
| CPU time | 4.26 seconds |
| Started | Aug 23 07:16:12 PM UTC 24 |
| Finished | Aug 23 07:16:17 PM UTC 24 |
| Peak memory | 231884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334999507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.334999507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_direct_to_disabled.2936322784 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 216068492 ps |
| CPU time | 2.26 seconds |
| Started | Aug 23 07:16:07 PM UTC 24 |
| Finished | Aug 23 07:16:10 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936322784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2936322784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_hwsw_invalid_input.3373386257 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 234346753 ps |
| CPU time | 3.19 seconds |
| Started | Aug 23 07:16:08 PM UTC 24 |
| Finished | Aug 23 07:16:12 PM UTC 24 |
| Peak memory | 224104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373386257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3373386257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_kmac_rsp_err.2482831083 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 273647888 ps |
| CPU time | 2.12 seconds |
| Started | Aug 23 07:16:10 PM UTC 24 |
| Finished | Aug 23 07:16:13 PM UTC 24 |
| Peak memory | 226020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482831083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2482831083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_lc_disable.2186087609 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 284015249 ps |
| CPU time | 2.71 seconds |
| Started | Aug 23 07:16:07 PM UTC 24 |
| Finished | Aug 23 07:16:11 PM UTC 24 |
| Peak memory | 232156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2186087609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2186087609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_random.1710972251 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 95042839 ps |
| CPU time | 3.86 seconds |
| Started | Aug 23 07:16:04 PM UTC 24 |
| Finished | Aug 23 07:16:09 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710972251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1710972251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_sideload.1234398677 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 1165354460 ps |
| CPU time | 19.17 seconds |
| Started | Aug 23 07:16:02 PM UTC 24 |
| Finished | Aug 23 07:16:22 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234398677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1234398677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_aes.2039860767 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 159751564 ps |
| CPU time | 4.32 seconds |
| Started | Aug 23 07:16:02 PM UTC 24 |
| Finished | Aug 23 07:16:07 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039860767 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2039860767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_kmac.2924884612 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 993972376 ps |
| CPU time | 27.56 seconds |
| Started | Aug 23 07:16:02 PM UTC 24 |
| Finished | Aug 23 07:16:31 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924884612 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2924884612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_otbn.310422404 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 413663156 ps |
| CPU time | 3.09 seconds |
| Started | Aug 23 07:16:02 PM UTC 24 |
| Finished | Aug 23 07:16:06 PM UTC 24 |
| Peak memory | 215904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310422404 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.310422404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_sideload_protect.1030420396 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 160728164 ps |
| CPU time | 2.54 seconds |
| Started | Aug 23 07:16:12 PM UTC 24 |
| Finished | Aug 23 07:16:15 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030420396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1030420396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_smoke.3863686079 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 45174555 ps |
| CPU time | 2.29 seconds |
| Started | Aug 23 07:16:00 PM UTC 24 |
| Finished | Aug 23 07:16:03 PM UTC 24 |
| Peak memory | 217860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863686079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3863686079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all.2185968639 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 116366661 ps |
| CPU time | 2.91 seconds |
| Started | Aug 23 07:16:14 PM UTC 24 |
| Finished | Aug 23 07:16:18 PM UTC 24 |
| Peak memory | 224024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185968639 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2185968639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_stress_all_with_rand_reset.102586674 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 1162368582 ps |
| CPU time | 13.2 seconds |
| Started | Aug 23 07:16:17 PM UTC 24 |
| Finished | Aug 23 07:16:31 PM UTC 24 |
| Peak memory | 232644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=102586674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr _stress_all_with_rand_reset.102586674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_sw_invalid_input.1488101567 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 640216133 ps |
| CPU time | 7.32 seconds |
| Started | Aug 23 07:16:07 PM UTC 24 |
| Finished | Aug 23 07:16:15 PM UTC 24 |
| Peak memory | 218304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488101567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1488101567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/49.keymgr_sync_async_fault_cross.1927845772 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 269615912 ps |
| CPU time | 1.23 seconds |
| Started | Aug 23 07:16:13 PM UTC 24 |
| Finished | Aug 23 07:16:15 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1927845772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1927845772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/49.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_alert_test.139496049 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 46125364 ps |
| CPU time | 0.77 seconds |
| Started | Aug 23 07:04:09 PM UTC 24 |
| Finished | Aug 23 07:04:11 PM UTC 24 |
| Peak memory | 214168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139496049 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.139496049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_cfg_regwen.3271477808 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 57581782 ps |
| CPU time | 3.48 seconds |
| Started | Aug 23 07:04:00 PM UTC 24 |
| Finished | Aug 23 07:04:04 PM UTC 24 |
| Peak memory | 226160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271477808 -assert nopostproc +UVM_TESTNAME=keymgr_base_te st +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/ke ymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3271477808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_direct_to_disabled.456915824 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 59941601 ps |
| CPU time | 1.69 seconds |
| Started | Aug 23 07:04:01 PM UTC 24 |
| Finished | Aug 23 07:04:03 PM UTC 24 |
| Peak memory | 215708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456915824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.456915824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_hwsw_invalid_input.1383262045 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 78716098 ps |
| CPU time | 1.45 seconds |
| Started | Aug 23 07:04:03 PM UTC 24 |
| Finished | Aug 23 07:04:06 PM UTC 24 |
| Peak memory | 223580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383262045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1383262045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_kmac_rsp_err.4013187554 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 590825769 ps |
| CPU time | 3.38 seconds |
| Started | Aug 23 07:04:03 PM UTC 24 |
| Finished | Aug 23 07:04:08 PM UTC 24 |
| Peak memory | 224044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013187554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4013187554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_lc_disable.1033342057 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 324203505 ps |
| CPU time | 3.5 seconds |
| Started | Aug 23 07:04:01 PM UTC 24 |
| Finished | Aug 23 07:04:05 PM UTC 24 |
| Peak memory | 217864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033342057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1033342057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_random.508988669 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 5535031780 ps |
| CPU time | 27.59 seconds |
| Started | Aug 23 07:03:59 PM UTC 24 |
| Finished | Aug 23 07:04:28 PM UTC 24 |
| Peak memory | 218280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508988669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.508988669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_sideload.705322025 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 67636130 ps |
| CPU time | 2.74 seconds |
| Started | Aug 23 07:03:54 PM UTC 24 |
| Finished | Aug 23 07:03:58 PM UTC 24 |
| Peak memory | 215828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705322025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.705322025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_kmac.2470794148 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 61081203 ps |
| CPU time | 2.68 seconds |
| Started | Aug 23 07:03:55 PM UTC 24 |
| Finished | Aug 23 07:03:59 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470794148 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2470794148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_otbn.3123482814 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 178145541 ps |
| CPU time | 3.59 seconds |
| Started | Aug 23 07:03:57 PM UTC 24 |
| Finished | Aug 23 07:04:02 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123482814 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3123482814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_sideload_protect.1031948263 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 1107616172 ps |
| CPU time | 6.61 seconds |
| Started | Aug 23 07:04:05 PM UTC 24 |
| Finished | Aug 23 07:04:13 PM UTC 24 |
| Peak memory | 217936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031948263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1031948263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_smoke.1157875427 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 117104509 ps |
| CPU time | 1.6 seconds |
| Started | Aug 23 07:03:54 PM UTC 24 |
| Finished | Aug 23 07:03:57 PM UTC 24 |
| Peak memory | 215712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157875427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1157875427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_stress_all.2089149400 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 400437690 ps |
| CPU time | 8.75 seconds |
| Started | Aug 23 07:04:06 PM UTC 24 |
| Finished | Aug 23 07:04:16 PM UTC 24 |
| Peak memory | 228124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089149400 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2089149400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_sw_invalid_input.2208916521 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 335064305 ps |
| CPU time | 5.89 seconds |
| Started | Aug 23 07:04:01 PM UTC 24 |
| Finished | Aug 23 07:04:08 PM UTC 24 |
| Peak memory | 226224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208916521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2208916521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/5.keymgr_sync_async_fault_cross.3157612151 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 178463492 ps |
| CPU time | 1.99 seconds |
| Started | Aug 23 07:04:06 PM UTC 24 |
| Finished | Aug 23 07:04:09 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157612151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3157612151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/5.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_alert_test.3034337458 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 26066669 ps |
| CPU time | 0.64 seconds |
| Started | Aug 23 07:04:26 PM UTC 24 |
| Finished | Aug 23 07:04:28 PM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034337458 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3034337458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_direct_to_disabled.1407139668 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 113435482 ps |
| CPU time | 2.93 seconds |
| Started | Aug 23 07:04:17 PM UTC 24 |
| Finished | Aug 23 07:04:21 PM UTC 24 |
| Peak memory | 228120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407139668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1407139668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_hwsw_invalid_input.1420659124 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 31798436 ps |
| CPU time | 1.76 seconds |
| Started | Aug 23 07:04:20 PM UTC 24 |
| Finished | Aug 23 07:04:23 PM UTC 24 |
| Peak memory | 223616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420659124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.1420659124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_kmac_rsp_err.510124287 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 111722795 ps |
| CPU time | 2.17 seconds |
| Started | Aug 23 07:04:21 PM UTC 24 |
| Finished | Aug 23 07:04:24 PM UTC 24 |
| Peak memory | 217924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510124287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/c overage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.510124287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_lc_disable.1079605720 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 114931369 ps |
| CPU time | 2.56 seconds |
| Started | Aug 23 07:04:18 PM UTC 24 |
| Finished | Aug 23 07:04:21 PM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079605720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1079605720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_random.1154752826 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 646546622 ps |
| CPU time | 6.71 seconds |
| Started | Aug 23 07:04:15 PM UTC 24 |
| Finished | Aug 23 07:04:24 PM UTC 24 |
| Peak memory | 228196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154752826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1154752826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_sideload.3548233052 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 47567616 ps |
| CPU time | 2.31 seconds |
| Started | Aug 23 07:04:10 PM UTC 24 |
| Finished | Aug 23 07:04:14 PM UTC 24 |
| Peak memory | 218216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548233052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3548233052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_aes.2447920349 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 129150013 ps |
| CPU time | 2.89 seconds |
| Started | Aug 23 07:04:14 PM UTC 24 |
| Finished | Aug 23 07:04:18 PM UTC 24 |
| Peak memory | 217884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447920349 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.2447920349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_kmac.3992254792 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 262400626 ps |
| CPU time | 2.25 seconds |
| Started | Aug 23 07:04:12 PM UTC 24 |
| Finished | Aug 23 07:04:16 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992254792 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3992254792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_otbn.3829424635 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 2823109119 ps |
| CPU time | 15.19 seconds |
| Started | Aug 23 07:04:14 PM UTC 24 |
| Finished | Aug 23 07:04:31 PM UTC 24 |
| Peak memory | 217944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829424635 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3829424635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_sideload_protect.4014556314 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 81970815 ps |
| CPU time | 2.49 seconds |
| Started | Aug 23 07:04:23 PM UTC 24 |
| Finished | Aug 23 07:04:27 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4014556314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.4014556314 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_smoke.203176058 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 249171050 ps |
| CPU time | 4.25 seconds |
| Started | Aug 23 07:04:09 PM UTC 24 |
| Finished | Aug 23 07:04:15 PM UTC 24 |
| Peak memory | 217820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203176058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.203176058 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all.3727360809 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 7179438002 ps |
| CPU time | 40.06 seconds |
| Started | Aug 23 07:04:24 PM UTC 24 |
| Finished | Aug 23 07:05:06 PM UTC 24 |
| Peak memory | 226468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3727360809 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3727360809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_stress_all_with_rand_reset.203333938 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 186523412 ps |
| CPU time | 6.77 seconds |
| Started | Aug 23 07:04:25 PM UTC 24 |
| Finished | Aug 23 07:04:33 PM UTC 24 |
| Peak memory | 232488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =keymgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=203333938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_ stress_all_with_rand_reset.203333938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_sw_invalid_input.111101017 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 101079034 ps |
| CPU time | 3.74 seconds |
| Started | Aug 23 07:04:19 PM UTC 24 |
| Finished | Aug 23 07:04:24 PM UTC 24 |
| Peak memory | 217952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111101017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.111101017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/6.keymgr_sync_async_fault_cross.4041113904 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 799595797 ps |
| CPU time | 2.25 seconds |
| Started | Aug 23 07:04:24 PM UTC 24 |
| Finished | Aug 23 07:04:28 PM UTC 24 |
| Peak memory | 218048 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041113904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4041113904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/6.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_alert_test.4002450737 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 11009061 ps |
| CPU time | 0.78 seconds |
| Started | Aug 23 07:04:41 PM UTC 24 |
| Finished | Aug 23 07:04:43 PM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002450737 -assert nopostproc +UVM_TESTNAME=key mgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.4002450737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_direct_to_disabled.3381317251 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 2311423696 ps |
| CPU time | 18.97 seconds |
| Started | Aug 23 07:04:32 PM UTC 24 |
| Finished | Aug 23 07:04:52 PM UTC 24 |
| Peak memory | 217944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381317251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3381317251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_hwsw_invalid_input.2979736635 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 186702327 ps |
| CPU time | 4.3 seconds |
| Started | Aug 23 07:04:34 PM UTC 24 |
| Finished | Aug 23 07:04:39 PM UTC 24 |
| Peak memory | 230704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979736635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2979736635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_kmac_rsp_err.3778653615 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 506996729 ps |
| CPU time | 4.81 seconds |
| Started | Aug 23 07:04:35 PM UTC 24 |
| Finished | Aug 23 07:04:41 PM UTC 24 |
| Peak memory | 219948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778653615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3778653615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_lc_disable.2234102318 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 38081137 ps |
| CPU time | 1.69 seconds |
| Started | Aug 23 07:04:33 PM UTC 24 |
| Finished | Aug 23 07:04:36 PM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234102318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2234102318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_random.1757986635 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 130213858 ps |
| CPU time | 4.24 seconds |
| Started | Aug 23 07:04:32 PM UTC 24 |
| Finished | Aug 23 07:04:37 PM UTC 24 |
| Peak memory | 217920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757986635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1757986635 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_sideload.667722194 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 154827872 ps |
| CPU time | 4.45 seconds |
| Started | Aug 23 07:04:27 PM UTC 24 |
| Finished | Aug 23 07:04:33 PM UTC 24 |
| Peak memory | 218208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667722194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.667722194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_aes.1140248982 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 48034784 ps |
| CPU time | 2.27 seconds |
| Started | Aug 23 07:04:28 PM UTC 24 |
| Finished | Aug 23 07:04:32 PM UTC 24 |
| Peak memory | 215908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140248982 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1140248982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_kmac.3577525708 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 215912131 ps |
| CPU time | 4.53 seconds |
| Started | Aug 23 07:04:28 PM UTC 24 |
| Finished | Aug 23 07:04:34 PM UTC 24 |
| Peak memory | 218248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577525708 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3577525708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_otbn.1633647575 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 2535706803 ps |
| CPU time | 10.19 seconds |
| Started | Aug 23 07:04:30 PM UTC 24 |
| Finished | Aug 23 07:04:41 PM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1633647575 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1633647575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_sideload_protect.382565899 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 58953071 ps |
| CPU time | 2.23 seconds |
| Started | Aug 23 07:04:38 PM UTC 24 |
| Finished | Aug 23 07:04:42 PM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382565899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.382565899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_smoke.1763820098 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 50122424 ps |
| CPU time | 1.96 seconds |
| Started | Aug 23 07:04:27 PM UTC 24 |
| Finished | Aug 23 07:04:31 PM UTC 24 |
| Peak memory | 214180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763820098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1763820098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_stress_all.1269178041 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 3992280193 ps |
| CPU time | 38.5 seconds |
| Started | Aug 23 07:04:41 PM UTC 24 |
| Finished | Aug 23 07:05:21 PM UTC 24 |
| Peak memory | 232572 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269178041 -assert nopostproc +UVM_TESTNAME= keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1269178041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_sw_invalid_input.2502680849 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 260343803 ps |
| CPU time | 4.98 seconds |
| Started | Aug 23 07:04:34 PM UTC 24 |
| Finished | Aug 23 07:04:40 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502680849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2502680849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/7.keymgr_sync_async_fault_cross.3049006699 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 41338975 ps |
| CPU time | 1.68 seconds |
| Started | Aug 23 07:04:40 PM UTC 24 |
| Finished | Aug 23 07:04:43 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049006699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3049006699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/7.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_alert_test.14529674 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 13929539 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 07:04:53 PM UTC 24 |
| Finished | Aug 23 07:04:55 PM UTC 24 |
| Peak memory | 214232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14529674 -assert nopostproc +UVM_TESTNAME=keymg r_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.14529674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_cfg_regwen.41839580 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 88629015 ps |
| CPU time | 2.36 seconds |
| Started | Aug 23 07:04:45 PM UTC 24 |
| Finished | Aug 23 07:04:48 PM UTC 24 |
| Peak memory | 224420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41839580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keym gr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.41839580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_custom_cm.1500127141 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 261517053 ps |
| CPU time | 3.06 seconds |
| Started | Aug 23 07:04:49 PM UTC 24 |
| Finished | Aug 23 07:04:53 PM UTC 24 |
| Peak memory | 218448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500127141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cov erage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1500127141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_direct_to_disabled.310904486 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 55012407 ps |
| CPU time | 2.45 seconds |
| Started | Aug 23 07:04:45 PM UTC 24 |
| Finished | Aug 23 07:04:48 PM UTC 24 |
| Peak memory | 217888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310904486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.310904486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_hwsw_invalid_input.2472440431 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 187624684 ps |
| CPU time | 2.46 seconds |
| Started | Aug 23 07:04:48 PM UTC 24 |
| Finished | Aug 23 07:04:52 PM UTC 24 |
| Peak memory | 224100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472440431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2472440431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_kmac_rsp_err.2928791433 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 35429669 ps |
| CPU time | 1.83 seconds |
| Started | Aug 23 07:04:49 PM UTC 24 |
| Finished | Aug 23 07:04:52 PM UTC 24 |
| Peak memory | 224480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928791433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2928791433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_lc_disable.27244834 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 418772225 ps |
| CPU time | 2.6 seconds |
| Started | Aug 23 07:04:47 PM UTC 24 |
| Finished | Aug 23 07:04:51 PM UTC 24 |
| Peak memory | 230316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27244834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ= keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.27244834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_random.1770464971 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 41765318 ps |
| CPU time | 2.51 seconds |
| Started | Aug 23 07:04:44 PM UTC 24 |
| Finished | Aug 23 07:04:47 PM UTC 24 |
| Peak memory | 218276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1770464971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1770464971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_sideload.3568478957 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 124878381 ps |
| CPU time | 1.71 seconds |
| Started | Aug 23 07:04:42 PM UTC 24 |
| Finished | Aug 23 07:04:44 PM UTC 24 |
| Peak memory | 217692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568478957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3568478957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_aes.278464520 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3593090354 ps |
| CPU time | 19.84 seconds |
| Started | Aug 23 07:04:43 PM UTC 24 |
| Finished | Aug 23 07:05:04 PM UTC 24 |
| Peak memory | 215912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278464520 -assert nopostproc +UVM_TESTNAME=keymgr_base _test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.278464520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_kmac.928203036 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 118010680 ps |
| CPU time | 2.79 seconds |
| Started | Aug 23 07:04:43 PM UTC 24 |
| Finished | Aug 23 07:04:46 PM UTC 24 |
| Peak memory | 217516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928203036 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.928203036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_otbn.2166799655 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 65336196 ps |
| CPU time | 2.15 seconds |
| Started | Aug 23 07:04:44 PM UTC 24 |
| Finished | Aug 23 07:04:47 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166799655 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2166799655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_sideload_protect.3087085628 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 864338116 ps |
| CPU time | 7.32 seconds |
| Started | Aug 23 07:04:51 PM UTC 24 |
| Finished | Aug 23 07:05:00 PM UTC 24 |
| Peak memory | 218020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087085628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3087085628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_smoke.1540378856 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 303709554 ps |
| CPU time | 1.89 seconds |
| Started | Aug 23 07:04:41 PM UTC 24 |
| Finished | Aug 23 07:04:44 PM UTC 24 |
| Peak memory | 216228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540378856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverag e/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1540378856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_sw_invalid_input.2588594556 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 336502526 ps |
| CPU time | 3.67 seconds |
| Started | Aug 23 07:04:48 PM UTC 24 |
| Finished | Aug 23 07:04:53 PM UTC 24 |
| Peak memory | 215836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588594556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2588594556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/8.keymgr_sync_async_fault_cross.1280112998 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 74030663 ps |
| CPU time | 1.48 seconds |
| Started | Aug 23 07:04:52 PM UTC 24 |
| Finished | Aug 23 07:04:55 PM UTC 24 |
| Peak memory | 217644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280112998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1280112998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/8.keymgr_sync_async_fault_cross/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_alert_test.757112813 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 198959519 ps |
| CPU time | 0.69 seconds |
| Started | Aug 23 07:05:13 PM UTC 24 |
| Finished | Aug 23 07:05:14 PM UTC 24 |
| Peak memory | 213536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757112813 -assert nopostproc +UVM_TESTNAME=keym gr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08 _22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.757112813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_cfg_regwen.130641402 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 51865016 ps |
| CPU time | 3.2 seconds |
| Started | Aug 23 07:05:02 PM UTC 24 |
| Finished | Aug 23 07:05:06 PM UTC 24 |
| Peak memory | 226184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130641402 -assert nopostproc +UVM_TESTNAME=keymgr_base_tes t +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/key mgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.130641402 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_cfg_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_custom_cm.684694554 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 798433079 ps |
| CPU time | 16.58 seconds |
| Started | Aug 23 07:05:07 PM UTC 24 |
| Finished | Aug 23 07:05:25 PM UTC 24 |
| Peak memory | 224368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684694554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cove rage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.684694554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_custom_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_direct_to_disabled.3646716989 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 57478685 ps |
| CPU time | 1.88 seconds |
| Started | Aug 23 07:05:03 PM UTC 24 |
| Finished | Aug 23 07:05:06 PM UTC 24 |
| Peak memory | 217688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646716989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_direct_to_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3646716989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_direct_to_disabled/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_hwsw_invalid_input.1399922368 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 376664830 ps |
| CPU time | 4.11 seconds |
| Started | Aug 23 07:05:06 PM UTC 24 |
| Finished | Aug 23 07:05:11 PM UTC 24 |
| Peak memory | 231000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1399922368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1399922368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_hwsw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_kmac_rsp_err.2949269948 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 937816635 ps |
| CPU time | 5.86 seconds |
| Started | Aug 23 07:05:07 PM UTC 24 |
| Finished | Aug 23 07:05:14 PM UTC 24 |
| Peak memory | 224124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949269948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/ coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2949269948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_kmac_rsp_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_lc_disable.2353053483 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 91321314 ps |
| CPU time | 3.99 seconds |
| Started | Aug 23 07:05:04 PM UTC 24 |
| Finished | Aug 23 07:05:09 PM UTC 24 |
| Peak memory | 217988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353053483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/co verage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2353053483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_lc_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_random.2185834859 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 797800100 ps |
| CPU time | 4.87 seconds |
| Started | Aug 23 07:05:01 PM UTC 24 |
| Finished | Aug 23 07:05:07 PM UTC 24 |
| Peak memory | 224028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2185834859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/covera ge/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2185834859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_random/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_sideload.407629940 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3501161422 ps |
| CPU time | 5.08 seconds |
| Started | Aug 23 07:04:56 PM UTC 24 |
| Finished | Aug 23 07:05:02 PM UTC 24 |
| Peak memory | 218036 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=407629940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/cover age/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.407629940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_sideload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_aes.1242264438 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 239023134 ps |
| CPU time | 2.56 seconds |
| Started | Aug 23 07:04:58 PM UTC 24 |
| Finished | Aug 23 07:05:01 PM UTC 24 |
| Peak memory | 216164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242264438 -assert nopostproc +UVM_TESTNAME=keymgr_bas e_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1242264438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_sideload_aes/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_kmac.1072381572 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 24619270 ps |
| CPU time | 1.67 seconds |
| Started | Aug 23 07:04:56 PM UTC 24 |
| Finished | Aug 23 07:04:58 PM UTC 24 |
| Peak memory | 214172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072381572 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1072381572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_sideload_kmac/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_otbn.3278095500 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 1660131333 ps |
| CPU time | 49.06 seconds |
| Started | Aug 23 07:04:59 PM UTC 24 |
| Finished | Aug 23 07:05:49 PM UTC 24 |
| Peak memory | 217880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278095500 -assert nopostproc +UVM_TESTNAME=keymgr_ba se_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_08_22/keymgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3278095500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_sideload_otbn/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_sideload_protect.1183766185 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 476777211 ps |
| CPU time | 9.12 seconds |
| Started | Aug 23 07:05:07 PM UTC 24 |
| Finished | Aug 23 07:05:18 PM UTC 24 |
| Peak memory | 224212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183766185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sideload_protect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1183766185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_sideload_protect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_smoke.909825916 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 63230907 ps |
| CPU time | 1.47 seconds |
| Started | Aug 23 07:04:55 PM UTC 24 |
| Finished | Aug 23 07:04:57 PM UTC 24 |
| Peak memory | 215620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909825916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage /default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.909825916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_sw_invalid_input.324905922 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 1222973959 ps |
| CPU time | 7.08 seconds |
| Started | Aug 23 07:05:06 PM UTC 24 |
| Finished | Aug 23 07:05:14 PM UTC 24 |
| Peak memory | 218204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324905922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ =keymgr_sw_invalid_input_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.324905922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_sw_invalid_input/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/coverage/default/9.keymgr_sync_async_fault_cross.1429066656 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 91780562 ps |
| CPU time | 1.34 seconds |
| Started | Aug 23 07:05:07 PM UTC 24 |
| Finished | Aug 23 07:05:10 PM UTC 24 |
| Peak memory | 217632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429066656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE Q=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_22/keymg r-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1429066656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_22/keymgr-sim-vcs/9.keymgr_sync_async_fault_cross/latest |
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