Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
73.02	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

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Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	16	33	67.35

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	15	20	57.14	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	45	1			T70	1		T130	1		T121	1
auto[OpGenId]	21	1			T5	1		T30	1		T78	1
auto[OpGenSwOut]	20	1			T60	1		T109	1		T91	2
auto[OpGenHwOut]	11	1			T6	2		T7	1		T8	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1805	1			T65	3		T11	180		T12	180
auto[StInit]	67	1			T130	1		T78	1		T89	1
auto[StCreatorRootKey]	60	1			T5	1		T35	1		T60	1
auto[StOwnerIntKey]	46	1			T15	1		T69	1		T6	2
auto[StOwnerKey]	37	1			T90	1		T135	1		T136	1
auto[StDisabled]	463	1			T30	1		T65	2		T66	3
auto[StInvalid]	50	1			T16	1		T20	1		T77	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3510

1

T1

1

T2

1

T3

1

auto[1]

97

1

T5

1

T30

1

T60

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1796	1			T65	3		T11	180		T12	180
auto[StReset]	auto[1]	9	1			T70	1		T121	1		T139	1
auto[StInit]	auto[0]	32	1			T89	1		T90	1		T28	1
auto[StInit]	auto[1]	35	1			T130	1		T78	1		T7	1
auto[StCreatorRootKey]	auto[0]	38	1			T35	1		T36	1		T21	1
auto[StCreatorRootKey]	auto[1]	22	1			T5	1		T60	1		T106	1
auto[StOwnerIntKey]	auto[0]	35	1			T15	1		T69	1		T31	1
auto[StOwnerIntKey]	auto[1]	11	1			T6	2		T109	1		T111	1
auto[StOwnerKey]	auto[0]	30	1			T90	1		T135	1		T33	1
auto[StOwnerKey]	auto[1]	7	1			T136	1		T143	1		T222	1
auto[StDisabled]	auto[0]	450	1			T65	2		T66	3		T70	5
auto[StDisabled]	auto[1]	13	1			T30	1		T110	1		T93	1
auto[StInvalid]	auto[0]	50	1			T16	1		T20	1		T77	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	15	20	57.14	15

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	4
[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	3
[auto[StOwnerKey]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	9	1			T70	1		T121	1		T139	1
auto[StInit]	auto[OpAdvance]	12	1			T130	1		T68	1		T136	1
auto[StInit]	auto[OpGenId]	5	1			T78	1		T136	1		T195	1
auto[StInit]	auto[OpGenSwOut]	12	1			T91	2		T223	1		T224	1
auto[StInit]	auto[OpGenHwOut]	6	1			T7	1		T225	1		T202	1
auto[StCreatorRootKey]	auto[OpAdvance]	13	1			T106	1		T137	1		T92	1
auto[StCreatorRootKey]	auto[OpGenId]	6	1			T5	1		T226	1		T224	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T60	1		T227	1		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	1	1			T228	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T111	1		T229	1		T152	1
auto[StOwnerIntKey]	auto[OpGenId]	3	1			T230	1		T231	1		T10	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	1	1			T109	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	2	1			T6	2		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	3	1			T222	1		T152	1		T232	1
auto[StOwnerKey]	auto[OpGenId]	2	1			T136	1		T143	1		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T233	1		T234	1		-	-
auto[StDisabled]	auto[OpAdvance]	3	1			T110	1		T235	1		T236	1
auto[StDisabled]	auto[OpGenId]	5	1			T30	1		T123	1		T202	1
auto[StDisabled]	auto[OpGenSwOut]	3	1			T93	1		T237	1		T238	1
auto[StDisabled]	auto[OpGenHwOut]	2	1			T8	1		T232	1		-	-