Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4845

1

T1

5

T3

8

T14

3

auto[1]

566

1

T4

5

T18

2

T19

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4845

1

T1

5

T3

8

T14

3

auto[1]

566

1

T4

5

T18

2

T19

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4837

1

T1

2

T3

8

T14

3

auto[1]

574

1

T1

3

T18

2

T43

3

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4837

1

T1

2

T3

8

T14

3

auto[1]

574

1

T1

3

T18

2

T43

3

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	390	1			T16	1		T19	1		T82	1
auto[OpGenId]	1203	1			T1	2		T14	2		T15	1
auto[OpGenSwOut]	1152	1			T1	1		T5	1		T15	1
auto[OpGenHwOut]	2592	1			T1	2		T3	8		T14	1
auto[OpDisable]	74	1			T34	1		T66	1		T131	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	390	1			T16	1		T19	1		T82	1
auto[OpGenId]	1203	1			T1	2		T14	2		T15	1
auto[OpGenSwOut]	1152	1			T1	1		T5	1		T15	1
auto[OpGenHwOut]	2592	1			T1	2		T3	8		T14	1
auto[OpDisable]	74	1			T34	1		T66	1		T131	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4880

1

T1

3

T3

6

T14

3

auto[1]

531

1

T1

2

T3

2

T18

1

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4880

1

T1

3

T3

6

T14

3

auto[1]

531

1

T1

2

T3

2

T18

1

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5141

1

T1

5

T3

8

T14

3

auto[1]

270

1

T82

3

T83

5

T74

1

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1830	1			T1	1		T3	1		T14	1
auto[1]	714	1			T1	1		T4	1		T16	1
auto[2]	670	1			T1	1		T3	2		T4	1
auto[3]	742	1			T1	2		T3	5		T4	3
auto[4]	348	1			T16	1		T34	1		T88	1
auto[5]	399	1			T14	1		T4	1		T19	1
auto[6]	345	1			T17	1		T43	1		T88	2
auto[7]	363	1			T14	1		T16	1		T67	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1455	1			T14	2		T4	1		T16	2
clear_one[1]	714	1			T1	1		T4	1		T16	1
clear_one[2]	670	1			T1	1		T3	2		T4	1
clear_one[3]	742	1			T1	2		T3	5		T4	3
clear_none	1830	1			T1	1		T3	1		T14	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1038	1			T14	1		T15	2		T16	5
auto[StInit]	641	1			T1	1		T3	1		T4	1
auto[StCreatorRootKey]	590	1			T3	1		T4	1		T19	1
auto[StOwnerIntKey]	531	1			T3	1		T4	1		T17	1
auto[StOwnerKey]	461	1			T3	1		T4	1		T19	1
auto[StDisabled]	1892	1			T1	4		T3	4		T4	4
auto[StInvalid]	258	1			T14	2		T16	5		T20	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1038	1			T14	1		T15	2		T16	5
auto[StInit]	641	1			T1	1		T3	1		T4	1
auto[StCreatorRootKey]	590	1			T3	1		T4	1		T19	1
auto[StOwnerIntKey]	531	1			T3	1		T4	1		T17	1
auto[StOwnerKey]	461	1			T3	1		T4	1		T19	1
auto[StDisabled]	1892	1			T1	4		T3	4		T4	4
auto[StInvalid]	258	1			T14	2		T16	5		T20	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	57	223	79.64	57

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[1] - auto[5]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[1] - auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[1] - auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5
[auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpAdvance]]	--	--	2
[auto[6]]	[auto[StReset] , auto[StInit]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StCreatorRootKey] , auto[StOwnerIntKey]]	[auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StOwnerKey]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	5	1			T82	1		T112	1		T244	1
auto[0]	auto[StReset]	auto[OpGenId]	174	1			T15	1		T16	1		T34	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	147	1			T83	1		T20	2		T65	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	267	1			T14	1		T16	1		T88	2
auto[0]	auto[StInit]	auto[OpAdvance]	43	1			T69	1		T30	1		T51	1
auto[0]	auto[StInit]	auto[OpGenId]	84	1			T17	1		T19	1		T66	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	96	1			T1	1		T5	1		T65	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	174	1			T3	1		T4	1		T43	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T44	1		T108	1		T245	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	60	1			T82	1		T246	1		T216	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	55	1			T72	1		T70	1		T6	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	79	1			T159	1		T21	1		T6	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T208	1		T235	1		T123	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	33	1			T82	2		T51	1		T218	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	32	1			T74	1		T70	1		T105	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	59	1			T159	1		T76	1		T247	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T108	1		T248	1		T194	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	16	1			T102	1		T157	1		T122	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	26	1			T158	1		T70	1		T93	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T43	1		T97	1		T249	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	27	1			T107	1		T208	1		T248	1
auto[0]	auto[StDisabled]	auto[OpGenId]	55	1			T73	1		T52	1		T219	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	68	1			T102	1		T104	1		T157	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	151	1			T4	1		T18	1		T43	1
auto[0]	auto[StDisabled]	auto[OpDisable]	28	1			T66	1		T132	1		T133	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	12	1			T48	1		T250	1		T251	1
auto[0]	auto[StInvalid]	auto[OpGenId]	17	1			T45	1		T251	1		T46	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	25	1			T16	1		T252	1		T253	2
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T48	1		T253	1		T254	1
auto[1]	auto[StReset]	auto[OpGenId]	20	1			T255	1		T91	1		T235	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	20	1			T34	1		T108	1		T256	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	53	1			T67	1		T159	1		T20	1
auto[1]	auto[StInit]	auto[OpAdvance]	6	1			T33	1		T257	1		T258	1
auto[1]	auto[StInit]	auto[OpGenId]	17	1			T138	1		T65	1		T224	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	4	1			T235	1		T259	1		T260	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	19	1			T98	1		T261	1		T262	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T30	1		T263	1		T264	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T265	1		T215	1		T266	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	21	1			T73	1		T75	1		T133	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	36	1			T97	1		T37	1		T267	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T94	1		T264	1		T268	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T138	1		T269	1		T235	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	19	1			T65	1		T218	1		T270	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	38	1			T88	1		T97	1		T205	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T271	1		T199	1		T272	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	12	1			T92	1		T237	1		T273	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T274	1		T216	1		T264	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	31	1			T4	1		T88	1		T78	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	26	1			T157	1		T219	1		T215	1
auto[1]	auto[StDisabled]	auto[OpGenId]	68	1			T66	1		T154	1		T265	2
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	49	1			T65	1		T73	1		T255	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	165	1			T1	1		T88	1		T98	1
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T34	1		T6	1		T275	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	7	1			T46	1		T256	1		T276	1
auto[1]	auto[StInvalid]	auto[OpGenId]	9	1			T250	1		T251	1		T277	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T77	1		T278	1		T279	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	13	1			T16	1		T77	1		T280	1
auto[2]	auto[StReset]	auto[OpGenId]	18	1			T16	1		T77	1		T281	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	23	1			T73	1		T45	1		T255	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	43	1			T159	1		T130	1		T282	1
auto[2]	auto[StInit]	auto[OpAdvance]	6	1			T283	3		T284	1		T285	1
auto[2]	auto[StInit]	auto[OpGenId]	7	1			T131	1		T37	1		T286	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	13	1			T248	1		T287	1		T273	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	16	1			T209	1		T288	1		T289	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T210	1		T290	1		T291	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T70	1		T292	1		T208	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T293	1		T185	1		T186	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	33	1			T3	1		T43	1		T88	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T294	1		T295	1		T296	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T217	1		T208	1		T238	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	18	1			T297	1		T289	1		T230	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T3	1		T70	1		T156	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T298	1		T201	1		T299	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	8	1			T300	1		T301	1		T185	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T302	1		T303	1		T238	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T138	1		T6	1		T261	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	26	1			T304	1		T122	1		T218	1
auto[2]	auto[StDisabled]	auto[OpGenId]	59	1			T34	1		T19	1		T102	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T19	1		T66	1		T107	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	157	1			T1	1		T4	1		T43	2
auto[2]	auto[StDisabled]	auto[OpDisable]	7	1			T131	1		T6	1		T248	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	3	1			T279	1		T305	1		T306	1
auto[2]	auto[StInvalid]	auto[OpGenId]	12	1			T16	1		T20	1		T280	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T307	1		T256	1		T308	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T251	1		T309	2		T310	1
auto[3]	auto[StReset]	auto[OpGenId]	19	1			T16	1		T106	1		T218	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	26	1			T15	1		T20	1		T6	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	49	1			T159	1		T214	1		T70	1
auto[3]	auto[StInit]	auto[OpAdvance]	2	1			T222	1		T311	1		-	-
auto[3]	auto[StInit]	auto[OpGenId]	11	1			T73	1		T204	1		T191	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	12	1			T108	1		T211	1		T312	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	29	1			T282	1		T313	1		T92	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T218	1		T314	1		T315	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T6	1		T269	1		T92	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T154	1		T297	1		T22	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T4	1		T19	1		T67	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T316	1		T216	1		T211	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T6	1		T31	1		T266	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T214	1		T154	1		T248	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T4	1		T43	1		T267	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T317	1		T318	1		-	-
auto[3]	auto[StOwnerKey]	auto[OpGenId]	18	1			T319	1		T136	1		T320	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T65	1		T211	1		T91	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T3	1		T67	1		T51	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	17	1			T304	1		T321	1		T211	1
auto[3]	auto[StDisabled]	auto[OpGenId]	60	1			T1	2		T82	1		T83	2
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	44	1			T18	1		T70	1		T108	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	173	1			T3	4		T4	1		T159	2
auto[3]	auto[StDisabled]	auto[OpDisable]	10	1			T90	1		T134	1		T136	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	7	1			T48	1		T212	1		T308	1
auto[3]	auto[StInvalid]	auto[OpGenId]	14	1			T48	1		T307	1		T212	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T16	1		T250	1		T251	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T20	1		T277	1		T322	1
auto[4]	auto[StReset]	auto[OpGenId]	15	1			T312	1		T323	1		T224	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	11	1			T269	1		T93	1		T294	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	21	1			T76	1		T136	1		T324	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T238	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	8	1			T208	2		T319	1		T136	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	3	1			T34	1		T59	1		T325	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	16	1			T326	1		T324	1		T327	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T237	1		T148	1		T328	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T274	1		T329	1		T330	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T204	1		T6	2		T316	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	26	1			T98	1		T76	1		T331	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T332	1		T333	1		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T334	1		T201	1		T335	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T238	1		T149	1		T336	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T219	1		T337	1		T90	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T257	1		T39	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	11	1			T314	1		T338	1		T298	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	5	1			T339	1		T340	1		T341	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	26	1			T75	1		T156	1		T267	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	11	1			T218	1		T216	1		T342	1
auto[4]	auto[StDisabled]	auto[OpGenId]	24	1			T72	1		T218	1		T216	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T74	1		T75	1		T70	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	60	1			T88	1		T67	1		T159	1
auto[4]	auto[StDisabled]	auto[OpDisable]	10	1			T6	1		T235	1		T139	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	5	1			T16	1		T48	1		T276	1
auto[4]	auto[StInvalid]	auto[OpGenId]	7	1			T309	1		T49	1		T343	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T46	1		T344	1		T345	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T308	1		T278	1		T346	1
auto[5]	auto[StReset]	auto[OpGenId]	8	1			T112	1		T235	1		T308	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	12	1			T216	1		T92	1		T136	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	18	1			T216	1		T347	1		T348	1
auto[5]	auto[StInit]	auto[OpAdvance]	6	1			T60	1		T349	2		T350	2
auto[5]	auto[StInit]	auto[OpGenId]	6	1			T351	1		T38	1		T338	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	4	1			T352	1		T152	1		T291	2
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T88	1		T353	1		T354	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T69	1		T255	1		T355	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T351	1		T347	1		T356	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T238	1		T357	1		T333	2
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	21	1			T358	1		T359	1		T262	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T351	1		T188	1		T360	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	15	1			T246	1		T25	1		T108	2
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T104	1		T199	1		T361	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T362	1		T209	1		T249	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T19	1		T218	1		T363	2
auto[5]	auto[StOwnerKey]	auto[OpGenId]	9	1			T108	1		T364	1		T201	2
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T215	1		T108	1		T365	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	27	1			T74	2		T205	1		T154	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T78	1		T295	1		T328	1
auto[5]	auto[StDisabled]	auto[OpGenId]	36	1			T6	1		T25	1		T215	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	34	1			T158	1		T219	1		T294	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	98	1			T4	1		T97	1		T156	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T224	1		T366	1		T236	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	2	1			T367	1		T346	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	5	1			T14	1		T26	1		T368	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T77	1		T369	1		T370	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T280	1		T250	2		T343	1
auto[6]	auto[StReset]	auto[OpGenId]	8	1			T371	1		T248	1		T372	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	13	1			T70	1		T78	1		T136	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	25	1			T88	1		T159	1		T73	1
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T315	1		T199	1		T373	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	5	1			T295	1		T185	1		T374	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	17	1			T159	1		T359	1		T108	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T83	1		T65	1		T157	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T218	1		T95	1		T375	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T137	1		T299	1		T376	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T51	1		T377	1		T209	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T378	1		T248	1		T379	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T72	1		T356	1		T228	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T218	1		T22	1		T263	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	15	1			T17	1		T98	1		T70	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T99	1		T380	1		T379	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T83	3		T154	1		T381	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T331	1		T382	1		T383	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T378	1		T244	1		T264	1
auto[6]	auto[StDisabled]	auto[OpGenId]	31	1			T70	1		T216	1		T220	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T215	1		T235	1		T296	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T43	1		T88	1		T67	1
auto[6]	auto[StDisabled]	auto[OpDisable]	2	1			T384	1		T152	1		-	-
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T307	1		T277	1		T385	1
auto[6]	auto[StInvalid]	auto[OpGenId]	3	1			T47	1		T386	1		T387	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T47	1		T310	1		T388	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T322	1		T310	1		T367	1
auto[7]	auto[StReset]	auto[OpGenId]	18	1			T65	1		T218	1		T216	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	5	1			T16	1		T108	1		T389	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	20	1			T390	1		T391	1		T392	2
auto[7]	auto[StInit]	auto[OpAdvance]	1	1			T230	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenId]	4	1			T95	1		T393	1		T334	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	3	1			T148	1		T394	1		T239	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	8	1			T267	1		T241	1		T395	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	1	1			T396	1		-	-		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T219	1		T289	1		T397	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T136	1		T238	1		T398	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T214	1		T247	1		T270	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T136	1		T399	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T400	1		T94	1		T287	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T75	1		T157	1		T6	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T67	1		T261	1		T353	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T70	1		T92	1		T401	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	9	1			T219	1		T316	1		T59	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T266	1		T110	1		T99	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T159	1		T98	1		T76	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	16	1			T265	1		T107	1		T215	1
auto[7]	auto[StDisabled]	auto[OpGenId]	34	1			T51	1		T108	1		T112	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	28	1			T157	1		T218	1		T297	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	86	1			T159	1		T44	1		T76	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T402	1		T403	1		T153	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	5	1			T45	1		T276	1		T404	1
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T14	1		T241	1		T367	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T20	1		T45	2		T369	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T252	1		T309	1		T405	1