Unified Coverage Report :: Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

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Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1455

1

T14

2

T4

1

T16

2

clear_one[1]

auto[0]

auto[0]

auto[0]

407

1

T4

1

T16

1

T34

2

clear_one[1]

auto[0]

auto[0]

auto[1]

114

1

T73

1

T76

2

T6

1

clear_one[1]

auto[0]

auto[1]

auto[0]

139

1

T88

3

T98

1

T66

2

clear_one[1]

auto[0]

auto[1]

auto[1]

54

1

T1

1

T6

1

T255

1

clear_one[2]

auto[0]

auto[0]

auto[0]

385

1

T16

2

T19

2

T43

3

clear_one[2]

auto[0]

auto[0]

auto[1]

114

1

T1

1

T3

2

T34

1

clear_one[2]

auto[1]

auto[0]

auto[0]

128

1

T4

1

T67

2

T156

3

clear_one[2]

auto[1]

auto[0]

auto[1]

43

1

T102

2

T70

3

T216

1

clear_one[3]

auto[0]

auto[0]

auto[0]

432

1

T3

5

T15

1

T16

2

clear_one[3]

auto[0]

auto[1]

auto[0]

136

1

T1

2

T43

1

T82

1

clear_one[3]

auto[1]

auto[0]

auto[0]

139

1

T4

3

T19

1

T67

2

clear_one[3]

auto[1]

auto[1]

auto[0]

35

1

T18

1

T70

1

T265

1

clear_none

auto[0]

auto[0]

auto[0]

1329

1

T1

1

T3

1

T14

1

clear_none

auto[0]

auto[0]

auto[1]

124

1

T159

2

T73

1

T76

1

clear_none

auto[0]

auto[1]

auto[0]

123

1

T43

2

T82

3

T98

1

clear_none

auto[0]

auto[1]

auto[1]

33

1

T158

1

T78

1

T122

1

clear_none

auto[1]

auto[0]

auto[0]

141

1

T4

1

T97

2

T102

1

clear_none

auto[1]

auto[0]

auto[1]

26

1

T102

1

T70

1

T6

1

clear_none

auto[1]

auto[1]

auto[0]

31

1

T105

1

T219

1

T108

1

clear_none

auto[1]

auto[1]

auto[1]

23

1

T18

1

T269

1

T108

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1352	1			T14	2		T4	1		T16	2
clear_all	auto[1]	103	1			T83	3		T74	1		T107	1
clear_one[1]	auto[0]	679	1			T1	1		T4	1		T16	1
clear_one[1]	auto[1]	35	1			T269	2		T264	2		T349	4
clear_one[2]	auto[0]	637	1			T1	1		T3	2		T4	1
clear_one[2]	auto[1]	33	1			T122	2		T107	1		T208	2
clear_one[3]	auto[0]	716	1			T1	2		T3	5		T4	3
clear_one[3]	auto[1]	26	1			T82	1		T83	2		T112	1
clear_none	auto[0]	1757	1			T1	1		T3	1		T14	1
clear_none	auto[1]	73	1			T82	2		T122	3		T107	1