Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
38.68	1	100	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/keymgr-sim-vcs/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	1	19	95.00
Crosses	360	232	128	35.56

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	1	6	85.71	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	184	96	34.29	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11452

1

T1

3

T2

4

T3

3

auto[Attestation]

7726

1

T1

5

T2

4

T3

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2751	1			T2	2		T14	3		T15	3
auto[Aes]	3482	1			T2	1		T14	1		T4	8
auto[Kmac]	3471	1			T1	1		T2	1		T5	1
auto[Otbn]	3453	1			T1	3		T2	2		T3	8

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7694	1			T1	8		T2	8		T3	8
auto[OpGenId]	6021	1			T1	4		T2	2		T14	1
auto[OpGenSwOut]	5984	1			T1	1		T2	6		T14	3
auto[OpGenHwOut]	7173	1			T1	3		T3	8		T14	1
auto[OpDisable]	149	1			T34	1		T138	1		T72	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10941

1

T1

8

T2

8

T3

8

auto[OpDoneFail]

16080

1

T1

8

T2

8

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	1	6	85.71

Automatically Generated Bins for state_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[StInvalid]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6410	1			T1	1		T2	1		T3	1
auto[StInit]	3818	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3283	1			T1	2		T2	2		T3	2
auto[StOwnerIntKey]	2893	1			T1	2		T2	2		T3	2
auto[StOwnerKey]	2602	1			T1	2		T2	2		T3	2
auto[StDisabled]	8015	1			T1	7		T2	7		T3	7

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	184	96	34.29	184

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpGenSwOut] , auto[OpGenHwOut]]	*	*	[auto[StInvalid]]	--	--	16
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	302	1			T14	2		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	87	1			T70	1		T154	1		T157	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	78	1			T15	1		T35	1		T158	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	82	1			T19	1		T214	1		T75	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	66	1			T158	1		T6	1		T215	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	233	1			T2	1		T18	1		T19	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	322	1			T14	1		T16	1		T83	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	120	1			T5	1		T65	1		T66	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	101	1			T82	1		T70	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	73	1			T15	2		T70	1		T105	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	66	1			T2	1		T83	1		T70	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	227	1			T44	1		T65	1		T96	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	324	1			T15	1		T16	1		T20	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	117	1			T5	1		T66	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	76	1			T73	1		T21	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	67	1			T44	1		T65	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	55	1			T158	1		T83	1		T65	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	227	1			T19	1		T82	1		T73	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	343	1			T15	1		T34	1		T158	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	109	1			T15	1		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	106	1			T72	2		T70	2		T105	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	92	1			T30	1		T96	1		T70	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	75	1			T83	1		T96	1		T203	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	217	1			T18	1		T19	1		T158	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	75	1			T65	1		T6	6		T216	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	80	1			T17	1		T65	1		T70	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	92	1			T96	1		T51	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	90	1			T70	1		T105	1		T155	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	65	1			T44	1		T65	1		T154	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	209	1			T2	1		T65	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	64	1			T65	1		T66	2		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	106	1			T138	2		T20	1		T72	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	89	1			T66	2		T70	1		T203	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	69	1			T17	1		T154	1		T78	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	74	1			T83	1		T157	1		T217	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	228	1			T96	1		T102	1		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	73	1			T66	1		T6	1		T218	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	117	1			T158	1		T66	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T83	1		T72	1		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	83	1			T83	1		T157	1		T219	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	50	1			T74	1		T25	1		T219	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	204	1			T2	1		T19	3		T82	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	65	1			T65	4		T6	2		T216	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	80	1			T1	1		T82	2		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	87	1			T2	1		T17	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	68	1			T2	1		T74	1		T66	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	56	1			T65	1		T75	1		T154	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	216	1			T18	1		T34	1		T82	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	271	1			T14	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	104	1			T18	2		T74	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	88	1			T19	1		T83	1		T154	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T72	1		T75	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	47	1			T154	1		T220	1		T221	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	192	1			T138	1		T44	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	480	1			T16	2		T67	8		T20	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	118	1			T4	1		T97	1		T104	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	107	1			T4	1		T67	1		T156	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	94	1			T4	1		T17	1		T67	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	98	1			T4	1		T74	1		T156	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	277	1			T4	3		T18	1		T67	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	493	1			T16	2		T34	1		T88	7
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	123	1			T43	1		T138	1		T214	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	115	1			T88	1		T82	1		T98	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	107	1			T17	2		T88	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	115	1			T43	1		T88	1		T138	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	283	1			T18	2		T43	2		T88	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	461	1			T15	1		T16	5		T159	9
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	122	1			T159	1		T83	1		T66	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	108	1			T3	1		T18	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	95	1			T3	1		T17	1		T159	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	99	1			T44	2		T76	1		T70	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	281	1			T1	1		T3	1		T34	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	50	1			T66	1		T218	2		T216	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	76	1			T19	1		T65	1		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	87	1			T35	1		T36	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	65	1			T65	1		T66	1		T102	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T75	1		T51	2		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	192	1			T18	1		T66	1		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	50	1			T65	3		T216	1		T92	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	124	1			T19	1		T67	1		T156	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	104	1			T19	1		T214	1		T97	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	103	1			T69	1		T214	1		T70	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	89	1			T67	1		T97	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	299	1			T4	1		T67	2		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	57	1			T65	1		T66	1		T6	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	126	1			T88	1		T82	1		T102	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	109	1			T1	1		T18	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T43	1		T69	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	96	1			T82	1		T98	1		T74	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	285	1			T19	1		T43	2		T88	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	49	1			T65	2		T6	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	119	1			T3	1		T5	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	107	1			T159	1		T76	1		T36	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	106	1			T17	1		T18	1		T70	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	109	1			T3	1		T158	1		T159	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	283	1			T1	1		T3	3		T159	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	205	1			T15	1		T35	1		T158	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	643	1			T2	1		T14	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	218	1			T2	1		T15	2		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	691	1			T14	1		T5	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	175	1			T158	1		T83	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	691	1			T5	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	257	1			T83	1		T30	1		T96	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	685	1			T15	2		T17	1		T18	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	232	1			T44	1		T65	1		T96	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	379	1			T2	1		T17	1		T65	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	210	1			T17	1		T83	1		T66	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	420	1			T138	2		T20	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	190	1			T83	2		T72	1		T74	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	416	1			T2	1		T19	3		T158	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	199	1			T2	2		T17	1		T83	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	373	1			T1	1		T18	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	183	1			T19	1		T83	1		T72	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	588	1			T14	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	278	1			T4	3		T17	1		T67	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	896	1			T4	4		T16	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	316	1			T17	2		T43	1		T88	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	920	1			T16	2		T18	2		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	283	1			T3	2		T17	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	883	1			T1	1		T3	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	185	1			T35	1		T65	1		T66	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	336	1			T18	1		T19	1		T65	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	276	1			T19	1		T67	1		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	493	1			T4	1		T19	1		T67	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	281	1			T1	1		T18	1		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	482	1			T19	1		T43	2		T88	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	298	1			T3	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	475	1			T1	1		T3	4		T5	1