Unified Coverage Report :: Group Instance : attest_sw_binding_2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33028

1

T1

18

T2

21

T3

22

auto[1]

309

1

T82

10

T83

7

T74

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33035	1			T1	18		T2	21		T3	22
auto[134217728:268435455]	15	1			T82	1		T107	1		T269	1
auto[268435456:402653183]	14	1			T269	1		T255	1		T351	1
auto[402653184:536870911]	8	1			T82	1		T349	1		T268	1
auto[536870912:671088639]	10	1			T269	1		T263	1		T363	1
auto[671088640:805306367]	5	1			T105	1		T112	1		T379	1
auto[805306368:939524095]	6	1			T349	1		T298	1		T268	1
auto[939524096:1073741823]	6	1			T82	1		T424	1		T425	1
auto[1073741824:1207959551]	9	1			T107	1		T255	1		T112	1
auto[1207959552:1342177279]	4	1			T283	1		T426	1		T427	1
auto[1342177280:1476395007]	10	1			T82	1		T244	1		T296	1
auto[1476395008:1610612735]	15	1			T269	1		T112	1		T401	1
auto[1610612736:1744830463]	6	1			T374	1		T428	1		T429	2
auto[1744830464:1879048191]	12	1			T83	1		T74	1		T105	1
auto[1879048192:2013265919]	12	1			T107	1		T269	1		T401	1
auto[2013265920:2147483647]	11	1			T122	2		T269	1		T283	1
auto[2147483648:2281701375]	7	1			T269	1		T349	1		T283	1
auto[2281701376:2415919103]	15	1			T269	1		T268	2		T379	1
auto[2415919104:2550136831]	11	1			T269	1		T194	1		T283	1
auto[2550136832:2684354559]	11	1			T83	2		T269	1		T351	1
auto[2684354560:2818572287]	14	1			T83	1		T107	2		T269	1
auto[2818572288:2952790015]	11	1			T122	1		T269	1		T194	1
auto[2952790016:3087007743]	7	1			T82	1		T363	1		T283	1
auto[3087007744:3221225471]	9	1			T83	1		T122	1		T269	1
auto[3221225472:3355443199]	5	1			T82	1		T269	1		T430	1
auto[3355443200:3489660927]	6	1			T244	1		T431	1		T257	1
auto[3489660928:3623878655]	9	1			T83	1		T122	1		T255	1
auto[3623878656:3758096383]	10	1			T82	1		T83	1		T122	1
auto[3758096384:3892314111]	19	1			T269	1		T255	1		T244	1
auto[3892314112:4026531839]	8	1			T82	3		T244	1		T432	1
auto[4026531840:4160749567]	14	1			T255	1		T283	1		T379	1
auto[4160749568:4294967295]	3	1			T269	1		T268	1		T429	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33028	1			T1	18		T2	21		T3	22
auto[0:134217727]	auto[1]	7	1			T433	1		T349	1		T430	1
auto[134217728:268435455]	auto[1]	15	1			T82	1		T107	1		T269	1
auto[268435456:402653183]	auto[1]	14	1			T269	1		T255	1		T351	1
auto[402653184:536870911]	auto[1]	8	1			T82	1		T349	1		T268	1
auto[536870912:671088639]	auto[1]	10	1			T269	1		T263	1		T363	1
auto[671088640:805306367]	auto[1]	5	1			T105	1		T112	1		T379	1
auto[805306368:939524095]	auto[1]	6	1			T349	1		T298	1		T268	1
auto[939524096:1073741823]	auto[1]	6	1			T82	1		T424	1		T425	1
auto[1073741824:1207959551]	auto[1]	9	1			T107	1		T255	1		T112	1
auto[1207959552:1342177279]	auto[1]	4	1			T283	1		T426	1		T427	1
auto[1342177280:1476395007]	auto[1]	10	1			T82	1		T244	1		T296	1
auto[1476395008:1610612735]	auto[1]	15	1			T269	1		T112	1		T401	1
auto[1610612736:1744830463]	auto[1]	6	1			T374	1		T428	1		T429	2
auto[1744830464:1879048191]	auto[1]	12	1			T83	1		T74	1		T105	1
auto[1879048192:2013265919]	auto[1]	12	1			T107	1		T269	1		T401	1
auto[2013265920:2147483647]	auto[1]	11	1			T122	2		T269	1		T283	1
auto[2147483648:2281701375]	auto[1]	7	1			T269	1		T349	1		T283	1
auto[2281701376:2415919103]	auto[1]	15	1			T269	1		T268	2		T379	1
auto[2415919104:2550136831]	auto[1]	11	1			T269	1		T194	1		T283	1
auto[2550136832:2684354559]	auto[1]	11	1			T83	2		T269	1		T351	1
auto[2684354560:2818572287]	auto[1]	14	1			T83	1		T107	2		T269	1
auto[2818572288:2952790015]	auto[1]	11	1			T122	1		T269	1		T194	1
auto[2952790016:3087007743]	auto[1]	7	1			T82	1		T363	1		T283	1
auto[3087007744:3221225471]	auto[1]	9	1			T83	1		T122	1		T269	1
auto[3221225472:3355443199]	auto[1]	5	1			T82	1		T269	1		T430	1
auto[3355443200:3489660927]	auto[1]	6	1			T244	1		T431	1		T257	1
auto[3489660928:3623878655]	auto[1]	9	1			T83	1		T122	1		T255	1
auto[3623878656:3758096383]	auto[1]	10	1			T82	1		T83	1		T122	1
auto[3758096384:3892314111]	auto[1]	19	1			T269	1		T255	1		T244	1
auto[3892314112:4026531839]	auto[1]	8	1			T82	3		T244	1		T432	1
auto[4026531840:4160749567]	auto[1]	14	1			T255	1		T283	1		T379	1
auto[4160749568:4294967295]	auto[1]	3	1			T269	1		T268	1		T429	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1698

1

T15

9

T16

4

T17

1

auto[1]

1803

1

T14

6

T5

1

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	118	1			T15	1		T138	1		T69	1
auto[134217728:268435455]	89	1			T158	1		T82	1		T77	1
auto[268435456:402653183]	94	1			T16	1		T83	1		T20	1
auto[402653184:536870911]	106	1			T5	1		T20	1		T65	2
auto[536870912:671088639]	119	1			T15	1		T18	1		T60	1
auto[671088640:805306367]	99	1			T15	1		T20	1		T157	1
auto[805306368:939524095]	125	1			T138	1		T72	1		T6	1
auto[939524096:1073741823]	115	1			T15	1		T74	1		T60	1
auto[1073741824:1207959551]	122	1			T15	1		T20	1		T65	1
auto[1207959552:1342177279]	104	1			T14	1		T44	1		T130	2
auto[1342177280:1476395007]	116	1			T16	1		T82	1		T30	1
auto[1476395008:1610612735]	136	1			T14	1		T214	1		T65	1
auto[1610612736:1744830463]	110	1			T14	2		T15	1		T16	1
auto[1744830464:1879048191]	116	1			T14	1		T130	1		T37	1
auto[1879048192:2013265919]	107	1			T14	1		T44	1		T77	1
auto[2013265920:2147483647]	111	1			T82	1		T138	1		T83	1
auto[2147483648:2281701375]	104	1			T17	1		T83	1		T214	1
auto[2281701376:2415919103]	104	1			T18	1		T66	1		T60	1
auto[2415919104:2550136831]	100	1			T15	1		T16	1		T82	1
auto[2550136832:2684354559]	111	1			T69	1		T74	1		T6	2
auto[2684354560:2818572287]	142	1			T34	1		T19	1		T82	1
auto[2818572288:2952790015]	110	1			T16	1		T69	1		T20	2
auto[2952790016:3087007743]	91	1			T16	1		T20	1		T72	1
auto[3087007744:3221225471]	107	1			T17	1		T131	1		T48	1
auto[3221225472:3355443199]	115	1			T65	1		T78	1		T280	1
auto[3355443200:3489660927]	101	1			T19	1		T77	1		T70	2
auto[3489660928:3623878655]	112	1			T16	1		T18	1		T138	1
auto[3623878656:3758096383]	101	1			T34	1		T19	1		T70	1
auto[3758096384:3892314111]	98	1			T16	1		T65	1		T77	1
auto[3892314112:4026531839]	101	1			T15	1		T83	2		T69	1
auto[4026531840:4160749567]	114	1			T18	1		T158	1		T77	2
auto[4160749568:4294967295]	103	1			T15	2		T66	2		T103	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T15	1		T37	1		T6	2
auto[0:134217727]	auto[1]	70	1			T138	1		T69	1		T75	1
auto[134217728:268435455]	auto[0]	48	1			T158	1		T82	1		T77	1
auto[134217728:268435455]	auto[1]	41	1			T105	1		T6	1		T78	1
auto[268435456:402653183]	auto[0]	41	1			T83	1		T75	1		T6	2
auto[268435456:402653183]	auto[1]	53	1			T16	1		T20	1		T30	1
auto[402653184:536870911]	auto[0]	58	1			T20	1		T65	2		T70	1
auto[402653184:536870911]	auto[1]	48	1			T5	1		T66	2		T52	1
auto[536870912:671088639]	auto[0]	60	1			T15	1		T60	1		T130	1
auto[536870912:671088639]	auto[1]	59	1			T18	1		T70	2		T157	1
auto[671088640:805306367]	auto[0]	42	1			T15	1		T106	1		T108	1
auto[671088640:805306367]	auto[1]	57	1			T20	1		T157	1		T28	1
auto[805306368:939524095]	auto[0]	58	1			T6	1		T217	1		T215	1
auto[805306368:939524095]	auto[1]	67	1			T138	1		T72	1		T217	1
auto[939524096:1073741823]	auto[0]	52	1			T15	1		T60	1		T122	1
auto[939524096:1073741823]	auto[1]	63	1			T74	1		T70	1		T6	1
auto[1073741824:1207959551]	auto[0]	51	1			T15	1		T20	1		T130	1
auto[1073741824:1207959551]	auto[1]	71	1			T65	1		T105	1		T280	2
auto[1207959552:1342177279]	auto[0]	56	1			T130	2		T6	1		T251	1
auto[1207959552:1342177279]	auto[1]	48	1			T14	1		T44	1		T210	1
auto[1342177280:1476395007]	auto[0]	52	1			T30	1		T6	1		T137	1
auto[1342177280:1476395007]	auto[1]	64	1			T16	1		T82	1		T77	1
auto[1476395008:1610612735]	auto[0]	60	1			T214	1		T70	1		T51	1
auto[1476395008:1610612735]	auto[1]	76	1			T14	1		T65	1		T52	1
auto[1610612736:1744830463]	auto[0]	52	1			T16	1		T20	1		T280	1
auto[1610612736:1744830463]	auto[1]	58	1			T14	2		T15	1		T217	1
auto[1744830464:1879048191]	auto[0]	63	1			T130	1		T37	1		T52	1
auto[1744830464:1879048191]	auto[1]	53	1			T14	1		T216	1		T270	1
auto[1879048192:2013265919]	auto[0]	48	1			T48	1		T6	2		T280	1
auto[1879048192:2013265919]	auto[1]	59	1			T14	1		T44	1		T77	1
auto[2013265920:2147483647]	auto[0]	53	1			T83	1		T6	1		T280	1
auto[2013265920:2147483647]	auto[1]	58	1			T82	1		T138	1		T75	1
auto[2147483648:2281701375]	auto[0]	55	1			T214	1		T70	2		T48	1
auto[2147483648:2281701375]	auto[1]	49	1			T17	1		T83	1		T102	1
auto[2281701376:2415919103]	auto[0]	60	1			T18	1		T66	1		T60	1
auto[2281701376:2415919103]	auto[1]	44	1			T51	1		T217	1		T304	1
auto[2415919104:2550136831]	auto[0]	49	1			T15	1		T16	1		T51	2
auto[2415919104:2550136831]	auto[1]	51	1			T82	1		T83	1		T66	1
auto[2550136832:2684354559]	auto[0]	58	1			T6	2		T219	1		T31	1
auto[2550136832:2684354559]	auto[1]	53	1			T69	1		T74	1		T106	1
auto[2684354560:2818572287]	auto[0]	70	1			T19	1		T82	1		T65	1
auto[2684354560:2818572287]	auto[1]	72	1			T34	1		T44	1		T65	1
auto[2818572288:2952790015]	auto[0]	51	1			T16	1		T20	1		T65	1
auto[2818572288:2952790015]	auto[1]	59	1			T69	1		T20	1		T72	1
auto[2952790016:3087007743]	auto[0]	44	1			T6	1		T90	2		T434	1
auto[2952790016:3087007743]	auto[1]	47	1			T16	1		T20	1		T72	1
auto[3087007744:3221225471]	auto[0]	44	1			T17	1		T131	1		T48	1
auto[3087007744:3221225471]	auto[1]	63	1			T157	1		T107	1		T216	1
auto[3221225472:3355443199]	auto[0]	60	1			T78	1		T280	1		T107	1
auto[3221225472:3355443199]	auto[1]	55	1			T65	1		T265	1		T121	1
auto[3355443200:3489660927]	auto[0]	39	1			T37	1		T215	1		T250	1
auto[3355443200:3489660927]	auto[1]	62	1			T19	1		T77	1		T70	2
auto[3489660928:3623878655]	auto[0]	58	1			T69	1		T44	1		T131	1
auto[3489660928:3623878655]	auto[1]	54	1			T16	1		T18	1		T138	1
auto[3623878656:3758096383]	auto[0]	50	1			T34	1		T157	1		T6	1
auto[3623878656:3758096383]	auto[1]	51	1			T19	1		T70	1		T48	1
auto[3758096384:3892314111]	auto[0]	54	1			T16	1		T65	1		T21	1
auto[3758096384:3892314111]	auto[1]	44	1			T77	1		T78	1		T90	1
auto[3892314112:4026531839]	auto[0]	48	1			T15	1		T70	3		T37	1
auto[3892314112:4026531839]	auto[1]	53	1			T83	2		T69	1		T218	1
auto[4026531840:4160749567]	auto[0]	61	1			T77	2		T304	1		T106	1
auto[4026531840:4160749567]	auto[1]	53	1			T18	1		T158	1		T251	1
auto[4160749568:4294967295]	auto[0]	55	1			T15	2		T66	2		T105	1
auto[4160749568:4294967295]	auto[1]	48	1			T103	1		T107	1		T218	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1679

1

T14

1

T15

10

T16

4

auto[1]

1822

1

T14

5

T5

1

T16

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	121	1			T65	1		T131	1		T130	1
auto[134217728:268435455]	88	1			T15	1		T214	1		T66	2
auto[268435456:402653183]	131	1			T14	1		T16	1		T18	1
auto[402653184:536870911]	103	1			T14	1		T30	1		T75	1
auto[536870912:671088639]	97	1			T19	1		T138	2		T69	1
auto[671088640:805306367]	100	1			T19	1		T83	1		T20	1
auto[805306368:939524095]	128	1			T18	1		T82	1		T20	1
auto[939524096:1073741823]	123	1			T158	1		T44	1		T51	1
auto[1073741824:1207959551]	99	1			T14	1		T69	1		T74	1
auto[1207959552:1342177279]	116	1			T15	1		T16	1		T82	1
auto[1342177280:1476395007]	110	1			T16	1		T158	1		T138	1
auto[1476395008:1610612735]	100	1			T66	1		T21	1		T70	2
auto[1610612736:1744830463]	119	1			T34	1		T83	2		T77	1
auto[1744830464:1879048191]	103	1			T18	1		T82	1		T103	1
auto[1879048192:2013265919]	100	1			T65	1		T6	1		T78	1
auto[2013265920:2147483647]	118	1			T15	1		T69	3		T65	2
auto[2147483648:2281701375]	103	1			T14	1		T16	1		T17	1
auto[2281701376:2415919103]	116	1			T15	1		T82	1		T51	1
auto[2415919104:2550136831]	100	1			T15	1		T17	1		T19	1
auto[2550136832:2684354559]	93	1			T14	1		T15	1		T16	1
auto[2684354560:2818572287]	114	1			T44	1		T6	6		T78	1
auto[2818572288:2952790015]	113	1			T15	1		T77	1		T48	1
auto[2952790016:3087007743]	130	1			T131	1		T157	1		T6	2
auto[3087007744:3221225471]	104	1			T20	1		T30	1		T66	1
auto[3221225472:3355443199]	105	1			T70	1		T48	1		T37	1
auto[3355443200:3489660927]	101	1			T83	1		T60	1		T105	1
auto[3489660928:3623878655]	110	1			T15	1		T16	1		T83	1
auto[3623878656:3758096383]	110	1			T15	1		T18	1		T138	1
auto[3758096384:3892314111]	108	1			T16	1		T60	1		T265	1
auto[3892314112:4026531839]	110	1			T5	1		T34	1		T214	1
auto[4026531840:4160749567]	119	1			T14	1		T15	1		T20	1
auto[4160749568:4294967295]	109	1			T16	1		T82	1		T70	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T131	1		T130	1		T6	1
auto[0:134217727]	auto[1]	68	1			T65	1		T78	1		T218	1
auto[134217728:268435455]	auto[0]	41	1			T15	1		T214	1		T66	1
auto[134217728:268435455]	auto[1]	47	1			T66	1		T75	1		T70	1
auto[268435456:402653183]	auto[0]	67	1			T52	1		T6	2		T106	1
auto[268435456:402653183]	auto[1]	64	1			T14	1		T16	1		T18	1
auto[402653184:536870911]	auto[0]	52	1			T30	1		T75	1		T157	1
auto[402653184:536870911]	auto[1]	51	1			T14	1		T48	1		T6	1
auto[536870912:671088639]	auto[0]	51	1			T19	1		T48	1		T6	1
auto[536870912:671088639]	auto[1]	46	1			T138	2		T69	1		T70	1
auto[671088640:805306367]	auto[0]	47	1			T83	1		T20	1		T77	2
auto[671088640:805306367]	auto[1]	53	1			T19	1		T44	1		T77	1
auto[805306368:939524095]	auto[0]	62	1			T37	1		T304	1		T107	1
auto[805306368:939524095]	auto[1]	66	1			T18	1		T82	1		T20	1
auto[939524096:1073741823]	auto[0]	63	1			T158	1		T378	1		T434	1
auto[939524096:1073741823]	auto[1]	60	1			T44	1		T51	1		T6	2
auto[1073741824:1207959551]	auto[0]	49	1			T69	1		T66	1		T217	1
auto[1073741824:1207959551]	auto[1]	50	1			T14	1		T74	1		T6	1
auto[1207959552:1342177279]	auto[0]	54	1			T15	1		T16	1		T20	1
auto[1207959552:1342177279]	auto[1]	62	1			T82	1		T20	1		T102	1
auto[1342177280:1476395007]	auto[0]	52	1			T20	1		T65	1		T105	1
auto[1342177280:1476395007]	auto[1]	58	1			T16	1		T158	1		T138	1
auto[1476395008:1610612735]	auto[0]	41	1			T66	1		T21	1		T70	1
auto[1476395008:1610612735]	auto[1]	59	1			T70	1		T435	1		T274	1
auto[1610612736:1744830463]	auto[0]	64	1			T83	1		T77	1		T70	1
auto[1610612736:1744830463]	auto[1]	55	1			T34	1		T83	1		T70	1
auto[1744830464:1879048191]	auto[0]	45	1			T130	1		T37	1		T314	1
auto[1744830464:1879048191]	auto[1]	58	1			T18	1		T82	1		T103	1
auto[1879048192:2013265919]	auto[0]	47	1			T65	1		T436	1		T109	1
auto[1879048192:2013265919]	auto[1]	53	1			T6	1		T78	1		T250	1
auto[2013265920:2147483647]	auto[0]	59	1			T15	1		T66	1		T6	1
auto[2013265920:2147483647]	auto[1]	59	1			T69	3		T65	2		T92	1
auto[2147483648:2281701375]	auto[0]	57	1			T14	1		T16	1		T6	2
auto[2147483648:2281701375]	auto[1]	46	1			T17	1		T65	1		T218	1
auto[2281701376:2415919103]	auto[0]	57	1			T15	1		T51	1		T6	1
auto[2281701376:2415919103]	auto[1]	59	1			T82	1		T122	1		T107	1
auto[2415919104:2550136831]	auto[0]	50	1			T15	1		T17	1		T65	1
auto[2415919104:2550136831]	auto[1]	50	1			T19	1		T51	1		T6	1
auto[2550136832:2684354559]	auto[0]	44	1			T15	1		T16	1		T20	1
auto[2550136832:2684354559]	auto[1]	49	1			T14	1		T72	1		T52	1
auto[2684354560:2818572287]	auto[0]	43	1			T6	3		T78	1		T269	1
auto[2684354560:2818572287]	auto[1]	71	1			T44	1		T6	3		T270	1
auto[2818572288:2952790015]	auto[0]	58	1			T15	1		T77	1		T48	1
auto[2818572288:2952790015]	auto[1]	55	1			T25	1		T215	1		T56	1
auto[2952790016:3087007743]	auto[0]	61	1			T131	1		T6	1		T280	1
auto[2952790016:3087007743]	auto[1]	69	1			T157	1		T6	1		T217	1
auto[3087007744:3221225471]	auto[0]	46	1			T70	1		T6	1		T106	1
auto[3087007744:3221225471]	auto[1]	58	1			T20	1		T30	1		T66	1
auto[3221225472:3355443199]	auto[0]	54	1			T70	1		T48	1		T37	1
auto[3221225472:3355443199]	auto[1]	51	1			T6	1		T218	1		T108	2
auto[3355443200:3489660927]	auto[0]	38	1			T60	1		T47	1		T294	1
auto[3355443200:3489660927]	auto[1]	63	1			T83	1		T105	1		T304	1
auto[3489660928:3623878655]	auto[0]	52	1			T15	1		T70	1		T78	1
auto[3489660928:3623878655]	auto[1]	58	1			T16	1		T83	1		T65	1
auto[3623878656:3758096383]	auto[0]	48	1			T15	1		T65	1		T6	2
auto[3623878656:3758096383]	auto[1]	62	1			T18	1		T138	1		T77	1
auto[3758096384:3892314111]	auto[0]	49	1			T16	1		T60	1		T265	1
auto[3758096384:3892314111]	auto[1]	59	1			T108	1		T211	1		T244	2
auto[3892314112:4026531839]	auto[0]	62	1			T214	1		T130	1		T6	1
auto[3892314112:4026531839]	auto[1]	48	1			T5	1		T34	1		T66	1
auto[4026531840:4160749567]	auto[0]	52	1			T15	1		T44	1		T130	1
auto[4026531840:4160749567]	auto[1]	67	1			T14	1		T20	1		T30	1
auto[4160749568:4294967295]	auto[0]	61	1			T130	1		T6	1		T219	2
auto[4160749568:4294967295]	auto[1]	48	1			T16	1		T82	1		T70	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1687

1

T14

1

T15

9

T16

4

auto[1]

1815

1

T14

5

T5

1

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T14	1		T5	1		T65	1
auto[134217728:268435455]	110	1			T16	1		T83	1		T48	1
auto[268435456:402653183]	110	1			T15	1		T16	1		T19	1
auto[402653184:536870911]	103	1			T14	1		T15	1		T16	1
auto[536870912:671088639]	117	1			T15	2		T16	1		T60	1
auto[671088640:805306367]	127	1			T138	1		T65	1		T66	1
auto[805306368:939524095]	93	1			T69	1		T20	1		T72	1
auto[939524096:1073741823]	124	1			T19	1		T82	2		T103	1
auto[1073741824:1207959551]	120	1			T83	1		T214	1		T77	1
auto[1207959552:1342177279]	112	1			T15	2		T48	1		T37	1
auto[1342177280:1476395007]	90	1			T75	1		T70	1		T51	1
auto[1476395008:1610612735]	112	1			T16	1		T66	1		T77	1
auto[1610612736:1744830463]	113	1			T20	1		T70	1		T157	1
auto[1744830464:1879048191]	112	1			T16	1		T51	1		T6	1
auto[1879048192:2013265919]	128	1			T18	1		T158	1		T65	1
auto[2013265920:2147483647]	122	1			T138	1		T44	1		T70	1
auto[2147483648:2281701375]	90	1			T14	1		T16	1		T18	1
auto[2281701376:2415919103]	105	1			T18	1		T30	1		T77	1
auto[2415919104:2550136831]	100	1			T14	1		T15	1		T20	1
auto[2550136832:2684354559]	118	1			T15	1		T65	1		T77	1
auto[2684354560:2818572287]	104	1			T83	2		T106	1		T137	1
auto[2818572288:2952790015]	108	1			T14	1		T83	1		T69	2
auto[2952790016:3087007743]	76	1			T65	2		T70	3		T137	1
auto[3087007744:3221225471]	110	1			T17	1		T20	2		T70	1
auto[3221225472:3355443199]	107	1			T34	1		T19	1		T82	1
auto[3355443200:3489660927]	132	1			T138	1		T69	1		T44	2
auto[3489660928:3623878655]	110	1			T14	1		T15	1		T82	1
auto[3623878656:3758096383]	116	1			T18	1		T30	1		T65	1
auto[3758096384:3892314111]	112	1			T214	1		T65	1		T131	1
auto[3892314112:4026531839]	106	1			T16	1		T17	1		T83	1
auto[4026531840:4160749567]	105	1			T60	1		T70	1		T52	1
auto[4160749568:4294967295]	104	1			T15	1		T157	1		T52	1