dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 4778 1 T14 12 T5 2 T15 20
auto[1] 2224 1 T16 8 T18 4 T34 2



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 232 1 T15 4 T18 2 T70 2
auto[134217728:268435455] 182 1 T15 2 T16 2 T214 2
auto[268435456:402653183] 200 1 T14 2 T16 2 T82 2
auto[402653184:536870911] 184 1 T16 2 T82 2 T20 2
auto[536870912:671088639] 188 1 T19 2 T65 2 T66 2
auto[671088640:805306367] 200 1 T82 2 T138 2 T72 2
auto[805306368:939524095] 244 1 T6 4 T217 2 T31 2
auto[939524096:1073741823] 202 1 T82 2 T20 2 T30 2
auto[1073741824:1207959551] 232 1 T15 2 T69 2 T70 2
auto[1207959552:1342177279] 202 1 T18 2 T69 2 T44 2
auto[1342177280:1476395007] 230 1 T83 2 T44 2 T214 4
auto[1476395008:1610612735] 222 1 T16 2 T19 2 T69 2
auto[1610612736:1744830463] 208 1 T18 2 T34 2 T30 2
auto[1744830464:1879048191] 218 1 T15 2 T48 2 T6 2
auto[1879048192:2013265919] 252 1 T16 2 T30 2 T44 2
auto[2013265920:2147483647] 218 1 T158 2 T138 2 T83 2
auto[2147483648:2281701375] 256 1 T14 4 T15 2 T16 2
auto[2281701376:2415919103] 274 1 T15 2 T70 4 T51 2
auto[2415919104:2550136831] 226 1 T16 2 T18 2 T83 2
auto[2550136832:2684354559] 244 1 T5 2 T15 2 T34 2
auto[2684354560:2818572287] 226 1 T17 2 T65 2 T21 2
auto[2818572288:2952790015] 228 1 T17 2 T6 6 T217 2
auto[2952790016:3087007743] 190 1 T15 2 T6 2 T78 2
auto[3087007744:3221225471] 188 1 T20 2 T74 2 T130 2
auto[3221225472:3355443199] 214 1 T19 2 T65 2 T75 2
auto[3355443200:3489660927] 206 1 T14 2 T69 2 T65 2
auto[3489660928:3623878655] 208 1 T14 2 T65 2 T77 2
auto[3623878656:3758096383] 196 1 T16 2 T65 2 T70 2
auto[3758096384:3892314111] 238 1 T82 2 T77 2 T37 2
auto[3892314112:4026531839] 230 1 T83 2 T20 2 T77 2
auto[4026531840:4160749567] 222 1 T83 2 T44 2 T66 2
auto[4160749568:4294967295] 242 1 T14 2 T15 2 T138 2



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 170 1 T15 4 T18 2 T70 2
auto[0:134217727] auto[1] 62 1 T105 2 T133 2 T90 8
auto[134217728:268435455] auto[0] 128 1 T15 2 T214 2 T216 2
auto[134217728:268435455] auto[1] 54 1 T16 2 T66 2 T219 2
auto[268435456:402653183] auto[0] 132 1 T14 2 T16 2 T82 2
auto[268435456:402653183] auto[1] 68 1 T37 2 T108 2 T441 2
auto[402653184:536870911] auto[0] 138 1 T16 2 T82 2 T20 2
auto[402653184:536870911] auto[1] 46 1 T65 2 T70 2 T51 2
auto[536870912:671088639] auto[0] 120 1 T65 2 T157 2 T217 2
auto[536870912:671088639] auto[1] 68 1 T19 2 T66 2 T70 2
auto[671088640:805306367] auto[0] 134 1 T82 2 T138 2 T72 2
auto[671088640:805306367] auto[1] 66 1 T66 2 T70 2 T51 2
auto[805306368:939524095] auto[0] 186 1 T6 4 T217 2 T307 2
auto[805306368:939524095] auto[1] 58 1 T31 2 T90 2 T255 2
auto[939524096:1073741823] auto[0] 142 1 T82 2 T20 2 T30 2
auto[939524096:1073741823] auto[1] 60 1 T103 2 T6 2 T269 2
auto[1073741824:1207959551] auto[0] 148 1 T15 2 T69 2 T70 2
auto[1073741824:1207959551] auto[1] 84 1 T51 2 T280 2 T45 2
auto[1207959552:1342177279] auto[0] 130 1 T69 2 T51 2 T130 2
auto[1207959552:1342177279] auto[1] 72 1 T18 2 T44 2 T60 2
auto[1342177280:1476395007] auto[0] 160 1 T44 2 T214 2 T70 6
auto[1342177280:1476395007] auto[1] 70 1 T83 2 T214 2 T75 2
auto[1476395008:1610612735] auto[0] 156 1 T16 2 T69 2 T74 2
auto[1476395008:1610612735] auto[1] 66 1 T19 2 T21 2 T108 2
auto[1610612736:1744830463] auto[0] 142 1 T30 2 T6 2 T217 2
auto[1610612736:1744830463] auto[1] 66 1 T18 2 T34 2 T48 2
auto[1744830464:1879048191] auto[0] 152 1 T15 2 T48 2 T6 2
auto[1744830464:1879048191] auto[1] 66 1 T314 2 T442 4 T320 2
auto[1879048192:2013265919] auto[0] 188 1 T30 2 T44 2 T60 2
auto[1879048192:2013265919] auto[1] 64 1 T16 2 T136 6 T93 2
auto[2013265920:2147483647] auto[0] 142 1 T158 2 T138 2 T83 2
auto[2013265920:2147483647] auto[1] 76 1 T70 2 T6 2 T218 2
auto[2147483648:2281701375] auto[0] 152 1 T14 4 T15 2 T20 2
auto[2147483648:2281701375] auto[1] 104 1 T16 2 T138 2 T65 2
auto[2281701376:2415919103] auto[0] 176 1 T15 2 T70 4 T48 2
auto[2281701376:2415919103] auto[1] 98 1 T51 2 T6 4 T107 2
auto[2415919104:2550136831] auto[0] 154 1 T16 2 T18 2 T83 2
auto[2415919104:2550136831] auto[1] 72 1 T20 2 T66 2 T60 2
auto[2550136832:2684354559] auto[0] 174 1 T5 2 T15 2 T34 2
auto[2550136832:2684354559] auto[1] 70 1 T158 2 T6 2 T25 2
auto[2684354560:2818572287] auto[0] 146 1 T17 2 T65 2 T70 2
auto[2684354560:2818572287] auto[1] 80 1 T21 2 T6 2 T304 2
auto[2818572288:2952790015] auto[0] 162 1 T17 2 T6 2 T217 2
auto[2818572288:2952790015] auto[1] 66 1 T6 4 T321 2 T109 2
auto[2952790016:3087007743] auto[0] 130 1 T15 2 T137 2 T269 2
auto[2952790016:3087007743] auto[1] 60 1 T6 2 T78 2 T251 2
auto[3087007744:3221225471] auto[0] 120 1 T130 2 T6 2 T25 2
auto[3087007744:3221225471] auto[1] 68 1 T20 2 T74 2 T6 4
auto[3221225472:3355443199] auto[0] 126 1 T65 2 T75 2 T48 2
auto[3221225472:3355443199] auto[1] 88 1 T19 2 T77 2 T131 2
auto[3355443200:3489660927] auto[0] 148 1 T14 2 T69 2 T65 2
auto[3355443200:3489660927] auto[1] 58 1 T102 2 T68 2 T434 2
auto[3489660928:3623878655] auto[0] 134 1 T14 2 T65 2 T77 2
auto[3489660928:3623878655] auto[1] 74 1 T108 4 T91 2 T92 2
auto[3623878656:3758096383] auto[0] 134 1 T65 2 T70 2 T6 2
auto[3623878656:3758096383] auto[1] 62 1 T16 2 T52 2 T265 2
auto[3758096384:3892314111] auto[0] 174 1 T82 2 T77 2 T37 2
auto[3758096384:3892314111] auto[1] 64 1 T6 2 T78 4 T219 2
auto[3892314112:4026531839] auto[0] 150 1 T83 2 T77 2 T70 2
auto[3892314112:4026531839] auto[1] 80 1 T20 2 T218 2 T250 2
auto[4026531840:4160749567] auto[0] 158 1 T83 2 T44 2 T75 2
auto[4026531840:4160749567] auto[1] 64 1 T66 2 T316 2 T251 2
auto[4160749568:4294967295] auto[0] 172 1 T14 2 T15 2 T138 2
auto[4160749568:4294967295] auto[1] 70 1 T77 2 T37 2 T6 2

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%